Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/lib/jenkins/workspace/Risco 5 [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -Rf Risco-5/ build/ [Pipeline] sh + git clone https://github.com/JN513/Risco-5 Cloning into 'Risco-5'... [Pipeline] sh + cd Risco-5 [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (IVerilog) [Pipeline] sh + mkdir -p build [Pipeline] sh + cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/csr_unit.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/fifo.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v [Pipeline] sh + /eda/oss-cad-suite/bin/vvp build/soc_test.o ERROR: Risco-5/src/peripheral/memory.v:29: $readmemh: Unable to open software/memory/generic.hex for reading. VCD info: dumpfile build/soc.vcd opened for output. Risco-5/tests/soc_test.v:34: $finish called at 1206 (1s) [Pipeline] sh + rm -f Risco-5/software/memory/generic.hex [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Síntese) [Pipeline] parallel [Pipeline] { (Branch: OSS-Cad-Suite) [Pipeline] { (Branch: Gowin) [Pipeline] { (Branch: Vivado) [Pipeline] stage [Pipeline] { (OSS-Cad-Suite) [Pipeline] stage [Pipeline] { (Gowin) [Pipeline] stage [Pipeline] { (Vivado) [Pipeline] stage [Pipeline] { (Yosys) [Pipeline] sh [Pipeline] sh + rm -rf Risco-5/impl/pnr [Pipeline] sh + cd Risco-5/fpga/nexys4_ddr + mkdir build + /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source run.tcl [Pipeline] sh + mkdir -p Risco-5/impl/pnr [Pipeline] } + /eda/oss-cad-suite/bin/yosys -p read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf <claire@yosyshq.com> | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) -- Running command ` read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 ' -- 1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: Risco-5/debug/reset.v Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation. Generating RTLIL representation for module `\ResetBootSystem'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation. Generating RTLIL representation for module `\Alu'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation. Generating RTLIL representation for module `\ALU_Control'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation. Generating RTLIL representation for module `\Control_Unit'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: Risco-5/src/core/core.v Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation. Generating RTLIL representation for module `\Core'. Risco-5/src/core/core.v:106: Warning: Identifier `\pc_source' is implicitly declared. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: Risco-5/src/core/csr_unit.v Parsing Verilog input from `Risco-5/src/core/csr_unit.v' to AST representation. Generating RTLIL representation for module `\CSR_Unit'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation. Generating RTLIL representation for module `\Immediate_Generator'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation. Generating RTLIL representation for module `\MUX'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation. Generating RTLIL representation for module `\PC'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation. Generating RTLIL representation for module `\Registers'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation. Generating RTLIL representation for module `\BUS'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/fifo.v Parsing Verilog input from `Risco-5/src/peripheral/fifo.v' to AST representation. Generating RTLIL representation for module `\FIFO'. Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9) Generating RTLIL representation for module `\GPIO'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation. Generating RTLIL representation for module `\GPIOS'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation. Generating RTLIL representation for module `\LEDs'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation. Generating RTLIL representation for module `\Memory'. Successfully finished Verilog frontend. 18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation. Generating RTLIL representation for module `\Risco_5_SOC'. Successfully finished Verilog frontend. 19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation. Generating RTLIL representation for module `\UART'. Successfully finished Verilog frontend. 20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_tool_rx'. Successfully finished Verilog frontend. 21. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tool_tx'. Successfully finished Verilog frontend. 22. Executing SYNTH_ECP5 pass. 22.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\DP16KD'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 22.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCUA'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Successfully finished Verilog frontend. 22.3. Executing HIERARCHY pass (managing design hierarchy). 22.3.1. Finding top of design hierarchy.. root of 0 design levels: uart_tool_tx root of 0 design levels: uart_tool_rx root of 1 design levels: UART root of 2 design levels: Risco_5_SOC root of 0 design levels: Memory root of 0 design levels: LEDs root of 1 design levels: GPIOS root of 0 design levels: GPIO root of 0 design levels: FIFO root of 0 design levels: BUS root of 0 design levels: Registers root of 0 design levels: PC root of 0 design levels: MUX root of 0 design levels: Immediate_Generator root of 0 design levels: CSR_Unit root of 1 design levels: Core root of 0 design levels: Control_Unit root of 0 design levels: ALU_Control root of 0 design levels: Alu root of 0 design levels: ResetBootSystem root of 3 design levels: top Automatically selected top as design top module. 22.3.2. Analyzing design hierarchy.. Top module: \top Used module: \Risco_5_SOC Used module: \GPIOS Used module: \GPIO Used module: \UART Used module: \uart_tool_tx Used module: \uart_tool_rx Used module: \FIFO Used module: \LEDs Used module: \BUS Used module: \Memory Used module: \Core Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: \ResetBootSystem Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \MEMORY_SIZE = 2048 Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000 Parameter \GPIO_WIDHT = 6 22.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \MEMORY_SIZE = 2048 Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000 Parameter \GPIO_WIDHT = 6 Generating RTLIL representation for module `$paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC'. Parameter \CYCLES = 20 22.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'. Parameter \CYCLES = 20 Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'. Parameter \WIDHT = 5 22.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'. Parameter \WIDHT = 5 Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 9600 22.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Generating RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 22.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \BOOT_ADDRESS = 0 22.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'. Parameter \BOOT_ADDRESS = 0 Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'. Risco-5/src/core/core.v:106: Warning: Identifier `\pc_source' is implicitly declared. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 22.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 22.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 22.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 22.3.12. Analyzing design hierarchy.. Top module: \top Used module: $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC Used module: \GPIOS Used module: \GPIO Used module: \UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \LEDs Used module: \BUS Used module: \Memory Used module: \Core Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Parameter \WIDHT = 6 22.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'. Parameter \WIDHT = 6 Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 115200 22.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Generating RTLIL representation for module `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART'. Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000 Parameter \MEMORY_SIZE = 2048 22.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000 Parameter \MEMORY_SIZE = 2048 Generating RTLIL representation for module `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory'. Parameter \BOOT_ADDRESS = 0 Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'. 22.3.16. Analyzing design hierarchy.. Top module: \top Used module: $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART Used module: \uart_tool_tx Used module: \uart_tool_rx Used module: \FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 22.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 22.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 22.3.19. Analyzing design hierarchy.. Top module: \top Used module: $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 22.3.20. Analyzing design hierarchy.. Top module: \top Used module: $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'. Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'. Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Removing unused module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'. Removing unused module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'. Removing unused module `\uart_tool_tx'. Removing unused module `\uart_tool_rx'. Removing unused module `\UART'. Removing unused module `\Risco_5_SOC'. Removing unused module `\Memory'. Removing unused module `\GPIOS'. Removing unused module `\FIFO'. Removing unused module `\Core'. Removing unused module `\ResetBootSystem'. Removed 14 unused modules. 22.4. Executing PROC pass (convert processes to netlists). 22.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$495'. Found and cleaned up 1 empty switch in `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:0$883'. Removing empty process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:0$883'. Cleaned up 2 empty switches. 22.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$602 in module TRELLIS_FF. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554 in module DPR16X4C. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496 in module TRELLIS_DPR16X4. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/fifo.v:24$794 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:197$976 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:186$974 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:171$966 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:160$963 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:148$957 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:133$952 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:116$947 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:97$938 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:173$925 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:162$923 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:147$915 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:130$901 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:115$895 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:98$890 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:179$684 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:45$881 in module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:33$844 in module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$215 in module LEDs. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:76$834 in module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:41$820 in module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:29$818 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:22$73 in module Registers. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:15$63 in module PC. Removed 1 dead cases from process $proc$Risco-5/src/core/mux.v:10$62 in module MUX. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/mux.v:10$62 in module MUX. Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:18$60 in module Immediate_Generator. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:181$58 in module CSR_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:172$54 in module CSR_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:158$52 in module CSR_Unit. Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:113$45 in module CSR_Unit. Marked 5 switch rules as full_case in process $proc$Risco-5/debug/reset.v:24$605 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Removed 1 dead cases from process $proc$Risco-5/src/core/control_unit.v:122$33 in module Control_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:122$33 in module Control_Unit. Removed 1 dead cases from process $proc$Risco-5/src/core/control_unit.v:80$31 in module Control_Unit. Marked 3 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:80$31 in module Control_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:72$30 in module Control_Unit. Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:9$26 in module ALU_Control. Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:9$26 in module ALU_Control. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:23$11 in module Alu. Removed a total of 4 dead cases. 22.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 11 redundant assignments. Promoted 146 assignments to connections. 22.4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$603'. Set init value: \Q = 1'0 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$978'. Set init value: \i = 0 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$931'. Set init value: \i = 0 Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$687'. Set init value: \instruction_register = 0 Set init value: \memory_register = 0 Set init value: \alu_out_register = 0 Set init value: \register_data_1 = 0 Set init value: \register_data_2 = 0 Set init value: \pc_old = 0 Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$218'. Set init value: \data = 33'000000000000000000000000000000000 Found init rule in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$837'. Set init value: \uart_tx_en = 1'0 Set init value: \tx_fifo_read = 1'0 Set init value: \tx_fifo_write = 1'0 Set init value: \rx_fifo_read = 1'0 Set init value: \rx_fifo_write = 1'0 Set init value: \buffer_full = 1'0 Set init value: \uart_tx_data = 8'00000000 Set init value: \tx_fifo_write_data = 8'00000000 Set init value: \rx_fifo_write_data = 8'00000000 Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$66'. Set init value: \Output = 0 Found init rule in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'. Set init value: \csr_mcause = 0 Set init value: \csr_mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000 Set init value: \csr_mepc = 0 Set init value: \csr_mie_mfie = 16'0000000000000000 Set init value: \csr_mie_meie = 1'0 Set init value: \csr_mie_msie = 1'0 Set init value: \csr_mie_mtie = 1'0 Set init value: \csr_mip_mfip = 16'0000000000000000 Set init value: \csr_mip_meip = 1'0 Set init value: \csr_mip_mtip = 1'0 Set init value: \csr_mip_msip = 1'0 Set init value: \csr_minstret = 64'0000000000000000000000000000000000000000000000000000000000000000 Set init value: \csr_mscratch = 0 Set init value: \csr_mstatus_mie = 1'0 Set init value: \csr_mstatus_mpie = 1'0 Set init value: \csr_mtvec = 0 Set init value: \csr_mtval = 0 Set init value: \csr_write_data = 0 Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$611'. Set init value: \reset_o = 1'0 Set init value: \state = 2'01 Set init value: \counter = 6'000000 Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$34'. Set init value: \state = 4'0000 Set init value: \is_immediate = 1'0 Set init value: \lorD = 1'0 Set init value: \pc_write = 1'0 Set init value: \ir_write = 1'0 Set init value: \pc_source = 1'0 Set init value: \reg_write = 1'0 Set init value: \memory_read = 1'0 Set init value: \memory_write = 1'0 Set init value: \pc_write_cond = 1'0 Set init value: \csr_write_enable = 1'0 Set init value: \aluop = 2'00 Set init value: \alu_src_a = 2'00 Set init value: \alu_src_b = 2'00 Set init value: \memory_to_reg = 2'00 Set init value: \nextstate = 4'0000 22.4.5. Executing PROC_ARST pass (detect async resets in processes). 22.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 1 switch. <suppressed ~88 debug messages> 22.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$603'. Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$602'. 1/1: $0\Q[0:0] Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554'. 1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_EN[3:0]$560 2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_DATA[3:0]$559 3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_ADDR[3:0]$558 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_EN[3:0]$502 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_DATA[3:0]$501 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_ADDR[3:0]$500 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$495'. Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'. 1/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$806 2/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_DATA[7:0]$805 3/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$804 4/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$801 5/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_DATA[7:0]$800 6/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$799 7/8: $0\write_ptr[5:0] 8/8: $0\read_ptr[5:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$978'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$976'. 1/2: $0\rxd_reg_0[0:0] 2/2: $0\rxd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$974'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$966'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$963'. 1/1: $0\bit_sample[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$957'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$952'. 1/11: $3\i[31:0] 2/11: $0\recieved_data[7:0] [1] 3/11: $0\recieved_data[7:0] [0] 4/11: $0\recieved_data[7:0] [2] 5/11: $0\recieved_data[7:0] [3] 6/11: $0\recieved_data[7:0] [4] 7/11: $0\recieved_data[7:0] [5] 8/11: $0\recieved_data[7:0] [6] 9/11: $0\recieved_data[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$947'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$938'. 1/1: $0\uart_rx_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$931'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$925'. 1/1: $0\txd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$923'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$915'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$901'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$895'. 1/11: $3\i[31:0] 2/11: $0\data_to_send[7:0] [1] 3/11: $0\data_to_send[7:0] [0] 4/11: $0\data_to_send[7:0] [2] 5/11: $0\data_to_send[7:0] [3] 6/11: $0\data_to_send[7:0] [4] 7/11: $0\data_to_send[7:0] [5] 8/11: $0\data_to_send[7:0] [6] 9/11: $0\data_to_send[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$890'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$687'. Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$684'. 1/6: $0\alu_out_register[31:0] 2/6: $0\register_data_2[31:0] 3/6: $0\register_data_1[31:0] 4/6: $0\memory_register[31:0] 5/6: $0\pc_old[31:0] 6/6: $0\instruction_register[31:0] Creating decoders for process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$881'. 1/1: $1\read_data[31:0] Creating decoders for process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'. 1/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$877 2/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_DATA[31:0]$876 3/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$875 4/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$880 5/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_DATA[31:0]$879 6/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$878 7/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$867 8/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_DATA[31:0]$866 9/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_ADDR[31:0]$865 10/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$873 11/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_DATA[31:0]$872 12/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$871 13/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$870 14/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_DATA[31:0]$869 15/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$868 16/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$863 17/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_DATA[31:0]$862 18/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$861 19/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$860 20/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_DATA[31:0]$859 21/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$858 22/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$857 23/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_DATA[31:0]$856 24/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_ADDR[31:0]$855 Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$218'. Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$215'. 1/1: $0\data[32:0] Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$837'. Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$834'. 1/1: $1\read_data[31:0] Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'. 1/9: $0\rx_fifo_write[0:0] 2/9: $0\rx_fifo_read[0:0] 3/9: $0\tx_fifo_write[0:0] 4/9: $0\tx_fifo_read[0:0] 5/9: $0\uart_tx_en[0:0] 6/9: $0\rx_fifo_write_data[7:0] 7/9: $0\tx_fifo_write_data[7:0] 8/9: $0\uart_tx_data[7:0] 9/9: $0\buffer_full[0:0] Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$818'. 1/2: $0\gpio_value[5:0] 2/2: $0\gpio_direction[5:0] Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$91'. Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'. 1/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$88 2/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$69_DATA[31:0]$87 3/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$69_ADDR[4:0]$86 4/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$89 5/9: $1$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$80 6/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$84 7/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$83 8/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$69_DATA[31:0]$82 9/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$69_ADDR[4:0]$81 Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$66'. Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:15$63'. 1/1: $0\Output[31:0] Creating decoders for process `\MUX.$proc$Risco-5/src/core/mux.v:10$62'. 1/1: $1\S[31:0] Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$60'. 1/4: $4\immediate[31:0] 2/4: $3\immediate[31:0] 3/4: $2\immediate[31:0] 4/4: $1\immediate[31:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'. Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:181$58'. 1/1: $1\csr_data_out[31:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54'. 1/1: $1\csr_write_data[31:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$52'. 1/4: $0\csr_mip_msip[0:0] 2/4: $0\csr_mip_mtip[0:0] 3/4: $0\csr_mip_meip[0:0] 4/4: $0\csr_mip_mfip[15:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$45'. 1/13: $0\csr_mtval[31:0] 2/13: $0\csr_mtvec[31:0] 3/13: $0\csr_mstatus_mpie[0:0] 4/13: $0\csr_mstatus_mie[0:0] 5/13: $0\csr_mscratch[31:0] 6/13: $0\csr_minstret[63:0] 7/13: $0\csr_mie_mtie[0:0] 8/13: $0\csr_mie_msie[0:0] 9/13: $0\csr_mie_meie[0:0] 10/13: $0\csr_mie_mfie[15:0] 11/13: $0\csr_mepc[31:0] 12/13: $0\csr_mcycle[63:0] 13/13: $0\csr_mcause[31:0] Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$611'. Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'. 1/3: $0\counter[5:0] 2/3: $0\state[1:0] 3/3: $0\reset_o[0:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$34'. Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'. 1/1: { $1\pc_write[0:0] $1\alu_src_b[1:0] $1\ir_write[0:0] $1\memory_read[0:0] $1\memory_to_reg[1:0] $1\alu_src_a[1:0] $1\aluop[1:0] $1\csr_write_enable[0:0] $1\pc_write_cond[0:0] $1\memory_write[0:0] $1\reg_write[0:0] $1\pc_source[0:0] $1\lorD[0:0] $1\is_immediate[0:0] } Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31'. 1/3: $3\nextstate[3:0] 2/3: $2\nextstate[3:0] 3/3: $1\nextstate[3:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$30'. 1/1: $0\state[3:0] Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'. 1/4: $4\aluop_out[3:0] 2/4: $3\aluop_out[3:0] 3/4: $2\aluop_out[3:0] 4/4: $1\aluop_out[3:0] Creating decoders for process `\Alu.$proc$Risco-5/src/core/alu.v:23$11'. 1/1: $1\ALU_out_S[31:0] 22.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$947'. No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$890'. No latch inferred for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.\read_data' from process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$881'. No latch inferred for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\read_data' from process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$834'. No latch inferred for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:16$67_EN' from process `\Registers.$proc$Risco-5/src/core/registers.v:0$91'. No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$Risco-5/src/core/mux.v:10$62'. No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$60'. No latch inferred for signal `\CSR_Unit.\csr_mcause_code' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'. No latch inferred for signal `\CSR_Unit.\csr_mcause_interrupt_flag' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'. No latch inferred for signal `\CSR_Unit.\csr_utime' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'. No latch inferred for signal `\CSR_Unit.\csr_data_out' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:181$58'. No latch inferred for signal `\CSR_Unit.\csr_write_data' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54'. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [0]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [1]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [2]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [3]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [4]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [5]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [6]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [7]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [8]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [9]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [10]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [11]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [12]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [13]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [14]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [15]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [16]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [17]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [18]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [19]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [20]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [21]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [22]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [23]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [24]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [25]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [26]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [27]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [28]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [29]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [30]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [31]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54`. No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\csr_write_enable` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`. No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31`. Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26': $auto$proc_dlatch.cc:433:proc_dlatch$2029 No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$Risco-5/src/core/alu.v:23$11'. 22.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$602'. created $dff cell `$procdff$2052' with positive edge clock. Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$538_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$539_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$540_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$541_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$542_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$543_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$544_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$545_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$546_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$547_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$548_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$549_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$550_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$551_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$552_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554'. created $dff cell `$procdff$2053' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554'. created $dff cell `$procdff$2054' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554'. created $dff cell `$procdff$2055' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$478_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$479_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$480_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$481_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$482_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$483_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$484_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$485_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$486_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$487_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$488_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$489_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$490_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$491_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$492_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$493_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496'. created $dff cell `$procdff$2056' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496'. created $dff cell `$procdff$2057' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496'. created $dff cell `$procdff$2058' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$495'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'. created $dff cell `$procdff$2059' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'. created $dff cell `$procdff$2060' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'. created $dff cell `$procdff$2061' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'. created $dff cell `$procdff$2062' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'. created $dff cell `$procdff$2063' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$976'. created $dff cell `$procdff$2064' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$976'. created $dff cell `$procdff$2065' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$974'. created $dff cell `$procdff$2066' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$966'. created $dff cell `$procdff$2067' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$963'. created $dff cell `$procdff$2068' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$957'. created $dff cell `$procdff$2069' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$952'. created $dff cell `$procdff$2070' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$952'. created $dff cell `$procdff$2071' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$938'. created $dff cell `$procdff$2072' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$925'. created $dff cell `$procdff$2073' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$923'. created $dff cell `$procdff$2074' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$915'. created $dff cell `$procdff$2075' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$901'. created $dff cell `$procdff$2076' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$895'. created $dff cell `$procdff$2077' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$895'. created $dff cell `$procdff$2078' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$684'. created $dff cell `$procdff$2079' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$684'. created $dff cell `$procdff$2080' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$684'. created $dff cell `$procdff$2081' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$684'. created $dff cell `$procdff$2082' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$684'. created $dff cell `$procdff$2083' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$684'. created $dff cell `$procdff$2084' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_ADDR' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'. created $dff cell `$procdff$2085' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_DATA' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'. created $dff cell `$procdff$2086' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'. created $dff cell `$procdff$2087' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'. created $dff cell `$procdff$2088' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_DATA' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'. created $dff cell `$procdff$2089' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'. created $dff cell `$procdff$2090' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'. created $dff cell `$procdff$2091' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_DATA' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'. created $dff cell `$procdff$2092' with positive edge clock. Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'. created $dff cell `$procdff$2093' with positive edge clock. Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$215'. created $dff cell `$procdff$2094' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\uart_tx_en' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'. created $dff cell `$procdff$2095' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_read' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'. created $dff cell `$procdff$2096' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_write' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'. created $dff cell `$procdff$2097' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_read' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'. created $dff cell `$procdff$2098' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_write' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'. created $dff cell `$procdff$2099' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\buffer_full' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'. created $dff cell `$procdff$2100' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\uart_tx_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'. created $dff cell `$procdff$2101' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_write_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'. created $dff cell `$procdff$2102' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_write_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'. created $dff cell `$procdff$2103' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$818'. created $dff cell `$procdff$2104' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$818'. created $dff cell `$procdff$2105' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'. created $dff cell `$procdff$2106' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$69_ADDR' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'. created $dff cell `$procdff$2107' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$69_DATA' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'. created $dff cell `$procdff$2108' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'. created $dff cell `$procdff$2109' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'. created $dff cell `$procdff$2110' with positive edge clock. Creating register for signal `\PC.\Output' using process `\PC.$proc$Risco-5/src/core/pc.v:15$63'. created $dff cell `$procdff$2111' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mip_mfip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$52'. created $dff cell `$procdff$2112' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mip_meip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$52'. created $dff cell `$procdff$2113' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mip_mtip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$52'. created $dff cell `$procdff$2114' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mip_msip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$52'. created $dff cell `$procdff$2115' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mcause' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$45'. created $dff cell `$procdff$2116' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mcycle' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$45'. created $dff cell `$procdff$2117' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mepc' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$45'. created $dff cell `$procdff$2118' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mie_mfie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$45'. created $dff cell `$procdff$2119' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mie_meie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$45'. created $dff cell `$procdff$2120' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mie_msie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$45'. created $dff cell `$procdff$2121' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mie_mtie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$45'. created $dff cell `$procdff$2122' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_minstret' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$45'. created $dff cell `$procdff$2123' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mscratch' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$45'. created $dff cell `$procdff$2124' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mstatus_mie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$45'. created $dff cell `$procdff$2125' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mstatus_mpie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$45'. created $dff cell `$procdff$2126' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mtvec' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$45'. created $dff cell `$procdff$2127' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mtval' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$45'. created $dff cell `$procdff$2128' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'. created $dff cell `$procdff$2129' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'. created $dff cell `$procdff$2130' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'. created $dff cell `$procdff$2131' with positive edge clock. Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$30'. created $dff cell `$procdff$2132' with positive edge clock. 22.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$603'. Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$602'. Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$602'. Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'. Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'. Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$495'. Found and cleaned up 3 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$978'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$976'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$976'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$974'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$974'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$966'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$966'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$963'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$963'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$957'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$957'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$952'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$952'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$947'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$947'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$938'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$938'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$931'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$925'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$925'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$923'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$923'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$915'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$915'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$901'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$901'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$895'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$895'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$890'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$890'. Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$687'. Found and cleaned up 2 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$684'. Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:179$684'. Found and cleaned up 1 empty switch in `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$881'. Removing empty process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$881'. Found and cleaned up 3 empty switches in `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'. Removing empty process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'. Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$218'. Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$215'. Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$215'. Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$837'. Found and cleaned up 1 empty switch in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$834'. Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$834'. Found and cleaned up 5 empty switches in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'. Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'. Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$818'. Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$818'. Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$91'. Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:22$73'. Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:22$73'. Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$66'. Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:15$63'. Removing empty process `PC.$proc$Risco-5/src/core/pc.v:15$63'. Found and cleaned up 1 empty switch in `\MUX.$proc$Risco-5/src/core/mux.v:10$62'. Removing empty process `MUX.$proc$Risco-5/src/core/mux.v:10$62'. Found and cleaned up 4 empty switches in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$60'. Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$60'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'. Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:181$58'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:181$58'. Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:172$54'. Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$52'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:158$52'. Found and cleaned up 3 empty switches in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$45'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:113$45'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$611'. Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$34'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'. Found and cleaned up 3 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$30'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$30'. Found and cleaned up 4 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'. Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'. Found and cleaned up 1 empty switch in `\Alu.$proc$Risco-5/src/core/alu.v:23$11'. Removing empty process `Alu.$proc$Risco-5/src/core/alu.v:23$11'. Cleaned up 89 empty switches. 22.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. <suppressed ~4 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. <suppressed ~21 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. <suppressed ~19 debug messages> Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. <suppressed ~4 debug messages> Optimizing module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory. <suppressed ~5 debug messages> Optimizing module LEDs. <suppressed ~3 debug messages> Optimizing module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART. <suppressed ~9 debug messages> Optimizing module GPIO. <suppressed ~3 debug messages> Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. <suppressed ~4 debug messages> Optimizing module BUS. Optimizing module Registers. <suppressed ~2 debug messages> Optimizing module PC. <suppressed ~2 debug messages> Optimizing module MUX. <suppressed ~1 debug messages> Optimizing module Immediate_Generator. <suppressed ~1 debug messages> Optimizing module CSR_Unit. <suppressed ~2 debug messages> Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. <suppressed ~7 debug messages> Optimizing module Control_Unit. <suppressed ~1 debug messages> Optimizing module ALU_Control. <suppressed ~15 debug messages> Optimizing module Alu. <suppressed ~1 debug messages> Optimizing module $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC. Optimizing module top. 22.5. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Deleting now unused module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory. Deleting now unused module LEDs. Deleting now unused module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART. Deleting now unused module GPIO. Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. Deleting now unused module BUS. Deleting now unused module Registers. Deleting now unused module PC. Deleting now unused module MUX. Deleting now unused module Immediate_Generator. Deleting now unused module CSR_Unit. Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Deleting now unused module Control_Unit. Deleting now unused module ALU_Control. Deleting now unused module Alu. Deleting now unused module $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC. <suppressed ~30 debug messages> 22.6. Executing TRIBUF pass. 22.7. Executing DEMINOUT pass (demote inout ports to input or output). 22.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~47 debug messages> 22.9. Executing OPT_CLEAN pass (remove unused cells and wires). [Pipeline] // stage [Pipeline] } Finding unused cells or wires in module \top.. Removed 64 unused cells and 728 unused wires. <suppressed ~82 debug messages> 22.10. Executing CHECK pass (checking for obvious problems). Checking module top... Warning: Wire top.\SOC.Core.PCSourceMUX.C [31] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [30] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [29] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [28] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [27] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [26] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [25] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [24] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [23] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [22] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [21] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [20] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [19] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [18] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [17] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [16] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [15] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [14] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [13] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [12] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [11] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [10] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [9] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [8] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [7] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [6] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [5] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [4] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [3] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [2] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [1] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.C [0] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [31] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [30] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [29] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [28] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [27] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [26] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [25] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [24] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [23] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [22] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [21] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [20] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [19] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [18] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [17] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [16] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [15] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [14] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [13] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [12] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [11] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [10] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [9] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [8] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [7] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [6] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [5] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [4] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [3] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [2] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [1] is used but has no driver. Warning: Wire top.\SOC.Core.PCSourceMUX.D [0] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [31] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [30] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [29] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [28] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [27] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [26] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [25] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [24] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [23] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [22] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [21] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [20] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [19] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [18] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [17] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [16] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [15] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [14] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [13] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [12] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [11] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [10] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [9] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [8] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [7] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [6] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [5] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [4] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [3] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [2] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [1] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryDataMUX.D [0] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [31] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [30] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [29] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [28] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [27] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [26] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [25] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [24] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [23] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [22] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [21] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [20] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [19] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [18] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [17] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [16] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [15] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [14] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [13] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [12] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [11] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [10] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [9] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [8] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [7] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [6] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [5] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [4] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [3] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [2] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [1] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [0] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [31] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [30] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [29] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [28] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [27] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [26] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [25] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [24] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [23] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [22] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [21] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [20] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [19] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [18] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [17] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [16] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [15] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [14] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [13] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [12] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [11] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [10] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [9] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [8] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [7] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [6] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [5] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [4] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [3] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [2] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [1] is used but has no driver. Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [0] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [15] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [14] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [13] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [12] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [11] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [10] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [9] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [8] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [7] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [6] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [5] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [4] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [3] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [2] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [1] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_fast [0] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_external is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_timer is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.irq_software is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [31] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [30] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [29] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [28] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [27] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [26] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [25] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [24] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [23] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [22] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [21] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [20] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [19] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [18] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [17] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [16] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [15] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [14] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [13] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [12] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [11] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [10] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [9] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [8] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [7] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [6] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [5] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [4] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [3] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [2] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [1] is used but has no driver. Warning: Wire top.\SOC.Core.AluInputBMUX.D [0] is used but has no driver. Found and reported 211 problems. 22.11. Executing OPT pass (performing simple optimizations). 22.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~6 debug messages> 22.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~351 debug messages> Removed a total of 117 cells. 22.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1923. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1951. dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1599. dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1601. dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1612. dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1627. dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1586. dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1586. dead port 1/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1586. dead port 2/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1586. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1546. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1552. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1558. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1564. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1343. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1345. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1352. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1354. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1361. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1363. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1370. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1372. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1379. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1381. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1388. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1390. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1396. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1402. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1408. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1414. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1420. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1426. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1432. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1438. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1444. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1010. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1016. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1022. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1010. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1016. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1022. Removed 41 multiplexer ports. <suppressed ~120 debug messages> 22.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1641: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1662_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1661_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1654_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1653_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1652_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1651_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1650_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1649_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1648_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1647_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1646_CMP $auto$opt_reduce.cc:134:opt_pmux$2189 $auto$opt_reduce.cc:134:opt_pmux$2187 $auto$opt_reduce.cc:134:opt_pmux$2185 $auto$opt_reduce.cc:134:opt_pmux$2183 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1940: { $auto$opt_reduce.cc:134:opt_pmux$2191 $flatten\SOC.\Core.\Control_Unit.$procmux$1948_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1947_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1946_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1945_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1944_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1943_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1942_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1941_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1953: { $flatten\SOC.\Core.\Control_Unit.$procmux$1969_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1952_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1924_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1966_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1958_CMP $auto$opt_reduce.cc:134:opt_pmux$2195 $auto$opt_reduce.cc:134:opt_pmux$2193 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1989: { $flatten\SOC.\Core.\ALU_Control.$procmux$1996_CMP $auto$opt_reduce.cc:134:opt_pmux$2197 $flatten\SOC.\Core.\ALU_Control.$procmux$1993_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1992_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1991_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1990_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1624: $auto$opt_reduce.cc:134:opt_pmux$2199 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1630: { $flatten\SOC.\Core.\Control_Unit.$procmux$1945_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1946_CMP $auto$opt_reduce.cc:134:opt_pmux$2203 $flatten\SOC.\Core.\Control_Unit.$procmux$1947_CMP $auto$opt_reduce.cc:134:opt_pmux$2201 $flatten\SOC.\Core.\Control_Unit.$procmux$1941_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1949_CMP } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1543: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1561: Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1567: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1340: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1340_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1340_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1340_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] $flatten\SOC.\Memory.$procmux$1340_Y [0] } New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2003: { $auto$opt_reduce.cc:134:opt_pmux$2207 $auto$opt_reduce.cc:134:opt_pmux$2205 $flatten\SOC.\Core.\ALU_Control.$procmux$1996_CMP } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1367: Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Memory.$procmux$1367_Y New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Memory.$procmux$1367_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1367_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] $flatten\SOC.\Memory.$procmux$1367_Y [0] } New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2012: { $flatten\SOC.\Core.\ALU_Control.$procmux$2014_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2013_CMP } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1394: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1394_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1394_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1394_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] $flatten\SOC.\Memory.$procmux$1394_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] New connections: $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] New connections: $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1570: Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$89, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1561_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1573: Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$88, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1543_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1412: Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$880, B=0, Y=$flatten\SOC.\Memory.$procmux$1412_Y New ports: A=$flatten\SOC.\Memory.$procmux$1367_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1412_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1412_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] $flatten\SOC.\Memory.$procmux$1412_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1430: Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$877, B=0, Y=$flatten\SOC.\Memory.$procmux$1430_Y New ports: A=$flatten\SOC.\Memory.$procmux$1340_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1430_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1430_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] $flatten\SOC.\Memory.$procmux$1430_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1465: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$867, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1394_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1025: Old ports: A=$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$806, B=8'00000000, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 New ports: A=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] New connections: $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1025: Old ports: A=$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$806, B=8'00000000, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 New ports: A=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] New connections: $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1447: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$873, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1412_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1456: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$870, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1430_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] } Optimizing cells in module \top. Performed a total of 25 changes. 22.11.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~9 debug messages> Removed a total of 3 cells. 22.11.6. Executing OPT_DFF pass (perform DFF optimizations). 22.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 3 unused cells and 169 unused wires. <suppressed ~8 debug messages> 22.11.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.11.9. Rerunning OPT passes. (Maybe there is more to do..) 22.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~119 debug messages> 22.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.11.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.11.13. Executing OPT_DFF pass (perform DFF optimizations). 22.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.11.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.11.16. Finished OPT passes. (There is nothing left to do.) 22.12. Executing FSM pass (extract and optimize FSM). 22.12.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking top.ResetBootSystem.state as FSM state register: Register has an initialization value. Circuit seems to be self-resetting. Not marking top.SOC.Core.CSR_Unit.csr_mip_mfip as FSM state register: Users of register don't seem to benefit from recoding. Register has an initialization value. Not marking top.SOC.Core.Control_Unit.state as FSM state register: Users of register don't seem to benefit from recoding. Register has an initialization value. Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state. Not marking top.SOC.Uart.i_uart_tx.fsm_state as FSM state register: Users of register don't seem to benefit from recoding. 22.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'. found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$2066 root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$940_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$955_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$968_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$954_Y found state code: 3'000 found ctrl input: \SOC.Uart.i_uart_rx.next_bit found state code: 3'011 found ctrl input: \SOC.Uart.i_uart_rx.payload_done found state code: 3'010 found state code: 3'001 found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$968_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$959_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$955_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$954_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$940_Y ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o } ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$940_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$954_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$955_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$959_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$968_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] } transition: 3'000 4'0--0 -> 3'001 8'01010001 transition: 3'000 4'1--0 -> 3'000 8'01010000 transition: 3'000 4'---1 -> 3'000 8'01010000 transition: 3'010 4'--00 -> 3'010 8'00100010 transition: 3'010 4'--10 -> 3'011 8'00100011 transition: 3'010 4'---1 -> 3'000 8'00100000 transition: 3'001 4'-0-0 -> 3'001 8'00011001 transition: 3'001 4'-1-0 -> 3'010 8'00011010 transition: 3'001 4'---1 -> 3'000 8'00011000 transition: 3'011 4'-0-0 -> 3'011 8'10010011 transition: 3'011 4'-1-0 -> 3'000 8'10010000 transition: 3'011 4'---1 -> 3'000 8'10010000 22.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2208' from module `\top'. 22.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 7 unused cells and 7 unused wires. <suppressed ~8 debug messages> 22.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2208' from module `\top'. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2]. 22.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2208' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ---1 010 -> --1- 001 -> -1-- 011 -> 1--- 22.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2208' from module `top': ------------------------------------- Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$2208 (\SOC.Uart.i_uart_rx.fsm_state): Number of input signals: 4 Number of output signals: 5 Number of state bits: 4 Input signals: 0: \ResetBootSystem.reset_o 1: \SOC.Uart.i_uart_rx.payload_done 2: \SOC.Uart.i_uart_rx.next_bit 3: \SOC.Uart.i_uart_rx.rxd_reg Output signals: 0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$968_Y 1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$959_Y 2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$955_Y 3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$954_Y 4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$940_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'1--0 -> 0 5'01010 1: 0 4'---1 -> 0 5'01010 2: 0 4'0--0 -> 2 5'01010 3: 1 4'---1 -> 0 5'00100 4: 1 4'--00 -> 1 5'00100 5: 1 4'--10 -> 3 5'00100 6: 2 4'---1 -> 0 5'00011 7: 2 4'-1-0 -> 1 5'00011 8: 2 4'-0-0 -> 2 5'00011 9: 3 4'-1-0 -> 0 5'10010 10: 3 4'---1 -> 0 5'10010 11: 3 4'-0-0 -> 3 5'10010 ------------------------------------- 22.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2208' from module `\top'. 22.13. Executing OPT pass (performing simple optimizations). 22.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5 debug messages> 22.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 22.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~118 debug messages> 22.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.13.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2078 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1291_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1285_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1276_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1267_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1258_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1249_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1231_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1240_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$2258 ($sdff) from module top (D = \SOC.Uart.uart_tx_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]). Adding EN signal on $auto$ff.cc:266:slice$2258 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1285_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1276_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1267_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1258_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1249_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1231_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1240_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2076 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1207_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$2263 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1207_Y, Q = \SOC.Uart.i_uart_tx.bit_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2075 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1196_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$2269 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$922_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2074 ($dff) from module top (D = \SOC.Uart.i_uart_tx.n_fsm_state, Q = \SOC.Uart.i_uart_tx.fsm_state, rval = 3'000). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2073 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1185_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$2274 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1185_Y, Q = \SOC.Uart.i_uart_tx.txd_reg). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2072 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1174_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$2280 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2071 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$1151_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1142_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1133_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1124_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1115_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1106_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1088_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1097_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$2282 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2069 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1070_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$2286 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$962_Y, Q = \SOC.Uart.i_uart_rx.bit_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2068 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1065_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$2290 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2067 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1057_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$2292 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$973_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2065 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2064 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1). Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$2060 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1034_Y, Q = \SOC.Uart.TX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2298 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$809_Y, Q = \SOC.Uart.TX_FIFO.write_ptr). Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$2059 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1039_Y, Q = \SOC.Uart.TX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2300 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814_Y [5:0], Q = \SOC.Uart.TX_FIFO.read_ptr). Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$2060 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1034_Y, Q = \SOC.Uart.RX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2302 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$809_Y, Q = \SOC.Uart.RX_FIFO.write_ptr). Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$2059 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1039_Y, Q = \SOC.Uart.RX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2304 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814_Y [5:0], Q = \SOC.Uart.RX_FIFO.read_ptr). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2103 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1508_Y, Q = \SOC.Uart.rx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$2306 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.uart_rx_data, Q = \SOC.Uart.rx_fifo_write_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2102 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1513_Y, Q = \SOC.Uart.tx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$2308 ($sdff) from module top (D = \SOC.Uart.write_data [7:0], Q = \SOC.Uart.tx_fifo_write_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2101 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1518_Y, Q = \SOC.Uart.uart_tx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$2310 ($sdff) from module top (D = \SOC.Uart.tx_fifo_read_data, Q = \SOC.Uart.uart_tx_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2099 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1483_Y, Q = \SOC.Uart.rx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2098 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1488_Y, Q = \SOC.Uart.rx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2097 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1493_Y, Q = \SOC.Uart.tx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$2095 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1498_Y, Q = \SOC.Uart.uart_tx_en, rval = 1'0). Adding SRST signal on $flatten\SOC.\Leds.$procdff$2094 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$1473_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$2316 ($sdff) from module top (D = { 1'0 \SOC.Leds.write_data }, Q = \SOC.Leds.data). Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2105 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1529_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2318 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_value). Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2104 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1537_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$2322 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_direction). Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$2111 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$1581_Y, Q = \SOC.Core.Pc.Output, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$2328 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.Output). Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$2132 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 4'0000). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2128 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1685_Y, Q = \SOC.Core.CSR_Unit.csr_mtval, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$2331 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mtval). Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2127 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 1'0 \SOC.Core.CSR_Unit.csr_write_data [0] }, Q = \SOC.Core.CSR_Unit.csr_mtvec). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2126 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1711_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$2340 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2125 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1728_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mie, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$2344 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mstatus_mie). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2124 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1744_Y, Q = \SOC.Core.CSR_Unit.csr_mscratch, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$2348 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mscratch). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2123 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1757_Y, Q = \SOC.Core.CSR_Unit.csr_minstret, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$2352 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1757_Y, Q = \SOC.Core.CSR_Unit.csr_minstret). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2122 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1775_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mtie, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$2356 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mie_mtie). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2121 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1793_Y, Q = \SOC.Core.CSR_Unit.csr_mie_msie, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$2360 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mie_msie). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2120 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1811_Y, Q = \SOC.Core.CSR_Unit.csr_mie_meie, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$2364 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [11], Q = \SOC.Core.CSR_Unit.csr_mie_meie). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2119 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1829_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mfie, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:266:slice$2368 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [31:16], Q = \SOC.Core.CSR_Unit.csr_mie_mfie). Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2118 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 2'00 }, Q = \SOC.Core.CSR_Unit.csr_mepc). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2117 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1852_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$2377 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1852_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2116 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1863_Y, Q = \SOC.Core.CSR_Unit.csr_mcause, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$2381 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mcause). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2115 ($dff) from module top (D = \SOC.Core.CSR_Unit.irq_software, Q = \SOC.Core.CSR_Unit.csr_mip_msip, rval = 1'0). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2114 ($dff) from module top (D = \SOC.Core.CSR_Unit.irq_timer, Q = \SOC.Core.CSR_Unit.csr_mip_mtip, rval = 1'0). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2113 ($dff) from module top (D = \SOC.Core.CSR_Unit.irq_external, Q = \SOC.Core.CSR_Unit.csr_mip_meip, rval = 1'0). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2112 ($dff) from module top (D = \SOC.Core.CSR_Unit.irq_fast, Q = \SOC.Core.CSR_Unit.csr_mip_mfip, rval = 16'0000000000000000). Adding SRST signal on $flatten\SOC.\Core.$procdff$2084 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1323_Y, Q = \SOC.Core.pc_old, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$2389 ($sdff) from module top (D = \SOC.Core.Pc.Output, Q = \SOC.Core.pc_old). Adding SRST signal on $flatten\SOC.\Core.$procdff$2083 ($dff) from module top (D = \SOC.Bus.write_data, Q = \SOC.Core.register_data_2, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$2082 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$2081 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$2080 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$2079 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1328_Y, Q = \SOC.Core.instruction_register, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$2395 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register). Adding EN signal on $flatten\ResetBootSystem.$procdff$2131 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter). Adding EN signal on $flatten\ResetBootSystem.$procdff$2130 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state). Adding EN signal on $flatten\ResetBootSystem.$procdff$2129 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o). Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2372 ($dffe) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2372 ($dffe) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2335 ($dffe) from module top. Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$2317 ($sdffe) from module top. 22.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 130 unused cells and 126 unused wires. <suppressed ~131 debug messages> 22.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5 debug messages> 22.13.9. Rerunning OPT passes. (Maybe there is more to do..) 22.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~76 debug messages> 22.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$2288: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o } Optimizing cells in module \top. Performed a total of 1 changes. 22.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~15 debug messages> Removed a total of 5 cells. 22.13.13. Executing OPT_DFF pass (perform DFF optimizations). 22.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 6 unused wires. <suppressed ~2 debug messages> 22.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.13.16. Rerunning OPT passes. (Maybe there is more to do..) 22.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~76 debug messages> 22.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.13.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.13.20. Executing OPT_DFF pass (perform DFF optimizations). 22.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.13.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.13.23. Finished OPT passes. (There is nothing left to do.) 22.14. Executing WREDUCE pass (reducing word size of cells). Removed top 28 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\Control_Unit.$auto$mem.cc:328:emit$982 ($flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2137 (SOC.Core.RegisterBank.registers). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2139 (SOC.Core.RegisterBank.registers). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$meminit$\registers$Risco-5/src/core/registers.v:16$90 (SOC.Core.RegisterBank.registers). Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2134 (SOC.Memory.memory). Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2135 (SOC.Memory.memory). Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2136 (SOC.Memory.memory). Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$882 (SOC.Memory.memory). Removed top 23 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$842 (SOC.Memory.memory). Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2133 (SOC.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$793 (SOC.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2133 (SOC.Uart.TX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\TX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$793 (SOC.Uart.TX_FIFO.memory). Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$1880_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$609 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608 ($add). Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608 ($add). Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$607 ($lt). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2403 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2408 ($ne). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:20$817 ($mux). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$1480_CMP0 ($eq). Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Uart.$procmux$1479 ($pmux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1031 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1019 ($mux). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814 ($mux). Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813 ($add). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$807 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$789 ($eq). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1031 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1019 ($mux). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814 ($mux). Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813 ($add). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$807 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$789 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$951 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$950 ($mux). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$949 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$948 ($mux). Removed top 2 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:111$943 ($eq). Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:109$941 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$917 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$909 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:135$907 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$904 ($ne). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$903 ($ne). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$899 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$894 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$893 ($mux). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$892 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$891 ($mux). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:94$887 ($eq). Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:92$885 ($eq). Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$214 ($mux). Removed top 20 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$94 ($le). Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$97 ($ge). Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$98 ($le). Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$101 ($ge). Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$102 ($le). Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$105 ($ge). Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$106 ($le). Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:75$136 ($mux). Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:84$152 ($mux). Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$166 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Memory.$procmux$1336_CMP0 ($eq). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1453 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1462 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1471 ($mux). Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:100$32 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1589_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1589_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1589_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1966_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1965_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1964_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1963_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1962_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1952_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1949_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1948_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1947_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1944_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1943_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1924_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1921 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2014_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1996_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1995_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1994_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1982 ($mux). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2027_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2026_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2025_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2024_CMP0 ($eq). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$25 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$17 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1667_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1654_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1653_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1652_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1651_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1650_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1649_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1648_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1647_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1646_CMP0 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:152$51 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:144$49 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:143$48 ($add). Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$93 ($ge). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1406 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1424 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1442 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1358 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1385 ($mux). Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:80$144 ($mux). Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608_Y. Removed top 24 bits (of 32) from wire top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$166_Y. Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0]. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$17_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$25_Y. Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\Control_Unit.$3\nextstate[3:0]. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_ADDR[31:0]$845. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$848. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$851. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_ADDR[31:0]$865. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$868. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$871. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$875. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$878. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$795. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$804. Removed top 1 bits (of 8) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_DATA[7:0]$805. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813_Y. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814_Y. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$795. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$804. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813_Y. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$948_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$949_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$950_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$951_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$891_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$892_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$893_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$894_Y. 22.15. Executing PEEPOPT pass (run peephole optimizers). 22.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 33 unused wires. <suppressed ~1 debug messages> 22.17. Executing SHARE pass (SAT-based resource sharing). Found 4 cells in module top that may be considered for resource sharing. Analyzing resource sharing options for $flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$793 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:57$103_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:55$99_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$95_Y $flatten\SOC.\Uart.$procmux$1482_CMP $flatten\SOC.\Uart.$procmux$1481_CMP $flatten\SOC.\Uart.$procmux$1480_CMP }. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$842 ($memrd): Found 5 activation_patterns using ctrl signal { $flatten\SOC.\Memory.$procmux$1337_CMP $flatten\SOC.\Memory.$procmux$1336_CMP \SOC.Memory.option $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$95_Y \SOC.Bus.slave_0_write \SOC.Bus.slave_0_read }. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:44$23 ($shr): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2019_CMP. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:42$22 ($shl): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2020_CMP. No candidates found. 22.18. Executing TECHMAP pass (map to technology primitives). 22.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 22.18.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~296 debug messages> 22.19. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.20. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.21. Executing TECHMAP pass (map to technology primitives). 22.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 22.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation. Generating RTLIL representation for module `\$__MUL18X18'. Successfully finished Verilog frontend. 22.21.3. Continuing TECHMAP pass. No more expansions possible. <suppressed ~5 debug messages> 22.22. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608 ($add). creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14 ($add). creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15 ($sub). creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:141$46 ($add). creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:142$47 ($add). creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:143$48 ($add). creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:144$49 ($add). creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:151$50 ($add). creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:152$51 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$962 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$973 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$911 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$922 ($add). creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$922. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$911. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$973. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$962. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786. creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:152$51. creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:151$50. creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:144$49. creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:143$48. creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:142$47. creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:141$46. creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15. creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14. creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608. creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$607 ($lt): new $alu creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$93 ($ge): new $alu creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$97 ($ge): new $alu creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$101 ($ge): new $alu creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$105 ($ge): new $alu creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$94 ($le): new $alu creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$98 ($le): new $alu creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$102 ($le): new $alu creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$106 ($le): new $alu creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24 ($ge): new $alu creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$16 ($lt): merged with $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24. creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$609 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$607. creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21 ($eq): merged with $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24. creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$106: $auto$alumacc.cc:485:replace_alu$2466 creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$102: $auto$alumacc.cc:485:replace_alu$2479 creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$98: $auto$alumacc.cc:485:replace_alu$2492 creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$94: $auto$alumacc.cc:485:replace_alu$2505 creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$105: $auto$alumacc.cc:485:replace_alu$2518 creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$101: $auto$alumacc.cc:485:replace_alu$2527 creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$97: $auto$alumacc.cc:485:replace_alu$2536 creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$93: $auto$alumacc.cc:485:replace_alu$2545 creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$607, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$609: $auto$alumacc.cc:485:replace_alu$2554 creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608: $auto$alumacc.cc:485:replace_alu$2565 creating $alu cell for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$16, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21: $auto$alumacc.cc:485:replace_alu$2568 creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14: $auto$alumacc.cc:485:replace_alu$2581 creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15: $auto$alumacc.cc:485:replace_alu$2584 creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:141$46: $auto$alumacc.cc:485:replace_alu$2587 creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:142$47: $auto$alumacc.cc:485:replace_alu$2590 creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:143$48: $auto$alumacc.cc:485:replace_alu$2593 creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:144$49: $auto$alumacc.cc:485:replace_alu$2596 creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:151$50: $auto$alumacc.cc:485:replace_alu$2599 creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:152$51: $auto$alumacc.cc:485:replace_alu$2602 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808: $auto$alumacc.cc:485:replace_alu$2605 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786: $auto$alumacc.cc:485:replace_alu$2608 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813: $auto$alumacc.cc:485:replace_alu$2611 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808: $auto$alumacc.cc:485:replace_alu$2614 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786: $auto$alumacc.cc:485:replace_alu$2617 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813: $auto$alumacc.cc:485:replace_alu$2620 creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$962: $auto$alumacc.cc:485:replace_alu$2623 creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$973: $auto$alumacc.cc:485:replace_alu$2626 creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$911: $auto$alumacc.cc:485:replace_alu$2629 creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$922: $auto$alumacc.cc:485:replace_alu$2632 created 29 $alu and 0 $macc cells. 22.23. Executing OPT pass (performing simple optimizations). 22.23.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~3 debug messages> 22.23.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~10 debug messages> Removed a total of 2 cells. 22.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~76 debug messages> 22.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.23.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.23.6. Executing OPT_DFF pass (perform DFF optimizations). 22.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 20 unused wires. <suppressed ~2 debug messages> 22.23.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.23.9. Rerunning OPT passes. (Maybe there is more to do..) 22.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~76 debug messages> 22.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.23.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.23.13. Executing OPT_DFF pass (perform DFF optimizations). 22.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.23.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.23.16. Finished OPT passes. (There is nothing left to do.) 22.24. Executing MEMORY pass. 22.24.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 22.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 22.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing top.SOC.Core.RegisterBank.registers write port 0. Analyzing top.SOC.Core.RegisterBank.registers write port 1. Analyzing top.SOC.Core.RegisterBank.registers write port 2. Analyzing top.SOC.Memory.memory write port 0. Analyzing top.SOC.Memory.memory write port 1. Analyzing top.SOC.Memory.memory write port 2. Analyzing top.SOC.Uart.RX_FIFO.memory write port 0. Analyzing top.SOC.Uart.TX_FIFO.memory write port 0. 22.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 22.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980'[0] in module `\top': no output FF found. Checking read port `\SOC.Core.RegisterBank.registers'[0] in module `\top': no output FF found. Checking read port `\SOC.Core.RegisterBank.registers'[1] in module `\top': merging output FF to cell. Write port 0: don't care on collision. Write port 1: non-transparent. Write port 2: non-transparent. Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found. Checking read port `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': no output FF found. Checking read port `\SOC.Uart.TX_FIFO.memory'[0] in module `\top': merging output FF to cell. Write port 0: non-transparent. Checking read port address `$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980'[0] in module `\top': address FF has fully-defined init value, not supported. Checking read port address `\SOC.Core.RegisterBank.registers'[0] in module `\top': address FF has fully-defined init value, not supported. Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found. Checking read port address `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': merged address FF to cell. 22.24.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 44 unused wires. <suppressed ~7 debug messages> 22.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating read ports of memory top.SOC.Core.RegisterBank.registers by address: Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address: Merging ports 0, 2 (address 5'00000). Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address: Consolidating write ports of memory top.SOC.Memory.memory by address: Merging ports 0, 1 (address \SOC.Memory.address [10:2]). Merging ports 0, 2 (address \SOC.Memory.address [10:2]). Consolidating write ports of memory top.SOC.Core.RegisterBank.registers using sat-based resource sharing: Checking group clocked with posedge \clk, width 32: ports 0, 1. Common input cone for all EN signals: 6 cells. Size of unconstrained SAT problem: 40 variables, 98 clauses Merging port 1 into port 0. 22.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 22.24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 8 unused cells and 8 unused wires. <suppressed ~9 debug messages> 22.24.10. Executing MEMORY_COLLECT pass (generating $mem cells). 22.25. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.26. Executing MEMORY_LIBMAP pass (mapping memories to cells). using FF mapping for memory top.$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980 mapping memory top.SOC.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_ Extracted data FF from read port 1 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[1] mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_ mapping memory top.SOC.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted addr FF from read port 0 of top.SOC.Uart.RX_FIFO.memory: $\SOC.Uart.RX_FIFO.memory$rdreg[0] mapping memory top.SOC.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of top.SOC.Uart.TX_FIFO.memory: $\SOC.Uart.TX_FIFO.memory$rdreg[0] <suppressed ~1100 debug messages> 22.27. Executing TECHMAP pass (map to technology primitives). 22.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation. Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 22.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ECP5_DP16KD_'. Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'. Successfully finished Verilog frontend. 22.27.3. Continuing TECHMAP pass. Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$1f7528d846def63a25ef79a14688e75507487b07\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$16483afc93766dfb5fb1eddfd226d96b3663d59c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$aaadea22aebcd84c93bb9858adaa720cf09b082d\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$4732e8e929fe8d0a57a6c959ddfc52773439ff42\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$5b36af983a34dea819263d47bd985c03f062c03b\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$5f84a8dd211265fde0680d1329e0aeb011857798\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$65b5a9049f0a0f5b9de58368be8ce2821f51e438\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$5a90b288fb430e0f24af5f61ee43ef935b86341e\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$58ddad20e9ef77e6675ec0a973f6df52cac15605\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$569f3b21b6212e6a0e436dd55c34df99d3696e0b\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$c21745a1d1b8202233eb4fd671436aaa3b71d7e7\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$eabd6f8a46e61d81805337b1dc746bfd80802602\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$98f4fff52781fee114365d416fa097fc5bdcc5a1\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$ef9fccd6f2ebbfd2f9ea51ad76fcd229dd950af9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$f05333f47f0fac035d1d00a83ba1f91fba94d570\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$e060b64551c3d3977f3359c6d9cbc2f183f778aa\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$5e6f6332f5b0abb114a71354918e4077127fc51f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$04114c6daf9b714920df2338bb84f1d824cfb28f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$df0229c2445eb19cad504fc663c8894a4b8ad2c2\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$82cf4a0fd82546fec0e453cb163e0b57b514e109\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$05123d0bc673513b0e5ab3de2414f4ca493424ef\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$3d62e89fd9fe82123196169686b7825d33b36c84\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$413228b6beffb528da7ce6c18481e68814727c46\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$74d116fba5fc319cbe4b4ef6fabb137b2ff9e708\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. No more expansions possible. <suppressed ~635 debug messages> 22.28. Executing OPT pass (performing simple optimizations). 22.28.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~142 debug messages> 22.28.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~21 debug messages> Removed a total of 7 cells. 22.28.3. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $\SOC.Uart.RX_FIFO.memory$rdreg[0] ($dff) from module top (D = $auto$rtlil.cc:2582:Mux$2686, Q = $\SOC.Uart.RX_FIFO.memory$rdreg[0]$q, rval = 3'000). Adding SRST signal on $auto$ff.cc:266:slice$2397 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$1877_Y, Q = \ResetBootSystem.counter, rval = 6'000000). Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2385 ($sdff) from module top. Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2388 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2388 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2388 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$2388 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$2388 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$2388 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$2388 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$2388 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$2388 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$2388 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$2388 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$2388 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$2388 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$2388 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$2388 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$2388 ($sdff) from module top. 22.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 20 unused cells and 2124 unused wires. <suppressed ~21 debug messages> 22.28.5. Rerunning OPT passes. (Removed registers in this run.) 22.28.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~2 debug messages> 22.28.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.28.8. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$3501 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$2423 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000). 22.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 3 unused cells and 3 unused wires. <suppressed ~4 debug messages> 22.28.10. Rerunning OPT passes. (Removed registers in this run.) 22.28.11. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.28.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.28.13. Executing OPT_DFF pass (perform DFF optimizations). 22.28.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.28.15. Finished fast OPT passes. 22.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). Mapping memory $flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980 in module \top: created 16 $dff cells and 0 static cells of width 18. read interface: 0 $dff and 15 $mux cells. write interface: 0 write mux blocks. 22.30. Executing OPT pass (performing simple optimizations). 22.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$2708: $auto$rtlil.cc:2489:ReduceOr$2702 -> 1'1 Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~59 debug messages> 22.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][6]$3546: Old ports: A=18'010000010000000000, B=18'010000011000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$3526 New ports: A=1'0, B=1'1, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$3526 [9] New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$3526 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$3526 [8:0] } = 17'01000001000000000 Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][5]$3543: Old ports: A=18'000000001010100100, B=18'101000010000000101, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3524 New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3524 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3524 [0] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3524 [17:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3524 [4:1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3524 [0] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3524 [0] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3524 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3524 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3524 [5] 5'00010 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][4]$3540: Old ports: A=18'010000001100000001, B=18'101000010000000100, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3523 New ports: A=2'01, B=2'10, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3523 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3523 [0] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3523 [17:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3523 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3523 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3523 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3523 [2] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3523 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3523 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3523 [0] 6'000000 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][3]$3537: Old ports: A=18'000000001100000000, B=18'000000000000001000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3521 New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3521 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3521 [3] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3521 [17:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3521 [7:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3521 [2:0] } = { 8'00000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3521 [8] 7'0000000 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][2]$3534: Old ports: A=18'000000100000001000, B=18'000000000000010010, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3520 New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3520 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3520 [1] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3520 [17:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3520 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3520 [0] } = { 6'000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3520 [3] 6'000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3520 [1] 2'00 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][1]$3531: Old ports: A=18'010000001000000000, B=18'000010000000000010, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3518 New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3518 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3518 [1] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3518 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3518 [8:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3518 [0] } = { 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3518 [9] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3518 [1] 11'00000000000 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][0]$3528: Old ports: A=18'101110000000000000, B=18'010000010000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3517 New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3517 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3517 [10] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3517 [17:14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3517 [12:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3517 [9:0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3517 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3517 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3517 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3517 [13] 12'000000000000 } Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$2693: Old ports: A={ \SOC.Memory.buffer [31:16] \SOC.Memory.write_data [15:0] }, B=\SOC.Memory.write_data, Y=$auto$rtlil.cc:2582:Mux$2694 New ports: A=\SOC.Memory.buffer [31:16], B=\SOC.Memory.write_data [31:16], Y=$auto$rtlil.cc:2582:Mux$2694 [31:16] New connections: $auto$rtlil.cc:2582:Mux$2694 [15:0] = \SOC.Memory.write_data [15:0] New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$1886: { $flatten\ResetBootSystem.$procmux$1881_CMP $flatten\ResetBootSystem.$procmux$1880_CMP } Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1889: Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$1889_Y New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$1889_Y [1] New connections: $flatten\ResetBootSystem.$procmux$1889_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1982: Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$2425 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$2425 [2] New connections: $auto$wreduce.cc:461:run$2425 [1:0] = 2'10 Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2003: Old ports: A=4'0110, B=12'101101111110, Y=$flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] New ports: A=3'010, B=9'101011110, Y={ $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [3:2] $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [0] } New connections: $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [1] = 1'1 New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1641: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1662_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1661_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1654_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1653_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1652_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1651_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1650_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1649_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1648_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1647_CMP $auto$opt_reduce.cc:134:opt_pmux$2189 $auto$opt_reduce.cc:134:opt_pmux$2187 $auto$opt_reduce.cc:134:opt_pmux$2185 $auto$opt_reduce.cc:134:opt_pmux$2183 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][7]$3549: Old ports: A=18'010000001000000000, B=18'000001000001001000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3527 New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3527 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3527 [3] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3527 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3527 [8:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3527 [2:0] } = { 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3527 [9] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3527 [3] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3527 [3] 5'00000 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1921: Old ports: A=3'101, B=3'011, Y=$auto$wreduce.cc:461:run$2429 [2:0] New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$2429 [2:1] New connections: $auto$wreduce.cc:461:run$2429 [0] = 1'1 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1597: Old ports: A={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] }, B={ 27'000000000000000000000000000 \SOC.Core.instruction_register [24:20] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] New ports: A=\SOC.Core.instruction_register [24], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] New connections: { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [31:6] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] \SOC.Core.instruction_register [24:20] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1624: Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, B={ 19'0000000000000000000 \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] New ports: A=\SOC.Core.instruction_register [31], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] New connections: { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [31:14] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 } Consolidated identical input bits for $pmux cell $flatten\SOC.\Memory.$procmux$1335: Old ports: A=\SOC.Memory.buffer, B={ 24'000000000000000000000000 \SOC.Memory.buffer [7:0] 16'0000000000000000 \SOC.Memory.buffer [15:0] }, Y=\SOC.Bus.slave_0_read_data New ports: A=\SOC.Memory.buffer [31:8], B={ 40'0000000000000000000000000000000000000000 \SOC.Memory.buffer [15:8] }, Y=\SOC.Bus.slave_0_read_data [31:8] New connections: \SOC.Bus.slave_0_read_data [7:0] = \SOC.Memory.buffer [7:0] Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_rx.$procmux$1169: Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$2447 [0] 1'0 $auto$wreduce.cc:461:run$2448 [1:0] 2'01 \SOC.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$2450 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$2447 [0] $auto$wreduce.cc:461:run$2448 [1:0] 1'1 \SOC.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$2450 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state [1:0] New connections: \SOC.Uart.i_uart_rx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$951: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2450 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2450 [0] New connections: $auto$wreduce.cc:461:run$2450 [1] = $auto$wreduce.cc:461:run$2450 [0] Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$1306: Old ports: A=3'000, B={ 2'00 \SOC.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$2452 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$2454 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state New ports: A=2'00, B={ 1'0 \SOC.Uart.uart_tx_en $auto$wreduce.cc:461:run$2452 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$2454 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0] New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$894: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2454 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2454 [0] New connections: $auto$wreduce.cc:461:run$2454 [1] = $auto$wreduce.cc:461:run$2454 [0] Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$3525: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$3526, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3527, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3515 New ports: A={ 2'11 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$3526 [9] 1'0 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3527 [9] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3527 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3527 [3] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3515 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3515 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3515 [3] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3515 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3515 [15:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3515 [8:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3515 [2:0] } = { 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3515 [3] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3515 [3] 5'00000 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$3522: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3523, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3524, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3523 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3523 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3523 [0] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3523 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3523 [0] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3524 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3524 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3524 [5] 1'1 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3524 [0] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [0] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [17:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [7:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [4:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [10] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [5] 4'0000 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$3519: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3520, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3521, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3520 [3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3520 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3520 [1] }, B={ 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3521 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3521 [3] 1'0 }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 [11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 [1] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 [17:12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 [7:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 [0] } = { 7'0000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 [8] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 [1] 2'00 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$3516: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3517, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3518, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3511 New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3517 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3517 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3517 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3517 [10] 2'00 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3518 [9] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3518 [1] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3518 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3518 [1] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3511 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3511 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3511 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3511 [1] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3511 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3511 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3511 [12:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3511 [8:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3511 [0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3511 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3511 [14] 10'0000000000 } Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$2697: Old ports: A=$auto$rtlil.cc:2582:Mux$2694, B={ \SOC.Memory.buffer [31:8] \SOC.Memory.write_data [7:0] }, Y=$auto$rtlil.cc:2582:Mux$2698 New ports: A={ $auto$rtlil.cc:2582:Mux$2694 [31:16] \SOC.Memory.write_data [15:8] }, B=\SOC.Memory.buffer [31:8], Y=$auto$rtlil.cc:2582:Mux$2698 [31:8] New connections: $auto$rtlil.cc:2582:Mux$2698 [7:0] = \SOC.Memory.write_data [7:0] Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1895: Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$1889_Y, Y=$flatten\ResetBootSystem.$procmux$1895_Y New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$1889_Y [1], Y=$flatten\ResetBootSystem.$procmux$1895_Y [1] New connections: $flatten\ResetBootSystem.$procmux$1895_Y [0] = 1'0 Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1608: Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:20] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] 20'00000000000000000000 \SOC.Core.instruction_register [31:20] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] New ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:25] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] 1'0 \SOC.Core.instruction_register [31:25] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12:5] New connections: { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [31:13] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] \SOC.Core.instruction_register [24:20] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$3513: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3515, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3514 [0] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3515 [16] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3515 [10:9] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3515 [3] 2'00 }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [16:15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [3:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [0] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [14:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [7:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [15] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [3] 2'00 } Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$3510: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3511, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3511 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3511 [14:13] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3511 [10:9] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3511 [1] }, B={ 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 [11] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 [1] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3512 [1] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [11:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [4:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [1] } New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [7:5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [14] 6'000000 } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$3507: Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509, Y={ \SOC.Core.pc_write \SOC.Core.AluInputBMUX.option \SOC.Core.Control_Unit.ir_write \SOC.Bus.read \SOC.Core.MemoryDataMUX.option \SOC.Core.AluInputAMUX.option \SOC.Core.ALU_Control.aluop_in \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond \SOC.Bus.write \SOC.Core.Control_Unit.reg_write \SOC.Core.PCSourceMUX.option [0] \SOC.Core.MemoryAddressMUX.option [0] \SOC.Core.ALU_Control.is_immediate } New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [11:8] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [4:3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3508 [1] 1'0 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [16:15] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [3:2] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3509 [0] }, Y={ \SOC.Core.AluInputBMUX.option \SOC.Core.Control_Unit.ir_write \SOC.Bus.read \SOC.Core.MemoryDataMUX.option [0] \SOC.Core.AluInputAMUX.option \SOC.Core.ALU_Control.aluop_in [1] \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond \SOC.Bus.write \SOC.Core.Control_Unit.reg_write \SOC.Core.PCSourceMUX.option [0] \SOC.Core.MemoryAddressMUX.option [0] \SOC.Core.ALU_Control.is_immediate } New connections: { \SOC.Core.pc_write \SOC.Core.MemoryDataMUX.option [1] \SOC.Core.ALU_Control.aluop_in [0] } = { \SOC.Core.AluInputBMUX.option [0] \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond } Optimizing cells in module \top. Performed a total of 34 changes. 22.30.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~15 debug messages> Removed a total of 5 cells. 22.30.6. Executing OPT_DFF pass (perform DFF optimizations). 22.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 22 unused wires. <suppressed ~2 debug messages> 22.30.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~1 debug messages> 22.30.9. Rerunning OPT passes. (Maybe there is more to do..) 22.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~62 debug messages> 22.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.30.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.30.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2273 ($sdff) from module top. 22.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.30.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~2 debug messages> 22.30.16. Rerunning OPT passes. (Maybe there is more to do..) 22.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~62 debug messages> 22.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.30.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.30.20. Executing OPT_DFF pass (perform DFF optimizations). 22.30.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.30.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.30.23. Finished OPT passes. (There is nothing left to do.) 22.31. Executing TECHMAP pass (map to technology primitives). 22.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 22.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ecp5_alu'. Successfully finished Verilog frontend. 22.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $sdffce. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $dffe. Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $logic_not. Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu. Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux. Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux. Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux. Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $sdffe. Using template $paramod$3111a1a8e90c88cc8c163ba5aed0203d96ddc46d\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $bmux. Using extmapper simplemap for cells of type $tribuf. Using extmapper simplemap for cells of type $logic_and. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_or. Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux. Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu. Using template $paramod$41ef080258eed1ff8fcfbb7776f540ab469a3d7b\_80_ecp5_alu for cells of type $alu. Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu. Using template $paramod$c4ef20b21801b37ea2d65c32a05dfe56e84a870d\_80_ecp5_alu for cells of type $alu. Using template $paramod$2407ada40cc3dda6c6015be2b49b748cddb5a800\_90_demux for cells of type $demux. Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux. Using template $paramod$f1fc4bc1d42e857fca43ce0fdd0da6ff25c612c4\_90_pmux for cells of type $pmux. Using template $paramod$4d45682f6d5f8751d24fc75184ef72226da353f7\_90_pmux for cells of type $pmux. Using template $paramod$a13703aa027da371a1931fc542d213d7de559b19\_90_pmux for cells of type $pmux. Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux. Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $dlatch. Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$56955d0f36f77738c952d3505dc563df3ee11b94\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr. Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod$a5f0941832cc861549e29ccafffe20bfdf2e5528\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $xor. Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu. Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux. Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux. Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux. No more expansions possible. <suppressed ~4252 debug messages> 22.32. Executing OPT pass (performing simple optimizations). 22.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~6087 debug messages> 22.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~4107 debug messages> Removed a total of 1369 cells. 22.32.3. Executing OPT_DFF pass (perform DFF optimizations). 22.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 758 unused cells and 4043 unused wires. <suppressed ~759 debug messages> 22.32.5. Finished fast OPT passes. 22.33. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 22.35. Executing TECHMAP pass (map to technology primitives). 22.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 22.35.2. Continuing TECHMAP pass. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_. Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_. No more expansions possible. <suppressed ~817 debug messages> 22.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~31 debug messages> 22.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 22.38. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in top. 22.39. Executing ATTRMVCP pass (move or copy attributes). 22.40. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 3995 unused wires. <suppressed ~1 debug messages> 22.41. Executing TECHMAP pass (map to technology primitives). 22.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 22.41.2. Continuing TECHMAP pass. 22.41.3. Executing SIMPLEMAP pass (map simple cells to gate primitives). Mapping \$_DLATCH_N_.$ternary$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$22281 ($mux). Mapping \$_DLATCH_N_.$logic_not$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$22280 ($logic_not). <suppressed ~4 debug messages> 22.41.4. Executing OPT pass (performing simple optimizations). 22.41.4.1. Executing OPT_EXPR pass (perform const folding). Optimizing module \$_DLATCH_N_. <suppressed ~1 debug messages> 22.41.4.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\$_DLATCH_N_'. Removed a total of 0 cells. 22.41.4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \$_DLATCH_N_.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 22.41.4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \$_DLATCH_N_. Performed a total of 0 changes. 22.41.4.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\$_DLATCH_N_'. Removed a total of 0 cells. 22.41.4.6. Executing OPT_DFF pass (perform DFF optimizations). 22.41.4.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \$_DLATCH_N_.. Removed 1 unused cells and 2 unused wires. <suppressed ~2 debug messages> 22.41.4.8. Executing OPT_EXPR pass (perform const folding). Optimizing module \$_DLATCH_N_. 22.41.4.9. Rerunning OPT passes. (Maybe there is more to do..) 22.41.4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \$_DLATCH_N_.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 22.41.4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \$_DLATCH_N_. Performed a total of 0 changes. 22.41.4.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\$_DLATCH_N_'. Removed a total of 0 cells. 22.41.4.13. Executing OPT_DFF pass (perform DFF optimizations). 22.41.4.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \$_DLATCH_N_.. 22.41.4.15. Executing OPT_EXPR pass (perform const folding). Optimizing module \$_DLATCH_N_. 22.41.4.16. Finished OPT passes. (There is nothing left to do.) Using template \$_DLATCH_N_ for cells of type $_DLATCH_N_. No more expansions possible. <suppressed ~4 debug messages> 22.42. Executing ABC9 pass. 22.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.3. Executing PROC pass (convert processes to netlists). 22.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22385'. Cleaned up 1 empty switch. 22.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22386 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.3.4. Executing PROC_INIT pass (extract init attributes). 22.42.3.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22386'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22384_EN[3:0]$22390 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22384_DATA[3:0]$22392 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22384_ADDR[3:0]$22391 Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22385'. 22.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22379_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22375_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22369_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22382_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22370_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22374_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22381_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22377_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22371_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22380_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22376_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22372_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22383_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22378_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22373_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22368_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22384_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22386'. created $dff cell `$procdff$22436' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22384_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22386'. created $dff cell `$procdff$22437' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22384_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22386'. created $dff cell `$procdff$22438' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22385'. created direct connection (no actual register cell created). 22.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22410'. Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22386'. Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22385'. Cleaned up 1 empty switch. 22.42.3.12. Executing OPT_EXPR pass (perform const folding). 22.42.4. Executing PROC pass (convert processes to netlists). 22.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22456'. Cleaned up 1 empty switch. 22.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22457 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.4.4. Executing PROC_INIT pass (extract init attributes). 22.42.4.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22457'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22455_EN[3:0]$22461 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22455_DATA[3:0]$22463 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22455_ADDR[3:0]$22462 Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22456'. 22.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22447_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22442_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22448_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22444_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22453_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22452_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22440_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22449_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22445_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22450_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22454_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22443_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22451_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22446_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22441_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22439_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22455_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22457'. created $dff cell `$procdff$22507' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22455_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22457'. created $dff cell `$procdff$22508' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22455_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22457'. created $dff cell `$procdff$22509' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22456'. created direct connection (no actual register cell created). 22.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22481'. Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22457'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22456'. Cleaned up 1 empty switch. 22.42.4.12. Executing OPT_EXPR pass (perform const folding). 22.42.5. Executing PROC pass (convert processes to netlists). 22.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22527'. Cleaned up 1 empty switch. 22.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22528 in module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.5.4. Executing PROC_INIT pass (extract init attributes). 22.42.5.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.5.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. Creating decoders for process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22528'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22526_EN[3:0]$22533 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22526_DATA[3:0]$22534 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22526_ADDR[3:0]$22532 Creating decoders for process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22527'. 22.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.\i' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22510_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22515_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22516_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22512_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22521_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22520_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22513_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22517_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22525_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22522_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22523_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22518_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22511_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22524_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22519_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22514_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. created direct connection (no actual register cell created). Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22526_ADDR' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22528'. created $dff cell `$procdff$22578' with positive edge clock. Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22526_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22528'. created $dff cell `$procdff$22579' with positive edge clock. Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22526_DATA' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22528'. created $dff cell `$procdff$22580' with positive edge clock. Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.\muxwre' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22527'. created direct connection (no actual register cell created). 22.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22552'. Found and cleaned up 1 empty switch in `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22528'. Removing empty process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22527'. Cleaned up 1 empty switch. 22.42.5.12. Executing OPT_EXPR pass (perform const folding). 22.42.6. Executing PROC pass (convert processes to netlists). 22.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22598'. Cleaned up 1 empty switch. 22.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22599 in module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.6.4. Executing PROC_INIT pass (extract init attributes). 22.42.6.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.6.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. Creating decoders for process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22599'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22597_EN[3:0]$22603 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22597_DATA[3:0]$22605 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22597_ADDR[3:0]$22604 Creating decoders for process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22598'. 22.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.\i' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22581_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22582_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22587_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22588_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22593_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22594_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22585_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22595_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22591_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22596_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22590_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22584_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22583_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22589_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22592_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22586_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22597_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22599'. created $dff cell `$procdff$22649' with positive edge clock. Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22597_ADDR' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22599'. created $dff cell `$procdff$22650' with positive edge clock. Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22597_DATA' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22599'. created $dff cell `$procdff$22651' with positive edge clock. Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22598'. created direct connection (no actual register cell created). 22.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22623'. Found and cleaned up 1 empty switch in `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22599'. Removing empty process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22598'. Cleaned up 1 empty switch. 22.42.6.12. Executing OPT_EXPR pass (perform const folding). 22.42.7. Executing PROC pass (convert processes to netlists). 22.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22669'. Cleaned up 1 empty switch. 22.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22670 in module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.7.4. Executing PROC_INIT pass (extract init attributes). 22.42.7.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.7.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. Creating decoders for process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22670'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22668_EN[3:0]$22674 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22668_DATA[3:0]$22675 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22668_ADDR[3:0]$22676 Creating decoders for process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22669'. 22.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.\i' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22652_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22653_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22658_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22659_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22664_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22663_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22654_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22655_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22660_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22661_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22666_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22667_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22657_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22665_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22662_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22656_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22668_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22670'. created $dff cell `$procdff$22720' with positive edge clock. Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22668_DATA' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22670'. created $dff cell `$procdff$22721' with positive edge clock. Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22668_ADDR' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22670'. created $dff cell `$procdff$22722' with positive edge clock. Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22669'. created direct connection (no actual register cell created). 22.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22694'. Found and cleaned up 1 empty switch in `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22670'. Removing empty process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22669'. Cleaned up 1 empty switch. 22.42.7.12. Executing OPT_EXPR pass (perform const folding). 22.42.8. Executing PROC pass (convert processes to netlists). 22.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22740'. Cleaned up 1 empty switch. 22.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22741 in module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.8.4. Executing PROC_INIT pass (extract init attributes). 22.42.8.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.8.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. Creating decoders for process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22741'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22739_EN[3:0]$22745 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22739_DATA[3:0]$22746 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22739_ADDR[3:0]$22747 Creating decoders for process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22740'. 22.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.\i' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22723_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22728_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22727_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22735_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22729_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22736_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22737_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22734_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22733_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22724_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22725_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22730_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22731_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22738_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22732_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22726_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. created direct connection (no actual register cell created). Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22739_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22741'. created $dff cell `$procdff$22791' with positive edge clock. Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22739_DATA' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22741'. created $dff cell `$procdff$22792' with positive edge clock. Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22739_ADDR' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22741'. created $dff cell `$procdff$22793' with positive edge clock. Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.\muxwre' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22740'. created direct connection (no actual register cell created). 22.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22765'. Found and cleaned up 1 empty switch in `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22741'. Removing empty process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22740'. Cleaned up 1 empty switch. 22.42.8.12. Executing OPT_EXPR pass (perform const folding). 22.42.9. Executing PROC pass (convert processes to netlists). 22.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22811'. Cleaned up 1 empty switch. 22.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22812 in module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.9.4. Executing PROC_INIT pass (extract init attributes). 22.42.9.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.9.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. Creating decoders for process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22812'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22810_EN[3:0]$22818 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22810_DATA[3:0]$22817 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22810_ADDR[3:0]$22816 Creating decoders for process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22811'. 22.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.\i' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22797_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22798_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22799_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22803_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22804_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22805_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22809_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22795_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22800_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22801_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22806_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22807_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22808_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22802_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22796_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22794_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. created direct connection (no actual register cell created). Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22810_ADDR' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22812'. created $dff cell `$procdff$22862' with positive edge clock. Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22810_DATA' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22812'. created $dff cell `$procdff$22863' with positive edge clock. Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22810_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22812'. created $dff cell `$procdff$22864' with positive edge clock. Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.\muxwre' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22811'. created direct connection (no actual register cell created). 22.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22836'. Found and cleaned up 1 empty switch in `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22812'. Removing empty process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22811'. Cleaned up 1 empty switch. 22.42.9.12. Executing OPT_EXPR pass (perform const folding). 22.42.10. Executing PROC pass (convert processes to netlists). 22.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22882'. Cleaned up 1 empty switch. 22.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22883 in module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.10.4. Executing PROC_INIT pass (extract init attributes). 22.42.10.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.10.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. Creating decoders for process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22883'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22881_EN[3:0]$22888 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22881_DATA[3:0]$22887 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22881_ADDR[3:0]$22889 Creating decoders for process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22882'. 22.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.\i' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22873_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22874_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22875_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22865_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22880_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22867_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22868_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22869_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22871_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22876_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22877_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22879_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22870_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22878_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22872_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22866_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. created direct connection (no actual register cell created). Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22881_DATA' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22883'. created $dff cell `$procdff$22933' with positive edge clock. Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22881_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22883'. created $dff cell `$procdff$22934' with positive edge clock. Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22881_ADDR' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22883'. created $dff cell `$procdff$22935' with positive edge clock. Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.\muxwre' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22882'. created direct connection (no actual register cell created). 22.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22907'. Found and cleaned up 1 empty switch in `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22883'. Removing empty process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22882'. Cleaned up 1 empty switch. 22.42.10.12. Executing OPT_EXPR pass (perform const folding). 22.42.11. Executing PROC pass (convert processes to netlists). 22.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22953'. Cleaned up 1 empty switch. 22.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22954 in module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.11.4. Executing PROC_INIT pass (extract init attributes). 22.42.11.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.11.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. Creating decoders for process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22954'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22952_EN[3:0]$22960 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22952_DATA[3:0]$22958 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22952_ADDR[3:0]$22959 Creating decoders for process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22953'. 22.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.\i' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22947_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22951_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22940_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22950_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22949_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22945_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22944_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22938_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22937_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22936_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22941_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22939_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22943_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22946_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22948_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22942_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. created direct connection (no actual register cell created). Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22952_DATA' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22954'. created $dff cell `$procdff$23004' with positive edge clock. Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22952_ADDR' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22954'. created $dff cell `$procdff$23005' with positive edge clock. Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22952_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22954'. created $dff cell `$procdff$23006' with positive edge clock. Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22953'. created direct connection (no actual register cell created). 22.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22978'. Found and cleaned up 1 empty switch in `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22954'. Removing empty process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22953'. Cleaned up 1 empty switch. 22.42.11.12. Executing OPT_EXPR pass (perform const folding). 22.42.12. Executing PROC pass (convert processes to netlists). 22.42.12.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23024'. Cleaned up 1 empty switch. 22.42.12.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23025 in module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.12.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.12.4. Executing PROC_INIT pass (extract init attributes). 22.42.12.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.12.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.12.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. Creating decoders for process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23025'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23023_EN[3:0]$23030 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23023_DATA[3:0]$23031 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23023_ADDR[3:0]$23029 Creating decoders for process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23024'. 22.42.12.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.12.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23007_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23022_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.\i' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23017_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23016_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23011_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23021_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23010_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23020_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23019_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23014_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23013_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23015_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23009_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23008_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23018_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23012_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. created direct connection (no actual register cell created). Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23023_ADDR' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23025'. created $dff cell `$procdff$23075' with positive edge clock. Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23023_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23025'. created $dff cell `$procdff$23076' with positive edge clock. Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23023_DATA' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23025'. created $dff cell `$procdff$23077' with positive edge clock. Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.\muxwre' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23024'. created direct connection (no actual register cell created). 22.42.12.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.12.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23049'. Found and cleaned up 1 empty switch in `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23025'. Removing empty process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23024'. Cleaned up 1 empty switch. 22.42.12.12. Executing OPT_EXPR pass (perform const folding). 22.42.13. Executing PROC pass (convert processes to netlists). 22.42.13.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23095'. Cleaned up 1 empty switch. 22.42.13.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23096 in module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.13.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.13.4. Executing PROC_INIT pass (extract init attributes). 22.42.13.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.13.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.13.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. Creating decoders for process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23096'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23094_EN[3:0]$23100 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23094_DATA[3:0]$23101 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23094_ADDR[3:0]$23102 Creating decoders for process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23095'. 22.42.13.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.13.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.\i' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23092_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23093_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23087_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23086_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23081_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23091_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23080_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23090_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23089_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23085_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23084_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23083_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23079_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23078_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23088_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23082_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. created direct connection (no actual register cell created). Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23094_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23096'. created $dff cell `$procdff$23146' with positive edge clock. Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23094_DATA' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23096'. created $dff cell `$procdff$23147' with positive edge clock. Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23094_ADDR' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23096'. created $dff cell `$procdff$23148' with positive edge clock. Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.\muxwre' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23095'. created direct connection (no actual register cell created). 22.42.13.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.13.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23120'. Found and cleaned up 1 empty switch in `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23096'. Removing empty process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23095'. Cleaned up 1 empty switch. 22.42.13.12. Executing OPT_EXPR pass (perform const folding). 22.42.14. Executing PROC pass (convert processes to netlists). 22.42.14.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23166'. Cleaned up 1 empty switch. 22.42.14.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23167 in module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.14.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.14.4. Executing PROC_INIT pass (extract init attributes). 22.42.14.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.14.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.14.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. Creating decoders for process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23167'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23165_EN[3:0]$23173 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23165_DATA[3:0]$23172 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23165_ADDR[3:0]$23171 Creating decoders for process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23166'. 22.42.14.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.14.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.\i' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23157_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23156_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23151_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23150_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23160_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23159_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23155_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23154_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23153_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23149_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23161_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23162_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23163_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23164_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23158_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23152_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. created direct connection (no actual register cell created). Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23165_ADDR' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23167'. created $dff cell `$procdff$23217' with positive edge clock. Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23165_DATA' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23167'. created $dff cell `$procdff$23218' with positive edge clock. Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23165_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23167'. created $dff cell `$procdff$23219' with positive edge clock. Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.\muxwre' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23166'. created direct connection (no actual register cell created). 22.42.14.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.14.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23191'. Found and cleaned up 1 empty switch in `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23167'. Removing empty process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23166'. Cleaned up 1 empty switch. 22.42.14.12. Executing OPT_EXPR pass (perform const folding). 22.42.15. Executing PROC pass (convert processes to netlists). 22.42.15.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23237'. Cleaned up 1 empty switch. 22.42.15.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23238 in module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.15.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.15.4. Executing PROC_INIT pass (extract init attributes). 22.42.15.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.15.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.15.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. Creating decoders for process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23238'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23236_EN[3:0]$23242 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23236_DATA[3:0]$23243 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23236_ADDR[3:0]$23244 Creating decoders for process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23237'. 22.42.15.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.15.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23233_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23232_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23227_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23226_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23221_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23235_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23231_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23230_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23229_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23225_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23224_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23223_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.\i' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23234_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23228_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23222_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23220_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23236_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23238'. created $dff cell `$procdff$23288' with positive edge clock. Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23236_DATA' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23238'. created $dff cell `$procdff$23289' with positive edge clock. Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23236_ADDR' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23238'. created $dff cell `$procdff$23290' with positive edge clock. Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.\muxwre' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23237'. created direct connection (no actual register cell created). 22.42.15.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.15.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23262'. Found and cleaned up 1 empty switch in `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23238'. Removing empty process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23237'. Cleaned up 1 empty switch. 22.42.15.12. Executing OPT_EXPR pass (perform const folding). 22.42.16. Executing PROC pass (convert processes to netlists). 22.42.16.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23308'. Cleaned up 1 empty switch. 22.42.16.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23309 in module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.16.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.16.4. Executing PROC_INIT pass (extract init attributes). 22.42.16.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.16.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.16.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. Creating decoders for process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23309'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23307_EN[3:0]$23313 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23307_DATA[3:0]$23314 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23307_ADDR[3:0]$23315 Creating decoders for process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23308'. 22.42.16.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.16.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.\i' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23303_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23302_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23297_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23296_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23306_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23305_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23301_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23300_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23299_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23295_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23294_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23293_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23291_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23304_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23298_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23292_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. created direct connection (no actual register cell created). Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23307_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23309'. created $dff cell `$procdff$23359' with positive edge clock. Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23307_DATA' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23309'. created $dff cell `$procdff$23360' with positive edge clock. Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23307_ADDR' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23309'. created $dff cell `$procdff$23361' with positive edge clock. Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.\muxwre' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23308'. created direct connection (no actual register cell created). 22.42.16.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.16.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23333'. Found and cleaned up 1 empty switch in `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23309'. Removing empty process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23308'. Cleaned up 1 empty switch. 22.42.16.12. Executing OPT_EXPR pass (perform const folding). 22.42.17. Executing PROC pass (convert processes to netlists). 22.42.17.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23379'. Cleaned up 1 empty switch. 22.42.17.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23380 in module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.17.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.17.4. Executing PROC_INIT pass (extract init attributes). 22.42.17.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.17.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.17.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. Creating decoders for process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23380'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23378_EN[3:0]$23386 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23378_DATA[3:0]$23385 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23378_ADDR[3:0]$23384 Creating decoders for process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23379'. 22.42.17.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.17.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.\i' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23373_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23372_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23367_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23377_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23366_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23376_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23375_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23371_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23370_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23369_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23363_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23365_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23364_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23362_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23374_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23368_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. created direct connection (no actual register cell created). Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23378_ADDR' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23380'. created $dff cell `$procdff$23430' with positive edge clock. Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23378_DATA' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23380'. created $dff cell `$procdff$23431' with positive edge clock. Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23378_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23380'. created $dff cell `$procdff$23432' with positive edge clock. Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.\muxwre' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23379'. created direct connection (no actual register cell created). 22.42.17.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.17.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23404'. Found and cleaned up 1 empty switch in `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23380'. Removing empty process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23379'. Cleaned up 1 empty switch. 22.42.17.12. Executing OPT_EXPR pass (perform const folding). 22.42.18. Executing PROC pass (convert processes to netlists). 22.42.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23450'. Cleaned up 1 empty switch. 22.42.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23451 in module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.18.4. Executing PROC_INIT pass (extract init attributes). 22.42.18.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.18.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. Creating decoders for process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23451'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23449_EN[3:0]$23455 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23449_DATA[3:0]$23457 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23449_ADDR[3:0]$23456 Creating decoders for process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23450'. 22.42.18.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.18.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23442_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23447_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23443_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.\i' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23448_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23437_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23446_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23436_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23445_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23441_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23440_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23439_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23435_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23434_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23433_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23444_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23438_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23449_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23451'. created $dff cell `$procdff$23501' with positive edge clock. Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23449_ADDR' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23451'. created $dff cell `$procdff$23502' with positive edge clock. Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23449_DATA' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23451'. created $dff cell `$procdff$23503' with positive edge clock. Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.\muxwre' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23450'. created direct connection (no actual register cell created). 22.42.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23475'. Found and cleaned up 1 empty switch in `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23451'. Removing empty process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23450'. Cleaned up 1 empty switch. 22.42.18.12. Executing OPT_EXPR pass (perform const folding). 22.42.19. Executing PROC pass (convert processes to netlists). 22.42.19.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23521'. Cleaned up 1 empty switch. 22.42.19.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23522 in module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.19.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.19.4. Executing PROC_INIT pass (extract init attributes). 22.42.19.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.19.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.19.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. Creating decoders for process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23522'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23520_EN[3:0]$23526 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23520_DATA[3:0]$23527 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23520_ADDR[3:0]$23528 Creating decoders for process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23521'. 22.42.19.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.19.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.\i' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23519_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23518_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23513_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23512_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23507_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23517_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23506_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23516_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23515_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23511_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23510_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23509_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23505_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23504_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23514_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23508_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. created direct connection (no actual register cell created). Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23520_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23522'. created $dff cell `$procdff$23572' with positive edge clock. Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23520_DATA' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23522'. created $dff cell `$procdff$23573' with positive edge clock. Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23520_ADDR' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23522'. created $dff cell `$procdff$23574' with positive edge clock. Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.\muxwre' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23521'. created direct connection (no actual register cell created). 22.42.19.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.19.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23546'. Found and cleaned up 1 empty switch in `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23522'. Removing empty process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23521'. Cleaned up 1 empty switch. 22.42.19.12. Executing OPT_EXPR pass (perform const folding). 22.42.20. Executing PROC pass (convert processes to netlists). 22.42.20.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23592'. Cleaned up 1 empty switch. 22.42.20.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23593 in module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.20.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.20.4. Executing PROC_INIT pass (extract init attributes). 22.42.20.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.20.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.20.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. Creating decoders for process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23593'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23591_EN[3:0]$23597 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23591_DATA[3:0]$23598 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23591_ADDR[3:0]$23599 Creating decoders for process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23592'. 22.42.20.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.20.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.\i' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23582_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23589_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23588_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23583_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23577_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23587_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23576_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23586_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23585_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23581_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23580_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23579_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23575_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23590_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23584_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23578_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23591_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23593'. created $dff cell `$procdff$23643' with positive edge clock. Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23591_DATA' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23593'. created $dff cell `$procdff$23644' with positive edge clock. Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23591_ADDR' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23593'. created $dff cell `$procdff$23645' with positive edge clock. Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23592'. created direct connection (no actual register cell created). 22.42.20.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.20.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23617'. Found and cleaned up 1 empty switch in `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23593'. Removing empty process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23592'. Cleaned up 1 empty switch. 22.42.20.12. Executing OPT_EXPR pass (perform const folding). 22.42.21. Executing PROC pass (convert processes to netlists). 22.42.21.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23663'. Cleaned up 1 empty switch. 22.42.21.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23664 in module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.21.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.21.4. Executing PROC_INIT pass (extract init attributes). 22.42.21.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.21.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.21.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. Creating decoders for process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23664'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23662_EN[3:0]$23668 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23662_DATA[3:0]$23670 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23662_ADDR[3:0]$23669 Creating decoders for process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23663'. 22.42.21.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.21.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.\i' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23659_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23649_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23650_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23651_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23655_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23656_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23657_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23661_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23647_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23652_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23653_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23658_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23660_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23654_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23648_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23646_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. created direct connection (no actual register cell created). Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23662_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23664'. created $dff cell `$procdff$23714' with positive edge clock. Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23662_ADDR' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23664'. created $dff cell `$procdff$23715' with positive edge clock. Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23662_DATA' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23664'. created $dff cell `$procdff$23716' with positive edge clock. Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.\muxwre' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23663'. created direct connection (no actual register cell created). 22.42.21.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.21.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23688'. Found and cleaned up 1 empty switch in `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23664'. Removing empty process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23663'. Cleaned up 1 empty switch. 22.42.21.12. Executing OPT_EXPR pass (perform const folding). 22.42.22. Executing PROC pass (convert processes to netlists). 22.42.22.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23734'. Cleaned up 1 empty switch. 22.42.22.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23735 in module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.22.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.22.4. Executing PROC_INIT pass (extract init attributes). 22.42.22.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.22.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.22.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. Creating decoders for process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23735'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23733_EN[3:0]$23740 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23733_DATA[3:0]$23741 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23733_ADDR[3:0]$23739 Creating decoders for process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23734'. 22.42.22.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.22.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.\i' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23717_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23732_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23722_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23723_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23728_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23729_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23731_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23727_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23726_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23725_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23721_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23720_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23719_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23730_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23724_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23718_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. created direct connection (no actual register cell created). Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23733_ADDR' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23735'. created $dff cell `$procdff$23785' with positive edge clock. Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23733_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23735'. created $dff cell `$procdff$23786' with positive edge clock. Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23733_DATA' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23735'. created $dff cell `$procdff$23787' with positive edge clock. Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.\muxwre' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23734'. created direct connection (no actual register cell created). 22.42.22.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.22.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23759'. Found and cleaned up 1 empty switch in `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23735'. Removing empty process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23734'. Cleaned up 1 empty switch. 22.42.22.12. Executing OPT_EXPR pass (perform const folding). 22.42.23. Executing PROC pass (convert processes to netlists). 22.42.23.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23805'. Cleaned up 1 empty switch. 22.42.23.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23806 in module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.23.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.23.4. Executing PROC_INIT pass (extract init attributes). 22.42.23.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.23.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.23.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. Creating decoders for process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23806'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23804_EN[3:0]$23810 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23804_DATA[3:0]$23811 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23804_ADDR[3:0]$23812 Creating decoders for process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23805'. 22.42.23.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.23.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.\i' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23802_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23797_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23796_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23791_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23801_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23790_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23800_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23799_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23795_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23794_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23793_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23789_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23788_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23803_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23798_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23792_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. created direct connection (no actual register cell created). Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23804_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23806'. created $dff cell `$procdff$23856' with positive edge clock. Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23804_DATA' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23806'. created $dff cell `$procdff$23857' with positive edge clock. Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23804_ADDR' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23806'. created $dff cell `$procdff$23858' with positive edge clock. Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.\muxwre' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23805'. created direct connection (no actual register cell created). 22.42.23.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.23.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23830'. Found and cleaned up 1 empty switch in `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23806'. Removing empty process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23805'. Cleaned up 1 empty switch. 22.42.23.12. Executing OPT_EXPR pass (perform const folding). 22.42.24. Executing PROC pass (convert processes to netlists). 22.42.24.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23876'. Cleaned up 1 empty switch. 22.42.24.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23877 in module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.24.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.24.4. Executing PROC_INIT pass (extract init attributes). 22.42.24.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.24.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.24.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. Creating decoders for process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23877'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23875_EN[3:0]$23882 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23875_DATA[3:0]$23883 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23875_ADDR[3:0]$23881 Creating decoders for process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23876'. 22.42.24.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.24.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.\i' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23864_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23867_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23871_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23868_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23863_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23872_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23873_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23869_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23866_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23861_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23862_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23874_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23859_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23870_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23865_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23860_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23875_ADDR' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23877'. created $dff cell `$procdff$23927' with positive edge clock. Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23875_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23877'. created $dff cell `$procdff$23928' with positive edge clock. Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23875_DATA' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23877'. created $dff cell `$procdff$23929' with positive edge clock. Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.\muxwre' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23876'. created direct connection (no actual register cell created). 22.42.24.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.24.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23901'. Found and cleaned up 1 empty switch in `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23877'. Removing empty process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23876'. Cleaned up 1 empty switch. 22.42.24.12. Executing OPT_EXPR pass (perform const folding). 22.42.25. Executing PROC pass (convert processes to netlists). 22.42.25.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23947'. Cleaned up 1 empty switch. 22.42.25.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23948 in module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.25.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.25.4. Executing PROC_INIT pass (extract init attributes). 22.42.25.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.25.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.25.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. Creating decoders for process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23948'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23946_EN[3:0]$23954 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23946_DATA[3:0]$23952 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23946_ADDR[3:0]$23953 Creating decoders for process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23947'. 22.42.25.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.25.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.\i' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23936_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23930_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23931_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23945_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23941_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23940_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23939_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23935_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23934_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23933_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23943_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23942_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23937_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23944_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23938_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23932_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. created direct connection (no actual register cell created). Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23946_DATA' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23948'. created $dff cell `$procdff$23998' with positive edge clock. Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23946_ADDR' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23948'. created $dff cell `$procdff$23999' with positive edge clock. Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23946_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23948'. created $dff cell `$procdff$24000' with positive edge clock. Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.\muxwre' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23947'. created direct connection (no actual register cell created). 22.42.25.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.25.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23972'. Found and cleaned up 1 empty switch in `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23948'. Removing empty process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23947'. Cleaned up 1 empty switch. 22.42.25.12. Executing OPT_EXPR pass (perform const folding). 22.42.26. Executing PROC pass (convert processes to netlists). 22.42.26.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24018'. Cleaned up 1 empty switch. 22.42.26.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24019 in module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.26.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.26.4. Executing PROC_INIT pass (extract init attributes). 22.42.26.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.26.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.26.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. Creating decoders for process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24019'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24017_EN[3:0]$24025 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24017_DATA[3:0]$24024 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24017_ADDR[3:0]$24023 Creating decoders for process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24018'. 22.42.26.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.26.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.\i' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24016_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24010_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24004_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24001_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24006_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24007_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24013_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24005_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24011_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24012_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24002_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24003_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24008_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24009_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24014_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24015_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24017_ADDR' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24019'. created $dff cell `$procdff$24069' with positive edge clock. Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24017_DATA' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24019'. created $dff cell `$procdff$24070' with positive edge clock. Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24017_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24019'. created $dff cell `$procdff$24071' with positive edge clock. Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.\muxwre' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24018'. created direct connection (no actual register cell created). 22.42.26.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.26.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24043'. Found and cleaned up 1 empty switch in `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24019'. Removing empty process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24018'. Cleaned up 1 empty switch. 22.42.26.12. Executing OPT_EXPR pass (perform const folding). 22.42.27. Executing PROC pass (convert processes to netlists). 22.42.27.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24089'. Cleaned up 1 empty switch. 22.42.27.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24090 in module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.27.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.27.4. Executing PROC_INIT pass (extract init attributes). 22.42.27.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.27.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.27.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. Creating decoders for process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24090'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24088_EN[3:0]$24094 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24088_DATA[3:0]$24096 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24088_ADDR[3:0]$24095 Creating decoders for process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24089'. 22.42.27.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.27.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.\i' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24084_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24078_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24072_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24085_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24076_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24073_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24074_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24075_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24079_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24080_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24081_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24086_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24087_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24077_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24082_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24083_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. created direct connection (no actual register cell created). Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24088_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24090'. created $dff cell `$procdff$24140' with positive edge clock. Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24088_ADDR' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24090'. created $dff cell `$procdff$24141' with positive edge clock. Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24088_DATA' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24090'. created $dff cell `$procdff$24142' with positive edge clock. Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.\muxwre' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24089'. created direct connection (no actual register cell created). 22.42.27.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.27.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24114'. Found and cleaned up 1 empty switch in `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24090'. Removing empty process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24089'. Cleaned up 1 empty switch. 22.42.27.12. Executing OPT_EXPR pass (perform const folding). 22.42.28. Executing PROC pass (convert processes to netlists). 22.42.28.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24160'. Cleaned up 1 empty switch. 22.42.28.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24161 in module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.28.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.28.4. Executing PROC_INIT pass (extract init attributes). 22.42.28.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.28.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.28.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. Creating decoders for process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24161'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24159_EN[3:0]$24167 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24159_DATA[3:0]$24166 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24159_ADDR[3:0]$24165 Creating decoders for process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24160'. 22.42.28.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.28.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.\i' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24158_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24152_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24146_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24148_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24149_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24153_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24154_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24155_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24143_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24147_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24144_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24145_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24150_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24151_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24156_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24157_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. created direct connection (no actual register cell created). Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24159_ADDR' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24161'. created $dff cell `$procdff$24211' with positive edge clock. Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24159_DATA' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24161'. created $dff cell `$procdff$24212' with positive edge clock. Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24159_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24161'. created $dff cell `$procdff$24213' with positive edge clock. Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24160'. created direct connection (no actual register cell created). 22.42.28.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.28.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24185'. Found and cleaned up 1 empty switch in `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24161'. Removing empty process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24160'. Cleaned up 1 empty switch. 22.42.28.12. Executing OPT_EXPR pass (perform const folding). 22.42.29. Executing SCC pass (detecting logic loops). Found an SCC: $techmap$auto$ff.cc:266:slice$8052.$auto$simplemap.cc:267:simplemap_mux$22283 Found an SCC: $techmap$auto$ff.cc:266:slice$8051.$auto$simplemap.cc:267:simplemap_mux$22283 Found an SCC: $techmap$auto$ff.cc:266:slice$8050.$auto$simplemap.cc:267:simplemap_mux$22283 Found an SCC: $techmap$auto$ff.cc:266:slice$8049.$auto$simplemap.cc:267:simplemap_mux$22283 Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$21392 $auto$ff.cc:266:slice$6117 $auto$simplemap.cc:126:simplemap_reduce$6224 $auto$simplemap.cc:126:simplemap_reduce$6239 $auto$ff.cc:266:slice$6118 $auto$ff.cc:266:slice$6119 $auto$opt_expr.cc:613:replace_const_cells$21388 $auto$simplemap.cc:267:simplemap_mux$12878 $auto$simplemap.cc:126:simplemap_reduce$12900 $auto$simplemap.cc:126:simplemap_reduce$12897 $auto$simplemap.cc:75:simplemap_bitop$12879 $auto$simplemap.cc:267:simplemap_mux$6205 $auto$simplemap.cc:225:simplemap_logbin$6214 $auto$simplemap.cc:196:simplemap_lognot$6229 $auto$simplemap.cc:126:simplemap_reduce$6227 $auto$simplemap.cc:126:simplemap_reduce$6225 $auto$simplemap.cc:126:simplemap_reduce$12888 $auto$simplemap.cc:75:simplemap_bitop$12881 $auto$simplemap.cc:196:simplemap_lognot$6244 $auto$simplemap.cc:126:simplemap_reduce$6242 $auto$simplemap.cc:126:simplemap_reduce$6240 $auto$opt_expr.cc:613:replace_const_cells$21182 $auto$ff.cc:266:slice$6120 $auto$simplemap.cc:126:simplemap_reduce$4220 $auto$simplemap.cc:126:simplemap_reduce$4218 $auto$simplemap.cc:225:simplemap_logbin$6164 $auto$simplemap.cc:196:simplemap_lognot$6174 $auto$simplemap.cc:126:simplemap_reduce$6172 $auto$opt_expr.cc:613:replace_const_cells$21192 $auto$simplemap.cc:267:simplemap_mux$12877 $auto$simplemap.cc:126:simplemap_reduce$12891 Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$4436 $auto$simplemap.cc:38:simplemap_not$4135 $auto$ff.cc:266:slice$3660 $auto$ff.cc:479:convert_ce_over_srst$21568 $auto$ff.cc:266:slice$3661 $auto$ff.cc:479:convert_ce_over_srst$21570 $auto$ff.cc:266:slice$3659 $auto$ff.cc:479:convert_ce_over_srst$21566 $auto$simplemap.cc:38:simplemap_not$14958 $auto$ff.cc:266:slice$3658 $auto$ff.cc:479:convert_ce_over_srst$21564 $auto$alumacc.cc:485:replace_alu$2554.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$2554.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$4138 $auto$simplemap.cc:38:simplemap_not$20100 $auto$ff.cc:266:slice$3657 $auto$ff.cc:479:convert_ce_over_srst$21562 $auto$simplemap.cc:126:simplemap_reduce$4375 $auto$simplemap.cc:75:simplemap_bitop$4136 $auto$simplemap.cc:38:simplemap_not$4052 $auto$alumacc.cc:485:replace_alu$2554.slice[4].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$4140 $auto$simplemap.cc:38:simplemap_not$20105 $auto$ff.cc:266:slice$3662 $auto$ff.cc:479:convert_ce_over_srst$21572 $auto$simplemap.cc:126:simplemap_reduce$4351 $auto$simplemap.cc:126:simplemap_reduce$4349 $auto$simplemap.cc:126:simplemap_reduce$4438 $auto$simplemap.cc:126:simplemap_reduce$4435 $auto$simplemap.cc:126:simplemap_reduce$4144 $auto$simplemap.cc:126:simplemap_reduce$4142 $auto$simplemap.cc:126:simplemap_reduce$4139 $auto$simplemap.cc:38:simplemap_not$14960 Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$21216 $auto$ff.cc:266:slice$6121 $auto$simplemap.cc:38:simplemap_not$11208 $auto$ff.cc:266:slice$6127 $auto$simplemap.cc:126:simplemap_reduce$6262 $auto$simplemap.cc:38:simplemap_not$11209 $auto$ff.cc:266:slice$6128 $auto$ff.cc:266:slice$6129 $auto$ff.cc:266:slice$6123 $auto$simplemap.cc:126:simplemap_reduce$6259 $auto$ff.cc:266:slice$6122 $auto$ff.cc:266:slice$6124 $auto$simplemap.cc:38:simplemap_not$11206 $auto$ff.cc:266:slice$6125 $auto$simplemap.cc:126:simplemap_reduce$6265 $auto$simplemap.cc:126:simplemap_reduce$6261 $auto$ff.cc:266:slice$6126 $auto$simplemap.cc:126:simplemap_reduce$4247 $auto$simplemap.cc:196:simplemap_lognot$6271 $auto$simplemap.cc:126:simplemap_reduce$6269 $auto$simplemap.cc:126:simplemap_reduce$6267 $auto$simplemap.cc:126:simplemap_reduce$6264 $auto$simplemap.cc:126:simplemap_reduce$6260 $auto$simplemap.cc:38:simplemap_not$11205 Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$21218 $auto$ff.cc:266:slice$5977 $auto$simplemap.cc:126:simplemap_reduce$6099 $auto$ff.cc:266:slice$5978 $auto$simplemap.cc:38:simplemap_not$11237 $auto$ff.cc:266:slice$5979 $auto$simplemap.cc:126:simplemap_reduce$6104 $auto$simplemap.cc:126:simplemap_reduce$6100 $auto$simplemap.cc:126:simplemap_reduce$6073 $auto$simplemap.cc:38:simplemap_not$11238 $auto$ff.cc:266:slice$5980 $auto$simplemap.cc:38:simplemap_not$11239 $auto$ff.cc:266:slice$5981 $auto$simplemap.cc:126:simplemap_reduce$6101 $auto$simplemap.cc:126:simplemap_reduce$6074 $auto$simplemap.cc:38:simplemap_not$11240 $auto$ff.cc:266:slice$5982 $auto$simplemap.cc:38:simplemap_not$11241 $auto$ff.cc:266:slice$5983 $auto$simplemap.cc:126:simplemap_reduce$6078 $auto$simplemap.cc:126:simplemap_reduce$6075 $auto$simplemap.cc:126:simplemap_reduce$6107 $auto$simplemap.cc:126:simplemap_reduce$6105 $auto$simplemap.cc:126:simplemap_reduce$6102 $auto$simplemap.cc:38:simplemap_not$11242 $auto$ff.cc:266:slice$5984 $auto$simplemap.cc:196:simplemap_lognot$6111 $auto$simplemap.cc:126:simplemap_reduce$6109 $auto$ff.cc:266:slice$5985 $auto$simplemap.cc:167:logic_reduce$4199 $auto$simplemap.cc:225:simplemap_logbin$6056 $auto$simplemap.cc:225:simplemap_logbin$6057 $auto$simplemap.cc:196:simplemap_lognot$6084 $auto$simplemap.cc:126:simplemap_reduce$6082 $auto$simplemap.cc:126:simplemap_reduce$6080 $auto$simplemap.cc:126:simplemap_reduce$6077 $auto$simplemap.cc:126:simplemap_reduce$6072 Found 8 SCCs in module top. Found 8 SCCs. 22.42.30. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.31. Executing PROC pass (convert processes to netlists). 22.42.31.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 22.42.31.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 22.42.31.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 22.42.31.4. Executing PROC_INIT pass (extract init attributes). 22.42.31.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.31.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 22.42.31.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 22.42.31.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.31.9. Executing PROC_DFF pass (convert process syncs to FFs). 22.42.31.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.31.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 22.42.31.12. Executing OPT_EXPR pass (perform const folding). 22.42.32. Executing TECHMAP pass (map to technology primitives). 22.42.32.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 22.42.32.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~212 debug messages> 22.42.33. Executing OPT pass (performing simple optimizations). 22.42.33.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4. Optimizing module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4. Optimizing module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4. Optimizing module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4. Optimizing module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4. Optimizing module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4. Optimizing module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4. Optimizing module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4. Optimizing module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4. Optimizing module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4. Optimizing module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4. Optimizing module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4. Optimizing module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4. Optimizing module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4. Optimizing module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4. Optimizing module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4. Optimizing module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4. Optimizing module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4. Optimizing module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4. Optimizing module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4. Optimizing module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4. Optimizing module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4. Optimizing module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4. Optimizing module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4. 22.42.33.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4'. Removed a total of 0 cells. 22.42.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 22.42.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing cells in module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4. Optimizing cells in module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4. Optimizing cells in module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4. Optimizing cells in module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4. Optimizing cells in module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4. Optimizing cells in module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4. Optimizing cells in module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4. Optimizing cells in module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4. Optimizing cells in module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4. Optimizing cells in module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4. Optimizing cells in module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4. Optimizing cells in module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4. Optimizing cells in module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4. Optimizing cells in module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4. Optimizing cells in module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4. Optimizing cells in module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4. Optimizing cells in module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4. Optimizing cells in module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4. Optimizing cells in module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4. Optimizing cells in module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4. Optimizing cells in module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4. Optimizing cells in module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4. Optimizing cells in module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4. Optimizing cells in module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4. Performed a total of 0 changes. 22.42.33.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4'. Removed a total of 0 cells. 22.42.33.6. Executing OPT_DFF pass (perform DFF optimizations). 22.42.33.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.. 22.42.33.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4. Optimizing module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4. Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4. Optimizing module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4. Optimizing module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4. Optimizing module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4. Optimizing module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4. Optimizing module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4. Optimizing module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4. Optimizing module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4. Optimizing module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4. Optimizing module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4. Optimizing module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4. Optimizing module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4. Optimizing module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4. Optimizing module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4. Optimizing module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4. Optimizing module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4. Optimizing module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4. Optimizing module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4. Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4. Optimizing module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4. Optimizing module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4. Optimizing module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4. 22.42.33.9. Finished OPT passes. (There is nothing left to do.) 22.42.34. Executing TECHMAP pass (map to technology primitives). 22.42.34.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 22.42.34.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Using template $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4 for cells of type $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4. Using template $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4 for cells of type $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4. Using template $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4 for cells of type $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4. Using template $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4 for cells of type $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4. Using template $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4 for cells of type $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4. Using template $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4 for cells of type $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4. Using template $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4 for cells of type $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4. Using template $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4 for cells of type $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4. Using template $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4 for cells of type $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4. Using template $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4 for cells of type $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4. Using template $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4 for cells of type $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4. Using template $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4 for cells of type $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4. Using template $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4 for cells of type $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4. Using template $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4 for cells of type $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4. Using template $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4 for cells of type $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4. Using template $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4 for cells of type $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4. Using template $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4 for cells of type $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4. Using template $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4 for cells of type $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4. Using template $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4 for cells of type $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4. Using template $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4 for cells of type $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4. Using template $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4 for cells of type $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4. Using template $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4 for cells of type $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4. Using template $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4 for cells of type $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4. Using template $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4 for cells of type $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4. No more expansions possible. <suppressed ~320 debug messages> 22.42.35. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 22.42.36. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 22.42.37. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.38. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 22.42.39. Executing TECHMAP pass (map to technology primitives). 22.42.39.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 22.42.39.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $not. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $mux. No more expansions possible. <suppressed ~251 debug messages> 22.42.40. Executing OPT pass (performing simple optimizations). 22.42.40.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~18 debug messages> 22.42.40.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 22.42.40.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 22.42.40.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.42.40.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.42.40.6. Executing OPT_DFF pass (perform DFF optimizations). 22.42.40.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 55 unused wires. <suppressed ~1 debug messages> 22.42.40.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.42.40.9. Rerunning OPT passes. (Maybe there is more to do..) 22.42.40.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 22.42.40.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.42.40.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.42.40.13. Executing OPT_DFF pass (perform DFF optimizations). 22.42.40.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.42.40.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.42.40.16. Finished OPT passes. (There is nothing left to do.) 22.42.41. Executing AIGMAP pass (map logic to AIG). Module top: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 2 $_OR_ 2 $_XOR_ 14 $_MUX_ not replaced 3 cell types: 31 $specify2 4 $_NOT_ 4 $_AND_ 22.42.42. Executing AIGMAP pass (map logic to AIG). Module top: replaced 3987 cells with 23913 new cells, skipped 3326 cells. replaced 3 cell types: 1332 $_OR_ 94 $_XOR_ 2561 $_MUX_ not replaced 59 cell types: 30 $scopeinfo 360 $_NOT_ 1255 $_AND_ 6 $_TBUF_ 1 $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4 1 $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4 1 $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4 702 TRELLIS_FF 1 $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4 1 $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4 1 $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4 1 $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4 1 $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4 1 $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4 1 $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4 1 $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4 1 $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4 1 $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4 1 $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4 1 $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4 1 $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp 252 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 1 $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4 1 $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp 1 $__ABC9_SCC_BREAKER 1 $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp 16 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 1 $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4 1 $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4 16 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4 1 $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4 1 $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4 1 $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4 1 $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4 1 $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4 1 $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp 252 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp 388 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 22.42.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.42.3. Executing XAIGER backend. <suppressed ~11 debug messages> Extracted 10552 AND gates and 30405 wires from module `top' to a netlist network with 1887 inputs and 733 outputs. 22.42.42.4. Executing ABC9_EXE pass (technology mapping using ABC9). 22.42.42.5. Executing ABC9. ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source run.tcl # read_verilog "main.v" Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_lut <abc-temp-dir>/input.lut ABC: + read_box <abc-temp-dir>/input.box ABC: + &read <abc-temp-dir>/input.xaig ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 1887/ 733 and = 9143 lev = 46 (5.17) mem = 0.27 MB box = 680 bb = 292 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 1887/ 733 and = 12122 lev = 62 (3.19) mem = 0.29 MB ch = 1349 box = 618 bb = 292 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 60. Obj = 140. Set = 636. CutMin = no ABC: Node = 12122. Ch = 1203. Total mem = 3.30 MB. Peak cut mem = 0.28 MB. ABC: P: Del = 6879.00. Ar = 12534.0. Edge = 15098. Cut = 172080. T = 0.04 sec ABC: P: Del = 6736.00. Ar = 11451.0. Edge = 13931. Cut = 173133. T = 0.04 sec ABC: P: Del = 6736.00. Ar = 6647.0. Edge = 12492. Cut = 368475. T = 0.08 sec ABC: F: Del = 6736.00. Ar = 4699.0. Edge = 11243. Cut = 324513. T = 0.08 sec ABC: A: Del = 6736.00. Ar = 4109.0. Edge = 9826. Cut = 292325. T = 0.11 sec ABC: A: Del = 6736.00. Ar = 4039.0. Edge = 9756. Cut = 288392. T = 0.11 sec ABC: Total time = 0.48 sec ABC: + &write -n <abc-temp-dir>/output.aig ABC: + &mfs ABC: + &ps -l ABC: <abc-temp-dir>/input : i/o = 1887/ 733 and = 8470 lev = 37 (3.34) mem = 0.25 MB box = 618 bb = 292 ABC: Mapping (K=7) : lut = 2480 edge = 9681 lev = 14 (1.44) levB = 41 mem = 0.13 MB ABC: LUT = 2480 : 2=280 11.3 % 3=581 23.4 % 4=1057 42.6 % 5=349 14.1 % 6=86 3.5 % 7=127 5.1 % Ave = 3.90 ABC: + &write -n <abc-temp-dir>/output.aig ABC: + time ABC: elapse: 5.39 seconds, total: 5.39 seconds 22.42.42.6. Executing AIGER frontend. <suppressed ~5314 debug messages> Removed 11783 unused cells and 23269 unused wires. 22.42.42.7. Executing ABC9_OPS pass (helper functions for ABC9). ABC RESULTS: $lut cells: 2505 ABC RESULTS: $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells: 16 ABC RESULTS: $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 252 ABC RESULTS: $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 326 ABC RESULTS: input signals: 337 ABC RESULTS: output signals: 131 Removing temp directory. 22.42.43. Executing TECHMAP pass (map to technology primitives). 22.42.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 22.42.43.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4 for cells of type $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4. Using template $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4 for cells of type $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4. Using template $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4 for cells of type $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4. Using template $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4 for cells of type $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4. Using template $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4 for cells of type $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4. Using template $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4 for cells of type $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4. Using template $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4 for cells of type $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4. Using template $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4 for cells of type $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4. Using template $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4 for cells of type $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4. Using template $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4 for cells of type $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4. Using template $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4 for cells of type $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4. Using template $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4 for cells of type $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4. Using template $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4 for cells of type $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4. Using template $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4 for cells of type $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4. Using template $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4 for cells of type $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4. Using template $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4 for cells of type $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4. Using template $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4 for cells of type $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4. Using template $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4 for cells of type $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4. Using template $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4 for cells of type $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4. Using template $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4 for cells of type $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4. Using template $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4 for cells of type $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4. Using template $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4 for cells of type $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4. Using template $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4 for cells of type $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4. Using template $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4 for cells of type $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4. Using template $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001000 for cells of type $__ABC9_SCC_BREAKER. No more expansions possible. <suppressed ~980 debug messages> Removed 319 unused cells and 36629 unused wires. 22.43. Executing TECHMAP pass (map to technology primitives). 22.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 22.43.2. Continuing TECHMAP pass. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut. Using template $paramod$d2d50fced6e06d123321409eee0a12cd3b79fb8c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$6e46ec5a196ba1a24b8e69ab094cadc07c13ac1f\$lut for cells of type $lut. Using template $paramod$052ca015f1400ebf950f85d5f181f7a5865c336c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut. Using template $paramod$70a934594406e8042bf2854c778fef542ef3ea5f\$lut for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. Using template $paramod$ccd3e15dc00d71b9284dff48e88ccef5be7362c8\$lut for cells of type $lut. Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut. Using template $paramod$fb7bbfbe62f17d1abd6f8eaee546f5a966c46c29\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod$40bf400bfab4b5cf32dcfe01e14f0900ac7f6b1b\$lut for cells of type $lut. Using template $paramod$8e1de9055515c7496a07ef8faf7889b539297813\$lut for cells of type $lut. Using template $paramod$df5c8730c0a53792c3f54c2192a2221c27162fb5\$lut for cells of type $lut. Using template $paramod$84bef48419505c45080a829b4c4b6379a157eb8b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$56d1a78632b07077a5fde81946aeef0a806ae664\$lut for cells of type $lut. Using template $paramod$7f1ac77c5d84ef62fa0ac317f9798af74d02a33d\$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. Using template $paramod$872def176acf0af46aee1a4df67a9291309e3c01\$lut for cells of type $lut. Using template $paramod$73168779d124d0e86f3f4da4f351086f6646bb40\$lut for cells of type $lut. Using template $paramod$e29249e81d1428d25d454322886217cd4b5c0d52\$lut for cells of type $lut. Using template $paramod$71112c23185f325d93f810329cb9d4a033178614\$lut for cells of type $lut. Using template $paramod$05402c79be82cc63a2eaed19f98c2af9df54d241\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$f361098d8377aec6fbadc440457e5027c787d2ac\$lut for cells of type $lut. Using template $paramod$2c18765a444559e718df785580a1a54d0ca9015a\$lut for cells of type $lut. Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut. Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut. Using template $paramod$c362ad8dedc7d166ed978091aca319ab1e81a2d4\$lut for cells of type $lut. Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$f546bd96bcec6e3bf1b78bdea64b0f5bbbaff6df\$lut for cells of type $lut. Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut. Using template $paramod$58d49ffbb43fac74e1430ef7dfa6e760bbd204ab\$lut for cells of type $lut. Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut. Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut. Using template $paramod$38400b76de2b00d7d5f8f09de118b82fd1b8be0a\$lut for cells of type $lut. Using template $paramod$3dcc6d56f3da66d1eb403ae5c8f32c1c42e3d606\$lut for cells of type $lut. Using template $paramod$d6e6d411b16e057eae3ca70523bb1b2722704525\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$9e1755e3954600257bb9b9ab192e2c0243b0f35a\$lut for cells of type $lut. Using template $paramod$3903b928bd3857b507f87213cb729ccd31581d43\$lut for cells of type $lut. Using template $paramod$df29fe9e6d6d694a9cc5697e4251bf7d8cd4d8e4\$lut for cells of type $lut. Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut. Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut. Using template $paramod$263b613d26e59958a0d1e36903a2016b82f2f359\$lut for cells of type $lut. Using template $paramod$42ff539ef2dece0a3be79f2f9f13e29a058fd3cf\$lut for cells of type $lut. Using template $paramod$d80c9b99dacb354fa564a6fcc23ca30753bf6623\$lut for cells of type $lut. Using template $paramod$90dc599eed99da511e64ad217d69e7ff2c1e56cc\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. Using template $paramod$f28a4401e00366386f5c9da01093cb438d2ef37a\$lut for cells of type $lut. Using template $paramod$ce44877a8aba311086973ef3ef648b154684306e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. Using template $paramod$173257c402a3003de28bff8c2a49d358e5f4004c\$lut for cells of type $lut. Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. Using template $paramod$63114da772fb28945ba24699e32f1e30ca7142f4\$lut for cells of type $lut. Using template $paramod$5400b6807adef39a9693b2fbff17f8c0ab116b66\$lut for cells of type $lut. Using template $paramod$23ba03b3f106a8b0f20f18bfebd862b419996ddc\$lut for cells of type $lut. Using template $paramod$7202672b7332febf25cdbe5424cf24593f5449be\$lut for cells of type $lut. Using template $paramod$c20bb0ec9b7ffe048b440bc5b52865dca055e17d\$lut for cells of type $lut. Using template $paramod$394086530b97e2ede4325cfef07483589916f736\$lut for cells of type $lut. Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. Using template $paramod$db8547c0ce3f404162c765a55df5db805b4e10bc\$lut for cells of type $lut. Using template $paramod$7aa8140c7d6de3160b21e7ff84e0f93f69f7fcc6\$lut for cells of type $lut. Using template $paramod$2e6f7636c4430e71acfafacf89034290c19a68d2\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod$faba0cf60f1c89602d59ba2d491152c8f0d36384\$lut for cells of type $lut. Using template $paramod$bde6c96e44b0f8e6d9db97eafdf28d77ceaa9a96\$lut for cells of type $lut. Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut. Using template $paramod$43b222efc278812f84aae21629319c00666b72b2\$lut for cells of type $lut. Using template $paramod$473fcd371d91799964bc73c98ad44aa026e26f19\$lut for cells of type $lut. Using template $paramod$08466811901d5e03ed77c75ae1ee4f324a7c22b7\$lut for cells of type $lut. Using template $paramod$35e780f9333f3666b86f6bdeb5e6c5f65477f87e\$lut for cells of type $lut. Using template $paramod$86e537003f602312dd4fc6eec44e711e66fd573e\$lut for cells of type $lut. Using template $paramod$bd860769e6801c50637ab5dc92ce390296b4c30f\$lut for cells of type $lut. Using template $paramod$4e45a60feb8bbe3cabd280417c9ffbefad6f6ef3\$lut for cells of type $lut. Using template $paramod$2a4b250d89be3556c74aa0e719a4f6242369d42f\$lut for cells of type $lut. Using template $paramod$86ac5e2f48216e1fecdb3a8cd4fb86321440ece3\$lut for cells of type $lut. Using template $paramod$1df6d41de86e48fa0e114cfe35ac61195abc3952\$lut for cells of type $lut. Using template $paramod$bed770a996b91d26bd8ec11fab40ed5b998c6937\$lut for cells of type $lut. Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut. Using template $paramod$d7a87ca2ecbda1d431eb014d7af4b3bc1067b28d\$lut for cells of type $lut. Using template $paramod$b2b362fa866354d5936edc937d825ffc48772447\$lut for cells of type $lut. Using template $paramod$3cc80e2a63856e1f46075e358d1c072c35cc4ca8\$lut for cells of type $lut. Using template $paramod$0fe8fbf45fc9407b7d9f6cdf3b662e78e91e9b55\$lut for cells of type $lut. Using template $paramod$b2b8f14c1dc45737f0261c4484079d734f30d41f\$lut for cells of type $lut. Using template $paramod$130ffa84d8c0712333eceff6854084179663a049\$lut for cells of type $lut. Using template $paramod$ee3ba3939f6ccdb74bf420a252d58cdb86511937\$lut for cells of type $lut. Using template $paramod$83c1b6108170249166239e09804c5f4542556524\$lut for cells of type $lut. Using template $paramod$f9c55c999dcf6c87c8508a041c8b2e28738fa25d\$lut for cells of type $lut. Using template $paramod$cffcdcfefee28cb7804202d59fcab831562282d3\$lut for cells of type $lut. Using template $paramod$2e42f4cdfa2b7be54cbecc74818d81b621a7793c\$lut for cells of type $lut. Using template $paramod$3b374b0454c507d1efadee363d480c52c3b3f58f\$lut for cells of type $lut. Using template $paramod$26d876869d6ab003366d0470e095daef2ccfcbd7\$lut for cells of type $lut. Using template $paramod$9b5adbcc1983522e183f7d22bb4ef0787febf9d7\$lut for cells of type $lut. Using template $paramod$c98da1ab510f98f1bdbbe5a79169ddcc9bfb334b\$lut for cells of type $lut. Using template $paramod$d1d6ba92d241de8fe25e24baaf3ad2e6ec893e9b\$lut for cells of type $lut. Using template $paramod$09312832496e3ee8317d1ddf4e4ce05d551d0a6d\$lut for cells of type $lut. Using template $paramod$4eb848e991ac2a992be9b4be01f278b220c0efac\$lut for cells of type $lut. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut. Using template $paramod$2e0c101d30f80073aa610a7c8862ce4fe1de2872\$lut for cells of type $lut. Using template $paramod$be95f3a2132281eadd1adcfe6229e43dbc3353c9\$lut for cells of type $lut. Using template $paramod$791ae37bef671b724edae9f13d094dc39cd7c8cb\$lut for cells of type $lut. Using template $paramod$6fc23ce09f2013cb9de2228dbcdda21841008f92\$lut for cells of type $lut. Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut. Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut. Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. Using template $paramod$7fc325150916e09e21db63cc9672b99a89ef9301\$lut for cells of type $lut. Using template $paramod$49a2a49f04797cd8c762f7e623379d982c922da2\$lut for cells of type $lut. Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut. Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut. Using template $paramod$633ae299df262467973f925d88826d85d4a12fb4\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut. Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut. Using template $paramod$c79aec6bf66334ca918f85c196e004c918c371ef\$lut for cells of type $lut. Using template $paramod$09ff6bc38860bc684248b0f5479347794277f7f7\$lut for cells of type $lut. Using template $paramod$723be7177967d6866729df0ff463a602326a012e\$lut for cells of type $lut. Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc\$lut for cells of type $lut. Using template $paramod$b8113752b08bd47f69a1c8c2bca1cfb157e800c9\$lut for cells of type $lut. Using template $paramod$7a0082b62579adab7423c09f5a537fdaa323b92f\$lut for cells of type $lut. Using template $paramod$cee6eb0dfafa502be58539ba09d1ac1089e06476\$lut for cells of type $lut. Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut. Using template $paramod$c5d791b2dd3d8afd456f4384acfd996b0f093f14\$lut for cells of type $lut. Using template $paramod$ec77ef2f39e0c5347eaada9711f26fca6a276050\$lut for cells of type $lut. Using template $paramod$21ae97a4a7b4150f4d543da554e192df87272b1f\$lut for cells of type $lut. Using template $paramod$8c11a155773d2e4aba9b1022fc059160b55313e8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$4b7a2575a604aa21eec6378b6833292a7c6978f8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$a29dc9226a883358910d3758606f48686bda2689\$lut for cells of type $lut. Using template $paramod$4d0440a90e55befc55639569976d9facbb4a73c8\$lut for cells of type $lut. Using template $paramod$9eb6ed834ec76c8dbfc2001ae6fa73b1bb6c3243\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$2caeb761483fdb6a547632a4cc3a2b2e1c966f51\$lut for cells of type $lut. Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut. Using template $paramod$34e326867bb04eb7166eb385de03f3f07fdc4c23\$lut for cells of type $lut. Using template $paramod$037be5c00d8a02858cdb1ab049b58a0133287ff1\$lut for cells of type $lut. Using template $paramod$60b758fd5679f6508bff32bea2afedb4f329e5f9\$lut for cells of type $lut. Using template $paramod$925eea857f8298053c64d4f418d8cb9b6cd6cb1e\$lut for cells of type $lut. Using template $paramod$c4af7f2c88559dab5f19c52110f1d82cb05f465f\$lut for cells of type $lut. Using template $paramod$12428c4217e00e6257ac0074a74f30fd71809836\$lut for cells of type $lut. Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut. Using template $paramod$cd77d5e7596a750e2c0ed130aacde2f323347f26\$lut for cells of type $lut. Using template $paramod$20ba583962918fa0136fc97b1558cc45cc91cc29\$lut for cells of type $lut. Using template $paramod$0291521cf5457e6358befa7154ed1af4554052b6\$lut for cells of type $lut. Using template $paramod$d7372df0dc02a6c940130cc6e3dbb5dc0398486d\$lut for cells of type $lut. Using template $paramod$81f38dbe34c0131668a5f4192c3c2c07e8338073\$lut for cells of type $lut. Using template $paramod$238823fd40f9a5ac8e89edce041f4007ec5d4406\$lut for cells of type $lut. Using template $paramod$8e83c7ea20bd1b26ae726084c54862f46443f3f1\$lut for cells of type $lut. Using template $paramod$a0213d503395b0fbd7ca6ddb29c8d3a8cf1cd1f1\$lut for cells of type $lut. Using template $paramod$1632c1c0242796acfc963a05742c4acd2f475c4e\$lut for cells of type $lut. Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut. Using template $paramod$3416dacc8eaab1f89b3d6b7398df3da766d29ef2\$lut for cells of type $lut. Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut. Using template $paramod$c39b4ae3eed03ff4e0ef2a41844cc5ea3df00d09\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut. Using template $paramod$4978360fe53bdcf6193c85aac631cf6592e5a5ce\$lut for cells of type $lut. Using template $paramod$bf6add2967325c59b1cc62393b93e39c101df9d8\$lut for cells of type $lut. Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut. Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut. Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut. Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut. Using template $paramod$4d1533dad4814c51bde53f9a378e78c03dd47a9f\$lut for cells of type $lut. Using template $paramod$b825578d19f70b5745094f84f5bc0dd9b602e095\$lut for cells of type $lut. Using template $paramod$2a20620c354bffb676ef0f9bc2892af8e67982c5\$lut for cells of type $lut. Using template $paramod$23e9bb0ff10d3a9c79f6d3d3cf26137e71ba410d\$lut for cells of type $lut. Using template $paramod$1dbc005c3ca46176ed5f71d3318762a2498d170f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut. Using template $paramod$b1447e7ac0047aadbefbf64d107b7ae81cabe38d\$lut for cells of type $lut. Using template $paramod$02750f8d568bd99efbda01449a05e084a3143ca8\$lut for cells of type $lut. Using template $paramod$b7c4f08b7346c19e2ae421f414a600eb78d5cf1c\$lut for cells of type $lut. Using template $paramod$efd9db50f639c84b61057002b4119366b96c7abc\$lut for cells of type $lut. Using template $paramod$a540b0a5bfdce016ce59e57feb8875b3bd8848ba\$lut for cells of type $lut. Using template $paramod$e3bcf162a509e74c0a17fd039abbd550e3db3002\$lut for cells of type $lut. Using template $paramod$ee09d6927966d306d9823e177362e5f2e087e811\$lut for cells of type $lut. Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut. Using template $paramod$e42911d5b4783f893e9fda29cce43782c36909b8\$lut for cells of type $lut. Using template $paramod$3531470707557f52fb507b4d48baf2694b9a571a\$lut for cells of type $lut. Using template $paramod$df3b65132f7020afafd5e2001ca04b29f12adcb4\$lut for cells of type $lut. Using template $paramod$4133fe00eb18442862a284ccc67a95f8194d041c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut. Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut. Using template $paramod$18368a3da11a7221c7fb674ec80ee0d0bd64b883\$lut for cells of type $lut. Using template $paramod$82a00bf0f959a345aaec45c197de61b70ee9c703\$lut for cells of type $lut. Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120\$lut for cells of type $lut. Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut. Using template $paramod$e50929688d8319f8cd7bdd627065cd59d2e91fe4\$lut for cells of type $lut. Using template $paramod$f7a897257decedfb6cc642e53d65fef7fc0df390\$lut for cells of type $lut. Using template $paramod$75ae9627805e0c99d176bdce0ae8ff0c02687aab\$lut for cells of type $lut. Using template $paramod$7ff054bf1849e35157c5493ac1b0fb5805fe014a\$lut for cells of type $lut. Using template $paramod$a81cf453a316218febe7a33c0cf3157f69dfa7dc\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut. Using template $paramod$39825c5ed3d135e502be79829033166f1762d78b\$lut for cells of type $lut. Using template $paramod$21a1ca6f9f5c15b304c8c46ce6cda8b91e063cf1\$lut for cells of type $lut. Using template $paramod$49f93da3bc72e2487024a93848b25121b5791efb\$lut for cells of type $lut. Using template $paramod$b455ae670d9c8dfd9a8351323c3c8064adab0ca3\$lut for cells of type $lut. Using template $paramod$ae6a86c125757108324af5e1de1be0d15f94f76e\$lut for cells of type $lut. Using template $paramod$8504d86f1088c038cefc453338e6ce07c755faf4\$lut for cells of type $lut. Using template $paramod$31b1afed6979f2cdee1b537cd42bf86a5659fe56\$lut for cells of type $lut. Using template $paramod$d8119e7cf18bdd1d72e1822e569d9c40a2fc5848\$lut for cells of type $lut. Using template $paramod$3fc32b40e3b4c5a5773908d058767dad56e4553d\$lut for cells of type $lut. Using template $paramod$100adb775e9727608a1dd57d3b5cdfbcdff7dc8a\$lut for cells of type $lut. Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut. Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut. Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut. Using template $paramod$c45b31c39ef0398de06172f315b1eb3ac962841d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. Using template $paramod$d08ae3e2fee668f1a68bd32fd012d46d229cb782\$lut for cells of type $lut. Using template $paramod$8d8a6111e2a82db0bfbd78666fa69c753d8df004\$lut for cells of type $lut. Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut. Using template $paramod$7a9b7d7d96d5349b2a3f800b325795fd17e50692\$lut for cells of type $lut. Using template $paramod$4d3ce2a03f75c776b89b7bd980aafa79b736b3c6\$lut for cells of type $lut. Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut. Using template $paramod$286ed3273cbe066b6afe10d043ec3b66405aa78e\$lut for cells of type $lut. Using template $paramod$333972bd8f7637b8cf38f0fc32364ec7a4dd1c02\$lut for cells of type $lut. Using template $paramod$c5e227af307b9c53329a9bcea914f98030ca9bc6\$lut for cells of type $lut. Using template $paramod$10352caa78a7d1fbb181ef6f61719dafe028589b\$lut for cells of type $lut. Using template $paramod$785192217a356b0d7e0772eb4b12ee1e5fe0b4c4\$lut for cells of type $lut. Using template $paramod$bedfb6ff92877d85732f9950ff60da1d31d4e17e\$lut for cells of type $lut. Using template $paramod$682dcf7a44e09cdf417bc55247ac658426f4c8e6\$lut for cells of type $lut. Using template $paramod$ce5c75e8689d86a2284735e9b1aaaf5cc40b83d5\$lut for cells of type $lut. Using template $paramod$b4a7c32164bf1092c3b6af97bb1c6821b8c22ad3\$lut for cells of type $lut. Using template $paramod$b698dd2b885039c9e1d53e243fc4e0191632dfd9\$lut for cells of type $lut. Using template $paramod$62008a5879a2c50141fb0d35185280c06907bf19\$lut for cells of type $lut. Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut. Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut. Using template $paramod$3f9a3800e34bd795630a4eaf44b2e1d4a7f48a74\$lut for cells of type $lut. Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f\$lut for cells of type $lut. Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut. Using template $paramod$a9ef64c6deb70a46d2aae4debf7ee3a62e9cab80\$lut for cells of type $lut. Using template $paramod$f5f41ee5d60dede31a2b59f58ec46b167939d713\$lut for cells of type $lut. Using template $paramod$e13156a22fa83545f7f55663d6f7c3e2833254df\$lut for cells of type $lut. Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. Using template $paramod$671ed0030d79054559119a43ece78828ceb97ee2\$lut for cells of type $lut. Using template $paramod$4609b78594455c119365db09d5686e5a19b5e34c\$lut for cells of type $lut. Using template $paramod$dd7c1583fe0ade167c7826c594e5d16b758a72fe\$lut for cells of type $lut. Using template $paramod$29fb0dcbea7e19908c494ce4a8a756b15e2a78b6\$lut for cells of type $lut. Using template $paramod$f109125ffdede8321ac65719b1066c75ff1eaef0\$lut for cells of type $lut. Using template $paramod$376f9826f7b15500613c50a4be731b02405c4ac4\$lut for cells of type $lut. Using template $paramod$b56552b15644de250f928c7e882226531acd70c9\$lut for cells of type $lut. Using template $paramod$440fc257ff71f43825756165ee27ac2beb8af188\$lut for cells of type $lut. Using template $paramod$3bc826339407d68f080842161835f11a965aed20\$lut for cells of type $lut. Using template $paramod$a08b5553a0b8825b754896808899f08d47a7f14e\$lut for cells of type $lut. Using template $paramod$6e3a03c79073e44642e8ed2dab4ee82dfd40dfba\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. Using template $paramod$6382f7860648fdb6f8a8dc690c25a62882cc501b\$lut for cells of type $lut. Using template $paramod$31387621d1610a0290872bbf4d90a41c51f62d2e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110101 for cells of type $lut. Using template $paramod$fc31732417b7be9ad8ea4524b9939a4cc422dcee\$lut for cells of type $lut. Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$6e4a86e6f1a5dc8f826898a131e83cdba4a4fc9e\$lut for cells of type $lut. Using template $paramod$137da1139b75bc63e28501c567008094083a8206\$lut for cells of type $lut. Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e\$lut for cells of type $lut. Using template $paramod$00da6ee835349555028231ae835c9b401a5c1dee\$lut for cells of type $lut. Using template $paramod$0168072450226b493f7201bdb9fc41a6a0b6f539\$lut for cells of type $lut. Using template $paramod$74b753a528e461d1e39fe2515916b34d124e6a14\$lut for cells of type $lut. Using template $paramod$50d0ed5c234a7335fb0b9558be3cce3681aa07a6\$lut for cells of type $lut. Using template $paramod$75e0e34d4dfcc6790c6d23b7c18487e4249acd2d\$lut for cells of type $lut. Using template $paramod$181733d3e31dcdcea8c52d0a4fc252b3aa453564\$lut for cells of type $lut. Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut. Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut. Using template $paramod$a719108d9c396525e0d07987640aa9393e771b89\$lut for cells of type $lut. Using template $paramod$62ec3aec26d96c2b9f32b2e7d07666e58cfd5f05\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut. Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod$19e5b38cca183d8b6b3a15d20dc995c09cd71893\$lut for cells of type $lut. Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2\$lut for cells of type $lut. Using template $paramod$7b42ee40460c24015b6f7a9841dbd2579367da0f\$lut for cells of type $lut. Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut. Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4\$lut for cells of type $lut. Using template $paramod$973394a6f8c13a435c2fa950b3fc699e041032a1\$lut for cells of type $lut. Using template $paramod$1608964cd44e926c22f8f8ce1065b9f3472e6f6d\$lut for cells of type $lut. Using template $paramod$a5e8c1e7cd3da97a7753a6d3982fd60e35cd98df\$lut for cells of type $lut. Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut. Using template $paramod$db6af21ea94ed22f9948a2d85897717bb02fa860\$lut for cells of type $lut. Using template $paramod$d111e7ef4c95d908e6ea5abb4e19619ecc8d8044\$lut for cells of type $lut. Using template $paramod$09b813bb6c5a558fc67def49aea529f64a1997b9\$lut for cells of type $lut. Using template $paramod$20aecb9a781743d0e93608b1c1e7d62ffc3a69a9\$lut for cells of type $lut. Using template $paramod$d5069ca035235e65bdd8a94fe440025b1dc5b469\$lut for cells of type $lut. Using template $paramod$863c404e3b83348ee34171710337d8e8efb7f8b2\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut. Using template $paramod$fe1497207981e9e4f2f9556fad9970ec052e0a6d\$lut for cells of type $lut. Using template $paramod$0b9bc34bc5bc0176cbdcd631f301593b211881b2\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. Using template $paramod$46a4c3f474ea31e3c4cf14519da23477f55d5a58\$lut for cells of type $lut. Using template $paramod$62e34d236b5cf9e50e7481784c0097067a15fba4\$lut for cells of type $lut. Using template $paramod$84004f0e0d52a00cc4e441af2eb9656c6f936131\$lut for cells of type $lut. Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut. Using template $paramod$f4257f9b9dfe762de25d0a149f2ea6e405c888f2\$lut for cells of type $lut. Using template $paramod$2ba51c7bf234f9ce3d769281ed286d6830810ff5\$lut for cells of type $lut. Using template $paramod$1f313f85ef575d13bac75382f04905a8c8be8f57\$lut for cells of type $lut. Using template $paramod$a1f4a64ca25b683307904a4d0b1fc3e866c70fbb\$lut for cells of type $lut. Using template $paramod$89ca3723ebb4dfdb3c4024f3f04b784a3e88f188\$lut for cells of type $lut. Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut. Using template $paramod$4a79186de344257676a91ff345ab1f2c676a1f82\$lut for cells of type $lut. Using template $paramod$fbe17bd8bf86b69b77487f81d886b2fccb4abeec\$lut for cells of type $lut. Using template $paramod$f62bf7b9bf368c5a044dd284e6192cdfb023ea0f\$lut for cells of type $lut. Using template $paramod$c101d02413e824957f961415409f37e87d695b11\$lut for cells of type $lut. Using template $paramod$bd5ab0e8aafd944724b16c86ac3df932003f970b\$lut for cells of type $lut. Using template $paramod$49637ade734e07e8ad89eefc6628a06bcc57ebe2\$lut for cells of type $lut. Using template $paramod$7f7120086b74d2ad6501bbaa30925c183268a1c2\$lut for cells of type $lut. Using template $paramod$0f1054d7a869eb1bffa14eab6537eeff64eb55da\$lut for cells of type $lut. Using template $paramod$ccd0ca33cca88a5f9dd0380c0483d68a8f2a8165\$lut for cells of type $lut. Using template $paramod$ef1cc14162296fd4d0d07385991da6aec0946444\$lut for cells of type $lut. Using template $paramod$0b411b7d1762b79400c7b7e65303823d9a001f59\$lut for cells of type $lut. Using template $paramod$5536a68d801b01a3adae6fa69e94ff752cb1d942\$lut for cells of type $lut. Using template $paramod$c69bd1e5c041e21522f7953a2df3248b5c81247c\$lut for cells of type $lut. Using template $paramod$2bc4db8bd4fb8d056f72dd182e27de9a154d9eee\$lut for cells of type $lut. Using template $paramod$9b5120652ba1719e45b6419c2d500e377154042f\$lut for cells of type $lut. Using template $paramod$129f5b55fa9a45614df91b4a79acd963ccf442b9\$lut for cells of type $lut. Using template $paramod$c68dfbd15f01829a95c6ef0c2d5ef109b6c9ab27\$lut for cells of type $lut. Using template $paramod$7c085cdbf0919cd3ad402d9495d97f0d71e4db93\$lut for cells of type $lut. Using template $paramod$e556cc25cbf7a7e4275a2d681487d87df1c5e8f8\$lut for cells of type $lut. Using template $paramod$1963b0805ad52a026a524678c1c755b3b833e0de\$lut for cells of type $lut. Using template $paramod$37863fb1d4b5c54888fbc168d735eadc19f59fdc\$lut for cells of type $lut. Using template $paramod$73123ef57cf5b679a999a57ecf6fb42fbb6533d3\$lut for cells of type $lut. Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514\$lut for cells of type $lut. Using template $paramod$55290dc5b2d325b1a51b6c31876bbb759b0b4b79\$lut for cells of type $lut. Using template $paramod$e684e947d725af21226ff9a9896770979345473f\$lut for cells of type $lut. Using template $paramod$4c0221505c29b55a66f4801128a7e9ab143964dc\$lut for cells of type $lut. Using template $paramod$050221686252202c3dcb014324b7b753c760a3f5\$lut for cells of type $lut. Using template $paramod$bc5e12b6f0294deb31680c53d3372629353cb418\$lut for cells of type $lut. Using template $paramod$a18efd9245448b0a198b87f7e710a6a1c17ab9de\$lut for cells of type $lut. Using template $paramod$8c0f019a61c0d22882e37a602acea8aadbc34527\$lut for cells of type $lut. Using template $paramod$fbd55d1b12935a22902cde46a0a7b6e309d6aa42\$lut for cells of type $lut. Using template $paramod$74bb18f03ae7d4d63f0045b9903bb94ae7da759a\$lut for cells of type $lut. Using template $paramod$418ccfc9e1257f2ae9b74be75eb51d31144c1072\$lut for cells of type $lut. Using template $paramod$afbb78ea2f898aa3cffa65de18f43b6b53d33ce1\$lut for cells of type $lut. Using template $paramod$d315acbf930db7c20b3f4ac2dad3b7982b1f437c\$lut for cells of type $lut. Using template $paramod$f24ba3ced4b870f8e829f5ac5a8af88573350e6f\$lut for cells of type $lut. Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut. Using template $paramod$d1e9dbd571a001347a9c2033df184d5283a0b7dd\$lut for cells of type $lut. Using template $paramod$18920b1c60eb7796d5277a53ea73aa0fb33f8801\$lut for cells of type $lut. Using template $paramod$8384e66d408d22ab39dfb451efb7879731befeb8\$lut for cells of type $lut. Using template $paramod$1313a6b1a6c981c250f4c9824fa8244853b185a0\$lut for cells of type $lut. Using template $paramod$72148f3545efac6f48701d6c21ae5eeb7a5f865b\$lut for cells of type $lut. Using template $paramod$f258f431a7c2fc52205873e71cd6683fdc689824\$lut for cells of type $lut. Using template $paramod$40f50322426372d948aaadc2f14dc77fbf5a9200\$lut for cells of type $lut. Using template $paramod$ce28387a24926807174fda3f6e095b6b4d11a89d\$lut for cells of type $lut. Using template $paramod$d0e42eec83ea592bf45e9ec906447f1ed04bd355\$lut for cells of type $lut. Using template $paramod$5350771ef649f966aea9542312c98451c55d975b\$lut for cells of type $lut. Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut. Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut. Using template $paramod$4ebbf381cf64b08e3304ae8194da41d0cd1eaa92\$lut for cells of type $lut. Using template $paramod$3749607c565908f31c3958f1cde3997ee2b605ef\$lut for cells of type $lut. Using template $paramod$5159aa72a9be8cd7c1ab392b987d253f353eb36d\$lut for cells of type $lut. Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut. Using template $paramod$84c5cfa8d7481774250caab0fcdd6d249a376a31\$lut for cells of type $lut. Using template $paramod$f03663c7f91be924d1e9df8220b895406b3f6489\$lut for cells of type $lut. Using template $paramod$130af793a2ec6ecceb3e0ef509cf6b180e856b6f\$lut for cells of type $lut. Using template $paramod$720138e033ca085bcb843caf4290749b9daa3724\$lut for cells of type $lut. Using template $paramod$758d9e8729b283bb3651b0fa835584bea2e26299\$lut for cells of type $lut. Using template $paramod$fdb7d2f78b1b1d86177579c82e917e4e8af6f77d\$lut for cells of type $lut. Using template $paramod$55f7d9850b8564509bff49b617d7ca817e320dc2\$lut for cells of type $lut. Using template $paramod$ddce54e04aa2e21dc36c3f216625e49798f2ceb0\$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut. Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut. Using template $paramod$ba4b1c9b57f942a38af35848615a2f06189d3bfe\$lut for cells of type $lut. Using template $paramod$fbed19fb84ee7c8a884778d28a96daea96245184\$lut for cells of type $lut. Using template $paramod$cba7d4f63aea5e4b3faf052f9f9805e0c6d202cb\$lut for cells of type $lut. Using template $paramod$2e94bd3f26faa1418da468862c21d0f40579ac6d\$lut for cells of type $lut. Using template $paramod$0199e84e12097fb5dd68a794423973d2ab777ac3\$lut for cells of type $lut. Using template $paramod$b66af2b8158579d12b02bd7ae4b5161b219e1924\$lut for cells of type $lut. Using template $paramod$4bf0340e251e6b71bc0d5237b346c714f1b8119e\$lut for cells of type $lut. Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71\$lut for cells of type $lut. Using template $paramod$262bfa094c1471fd1d7b6f0e3a507e88ada03a69\$lut for cells of type $lut. Using template $paramod$e2922126afb3c6df9be8375bf6f36b929cdc98c3\$lut for cells of type $lut. Using template $paramod$7328ff5203bb4525167eadf490aae4f747ef08ad\$lut for cells of type $lut. Using template $paramod$05f66240810e81b1a2e698a1f280f5252768dc46\$lut for cells of type $lut. Using template $paramod$1b9801dd9d6e50ba9290220e55993245830d035e\$lut for cells of type $lut. Using template $paramod$d9719b0f824f46dbdb84e92cc04e82fa43f39835\$lut for cells of type $lut. Using template $paramod$aaf2ef5cf75121bbc717334d538c8a2de3e26e03\$lut for cells of type $lut. Using template $paramod$49b034d0fa60c3e986a1c6dbe7a46c51627b5b93\$lut for cells of type $lut. Using template $paramod$4f6ef5838c139220e91b3d9534b74e9d61193cac\$lut for cells of type $lut. Using template $paramod$ea9f0804ffa1047d479d3e00429394419ff5856b\$lut for cells of type $lut. Using template $paramod$b574c1df31b19134bcccccd0450f90abe2dd8f26\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut. Using template $paramod$8b24fb07373c4ee224b517e500c9710a464b35dc\$lut for cells of type $lut. Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut. Using template $paramod$505ca6f83efadae0442899a08af73f5288142a52\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod$432f26b811c14bf54c5e87c8670ec65cbcaf38ac\$lut for cells of type $lut. Using template $paramod$75020cdf7715bd4a5f7067d80cafc74eabba6a01\$lut for cells of type $lut. Using template $paramod$e934877433e628b9aa4b7cb2bee8957bca3e1db5\$lut for cells of type $lut. Using template $paramod$14e62338c0694b7d80cbb5d0fd29f7c0d24a02a6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$031639056602a9dab4a0894878194a35372df974\$lut for cells of type $lut. Using template $paramod$609c49517ab794d57d991146438964a5de1a5cea\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. Using template $paramod$0e6f7067c2a44b2e3cbef1e1c87513a6042c22b4\$lut for cells of type $lut. Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111011 for cells of type $lut. Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut. Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a\$lut for cells of type $lut. Using template $paramod$de5328836923c44c99600bcab852423201246f91\$lut for cells of type $lut. Using template $paramod$71b6d833a4170eede1dcc8409c3fc7460c2df8d9\$lut for cells of type $lut. Using template $paramod$138253370bae6007e6e519350af9f987329e0b68\$lut for cells of type $lut. Using template $paramod$2a0e9830506418f5e4c5f66917d75cc61f44d1a8\$lut for cells of type $lut. Using template $paramod$4d673f44384ebded9d542bceabb0e9271e6f9336\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. No more expansions possible. <suppressed ~8298 debug messages> 22.44. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in top. Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73121.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73121.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$9497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$9492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$9492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$9492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$9258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$9258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$9258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$9258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$9238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$9238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[10].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[10].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[10].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[10].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[10].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[10].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$9204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$9204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$9204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$8604.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8604.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$8309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$8309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$8309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$8309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$8046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$8046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$8046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$auto$fsm_map.cc:170:map_fsm$2215[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7207.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7107.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72952.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72952.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$7062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$7062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$7062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7030.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$6985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6979.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72955.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6233.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6233.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72963.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$5979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$5869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$5738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$4355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$4346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$4346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$4346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$4346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$4346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$4340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$4257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$4257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$4257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$4257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$4257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$7331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$7331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$7331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$7331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6751.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$7119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$7119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$7119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$7119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72950.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72950.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$11332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$7423.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$7050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$7364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$7364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$7364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$7364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$6619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$5669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$5669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$5583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$5555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$5530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$10458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6109.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$6393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$10226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$5746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$5565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$4684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$5199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$4981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$4675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$4056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$4056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$4134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$4126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$4152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$10003.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10037.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$10049.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10187.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10193.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$10216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$10221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$10226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$10458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$10463.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$10656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$10832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$10740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10894.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10918.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$10943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$10950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11035.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11057.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$11121.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$11171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$11325.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$11332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$11365.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11412.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$11479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$11505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11516.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11523.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11541.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$11614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11619.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$11898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11928.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$11933.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$11967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$12045.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$12061.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$12068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$12075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$12086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$12093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$4068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$4112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$4126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$4138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$4152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$4126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$4165.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$4238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$4257.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4269.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$4280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$4355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$4667.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4698.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$4741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$4775.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4949.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73133.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$4985.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5344.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5130.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5203.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73179.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$5624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5249.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5290.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$5318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$5547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$5679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$5696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5746.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$5915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$5949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$5991.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6044.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6109.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$6067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6233.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$6393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6424.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6453.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6461.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$6641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6678.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6698.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6746.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6759.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6829.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6905.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$6972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$6992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7017.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7030.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$7176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$6483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$7386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$6793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7431.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7612.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$7687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$7787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$8046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$8053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$8309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$10009.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8598.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8604.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8796.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$8864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$8889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$8898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$8954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9249.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$9497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$9497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$9526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9655.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$aiger72871$9945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$72872$lut$auto$fsm_map.cc:170:map_fsm$2215[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut$auto$fsm_map.cc:170:map_fsm$2215[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$7700.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$72872$lut$auto$opt_dff.cc:219:make_patterns_logic$2404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut$aiger72871$11707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[10].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72964.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72936.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73060.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$72872$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72939.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72950.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72952.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$72872$lut$aiger72871$6771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$72978.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73117.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73121.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$72872$lut$aiger72871$5669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Removed 0 unused cells and 6899 unused wires. 22.45. Executing AUTONAME pass. read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1315.094 ; gain = 0.023 ; free physical = 2719 ; free virtual = 25884 # read_verilog ../../debug/reset.v # read_verilog ../../src/core/alu_control.v # read_verilog ../../src/core/alu.v # read_verilog ../../src/core/control_unit.v # read_verilog ../../src/core/core.v # read_verilog ../../src/core/immediate_generator.v # read_verilog ../../src/core/mux.v # read_verilog ../../src/core/pc.v # read_verilog ../../src/core/registers.v # read_verilog ../../src/core/csr_unit.v # read_verilog ../../src/peripheral/bus.v # read_verilog ../../src/peripheral/gpio.v # read_verilog ../../src/peripheral/gpios.v # read_verilog ../../src/peripheral/leds.v # read_verilog ../../src/peripheral/memory.v # read_verilog ../../src/peripheral/soc.v # read_verilog ../../src/peripheral/uart_rx.v # read_verilog ../../src/peripheral/uart_tx.v # read_verilog ../../src/peripheral/uart.v # read_verilog ../../src/peripheral/fifo.v # read_xdc "digilent_nexys4_ddr.xdc" # set_property PROCESSING_ORDER EARLY [get_files digilent_nexys4_ddr.xdc] # synth_design -top "top" -part "xc7a100tcsg324-1" Command: synth_design -top top -part xc7a100tcsg324-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' Renamed 327298 objects in module top (349 iterations). <suppressed ~11746 debug messages> 22.46. Executing HIERARCHY pass (managing design hierarchy). 22.46.1. Analyzing design hierarchy.. Top module: \top 22.46.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 22.47. Printing statistics. === top === Number of wires: 5430 Number of wire bits: 13174 Number of public wires: 5430 Number of public wire bits: 13174 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 6854 $_TBUF_ 6 $scopeinfo 30 CCU2C 326 L6MUX21 467 LUT4 4002 PFUMX 1029 TRELLIS_DPR16X4 292 TRELLIS_FF 702 22.48. Executing CHECK pass (checking for obvious problems). Checking module top... Found and reported 0 problems. 22.49. Executing JSON backend. Warnings: 213 unique messages, 214 total End of script. Logfile hash: dbab95a89c, CPU: user 7.64s system 0.08s, MEM: 222.38 MB peak Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) Time spent: 41% 1x abc9_exe (5 sec), 11% 11x techmap (1 sec), ... [Pipeline] } INFO: [Device 21-403] Loading part xc7a100tcsg324-1 [Pipeline] // stage [Pipeline] stage [Pipeline] { (NextPNR) [Pipeline] sh + /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained Info: constraining clock net 'clk' to 25.00 MHz Info: Logic utilisation before packing: Info: Total LUT4s: 6406/43848 14% Info: logic LUTs: 4002/43848 9% Info: carry LUTs: 652/43848 1% Info: RAM LUTs: 1168/ 5481 21% Info: RAMW LUTs: 584/10962 5% Info: Total DFFs: 702/43848 1% Info: Packing IOs.. Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'. Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'. Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'. Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'. Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'. Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'. Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'. Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'. Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'. Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'. Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'. Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'. Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'. Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'. Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'. Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'. Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'. Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 340 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: Checksum: 0x0e2a7dd5 Info: Device utilisation: Info: TRELLIS_IO: 18/ 245 7% Info: DCCA: 1/ 56 1% Info: DP16KD: 0/ 108 0% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 702/43848 1% Info: TRELLIS_COMB: 6498/43848 14% Info: TRELLIS_RAMW: 292/ 5481 5% Info: Placed 18 cells based on constraints. Info: Creating initial analytic placement for 3189 cells, random placement wirelen = 297925. Info: at initial placer iter 0, wirelen = 2976 Info: at initial placer iter 1, wirelen = 3254 Info: at initial placer iter 2, wirelen = 3034 Info: at initial placer iter 3, wirelen = 2925 Info: Running main analytical placer, max placement attempts per cell = 7051890. Info: at iteration #1, type ALL: wirelen solved = 2880, spread = 48571, legal = 49123; time = 0.16s Info: at iteration #2, type ALL: wirelen solved = 4792, spread = 37386, legal = 38031; time = 0.17s Info: at iteration #3, type ALL: wirelen solved = 6354, spread = 35931, legal = 36480; time = 0.17s INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 377133 /eda/vivado/Vivado/2023.2/bin/setupEnv.sh: line 236: [: /var/lib/jenkins/workspace/Risco: binary operator expected Info: at iteration #4, type ALL: wirelen solved = 7893, spread = 35727, legal = 36312; time = 0.17s Info: at iteration #5, type ALL: wirelen solved = 9458, spread = 32812, legal = 33420; time = 0.17s Info: at iteration #6, type ALL: wirelen solved = 10586, spread = 32238, legal = 33134; time = 0.17s Info: at iteration #7, type ALL: wirelen solved = 11279, spread = 30543, legal = 31143; time = 0.17s Info: at iteration #8, type ALL: wirelen solved = 12858, spread = 28683, legal = 29644; time = 0.16s Info: at iteration #9, type ALL: wirelen solved = 12630, spread = 27716, legal = 28646; time = 0.16s Info: at iteration #10, type ALL: wirelen solved = 12945, spread = 29163, legal = 29887; time = 0.16s Info: at iteration #11, type ALL: wirelen solved = 14505, spread = 29056, legal = 29557; time = 0.16s Info: at iteration #12, type ALL: wirelen solved = 14631, spread = 27555, legal = 28179; time = 0.16s Info: at iteration #13, type ALL: wirelen solved = 14959, spread = 26849, legal = 27636; time = 0.22s Info: at iteration #14, type ALL: wirelen solved = 15859, spread = 26671, legal = 27362; time = 0.17s Info: at iteration #15, type ALL: wirelen solved = 15789, spread = 26885, legal = 27766; time = 0.17s Info: at iteration #16, type ALL: wirelen solved = 16880, spread = 26441, legal = 27239; time = 0.15s Info: at iteration #17, type ALL: wirelen solved = 16751, spread = 26741, legal = 27439; time = 0.15s Info: at iteration #18, type ALL: wirelen solved = 17366, spread = 26290, legal = 27110; time = 0.15s Info: at iteration #19, type ALL: wirelen solved = 17389, spread = 26161, legal = 26973; time = 0.15s Info: at iteration #20, type ALL: wirelen solved = 17634, spread = 25976, legal = 26811; time = 0.15s Info: at iteration #21, type ALL: wirelen solved = 18415, spread = 25786, legal = 26591; time = 0.15s Info: at iteration #22, type ALL: wirelen solved = 18132, spread = 26458, legal = 27171; time = 0.15s Info: at iteration #23, type ALL: wirelen solved = 18513, spread = 26359, legal = 27195; time = 0.15s Info: at iteration #24, type ALL: wirelen solved = 18565, spread = 26066, legal = 27152; time = 0.15s Info: at iteration #25, type ALL: wirelen solved = 19027, spread = 26399, legal = 27142; time = 0.14s Info: at iteration #26, type ALL: wirelen solved = 19344, spread = 26395, legal = 27111; time = 0.15s Info: HeAP Placer Time: 6.48s Info: of which solving equations: 3.71s Info: of which spreading cells: 0.53s Info: of which strict legalisation: 0.19s Info: Running simulated annealing placer for refinement. --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2028.848 ; gain = 404.715 ; free physical = 1688 ; free virtual = 24862 --------------------------------------------------------------------------------- Info: at iteration #1: temp = 0.000000, timing cost = 4610, wirelen = 26591 INFO: [Synth 8-11241] undeclared symbol 'pc_source', assumed default net type 'wire' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:106] WARNING: [Synth 8-11065] parameter 'SET_DIRECTION' becomes localparam in 'GPIOS' with formal parameter declaration list [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/gpios.v:17] WARNING: [Synth 8-11065] parameter 'READ' becomes localparam in 'GPIOS' with formal parameter declaration list [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/gpios.v:18] WARNING: [Synth 8-9400] empty statement in sequential block [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/memory.v:40] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/uart_rx.v:17] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/uart_tx.v:16] INFO: [Synth 8-6157] synthesizing module 'top' [/var/lib/jenkins/workspace/Risco 5/Risco-5/fpga/nexys4_ddr/main.v:1] INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco 5/Risco-5/debug/reset.v:1] Parameter CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/debug/reset.v:1] WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco 5/Risco-5/fpga/nexys4_ddr/main.v:17] WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 3 connections declared, but only 2 given [/var/lib/jenkins/workspace/Risco 5/Risco-5/fpga/nexys4_ddr/main.v:17] INFO: [Synth 8-6157] synthesizing module 'Risco_5_SOC' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/soc.v:1] Parameter CLOCK_FREQ bound to: 100000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter MEMORY_SIZE bound to: 2048 - type: integer Parameter MEMORY_FILE bound to: ../../software/memory/fpga_test_3.hex - type: string Parameter GPIO_WIDHT bound to: 8 - type: integer INFO: [Synth 8-6157] synthesizing module 'Core' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:1] Parameter BOOT_ADDRESS bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'PC' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/pc.v:1] INFO: [Synth 8-6155] done synthesizing module 'PC' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/pc.v:1] INFO: [Synth 8-6157] synthesizing module 'MUX' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/mux.v:1] INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/mux.v:11] INFO: [Synth 8-6155] done synthesizing module 'MUX' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/mux.v:1] WARNING: [Synth 8-7071] port 'C' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:73] WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:73] WARNING: [Synth 8-7023] instance 'MemoryAddressMUX' of module 'MUX' has 6 connections declared, but only 4 given [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:73] WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'MemoryDataMUX' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:80] WARNING: [Synth 8-7023] instance 'MemoryDataMUX' of module 'MUX' has 6 connections declared, but only 5 given [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:80] WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'AluInputBMUX' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:97] WARNING: [Synth 8-7023] instance 'AluInputBMUX' of module 'MUX' has 6 connections declared, but only 5 given [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:97] WARNING: [Synth 8-7071] port 'C' of module 'MUX' is unconnected for instance 'PCSourceMUX' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:105] WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'PCSourceMUX' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:105] WARNING: [Synth 8-7023] instance 'PCSourceMUX' of module 'MUX' has 6 connections declared, but only 4 given [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:105] INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/registers.v:1] INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/registers.v:1] INFO: [Synth 8-6157] synthesizing module 'Control_Unit' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/control_unit.v:1] INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/control_unit.v:82] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/control_unit.v:86] INFO: [Synth 8-6155] done synthesizing module 'Control_Unit' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/control_unit.v:1] INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/alu_control.v:1] INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/alu_control.v:33] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/alu_control.v:10] INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/alu_control.v:1] INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/alu.v:1] INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/alu.v:1] INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/immediate_generator.v:1] INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/immediate_generator.v:1] INFO: [Synth 8-6157] synthesizing module 'CSR_Unit' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/csr_unit.v:1] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/csr_unit.v:127] INFO: [Synth 8-6155] done synthesizing module 'CSR_Unit' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/csr_unit.v:1] WARNING: [Synth 8-7071] port 'irq_external' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:168] WARNING: [Synth 8-7071] port 'irq_timer' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:168] WARNING: [Synth 8-7071] port 'irq_software' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:168] WARNING: [Synth 8-7071] port 'irq_fast' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:168] WARNING: [Synth 8-7023] instance 'CSR_Unit' of module 'CSR_Unit' has 12 connections declared, but only 8 given [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:168] INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/core.v:1] INFO: [Synth 8-6157] synthesizing module 'Memory' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/memory.v:1] Parameter MEMORY_FILE bound to: ../../software/memory/fpga_test_3.hex - type: string Parameter MEMORY_SIZE bound to: 2048 - type: integer INFO: [Synth 8-3876] $readmem data file '../../software/memory/fpga_test_3.hex' is read successfully [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/memory.v:29] INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/memory.v:1] INFO: [Synth 8-6157] synthesizing module 'BUS' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/bus.v:1] INFO: [Synth 8-6155] done synthesizing module 'BUS' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/bus.v:1] INFO: [Synth 8-6157] synthesizing module 'LEDs' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/leds.v:1] INFO: [Synth 8-6155] done synthesizing module 'LEDs' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/leds.v:1] INFO: [Synth 8-6157] synthesizing module 'UART' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/uart.v:1] Parameter CLOCK_FREQ bound to: 100000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer INFO: [Synth 8-6157] synthesizing module 'FIFO' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/fifo.v:1] Parameter DEPTH bound to: 8 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/fifo.v:1] INFO: [Synth 8-6157] synthesizing module 'uart_tool_rx' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/uart_rx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 100000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tool_rx' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/uart_rx.v:10] INFO: [Synth 8-6157] synthesizing module 'uart_tool_tx' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/uart_tx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 100000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tool_tx' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/uart_tx.v:10] INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/uart.v:1] INFO: [Synth 8-6157] synthesizing module 'GPIOS' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/gpios.v:1] Parameter WIDHT bound to: 8 - type: integer INFO: [Synth 8-6157] synthesizing module 'GPIO' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/gpio.v:1] INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/gpio.v:1] INFO: [Synth 8-6155] done synthesizing module 'GPIOS' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/gpios.v:1] INFO: [Synth 8-6155] done synthesizing module 'Risco_5_SOC' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/soc.v:1] INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/var/lib/jenkins/workspace/Risco 5/Risco-5/fpga/nexys4_ddr/main.v:1] WARNING: [Synth 8-6014] Unused sequential element buffer_full_reg was removed. [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/uart.v:49] WARNING: [Synth 8-6014] Unused sequential element tx_fifo_read_reg was removed. [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/peripheral/uart.v:43] WARNING: [Synth 8-7129] Port address[31] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[7] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[6] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[5] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[4] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[3] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[2] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[1] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[16] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[15] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[14] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[13] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[12] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[11] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[10] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[9] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[8] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[31] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[30] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[29] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[28] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[27] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[26] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[25] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[24] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[23] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[22] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[21] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[20] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[19] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[18] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[17] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[16] in module UART is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2113.816 ; gain = 489.684 ; free physical = 1543 ; free virtual = 24717 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2131.629 ; gain = 507.496 ; free physical = 1540 ; free virtual = 24715 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2131.629 ; gain = 507.496 ; free physical = 1540 ; free virtual = 24715 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2131.629 ; gain = 0.000 ; free physical = 1540 ; free virtual = 24715 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/var/lib/jenkins/workspace/Risco 5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] Info: at iteration #5: temp = 0.000000, timing cost = 5048, wirelen = 23674 Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco 5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco 5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2279.379 ; gain = 0.000 ; free physical = 1522 ; free virtual = 24697 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. lscpu: bad usage Try 'lscpu --help' for more information. Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2279.414 ; gain = 0.000 ; free physical = 1522 ; free virtual = 24697 Info: at iteration #10: temp = 0.000000, timing cost = 4978, wirelen = 22873 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2279.414 ; gain = 655.281 ; free physical = 1520 ; free virtual = 24695 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2279.414 ; gain = 655.281 ; free physical = 1520 ; free virtual = 24695 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2279.414 ; gain = 655.281 ; free physical = 1520 ; free virtual = 24695 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RESET_COUNTER | 00 | 01 IDLE | 01 | 10 INIT | 10 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FETCH | 0000000000000001 | 0000 DECODE | 0000000000000010 | 0001 MEMADR | 0000000000000100 | 0010 MEMREAD | 0000000000001000 | 0011 MEMWB | 0000000000010000 | 0100 MEMWRITE | 0000000000100000 | 0101 EXECUTER | 0000000001000000 | 0110 EXECUTEI | 0000000010000000 | 1000 JAL | 0000000100000000 | 1001 BEQ | 0000001000000000 | 1010 AUIPC | 0000010000000000 | 1100 LUI | 0000100000000000 | 1101 JALR_PC | 0001000000000000 | 1110 JALR | 0010000000000000 | 1011 ALUWB | 0100000000000000 | 0111 EXECUTECSR | 1000000000000000 | 1111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit' WARNING: [Synth 8-327] inferring latch for variable 'aluop_out_reg' [/var/lib/jenkins/workspace/Risco 5/Risco-5/src/core/alu_control.v:12] --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_RECV | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_SEND | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2279.414 ; gain = 655.281 ; free physical = 1520 ; free virtual = 24696 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 3 Input 32 Bit Adders := 1 2 Input 11 Bit Adders := 2 2 Input 6 Bit Adders := 4 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---XORs : 2 Input 32 Bit XORs := 1 +---Registers : 33 Bit Registers := 1 32 Bit Registers := 44 16 Bit Registers := 2 11 Bit Registers := 2 8 Bit Registers := 8 6 Bit Registers := 1 4 Bit Registers := 2 1 Bit Registers := 17 +---RAMs : 16K Bit (512 X 32 bit) RAMs := 1 64 Bit (8 X 8 bit) RAMs := 2 +---Muxes : 3 Input 33 Bit Muxes := 1 4 Input 32 Bit Muxes := 19 2 Input 32 Bit Muxes := 36 8 Input 32 Bit Muxes := 1 16 Input 32 Bit Muxes := 1 16 Input 16 Bit Muxes := 1 11 Input 16 Bit Muxes := 1 2 Input 16 Bit Muxes := 1 2 Input 8 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 3 Input 6 Bit Muxes := 1 2 Input 6 Bit Muxes := 4 2 Input 5 Bit Muxes := 1 10 Input 4 Bit Muxes := 1 8 Input 4 Bit Muxes := 1 23 Input 4 Bit Muxes := 1 10 Input 3 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 15 16 Input 2 Bit Muxes := 3 4 Input 2 Bit Muxes := 4 3 Input 1 Bit Muxes := 6 2 Input 1 Bit Muxes := 49 16 Input 1 Bit Muxes := 6 4 Input 1 Bit Muxes := 2 13 Input 1 Bit Muxes := 2 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met Info: at iteration #15: temp = 0.000000, timing cost = 4459, wirelen = 22271 INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template. Info: at iteration #20: temp = 0.000000, timing cost = 4590, wirelen = 22141 Info: at iteration #24: temp = 0.000000, timing cost = 4375, wirelen = 22091 Info: SA placement time 19.07s Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 38.42 MHz (PASS at 25.00 MHz) Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 11.75 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.28 ns Info: Slack histogram: Info: legend: * represents 44 endpoint(s) Info: + represents [1,44) endpoint(s) Info: [ 13975, 15239) |*+ Info: [ 15239, 16503) |*+ Info: [ 16503, 17767) |+ Info: [ 17767, 19031) |*****+ Info: [ 19031, 20295) |********+ Info: [ 20295, 21559) |***+ Info: [ 21559, 22823) |********+ Info: [ 22823, 24087) |*************** Info: [ 24087, 25351) |****************************+ Info: [ 25351, 26615) |************************************************************ Info: [ 26615, 27879) |*************************+ Info: [ 27879, 29143) |***********+ Info: [ 29143, 30407) |*+ Info: [ 30407, 31671) |*+ Info: [ 31671, 32935) |+ Info: [ 32935, 34199) |*+ Info: [ 34199, 35463) |********+ Info: [ 35463, 36727) |*******+ Info: [ 36727, 37991) |****+ Info: [ 37991, 39255) |**+ Info: Checksum: 0x29e3ab71 Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 28555 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 62 937 | 62 937 | 27812| 0.63 0.63| Info: 2000 | 244 1755 | 182 818 | 27035| 0.29 0.92| Info: 3000 | 380 2619 | 136 864 | 26472| 0.28 1.20| Info: 4000 | 491 3508 | 111 889 | 26033| 0.27 1.47| Info: 5000 | 609 4390 | 118 882 | 25435| 0.26 1.73| Info: 6000 | 741 5258 | 132 868 | 24681| 0.25 1.98| Info: 7000 | 880 6119 | 139 861 | 23897| 0.26 2.24| --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 2279.414 ; gain = 655.281 ; free physical = 1481 ; free virtual = 24664 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Preliminary Mapping Report (see note below) +------------+-----------------------------+-----------+----------------------+-----------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-----------------------------+-----------+----------------------+-----------------+ |top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 | |top | SOC/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |top | SOC/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | +------------+-----------------------------+-----------+----------------------+-----------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Info: 8000 | 1048 6951 | 168 832 | 23178| 0.27 2.52| Info: 9000 | 1215 7784 | 167 833 | 22464| 0.26 2.77| Info: 10000 | 1400 8599 | 185 815 | 21726| 0.26 3.03| Info: 11000 | 1603 9396 | 203 797 | 21041| 0.27 3.30| Info: 12000 | 1768 10231 | 165 835 | 20312| 0.26 3.56| Info: 13000 | 1925 11074 | 157 843 | 19814| 0.25 3.81| Info: 14000 | 2145 11854 | 220 780 | 19183| 0.27 4.08| Info: 15000 | 2413 12586 | 268 732 | 18536| 0.28 4.36| Info: 16000 | 2659 13340 | 246 754 | 17860| 0.28 4.64| Info: 17000 | 2920 14079 | 261 739 | 17247| 0.30 4.94| Info: 18000 | 3207 14792 | 287 713 | 16681| 0.31 5.25| Info: 19000 | 3498 15501 | 291 709 | 16069| 0.30 5.55| Info: 20000 | 3776 16223 | 278 722 | 15434| 0.30 5.86| Info: 21000 | 4128 16871 | 352 648 | 14995| 0.32 6.18| Info: 22000 | 4491 17508 | 363 637 | 14489| 0.31 6.49| Info: 23000 | 4885 18114 | 394 606 | 14000| 0.31 6.81| Info: 24000 | 5238 18761 | 353 647 | 13479| 0.32 7.12| Info: 25000 | 5687 19312 | 449 551 | 13055| 0.28 7.40| Info: 26000 | 6139 19860 | 452 548 | 12662| 0.32 7.72| --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:32 . Memory (MB): peak = 2279.414 ; gain = 655.281 ; free physical = 1478 ; free virtual = 24661 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Info: 27000 | 6604 20395 | 465 535 | 12235| 0.31 8.03| Info: 28000 | 7067 20932 | 463 537 | 11830| 0.33 8.36| Info: 29000 | 7546 21453 | 479 521 | 11401| 0.34 8.70| Info: 30000 | 8032 21960 | 486 507 | 10982| 0.30 9.00| Info: 31000 | 8379 22448 | 347 488 | 10478| 0.25 9.25| Info: 32000 | 8747 22957 | 368 509 | 9953| 0.23 9.48| Info: 33000 | 9078 23500 | 331 543 | 9364| 0.25 9.73| Info: 34000 | 9416 24063 | 338 563 | 8751| 0.25 9.98| Info: 35000 | 9714 24706 | 298 643 | 8114| 0.21 10.19| Info: 36000 | 10032 25329 | 318 623 | 7466| 0.22 10.41| Info: 37000 | 10331 25942 | 299 613 | 6781| 0.22 10.64| Info: 38000 | 10684 26489 | 353 547 | 6188| 0.25 10.88| Info: 39000 | 10801 27322 | 117 833 | 5321| 0.16 11.05| Info: 40000 | 10825 28283 | 24 961 | 4345| 0.07 11.12| Info: 41000 | 10841 29263 | 16 980 | 3367| 0.08 11.19| Info: 42000 | 10949 30135 | 108 872 | 2482| 0.15 11.34| Info: 43000 | 11133 30911 | 184 776 | 1681| 0.25 11.59| --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 2279.414 ; gain = 655.281 ; free physical = 1476 ; free virtual = 24659 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +------------+-----------------------------+-----------+----------------------+-----------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-----------------------------+-----------+----------------------+-----------------+ |top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 | |top | SOC/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |top | SOC/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | +------------+-----------------------------+-----------+----------------------+-----------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Info: 44000 | 11203 31739 | 70 828 | 757| 0.20 11.79| Info: 44762 | 11209 32156 | 6 417 | 0| 0.11 11.90| Info: Routing complete. Info: Router1 time 11.90s Info: Checksum: 0x88734f3f Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q.Q Info: 0.9 1.5 Net SOC.Core.Control_Unit.nextstate_L6MUX21_Z_D0_PFUMX_Z_C0[0] (18,27) -> (19,27) Info: Sink SOC.Core.Control_Unit.nextstate_PFUMX_Z_1_C0_LUT4_Z_B_LUT4_D_B_LUT4_D_Z_PFUMX_ALUT_C0_LUT4_D_1_Z_LUT4_Z.A Info: Defined in: Info: Risco-5/src/core/control_unit.v:51.11-51.16 Info: 0.2 1.7 Source SOC.Core.Control_Unit.nextstate_PFUMX_Z_1_C0_LUT4_Z_B_LUT4_D_B_LUT4_D_Z_PFUMX_ALUT_C0_LUT4_D_1_Z_LUT4_Z.F Info: 1.7 3.4 Net SOC.Core.Control_Unit.nextstate_PFUMX_Z_1_C0_LUT4_Z_B_LUT4_D_B_LUT4_D_Z_PFUMX_ALUT_C0_LUT4_D_1_Z[1] (19,27) -> (13,38) Info: Sink SOC.Core.Control_Unit.nextstate_PFUMX_Z_1_C0_LUT4_Z_B_LUT4_D_C_L6MUX21_SD_Z_LUT4_Z_B_LUT4_Z.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 3.6 Source SOC.Core.Control_Unit.nextstate_PFUMX_Z_1_C0_LUT4_Z_B_LUT4_D_C_L6MUX21_SD_Z_LUT4_Z_B_LUT4_Z.F Info: 0.6 4.2 Net SOC.Core.Control_Unit.nextstate_PFUMX_Z_1_C0_LUT4_Z_B_LUT4_D_C_L6MUX21_SD_Z_LUT4_Z_B[2] (13,38) -> (13,38) Info: Sink SOC.Core.Control_Unit.nextstate_PFUMX_Z_1_C0_LUT4_Z_B_LUT4_D_C_L6MUX21_SD_Z_LUT4_Z_B_LUT4_B.C Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.4 4.6 Source SOC.Core.Control_Unit.nextstate_PFUMX_Z_1_C0_LUT4_Z_B_LUT4_D_C_L6MUX21_SD_Z_LUT4_Z_B_LUT4_B.OFX Info: 1.4 6.0 Net SOC.Core.Control_Unit.nextstate_PFUMX_Z_1_C0_LUT4_Z_B_LUT4_D_C_L6MUX21_SD_Z_LUT4_Z_B_PFUMX_C0_Z[3] (13,38) -> (14,33) Info: Sink SOC.Core.Control_Unit.nextstate_PFUMX_Z_1_C0_LUT4_Z_B_LUT4_D_B_LUT4_D_Z_PFUMX_ALUT_C0_LUT4_B_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 6.3 Source SOC.Core.Control_Unit.nextstate_PFUMX_Z_1_C0_LUT4_Z_B_LUT4_D_B_LUT4_D_Z_PFUMX_ALUT_C0_LUT4_B_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z.F Info: 0.0 6.3 Net SOC.Core.Control_Unit.nextstate_PFUMX_Z_1_C0_LUT4_Z_B_LUT4_D_B_LUT4_D_Z_PFUMX_ALUT_C0_LUT4_B_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT (14,33) -> (14,33) Info: Sink SOC.Core.Control_Unit.nextstate_PFUMX_Z_1_C0_LUT4_Z_B_LUT4_D_B_LUT4_D_Z_PFUMX_ALUT_C0_LUT4_B_Z_PFUMX_BLUT_Z_PFUMX_Z_BLUT_LUT4_Z.F1 Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24 Info: 0.2 6.4 Source SOC.Core.Control_Unit.nextstate_PFUMX_Z_1_C0_LUT4_Z_B_LUT4_D_B_LUT4_D_Z_PFUMX_ALUT_C0_LUT4_B_Z_PFUMX_BLUT_Z_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 1.4 7.8 Net SOC.Core.Control_Unit.nextstate_PFUMX_Z_1_C0_LUT4_Z_B_LUT4_D_B_LUT4_D_Z_PFUMX_ALUT_C0_LUT4_B_Z_PFUMX_BLUT_Z[6] (14,33) -> (16,24) Info: Sink SOC.Core.CSR_Unit.csr_mie_msie_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_C_LUT4_Z_D_LUT4_Z_C_LUT4_C_3_Z_LUT4_D_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 8.1 Source SOC.Core.CSR_Unit.csr_mie_msie_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_C_LUT4_Z_D_LUT4_Z_C_LUT4_C_3_Z_LUT4_D_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 1.5 9.6 Net SOC.Core.CSR_Unit.csr_mie_msie_LUT4_A_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_C_LUT4_Z_D_LUT4_Z_C_LUT4_C_3_Z_LUT4_D_Z[5] (16,24) -> (13,14) Info: Sink SOC.Core.Control_Unit.nextstate_PFUMX_Z_1_C0_LUT4_Z_B_LUT4_D_C_LUT4_D_1_Z_LUT4_C_Z_PFUMX_BLUT_Z_PFUMX_C0_Z_PFUMX_C0_1_ALUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 9.9 Source SOC.Core.Control_Unit.nextstate_PFUMX_Z_1_C0_LUT4_Z_B_LUT4_D_C_LUT4_D_1_Z_LUT4_C_Z_PFUMX_BLUT_Z_PFUMX_C0_Z_PFUMX_C0_1_ALUT_LUT4_Z.OFX Info: 1.5 11.4 Net SOC.Core.Alu.ALU_out_S_L6MUX21_Z_1_SD_LUT4_Z_C[3] (13,14) -> (13,2) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_9_A_PFUMX_Z_1_C0_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 11.7 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_9_A_PFUMX_Z_1_C0_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 0.6 12.3 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_12_C_LUT4_Z_1_B_PFUMX_Z_C0[2] (13,2) -> (13,3) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_7_C_LUT4_Z_B_CCU2C_S0_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 12.6 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_7_C_LUT4_Z_B_CCU2C_S0_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 0.0 12.6 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_7_C_LUT4_Z_B_CCU2C_S0_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 (13,3) -> (13,3) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_7_C_LUT4_Z_B_CCU2C_S0_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.62-157.64 Info: 0.2 12.8 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_7_C_LUT4_Z_B_CCU2C_S0_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 0.0 12.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_7_C_LUT4_Z_B_CCU2C_S0_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_PFUMX_C0_Z_L6MUX21_Z_D1 (13,3) -> (13,3) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_7_C_LUT4_Z_B_CCU2C_S0_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72 Info: 0.2 13.0 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_7_C_LUT4_Z_B_CCU2C_S0_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 1.1 14.1 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_7_C_LUT4_Z_B_CCU2C_S0_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_PFUMX_C0_Z[5] (13,3) -> (15,5) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_7_C_LUT4_Z_B_CCU2C_S0_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z_2.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 14.4 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_7_C_LUT4_Z_B_CCU2C_S0_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z_2.F Info: 1.6 16.0 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_7_C_LUT4_Z_B_CCU2C_S0_S1_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_S1_LUT4_D_Z_PFUMX_C0_Z[5] (15,5) -> (15,17) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_A_Z_L6MUX21_Z_2_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 16.2 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_A_Z_L6MUX21_Z_2_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 0.9 17.2 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_A_Z_L6MUX21_Z_2_SD[4] (15,17) -> (7,17) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_A_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 17.4 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_A_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 0.0 17.4 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_A_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1 (7,17) -> (7,17) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_A_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.62-157.64 Info: 0.2 17.7 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_A_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 0.0 17.7 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_A_Z_L6MUX21_Z_2_D1 (7,17) -> (7,17) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_A_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72 Info: 0.2 17.9 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_A_Z_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 1.2 19.1 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_A_Z[6] (7,17) -> (15,18) Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 19.3 Source SOC.Core.Pc.load_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 1.3 20.6 Net SOC.Core.pc_load (15,18) -> (5,17) Info: Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_27.CE Info: Defined in: Info: Risco-5/src/core/core.v:42.38-42.45 Info: 0.0 20.6 Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_27.CE Info: 4.8 ns logic, 15.8 ns routing Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: curr total Info: 0.0 0.0 Source gpios[2]$tr_io.O Info: 5.4 5.4 Net gpios[2]$TRELLIS_IO_IN (90,23) -> (10,24) Info: Sink SOC.GPIOS.Gpios[2].direction_LUT4_C.B Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:7.16-7.21 Info: 0.2 5.6 Source SOC.GPIOS.Gpios[2].direction_LUT4_C.F Info: 0.6 6.2 Net SOC.GPIOS.Gpios[2].direction_LUT4_C_Z[2] (10,24) -> (10,24) Info: Sink SOC.GPIOS.Gpios[2].direction_LUT4_C_Z_LUT4_C.C Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 6.5 Source SOC.GPIOS.Gpios[2].direction_LUT4_C_Z_LUT4_C.F Info: 1.3 7.8 Net SOC.GPIOS.Gpios[2].direction_LUT4_C_Z_LUT4_C_Z[2] (10,24) -> (9,27) Info: Sink SOC.Core.read_data_LUT4_Z_17.C Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 8.0 Source SOC.Core.read_data_LUT4_Z_17.F Info: 1.6 9.6 Net SOC.read_data[2] (9,27) -> (15,36) Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_29.M Info: Defined in: Info: Risco-5/src/peripheral/soc.v:21.34-21.43 Info: 0.0 9.6 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_29.M Info: 0.7 ns logic, 8.9 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>': Info: curr total Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_29.Q Info: 4.2 4.7 Net SOC.Leds.data[2] (21,26) -> (80,35) Info: Sink led_LUT4_Z.D Info: Defined in: Info: Risco-5/src/peripheral/leds.v:15.12-15.16 Info: 0.2 4.9 Source led_LUT4_Z.F Info: 1.8 6.8 Net led[2]$TRELLIS_IO_OUT (80,35) -> (90,44) Info: Sink led[2]$tr_io.I Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:6.22-6.25 Info: 0.8 ns logic, 6.0 ns routing Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 48.52 MHz (PASS at 25.00 MHz) Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 9.63 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.76 ns Info: Slack histogram: Info: legend: * represents 51 endpoint(s) Info: + represents [1,51) endpoint(s) Info: [ 19388, 20372) |+ Info: [ 20372, 21356) |*+ Info: [ 21356, 22340) |********+ Info: [ 22340, 23324) |***+ Info: [ 23324, 24308) |*+ Info: [ 24308, 25292) |**+ Info: [ 25292, 26276) |**********+ Info: [ 26276, 27260) |**************+ Info: [ 27260, 28244) |************+ Info: [ 28244, 29228) |************************************************************ Info: [ 29228, 30212) |************************+ Info: [ 30212, 31196) |+ Info: [ 31196, 32180) |********+ Info: [ 32180, 33164) |***+ Info: [ 33164, 34148) |*+ Info: [ 34148, 35132) |*+ Info: [ 35132, 36116) |***+ Info: [ 36116, 37100) |*******+ Info: [ 37100, 38084) |****+ Info: [ 38084, 39068) |***+ Info: Program finished normally. [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (ECPPACK) --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2279.414 ; gain = 655.281 ; free physical = 1700 ; free virtual = 24902 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- [Pipeline] sh + /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // stage [Pipeline] } --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2279.414 ; gain = 655.281 ; free physical = 1697 ; free virtual = 24900 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2279.414 ; gain = 655.281 ; free physical = 1697 ; free virtual = 24900 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2279.414 ; gain = 655.281 ; free physical = 1697 ; free virtual = 24900 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2279.414 ; gain = 655.281 ; free physical = 1697 ; free virtual = 24900 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2279.414 ; gain = 655.281 ; free physical = 1697 ; free virtual = 24900 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2279.414 ; gain = 655.281 ; free physical = 1697 ; free virtual = 24900 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFG | 1| |2 |CARRY4 | 55| |3 |LUT1 | 10| |4 |LUT2 | 140| |5 |LUT3 | 51| |6 |LUT4 | 141| |7 |LUT5 | 371| |8 |LUT6 | 1366| |9 |MUXF7 | 256| |10 |RAM256X1S | 64| |11 |RAM32M | 2| |12 |RAM32X1D | 4| |13 |FDRE | 1739| |14 |FDSE | 5| |15 |LD | 4| |16 |IBUF | 2| |17 |IOBUF | 8| |18 |OBUF | 9| +------+----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2279.414 ; gain = 655.281 ; free physical = 1697 ; free virtual = 24900 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 9 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2279.414 ; gain = 507.496 ; free physical = 1697 ; free virtual = 24900 Synthesis Optimization Complete : Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2279.414 ; gain = 655.281 ; free physical = 1697 ; free virtual = 24900 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2279.414 ; gain = 0.000 ; free physical = 1985 ; free virtual = 25188 INFO: [Netlist 29-17] Analyzing 393 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/var/lib/jenkins/workspace/Risco 5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco 5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2351.410 ; gain = 0.000 ; free physical = 1982 ; free virtual = 25185 INFO: [Project 1-111] Unisim Transformation Summary: A total of 82 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 8 instances LD => LDCE: 4 instances RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances lscpu: bad usage Try 'lscpu --help' for more information. Synth Design complete | Checksum: 8250af15 INFO: [Common 17-83] Releasing license: Synthesis 75 Infos, 126 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:52 ; elapsed = 00:00:49 . Memory (MB): peak = 2351.445 ; gain = 1036.352 ; free physical = 1983 ; free virtual = 25186 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2071.157; main = 1782.172; forked = 435.756 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3237.895; main = 2351.414; forked = 982.527 # opt_design Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.64 . Memory (MB): peak = 2415.441 ; gain = 63.996 ; free physical = 1983 ; free virtual = 25186 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 143e2baec Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2519.262 ; gain = 103.820 ; free physical = 1948 ; free virtual = 25151 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 143e2baec Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2771.137 ; gain = 0.000 ; free physical = 1678 ; free virtual = 24880 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 143e2baec Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2771.137 ; gain = 0.000 ; free physical = 1678 ; free virtual = 24880 Phase 1 Initialization | Checksum: 143e2baec Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2771.137 ; gain = 0.000 ; free physical = 1678 ; free virtual = 24880 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 143e2baec Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2771.137 ; gain = 0.000 ; free physical = 1677 ; free virtual = 24880 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 143e2baec Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2771.137 ; gain = 0.000 ; free physical = 1677 ; free virtual = 24880 Phase 2 Timer Update And Timing Data Collection | Checksum: 143e2baec Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2771.137 ; gain = 0.000 ; free physical = 1677 ; free virtual = 24880 Phase 3 Retarget INFO: [Opt 31-1566] Pulled 2 inverters resulting in an inversion of 6 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 204605c91 Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2771.137 ; gain = 0.000 ; free physical = 1677 ; free virtual = 24880 Retarget | Checksum: 204605c91 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 2 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 204605c91 Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2771.137 ; gain = 0.000 ; free physical = 1677 ; free virtual = 24880 Constant propagation | Checksum: 204605c91 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep Phase 5 Sweep | Checksum: 15dad2d02 Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.2 . Memory (MB): peak = 2771.137 ; gain = 0.000 ; free physical = 1677 ; free virtual = 24880 Sweep | Checksum: 15dad2d02 INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 0 cells Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 15dad2d02 Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2803.152 ; gain = 32.016 ; free physical = 1677 ; free virtual = 24880 BUFG optimization | Checksum: 15dad2d02 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 15dad2d02 Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2803.152 ; gain = 32.016 ; free physical = 1677 ; free virtual = 24880 Shift Register Optimization | Checksum: 15dad2d02 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 14a4ea2af Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2803.152 ; gain = 32.016 ; free physical = 1677 ; free virtual = 24880 Post Processing Netlist | Checksum: 14a4ea2af INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1cf01f192 Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2803.152 ; gain = 32.016 ; free physical = 1677 ; free virtual = 24880 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.152 ; gain = 0.000 ; free physical = 1677 ; free virtual = 24880 Phase 9.2 Verifying Netlist Connectivity | Checksum: 1cf01f192 Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.3 . Memory (MB): peak = 2803.152 ; gain = 32.016 ; free physical = 1677 ; free virtual = 24880 Phase 9 Finalization | Checksum: 1cf01f192 Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.3 . Memory (MB): peak = 2803.152 ; gain = 32.016 ; free physical = 1677 ; free virtual = 24880 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 2 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 8 | 0 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 1cf01f192 Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.3 . Memory (MB): peak = 2803.152 ; gain = 32.016 ; free physical = 1677 ; free virtual = 24880 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.152 ; gain = 0.000 ; free physical = 1677 ; free virtual = 24880 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 1cf01f192 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2803.152 ; gain = 0.000 ; free physical = 1677 ; free virtual = 24880 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 1cf01f192 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.152 ; gain = 0.000 ; free physical = 1677 ; free virtual = 24880 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.152 ; gain = 0.000 ; free physical = 1677 ; free virtual = 24880 Ending Netlist Obfuscation Task | Checksum: 1cf01f192 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2803.152 ; gain = 0.000 ; free physical = 1677 ; free virtual = 24880 INFO: [Common 17-83] Releasing license: Implementation 19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2803.152 ; gain = 451.707 ; free physical = 1677 ; free virtual = 24880 # place_design Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-83] Releasing license: Implementation INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.168 ; gain = 0.000 ; free physical = 1677 ; free virtual = 24879 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 143689282 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2835.168 ; gain = 0.000 ; free physical = 1677 ; free virtual = 24879 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2835.168 ; gain = 0.000 ; free physical = 1677 ; free virtual = 24879 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 106e7cf05 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2835.168 ; gain = 0.000 ; free physical = 1676 ; free virtual = 24879 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1cdc0e798 Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1676 ; free virtual = 24879 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1cdc0e798 Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1676 ; free virtual = 24879 Phase 1 Placer Initialization | Checksum: 1cdc0e798 Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1676 ; free virtual = 24879 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1a5439612 Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1671 ; free virtual = 24874 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1af78d0fa Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1671 ; free virtual = 24874 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 1af78d0fa Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1671 ; free virtual = 24874 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 116bb453f Time (s): cpu = 00:00:14 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1645 ; free virtual = 24848 Phase 2.4.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 34 LUTNM shape to break, 48 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 14, two critical 20, total 34, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 55 nets or LUTs. Breaked 34 LUTs, combined 21 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization. INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1645 ; free virtual = 24848 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 34 | 21 | 55 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 34 | 21 | 55 | 0 | 9 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1782a92e6 Time (s): cpu = 00:00:15 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1645 ; free virtual = 24848 Phase 2.4 Global Placement Core | Checksum: e0dcbdc9 Time (s): cpu = 00:00:16 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1645 ; free virtual = 24848 Phase 2 Global Placement | Checksum: e0dcbdc9 Time (s): cpu = 00:00:16 ; elapsed = 00:00:05 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1645 ; free virtual = 24848 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 17ac39db6 Time (s): cpu = 00:00:17 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1645 ; free virtual = 24848 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 17fc7c12c Time (s): cpu = 00:00:18 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1645 ; free virtual = 24848 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1f69fb7bb Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1645 ; free virtual = 24848 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 2146babac Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1645 ; free virtual = 24848 Phase 3.5 Fast Optimization Phase 3.5 Fast Optimization | Checksum: 18d02401b Time (s): cpu = 00:00:22 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1642 ; free virtual = 24845 Phase 3.6 Small Shape Detail Placement Phase 3.6 Small Shape Detail Placement | Checksum: 11c676d1c Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1642 ; free virtual = 24845 Phase 3.7 Re-assign LUT pins Phase 3.7 Re-assign LUT pins | Checksum: 153f7ae85 Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1642 ; free virtual = 24845 Phase 3.8 Pipeline Register Optimization Phase 3.8 Pipeline Register Optimization | Checksum: 1d3efe367 Time (s): cpu = 00:00:24 ; elapsed = 00:00:10 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1642 ; free virtual = 24845 Phase 3.9 Fast Optimization Phase 3.9 Fast Optimization | Checksum: 24df6b01b Time (s): cpu = 00:00:30 ; elapsed = 00:00:14 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1643 ; free virtual = 24846 Phase 3 Detail Placement | Checksum: 24df6b01b Time (s): cpu = 00:00:30 ; elapsed = 00:00:14 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1643 ; free virtual = 24846 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: f68b2eba Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.827 | TNS=-43.115 | Phase 1 Physical Synthesis Initialization | Checksum: 159a1e503 Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1643 ; free virtual = 24846 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 159a1e503 Time (s): cpu = 00:00:00.97 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1643 ; free virtual = 24846 Phase 4.1.1.1 BUFG Insertion | Checksum: f68b2eba Time (s): cpu = 00:00:35 ; elapsed = 00:00:15 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1643 ; free virtual = 24846 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=0.161. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1da15cde9 Time (s): cpu = 00:01:08 ; elapsed = 00:00:43 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1641 ; free virtual = 24844 Time (s): cpu = 00:01:08 ; elapsed = 00:00:43 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1641 ; free virtual = 24844 Phase 4.1 Post Commit Optimization | Checksum: 1da15cde9 Time (s): cpu = 00:01:08 ; elapsed = 00:00:43 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1641 ; free virtual = 24844 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1da15cde9 Time (s): cpu = 00:01:08 ; elapsed = 00:00:43 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1641 ; free virtual = 24844 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 8x8| |___________|___________________|___________________| | South| 1x1| 2x2| |___________|___________________|___________________| | East| 1x1| 2x2| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1da15cde9 Time (s): cpu = 00:01:08 ; elapsed = 00:00:43 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1641 ; free virtual = 24844 Phase 4.3 Placer Reporting | Checksum: 1da15cde9 Time (s): cpu = 00:01:08 ; elapsed = 00:00:44 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1641 ; free virtual = 24844 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1641 ; free virtual = 24844 Time (s): cpu = 00:01:08 ; elapsed = 00:00:44 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1641 ; free virtual = 24844 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1dd3651a7 Time (s): cpu = 00:01:08 ; elapsed = 00:00:44 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1641 ; free virtual = 24844 Ending Placer Task | Checksum: e77b4651 Time (s): cpu = 00:01:08 ; elapsed = 00:00:44 . Memory (MB): peak = 2842.195 ; gain = 7.027 ; free physical = 1641 ; free virtual = 24844 37 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:01:09 ; elapsed = 00:00:44 . Memory (MB): peak = 2842.195 ; gain = 39.043 ; free physical = 1641 ; free virtual = 24844 # report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt # report_utilization -file digilent_nexys4ddr_utilization_place.rpt # report_io -file digilent_nexys4ddr_io.rpt report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1647 ; free virtual = 24851 # report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt report_control_sets: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1651 ; free virtual = 24854 # report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt # route_design Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design Checksum: PlaceDB: e0eab53f ConstDB: 0 ShapeSum: 6909112 RouteDB: 0 Post Restoration Checksum: NetGraph: e8009f99 | NumContArr: 1aa24a4e | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 287f4df21 Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1629 ; free virtual = 24832 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 287f4df21 Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1629 ; free virtual = 24832 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 287f4df21 Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1629 ; free virtual = 24832 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 123ec124d Time (s): cpu = 00:00:36 ; elapsed = 00:00:27 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1606 ; free virtual = 24809 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.388 | TNS=0.000 | WHS=-0.204 | THS=-15.599| Router Utilization Summary Global Vertical Routing Utilization = 0.000609305 % Global Horizontal Routing Utilization = 0.00269963 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 3354 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 3351 Number of Partially Routed Nets = 3 Number of Node Overlaps = 3 Phase 2 Router Initialization | Checksum: 1bbd18bb2 Time (s): cpu = 00:00:38 ; elapsed = 00:00:28 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1597 ; free virtual = 24800 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 1bbd18bb2 Time (s): cpu = 00:00:38 ; elapsed = 00:00:28 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1597 ; free virtual = 24800 Phase 3.2 Initial Net Routing Phase 3.2 Initial Net Routing | Checksum: 2f30e0566 Time (s): cpu = 00:00:41 ; elapsed = 00:00:28 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1597 ; free virtual = 24800 Phase 3 Initial Routing | Checksum: 2f30e0566 Time (s): cpu = 00:00:41 ; elapsed = 00:00:28 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1597 ; free virtual = 24800 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 1783 Number of Nodes with overlaps = 663 Number of Nodes with overlaps = 363 Number of Nodes with overlaps = 208 Number of Nodes with overlaps = 134 Number of Nodes with overlaps = 87 Number of Nodes with overlaps = 34 Number of Nodes with overlaps = 19 Number of Nodes with overlaps = 21 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.056 | TNS=-56.244| WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 2f4df617f Time (s): cpu = 00:01:16 ; elapsed = 00:00:42 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1595 ; free virtual = 24798 Phase 4.2 Global Iteration 1 Number of Nodes with overlaps = 592 Number of Nodes with overlaps = 357 Number of Nodes with overlaps = 235 Number of Nodes with overlaps = 169 Number of Nodes with overlaps = 112 Number of Nodes with overlaps = 83 Number of Nodes with overlaps = 58 Number of Nodes with overlaps = 36 Number of Nodes with overlaps = 15 Number of Nodes with overlaps = 16 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 7 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.706 | TNS=-23.418| WHS=N/A | THS=N/A | Phase 4.2 Global Iteration 1 | Checksum: 322045194 Time (s): cpu = 00:01:46 ; elapsed = 00:00:57 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24802 Phase 4.3 Global Iteration 2 Number of Nodes with overlaps = 532 Number of Nodes with overlaps = 250 Number of Nodes with overlaps = 237 Number of Nodes with overlaps = 151 Number of Nodes with overlaps = 116 Number of Nodes with overlaps = 84 Number of Nodes with overlaps = 39 Number of Nodes with overlaps = 46 Number of Nodes with overlaps = 35 Number of Nodes with overlaps = 23 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 14 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 13 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 9 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 5 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.550 | TNS=-12.456| WHS=N/A | THS=N/A | Phase 4.3 Global Iteration 2 | Checksum: 221344951 Time (s): cpu = 00:02:18 ; elapsed = 00:01:13 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24803 Phase 4.4 Global Iteration 3 Number of Nodes with overlaps = 640 Number of Nodes with overlaps = 328 Number of Nodes with overlaps = 268 Number of Nodes with overlaps = 120 Number of Nodes with overlaps = 91 Number of Nodes with overlaps = 43 Number of Nodes with overlaps = 25 Number of Nodes with overlaps = 17 Number of Nodes with overlaps = 11 Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.564 | TNS=-13.331| WHS=N/A | THS=N/A | Phase 4.4 Global Iteration 3 | Checksum: 32f9f1f27 Time (s): cpu = 00:02:46 ; elapsed = 00:01:25 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24802 Phase 4 Rip-up And Reroute | Checksum: 32f9f1f27 Time (s): cpu = 00:02:46 ; elapsed = 00:01:25 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24802 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing Phase 5.1.1 Update Timing | Checksum: 25430253c Time (s): cpu = 00:02:47 ; elapsed = 00:01:25 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24802 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.542 | TNS=-11.972| WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 Phase 5.1 Delay CleanUp | Checksum: 29b498d37 Time (s): cpu = 00:02:48 ; elapsed = 00:01:25 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24802 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 29b498d37 Time (s): cpu = 00:02:48 ; elapsed = 00:01:25 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24802 Phase 5 Delay and Skew Optimization | Checksum: 29b498d37 Time (s): cpu = 00:02:48 ; elapsed = 00:01:25 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24802 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 327179686 Time (s): cpu = 00:02:49 ; elapsed = 00:01:26 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24802 INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.521 | TNS=-11.274| WHS=0.036 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 2c5d2c0c6 Time (s): cpu = 00:02:49 ; elapsed = 00:01:26 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24802 Phase 6 Post Hold Fix | Checksum: 2c5d2c0c6 Time (s): cpu = 00:02:49 ; elapsed = 00:01:26 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24802 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 1.14336 % Global Horizontal Routing Utilization = 1.3729 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --GLOBAL Congestion: Utilization threshold used for congestion level computation: 0.85 Congestion Report North Dir 1x1 Area, Max Cong = 71.1712%, No Congested Regions. South Dir 1x1 Area, Max Cong = 86.4865%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): INT_R_X27Y146 -> INT_R_X27Y146 East Dir 1x1 Area, Max Cong = 72.0588%, No Congested Regions. West Dir 1x1 Area, Max Cong = 79.4118%, No Congested Regions. ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 1 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Phase 7 Route finalize | Checksum: 2c5d2c0c6 Time (s): cpu = 00:02:49 ; elapsed = 00:01:26 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24802 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 2c5d2c0c6 Time (s): cpu = 00:02:49 ; elapsed = 00:01:26 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24802 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 22a50cdd8 Time (s): cpu = 00:02:50 ; elapsed = 00:01:26 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24802 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.521 | TNS=-11.274| WHS=0.036 | THS=0.000 | WARNING: [Route 35-328] Router estimated timing not met. Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. Phase 10 Post Router Timing | Checksum: 22a50cdd8 Time (s): cpu = 00:02:51 ; elapsed = 00:01:26 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24802 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing Phase 11 Post-Route Event Processing | Checksum: 1192b4d81 Time (s): cpu = 00:02:51 ; elapsed = 00:01:27 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24802 Ending Routing Task | Checksum: 1192b4d81 Time (s): cpu = 00:02:51 ; elapsed = 00:01:27 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24802 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 15 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:02:52 ; elapsed = 00:01:27 . Memory (MB): peak = 2842.195 ; gain = 0.000 ; free physical = 1598 ; free virtual = 24802 # report_timing_summary -no_header -no_detailed_paths INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (12) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (4) 5. checking no_input_delay (9) 6. checking no_output_delay (17) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (12) ------------------------- There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[6]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[7]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[9]/Q (HIGH) 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (4) ------------------------------------------------ There are 4 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (9) ------------------------------ There are 9 input ports with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (17) -------------------------------- There are 17 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -0.522 -11.239 40 6708 0.037 0.000 0 6708 3.750 0.000 0 2033 Timing constraints are not met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- sys_clk_pin {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- sys_clk_pin -0.522 -11.239 40 6708 0.037 0.000 0 6708 3.750 0.000 0 2033 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- # report_route_status -file digilent_nexys4ddr_route_status.rpt # report_drc -file digilent_nexys4ddr_drc.rpt Command: report_drc -file digilent_nexys4ddr_drc.rpt INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco 5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt. report_drc completed successfully # report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs # report_power -file digilent_nexys4ddr_power.rpt Command: report_power -file digilent_nexys4ddr_power.rpt Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully # write_bitstream -force "./build/out.bit" Command: write_bitstream -force ./build/out.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. WARNING: [DRC PDRC-153] Gated clock check: Net SOC/Core/Control_Unit/FSM_onehot_state_reg[9]_0[0] is a gated clock net sourced by a combinational pin SOC/Core/Control_Unit/aluop_out_reg[3]_i_2/O, cell SOC/Core/Control_Unit/aluop_out_reg[3]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./build/out.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 3153.250 ; gain = 234.301 ; free physical = 1265 ; free virtual = 24473 INFO: [Common 17-206] Exiting Vivado at Thu Mar 21 02:38:51 2024... [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Flash) [Pipeline] parallel [Pipeline] { (Branch: openFPGAloader ECP5) [Pipeline] { (Branch: openFPGAloader Tangnano 20k) [Pipeline] { (Branch: openFPGAloader Nexys 4 DDR) [Pipeline] stage [Pipeline] { (openFPGAloader ECP5) [Pipeline] stage [Pipeline] { (openFPGAloader Tangnano 20k) [Pipeline] stage [Pipeline] { (openFPGAloader Nexys 4 DDR) [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] lock Trying to acquire lock on [ecp5] Resource [ecp5] did not exist. Created. Lock acquired on [ecp5] [Pipeline] { [Pipeline] lock Trying to acquire lock on [tangnano20k] Resource [tangnano20k] did not exist. Created. Lock acquired on [tangnano20k] [Pipeline] { [Pipeline] lock Trying to acquire lock on [nexys4] Resource [nexys4] did not exist. Created. Lock acquired on [nexys4] [Pipeline] { [Pipeline] echo FPGA ECP5 Broqueada [Pipeline] sh [Pipeline] echo FPGA TangNano Broqueada + /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit empty Found 1 compatible device: 0x0d28 0x0204 0x3 DAPLink CMSIS-DAP Open file: DONE b3bdffff Parse file: DONE Enable configuration: DONE SRAM erase: DONE [Pipeline] sh [Pipeline] echo FPGA Nexys 4 Broqueada + echo gravando na tang nano gravando na tang nano [Pipeline] sh + cd Risco-5/fpga/nexys4_ddr + /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 --busdev-num 002:012 ./build/out.bit empty Jtag frequency : requested 6.00MHz -> real 6.00MHz Open file DONE Parse file DONE load program [Pipeline] } Lock released on resource [tangnano20k] [Pipeline] // lock [Pipeline] } Loading: [====== ] 11.06%[Pipeline] // script [Pipeline] } Load SRAM: [========= ] 18.00%[Pipeline] // stage [Pipeline] } Loading: [============ ] 22.12% Load SRAM: [=================== ] 38.00% Loading: [================= ] 33.18% Load SRAM: [============================= ] 58.00% Loading: [======================= ] 44.24% Load SRAM: [======================================= ] 78.00% Loading: [============================ ] 55.30% Load SRAM: [================================================= ] 98.00% Load SRAM: [===================================================] 100.00% Done [Pipeline] } Loading: [================================== ] 66.36%Lock released on resource [nexys4] [Pipeline] // lock [Pipeline] } [Pipeline] // script [Pipeline] } [Pipeline] // stage Loading: [======================================= ] 77.42%[Pipeline] } Loading: [============================================= ] 88.48% Loading: [==================================================] 99.54% Loading: [==================================================] 100.00% Done Disable configuration: DONE [Pipeline] } Lock released on resource [ecp5] [Pipeline] // lock [Pipeline] } [Pipeline] // script [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Testes) [Pipeline] parallel [Pipeline] { (Branch: ECP5 - Testes) [Pipeline] { (Branch: TangNano - Testes) [Pipeline] { (Branch: Nexys 4 - Testes) [Pipeline] stage [Pipeline] { (ECP5 - Testes) [Pipeline] stage [Pipeline] { (TangNano - Testes) [Pipeline] stage [Pipeline] { (Nexys 4 - Testes) [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] echo Rodando teste na ECP5 [Pipeline] lock Trying to acquire lock on [ecp5] Resource [ecp5] did not exist. Created. Lock acquired on [ecp5] [Pipeline] { [Pipeline] echo Rodando teste na tang nano [Pipeline] lock Trying to acquire lock on [tangnano20k] Resource [tangnano20k] did not exist. Created. Lock acquired on [tangnano20k] [Pipeline] { [Pipeline] echo Rodando teste na Nexys 4 [Pipeline] lock Trying to acquire lock on [nexys4] Resource [nexys4] did not exist. Created. Lock acquired on [nexys4] [Pipeline] { [Pipeline] echo FPGA ECP5 Broqueada [Pipeline] sh [Pipeline] echo FPGA TangNano Broqueada + echo testando na ecp5 testando na ecp5 [Pipeline] sh [Pipeline] echo FPGA Nexys 4 Broqueada + echo testando na tang nano testando na tang nano [Pipeline] sh [Pipeline] } + echo testando na tang nano testando na tang nano Lock released on resource [ecp5] [Pipeline] } Lock released on resource [tangnano20k] [Pipeline] // lock [Pipeline] // lock [Pipeline] echo ECP5 liberada [Pipeline] } [Pipeline] echo TangNano liberada [Pipeline] } [Pipeline] } Lock released on resource [nexys4] [Pipeline] // script [Pipeline] // script [Pipeline] // lock [Pipeline] } [Pipeline] } [Pipeline] echo TangNano liberada [Pipeline] } [Pipeline] // stage [Pipeline] // stage [Pipeline] // script [Pipeline] } [Pipeline] } [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline Finished: SUCCESS