Started by user Julio Nunes Avelar
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Risco 5
[Pipeline] {
[Pipeline] stage
[Pipeline] { (git_clone)
[Pipeline] sh
+ rm -Rf Risco-5/ build/
[Pipeline] sh
+ git clone --depth 1 https://github.com/JN513/Risco-5
Cloning into 'Risco-5'...
[Pipeline] sh
+ cd Risco-5
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Yosys)
[Pipeline] sh
+ mkdir -p build
[Pipeline] sh
+ /eda/oss-cad-suite/bin/yosys -p                          read_verilog Risco-5/fpga/ecp5/*.v;                         read_verilog Risco-5/debug/clk_divider.v;                         read_verilog Risco-5/src/core/*.v;                         read_verilog Risco-5/src/peripheral/*.v;                         synth_ecp5 -json ./build/out.json -abc9                     

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.36+8 (git sha1 fb4cbfa73, clang 10.0.0-4ubuntu1 -fPIC -Os)


-- Running command `                         read_verilog Risco-5/fpga/ecp5/*.v;                         read_verilog Risco-5/debug/clk_divider.v;                         read_verilog Risco-5/src/core/*.v;                         read_verilog Risco-5/src/peripheral/*.v;                         synth_ecp5 -json ./build/out.json -abc9                     ' --

1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v
Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/reset.v
Parsing Verilog input from `Risco-5/fpga/ecp5/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: Risco-5/debug/clk_divider.v
Parsing Verilog input from `Risco-5/debug/clk_divider.v' to AST representation.
Generating RTLIL representation for module `\ClkDivider'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v
Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation.
Generating RTLIL representation for module `\ALU'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v
Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation.
Generating RTLIL representation for module `\ALU_Control'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v
Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: Risco-5/src/core/core.v
Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation.
Generating RTLIL representation for module `\Core'.
Risco-5/src/core/core.v:76: Warning: Identifier `\pc_source' is implicitly declared.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v
Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation.
Generating RTLIL representation for module `\Immediate_Generator'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v
Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation.
Generating RTLIL representation for module `\MUX'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v
Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation.
Generating RTLIL representation for module `\PC'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v
Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation.
Generating RTLIL representation for module `\Registers'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v
Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation.
Warning: Literal has a width of 2 bit, but value requires 3 bit. (Risco-5/src/peripheral/bus.v:51)
Generating RTLIL representation for module `\BUS'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v
Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9)
Generating RTLIL representation for module `\GPIO'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v
Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation.
Generating RTLIL representation for module `\GPIOS'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v
Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation.
Generating RTLIL representation for module `\LEDs'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v
Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v
Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation.
Generating RTLIL representation for module `\Risco_5_SOC'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v
Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_rx'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_tx'.
Successfully finished Verilog frontend.

21. Executing SYNTH_ECP5 pass.

21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

21.3. Executing HIERARCHY pass (managing design hierarchy).

21.3.1. Finding top of design hierarchy..
root of   0 design levels: uart_tool_tx        
root of   0 design levels: uart_tool_rx        
root of   1 design levels: UART                
root of   2 design levels: Risco_5_SOC         
root of   0 design levels: Memory              
root of   0 design levels: LEDs                
root of   1 design levels: GPIOS               
root of   0 design levels: GPIO                
root of   0 design levels: BUS                 
root of   0 design levels: Registers           
root of   0 design levels: PC                  
root of   0 design levels: MUX                 
root of   0 design levels: Immediate_Generator 
root of   1 design levels: Core                
root of   0 design levels: Control_Unit        
root of   0 design levels: ALU_Control         
root of   0 design levels: ALU                 
root of   0 design levels: ClkDivider          
root of   0 design levels: ResetBootSystem     
root of   3 design levels: top                 
Automatically selected top as design top module.

21.3.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     \ResetBootSystem
Used module:     \ClkDivider
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \MEMORY_SIZE = 4096
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 5

21.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \MEMORY_SIZE = 4096
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 5
Generating RTLIL representation for module `$paramod$e03256ea8e7445dc30f095427a7bac59d40d5a9f\Risco_5_SOC'.
Parameter \CYCLES = 20

21.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \COUNTER_BITS = 32

21.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Generating RTLIL representation for module `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000'.
Parameter \WIDHT = 5

21.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 5
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600

21.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Generating RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

21.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \BOOT_ADDRESS = 0

21.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'.
Parameter \BOOT_ADDRESS = 0
Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.
Risco-5/src/core/core.v:76: Warning: Identifier `\pc_source' is implicitly declared.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.

21.3.12. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e03256ea8e7445dc30f095427a7bac59d40d5a9f\Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000
Parameter \WIDHT = 5
Found cached RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Found cached RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 4096

21.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = 248'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011011000110111101101111011100000011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory'.
Parameter \BOOT_ADDRESS = 0
Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.

21.3.14. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e03256ea8e7445dc30f095427a7bac59d40d5a9f\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101
Used module:             \GPIO
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Found cached RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Found cached RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.

21.3.15. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e03256ea8e7445dc30f095427a7bac59d40d5a9f\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101
Used module:             \GPIO
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000

21.3.16. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e03256ea8e7445dc30f095427a7bac59d40d5a9f\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101
Used module:             \GPIO
Used module:         $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \Immediate_Generator
Used module:             \ALU
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000
Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Removing unused module `\uart_tool_tx'.
Removing unused module `\uart_tool_rx'.
Removing unused module `\UART'.
Removing unused module `\Risco_5_SOC'.
Removing unused module `\Memory'.
Removing unused module `\GPIOS'.
Removing unused module `\Core'.
Removing unused module `\ClkDivider'.
Removing unused module `\ResetBootSystem'.
Removed 10 unused modules.

21.4. Executing PROC pass (convert processes to netlists).

21.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$395'.
Found and cleaned up 1 empty switch in `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:0$663'.
Removing empty process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:0$663'.
Cleaned up 2 empty switches.

21.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$502 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$454 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$396 in module TRELLIS_DPR16X4.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:197$647 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:186$645 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:171$637 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:160$634 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:148$628 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:133$623 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:116$618 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:97$609 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:173$596 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:162$594 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:147$586 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:130$572 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:115$566 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:98$561 in module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:135$551 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:31$654 in module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$163 in module LEDs.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:29$532 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:155$69 in module Registers.
Removed 2 dead cases from process $proc$Risco-5/src/core/registers.v:81$68 in module Registers.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:81$68 in module Registers.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:19$64 in module PC.
Removed 1 dead cases from process $proc$Risco-5/src/core/mux.v:10$63 in module MUX.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/mux.v:10$63 in module MUX.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:7$60 in module Immediate_Generator.
Marked 3 switch rules as full_case in process $proc$Risco-5/debug/clk_divider.v:25$516 in module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:69$51 in module Control_Unit.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:52$48 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:44$47 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:8$45 in module ALU_Control.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:8$45 in module ALU_Control.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:11$30 in module ALU.
Marked 5 switch rules as full_case in process $proc$Risco-5/fpga/ecp5/reset.v:24$505 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Removed a total of 4 dead cases.

21.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 8 redundant assignments.
Promoted 131 assignments to connections.

21.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$503'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$649'.
  Set init value: \i = 0
Found init rule in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$602'.
  Set init value: \i = 0
Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$554'.
  Set init value: \instruction_register = 0
  Set init value: \memory_register = 0
  Set init value: \alu_out_register = 0
  Set init value: \register_data_1 = 0
  Set init value: \register_data_2 = 0
Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$166'.
  Set init value: \data = 33'000000000000000000000000000000000
Found init rule in `\Registers.$proc$Risco-5/src/core/registers.v:0$72'.
  Set init value: \register0 = 0
  Set init value: \register1 = 0
  Set init value: \register2 = 0
  Set init value: \register3 = 0
  Set init value: \register4 = 0
  Set init value: \register5 = 0
  Set init value: \register6 = 0
  Set init value: \register7 = 0
  Set init value: \register8 = 0
  Set init value: \register9 = 0
  Set init value: \register10 = 0
  Set init value: \register11 = 0
  Set init value: \register12 = 0
  Set init value: \register13 = 0
  Set init value: \register14 = 0
  Set init value: \register15 = 0
  Set init value: \register16 = 0
  Set init value: \register17 = 0
  Set init value: \register18 = 0
  Set init value: \register19 = 0
  Set init value: \register20 = 0
  Set init value: \register21 = 0
  Set init value: \register22 = 0
  Set init value: \register23 = 0
  Set init value: \register24 = 0
  Set init value: \register25 = 0
  Set init value: \register26 = 0
  Set init value: \register27 = 0
  Set init value: \register28 = 0
  Set init value: \register29 = 0
  Set init value: \register30 = 0
  Set init value: \register31 = 0
Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$67'.
  Set init value: \PC_Register = 0
Found init rule in `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$528'.
  Set init value: \clk_o_pulse = 1'0
  Set init value: \clk_o_auto = 1'0
  Set init value: \clk_counter = 0
Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$53'.
  Set init value: \state = 3'000
  Set init value: \pc_write_cond = 1'0
  Set init value: \pc_write = 1'0
  Set init value: \lorD = 1'0
  Set init value: \memory_read = 1'0
  Set init value: \memory_write = 1'0
  Set init value: \memory_to_reg = 1'0
  Set init value: \ir_write = 1'0
  Set init value: \pc_source = 1'0
  Set init value: \aluop = 2'00
  Set init value: \alu_src_a = 2'00
  Set init value: \alu_src_b = 2'00
  Set init value: \reg_write = 1'0
  Set init value: \nextstate = 3'000
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:0$511'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000

21.4.5. Executing PROC_ARST pass (detect async resets in processes).

21.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~78 debug messages>

21.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$503'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$502'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$454'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$453_EN[3:0]$460
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$453_DATA[3:0]$459
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$453_ADDR[3:0]$458
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$396'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$394_EN[3:0]$402
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$394_DATA[3:0]$401
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$394_ADDR[3:0]$400
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$395'.
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$649'.
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$647'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$645'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$637'.
     1/1: $0\cycle_counter[12:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$634'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$628'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$623'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$618'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$609'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$602'.
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$596'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$594'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$586'.
     1/1: $0\cycle_counter[12:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$572'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$566'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$561'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$554'.
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$551'.
     1/5: $0\alu_out_register[31:0]
     2/5: $0\register_data_2[31:0]
     3/5: $0\register_data_1[31:0]
     4/5: $0\memory_register[31:0]
     5/5: $0\instruction_register[31:0]
Creating decoders for process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$654'.
     1/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$661
     2/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_DATA[31:0]$660
     3/3: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_ADDR[31:0]$659
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$166'.
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$163'.
     1/1: $0\data[32:0]
Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.$proc$Risco-5/src/peripheral/gpios.v:29$532'.
     1/2: $0\gpio_value[4:0]
     2/2: $0\gpio_direction[4:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$72'.
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
     1/32: $0\register31[31:0]
     2/32: $0\register30[31:0]
     3/32: $0\register29[31:0]
     4/32: $0\register28[31:0]
     5/32: $0\register27[31:0]
     6/32: $0\register26[31:0]
     7/32: $0\register25[31:0]
     8/32: $0\register24[31:0]
     9/32: $0\register23[31:0]
    10/32: $0\register22[31:0]
    11/32: $0\register21[31:0]
    12/32: $0\register20[31:0]
    13/32: $0\register19[31:0]
    14/32: $0\register18[31:0]
    15/32: $0\register17[31:0]
    16/32: $0\register16[31:0]
    17/32: $0\register15[31:0]
    18/32: $0\register14[31:0]
    19/32: $0\register13[31:0]
    20/32: $0\register12[31:0]
    21/32: $0\register11[31:0]
    22/32: $0\register10[31:0]
    23/32: $0\register9[31:0]
    24/32: $0\register8[31:0]
    25/32: $0\register7[31:0]
    26/32: $0\register6[31:0]
    27/32: $0\register5[31:0]
    28/32: $0\register4[31:0]
    29/32: $0\register3[31:0]
    30/32: $0\register2[31:0]
    31/32: $0\register1[31:0]
    32/32: $0\register0[31:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:81$68'.
     1/2: $1\readData2[31:0]
     2/2: $1\readData1[31:0]
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$67'.
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:19$64'.
     1/1: $1\PC_Register[31:0]
Creating decoders for process `\MUX.$proc$Risco-5/src/core/mux.v:10$63'.
     1/1: $1\S[31:0]
Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$60'.
     1/1: $1\immediate[31:0]
Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$528'.
Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:46$526'.
Creating decoders for process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$516'.
     1/2: $0\clk_counter[31:0]
     2/2: $0\clk_o_auto[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$53'.
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
     1/23: $2\reg_write[0:0]
     2/23: $2\memory_write[0:0]
     3/23: $2\memory_read[0:0]
     4/23: $2\lorD[0:0]
     5/23: $2\aluop[1:0]
     6/23: $3\alu_src_a[1:0]
     7/23: $2\alu_src_b[1:0]
     8/23: $2\pc_source[0:0]
     9/23: $2\pc_write[0:0]
    10/23: $2\pc_write_cond[0:0]
    11/23: $2\alu_src_a[1:0]
    12/23: $1\pc_write[0:0]
    13/23: $1\alu_src_b[1:0]
    14/23: $1\ir_write[0:0]
    15/23: $1\memory_read[0:0]
    16/23: $1\reg_write[0:0]
    17/23: $1\alu_src_a[1:0]
    18/23: $1\aluop[1:0]
    19/23: $1\pc_source[0:0]
    20/23: $1\memory_to_reg[0:0]
    21/23: $1\memory_write[0:0]
    22/23: $1\lorD[0:0]
    23/23: $1\pc_write_cond[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48'.
     1/3: $3\nextstate[2:0]
     2/3: $2\nextstate[2:0]
     3/3: $1\nextstate[2:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:44$47'.
     1/1: $0\state[2:0]
Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:8$45'.
     1/4: $4\aluop_out[3:0]
     2/4: $3\aluop_out[3:0]
     3/4: $2\aluop_out[3:0]
     4/4: $1\aluop_out[3:0]
Creating decoders for process `\ALU.$proc$Risco-5/src/core/alu.v:11$30'.
     1/1: $1\ALU_out_S[31:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:0$511'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$505'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]

21.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\n_fsm_state' from process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$618'.
No latch inferred for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\n_fsm_state' from process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$561'.
No latch inferred for signal `\Registers.\readData1' from process `\Registers.$proc$Risco-5/src/core/registers.v:81$68'.
No latch inferred for signal `\Registers.\readData2' from process `\Registers.$proc$Risco-5/src/core/registers.v:81$68'.
No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$Risco-5/src/core/mux.v:10$63'.
No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$60'.
No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51`.
No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48`.
Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:8$45': $auto$proc_dlatch.cc:427:proc_dlatch$2149
No latch inferred for signal `\ALU.\ALU_out_S' from process `\ALU.$proc$Risco-5/src/core/alu.v:11$30'.

21.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$502'.
  created $dff cell `$procdff$2172' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$438_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$439_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$440_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$441_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$442_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$443_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$444_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$445_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$446_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$447_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$448_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$449_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$450_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$451_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$452_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$453_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$454'.
  created $dff cell `$procdff$2173' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$453_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$454'.
  created $dff cell `$procdff$2174' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$453_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$454'.
  created $dff cell `$procdff$2175' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$378_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$379_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$380_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$381_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$382_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$383_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$384_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$385_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$386_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$387_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$388_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$389_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$390_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$391_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$392_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$393_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$394_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$396'.
  created $dff cell `$procdff$2176' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$394_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$396'.
  created $dff cell `$procdff$2177' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$394_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$396'.
  created $dff cell `$procdff$2178' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$395'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\rxd_reg' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$647'.
  created $dff cell `$procdff$2179' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\rxd_reg_0' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$647'.
  created $dff cell `$procdff$2180' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\fsm_state' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$645'.
  created $dff cell `$procdff$2181' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\cycle_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$637'.
  created $dff cell `$procdff$2182' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\bit_sample' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$634'.
  created $dff cell `$procdff$2183' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\bit_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$628'.
  created $dff cell `$procdff$2184' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\i' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$623'.
  created $dff cell `$procdff$2185' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\recieved_data' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$623'.
  created $dff cell `$procdff$2186' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.\uart_rx_data' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$609'.
  created $dff cell `$procdff$2187' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\txd_reg' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$596'.
  created $dff cell `$procdff$2188' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\fsm_state' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$594'.
  created $dff cell `$procdff$2189' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\cycle_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$586'.
  created $dff cell `$procdff$2190' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\bit_counter' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$572'.
  created $dff cell `$procdff$2191' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\i' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$566'.
  created $dff cell `$procdff$2192' with positive edge clock.
Creating register for signal `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.\data_to_send' using process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$566'.
  created $dff cell `$procdff$2193' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$551'.
  created $dff cell `$procdff$2194' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$551'.
  created $dff cell `$procdff$2195' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$551'.
  created $dff cell `$procdff$2196' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$551'.
  created $dff cell `$procdff$2197' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$551'.
  created $dff cell `$procdff$2198' with positive edge clock.
Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_ADDR' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$654'.
  created $dff cell `$procdff$2199' with positive edge clock.
Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_DATA' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$654'.
  created $dff cell `$procdff$2200' with positive edge clock.
Creating register for signal `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN' using process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$654'.
  created $dff cell `$procdff$2201' with positive edge clock.
Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$163'.
  created $dff cell `$procdff$2202' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.$proc$Risco-5/src/peripheral/gpios.v:29$532'.
  created $dff cell `$procdff$2203' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.$proc$Risco-5/src/peripheral/gpios.v:29$532'.
  created $dff cell `$procdff$2204' with positive edge clock.
Creating register for signal `\Registers.\register0' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2205' with positive edge clock.
Creating register for signal `\Registers.\register1' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2206' with positive edge clock.
Creating register for signal `\Registers.\register2' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2207' with positive edge clock.
Creating register for signal `\Registers.\register3' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2208' with positive edge clock.
Creating register for signal `\Registers.\register4' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2209' with positive edge clock.
Creating register for signal `\Registers.\register5' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2210' with positive edge clock.
Creating register for signal `\Registers.\register6' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2211' with positive edge clock.
Creating register for signal `\Registers.\register7' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2212' with positive edge clock.
Creating register for signal `\Registers.\register8' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2213' with positive edge clock.
Creating register for signal `\Registers.\register9' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2214' with positive edge clock.
Creating register for signal `\Registers.\register10' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2215' with positive edge clock.
Creating register for signal `\Registers.\register11' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2216' with positive edge clock.
Creating register for signal `\Registers.\register12' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2217' with positive edge clock.
Creating register for signal `\Registers.\register13' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2218' with positive edge clock.
Creating register for signal `\Registers.\register14' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2219' with positive edge clock.
Creating register for signal `\Registers.\register15' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2220' with positive edge clock.
Creating register for signal `\Registers.\register16' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2221' with positive edge clock.
Creating register for signal `\Registers.\register17' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2222' with positive edge clock.
Creating register for signal `\Registers.\register18' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2223' with positive edge clock.
Creating register for signal `\Registers.\register19' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2224' with positive edge clock.
Creating register for signal `\Registers.\register20' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2225' with positive edge clock.
Creating register for signal `\Registers.\register21' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2226' with positive edge clock.
Creating register for signal `\Registers.\register22' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2227' with positive edge clock.
Creating register for signal `\Registers.\register23' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2228' with positive edge clock.
Creating register for signal `\Registers.\register24' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2229' with positive edge clock.
Creating register for signal `\Registers.\register25' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2230' with positive edge clock.
Creating register for signal `\Registers.\register26' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2231' with positive edge clock.
Creating register for signal `\Registers.\register27' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2232' with positive edge clock.
Creating register for signal `\Registers.\register28' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2233' with positive edge clock.
Creating register for signal `\Registers.\register29' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2234' with positive edge clock.
Creating register for signal `\Registers.\register30' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2235' with positive edge clock.
Creating register for signal `\Registers.\register31' using process `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
  created $dff cell `$procdff$2236' with positive edge clock.
Creating register for signal `\PC.\PC_Register' using process `\PC.$proc$Risco-5/src/core/pc.v:19$64'.
  created $dff cell `$procdff$2237' with positive edge clock.
Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\clk_o_pulse' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:46$526'.
  created $dff cell `$procdff$2238' with positive edge clock.
Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\clk_o_auto' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$516'.
  created $dff cell `$procdff$2239' with positive edge clock.
Creating register for signal `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.\clk_counter' using process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$516'.
  created $dff cell `$procdff$2240' with positive edge clock.
Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:44$47'.
  created $dff cell `$procdff$2241' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$505'.
  created $dff cell `$procdff$2242' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$505'.
  created $dff cell `$procdff$2243' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$505'.
  created $dff cell `$procdff$2244' with positive edge clock.

21.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$503'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$502'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$502'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$477'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$454'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$420'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$396'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$395'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$649'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$647'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$647'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$645'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$645'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$637'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$637'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$634'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$634'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$628'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$628'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$623'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$623'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$618'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$618'.
Found and cleaned up 2 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$609'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$609'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$602'.
Found and cleaned up 5 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$596'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$596'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$594'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$594'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$586'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$586'.
Found and cleaned up 5 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$572'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$572'.
Found and cleaned up 3 empty switches in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$566'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$566'.
Found and cleaned up 1 empty switch in `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$561'.
Removing empty process `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$561'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$554'.
Found and cleaned up 2 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$551'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:135$551'.
Found and cleaned up 1 empty switch in `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$654'.
Removing empty process `$paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.$proc$Risco-5/src/peripheral/memory.v:31$654'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$166'.
Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$163'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$163'.
Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.$proc$Risco-5/src/peripheral/gpios.v:29$532'.
Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.$proc$Risco-5/src/peripheral/gpios.v:29$532'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$72'.
Found and cleaned up 3 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:155$69'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:155$69'.
Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:81$68'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:81$68'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$67'.
Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:19$64'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:19$64'.
Found and cleaned up 1 empty switch in `\MUX.$proc$Risco-5/src/core/mux.v:10$63'.
Removing empty process `MUX.$proc$Risco-5/src/core/mux.v:10$63'.
Found and cleaned up 1 empty switch in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$60'.
Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:7$60'.
Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:0$528'.
Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:46$526'.
Found and cleaned up 4 empty switches in `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$516'.
Removing empty process `$paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.$proc$Risco-5/debug/clk_divider.v:25$516'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$53'.
Found and cleaned up 4 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:69$51'.
Found and cleaned up 3 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:52$48'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:44$47'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:44$47'.
Found and cleaned up 4 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:8$45'.
Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:8$45'.
Found and cleaned up 1 empty switch in `\ALU.$proc$Risco-5/src/core/alu.v:11$30'.
Removing empty process `ALU.$proc$Risco-5/src/core/alu.v:11$30'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:0$511'.
Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$505'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/fpga/ecp5/reset.v:24$505'.
Cleaned up 78 empty switches.

21.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
<suppressed ~2 debug messages>
Optimizing module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.
<suppressed ~2 debug messages>
Optimizing module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.
Optimizing module LEDs.
<suppressed ~3 debug messages>
Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.
<suppressed ~4 debug messages>
Optimizing module GPIO.
<suppressed ~3 debug messages>
Optimizing module BUS.
Optimizing module Registers.
<suppressed ~4 debug messages>
Optimizing module PC.
<suppressed ~2 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module Immediate_Generator.
Optimizing module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.
<suppressed ~5 debug messages>
Optimizing module Control_Unit.
<suppressed ~5 debug messages>
Optimizing module ALU_Control.
<suppressed ~13 debug messages>
Optimizing module ALU.
<suppressed ~1 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~7 debug messages>
Optimizing module $paramod$e03256ea8e7445dc30f095427a7bac59d40d5a9f\Risco_5_SOC.
Optimizing module top.

21.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx.
Deleting now unused module $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx.
Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Deleting now unused module $paramod$b0fc92e8cdf62082a7f2b82516d8e79c3d195aee\Memory.
Deleting now unused module $paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART.
Deleting now unused module LEDs.
Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101.
Deleting now unused module GPIO.
Deleting now unused module BUS.
Deleting now unused module Registers.
Deleting now unused module PC.
Deleting now unused module MUX.
Deleting now unused module Immediate_Generator.
Deleting now unused module $paramod\ClkDivider\COUNTER_BITS=s32'00000000000000000000000000100000.
Deleting now unused module Control_Unit.
Deleting now unused module ALU_Control.
Deleting now unused module ALU.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module $paramod$e03256ea8e7445dc30f095427a7bac59d40d5a9f\Risco_5_SOC.
<suppressed ~27 debug messages>

21.6. Executing TRIBUF pass.

21.7. Executing DEMINOUT pass (demote inout ports to input or output).

21.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~52 debug messages>

21.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 132 unused cells and 674 unused wires.
<suppressed ~171 debug messages>

21.10. Executing CHECK pass (checking for obvious problems).
Checking module top...
Warning: Wire top.\SOC.Core.PCSourceMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputAMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [31] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [30] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [29] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [28] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [27] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [26] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [25] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [24] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [23] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [22] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [21] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [20] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [19] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [18] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [17] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [16] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [15] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [14] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [13] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [12] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [11] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [10] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [9] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [8] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [7] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [6] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [5] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [4] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [3] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [2] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [1] is used but has no driver.
Warning: Wire top.\SOC.Bus.slave_2_read_data [0] is used but has no driver.
Found and reported 256 problems.

21.11. Executing OPT pass (performing simple optimizations).

21.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~9 debug messages>

21.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~465 debug messages>
Removed a total of 155 cells.

21.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1870.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1877.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1885.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1893.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1903.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1915.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1929.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1939.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1950.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1958.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1967.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2035.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2043.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1823.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1823.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryDataMUX.$procmux$1823.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryDataMUX.$procmux$1823.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1823.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1823.
Removed 19 multiplexer ports.
<suppressed ~93 debug messages>

21.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1864: $auto$opt_reduce.cc:134:opt_pmux$2257
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1890: $auto$opt_reduce.cc:134:opt_pmux$2259
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1899: { $auto$opt_reduce.cc:134:opt_pmux$2261 $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:57$49_Y }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1909: { $flatten\SOC.\Core.\Control_Unit.$procmux$1866_CMP $auto$opt_reduce.cc:134:opt_pmux$2263 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1922: { $auto$opt_reduce.cc:134:opt_pmux$2267 $auto$opt_reduce.cc:134:opt_pmux$2265 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1935: $auto$opt_reduce.cc:134:opt_pmux$2269
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1947: $auto$opt_reduce.cc:134:opt_pmux$2271
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1829: { $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:57$49_Y $flatten\SOC.\Core.\Control_Unit.$procmux$1865_CMP $auto$opt_reduce.cc:134:opt_pmux$2275 $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:61$50_Y $auto$opt_reduce.cc:134:opt_pmux$2273 $flatten\SOC.\Core.\Control_Unit.$procmux$1876_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1715: $auto$opt_reduce.cc:134:opt_pmux$2277
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2071: { $flatten\SOC.\Core.\ALU_Control.$procmux$2078_CMP $auto$opt_reduce.cc:134:opt_pmux$2279 $flatten\SOC.\Core.\ALU_Control.$procmux$2075_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2074_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2073_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2072_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2085: { $auto$opt_reduce.cc:134:opt_pmux$2283 $auto$opt_reduce.cc:134:opt_pmux$2281 $flatten\SOC.\Core.\ALU_Control.$procmux$2078_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2094: { $flatten\SOC.\Core.\ALU_Control.$procmux$2096_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2095_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$972:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_EN[31:0]$657 [0] }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$2262: { $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:57$49_Y $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:61$50_Y $flatten\SOC.\Core.\Control_Unit.$procmux$1868_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1869_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1876_CMP }
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$2264: { $flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:61$50_Y $flatten\SOC.\Core.\Control_Unit.$procmux$1866_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1867_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1868_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1876_CMP }
  Optimizing cells in module \top.
Performed a total of 17 changes.

21.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

21.11.6. Executing OPT_DFF pass (perform DFF optimizations).

21.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 186 unused wires.
<suppressed ~8 debug messages>

21.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.11.9. Rerunning OPT passes. (Maybe there is more to do..)

21.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~93 debug messages>

21.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.11.13. Executing OPT_DFF pass (perform DFF optimizations).

21.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.11.16. Finished OPT passes. (There is nothing left to do.)

21.12. Executing FSM pass (extract and optimize FSM).

21.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.
Not marking top.SOC.Core.Control_Unit.state as FSM state register:
    Register has an initialization value.
Not marking top.SOC.Core.RegisterBank.register0 as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Found FSM state register top.SOC.Uart.i_uart_tx.fsm_state.

21.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\SOC.Uart.i_uart_tx.fsm_state' from module `\top'.
  found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_tx.$procdff$2189
  root of input selection tree: $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$580_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$570_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$588_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$568_Y
  found state code: 3'000
  found ctrl input: \SOC.Uart.i_uart_tx.stop_done
  found state code: 3'011
  found ctrl input: \SOC.Uart.i_uart_tx.payload_done
  found state code: 3'010
  found ctrl input: \SOC.Uart.i_uart_tx.next_bit
  found state code: 3'001
  found ctrl input: \SOC.Uart.i_uart_tx.uart_tx_en
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$588_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$580_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$575_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$574_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$570_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$568_Y
  ctrl inputs: { \SOC.Uart.i_uart_tx.uart_tx_en \SOC.Uart.i_uart_tx.next_bit \SOC.Uart.i_uart_tx.payload_done \SOC.Uart.i_uart_tx.stop_done \ResetBootSystem.reset_o }
  ctrl outputs: { $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$568_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$570_Y $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$574_Y $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$575_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$580_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$588_Y $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] }
  transition:      3'000 5'0---0 ->      3'000 9'101100000
  transition:      3'000 5'1---0 ->      3'001 9'101100001
  transition:      3'000 5'----1 ->      3'000 9'101100000
  transition:      3'010 5'--0-0 ->      3'010 9'010100010
  transition:      3'010 5'--1-0 ->      3'011 9'010100011
  transition:      3'010 5'----1 ->      3'000 9'010100000
  transition:      3'001 5'-0--0 ->      3'001 9'001101001
  transition:      3'001 5'-1--0 ->      3'010 9'001101010
  transition:      3'001 5'----1 ->      3'000 9'001101000
  transition:      3'011 5'---00 ->      3'011 9'001010011
  transition:      3'011 5'---10 ->      3'000 9'001010000
  transition:      3'011 5'----1 ->      3'000 9'001010000

21.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2284' from module `\top'.

21.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 8 unused cells and 8 unused wires.
<suppressed ~9 debug messages>

21.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2284' from module `\top'.
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [2].

21.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2284' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---

21.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2284' from module `top':
-------------------------------------

  Information on FSM $fsm$\SOC.Uart.i_uart_tx.fsm_state$2284 (\SOC.Uart.i_uart_tx.fsm_state):

  Number of input signals:    5
  Number of output signals:   6
  Number of state bits:       4

  Input signals:
    0: \ResetBootSystem.reset_o
    1: \SOC.Uart.i_uart_tx.stop_done
    2: \SOC.Uart.i_uart_tx.payload_done
    3: \SOC.Uart.i_uart_tx.next_bit
    4: \SOC.Uart.i_uart_tx.uart_tx_en

  Output signals:
    0: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$588_Y
    1: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$580_Y
    2: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$575_Y
    3: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$574_Y
    4: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$570_Y
    5: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:118$568_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 5'0---0   ->     0 6'101100
      1:     0 5'----1   ->     0 6'101100
      2:     0 5'1---0   ->     2 6'101100
      3:     1 5'----1   ->     0 6'010100
      4:     1 5'--0-0   ->     1 6'010100
      5:     1 5'--1-0   ->     3 6'010100
      6:     2 5'----1   ->     0 6'001101
      7:     2 5'-1--0   ->     1 6'001101
      8:     2 5'-0--0   ->     2 6'001101
      9:     3 5'---10   ->     0 6'001010
     10:     3 5'----1   ->     0 6'001010
     11:     3 5'---00   ->     3 6'001010

-------------------------------------

21.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$2284' from module `\top'.

21.13. Executing OPT pass (performing simple optimizations).

21.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

21.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~92 debug messages>

21.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2193 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$934_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$928_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$919_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$910_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$901_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$892_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$874_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$883_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2336 ($sdff) from module top (D = \SOC.Bus.slave_2_write_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$2336 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$928_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$919_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$910_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$901_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$892_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$874_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$883_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2191 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$850_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$2341 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$850_Y, Q = \SOC.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2190 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$839_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 13'0000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2347 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$593_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2188 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$828_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$2351 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$828_Y, Q = \SOC.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\SOC.\Leds.$procdff$2202 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$980_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2357 ($sdff) from module top (D = { 1'0 \SOC.Leds.write_data }, Q = \SOC.Leds.data).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2204 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$988_Y, Q = \SOC.GPIOS.gpio_value, rval = 5'00000).
Adding EN signal on $auto$ff.cc:266:slice$2359 ($sdff) from module top (D = \SOC.GPIOS.write_data [4:0], Q = \SOC.GPIOS.gpio_value).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2203 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$996_Y, Q = \SOC.GPIOS.gpio_direction, rval = 5'00000).
Adding EN signal on $auto$ff.cc:266:slice$2363 ($sdff) from module top (D = \SOC.GPIOS.write_data [4:0], Q = \SOC.GPIOS.gpio_direction).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2236 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register31).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2235 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register30).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2234 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register29).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2233 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register28).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2232 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register27).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2231 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register26).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2230 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register25).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2229 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register24).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2228 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register23).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2227 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register22).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2226 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register21).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2225 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register20).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2224 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register19).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2223 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register18).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2222 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register17).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2221 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register16).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2220 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register15).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2219 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register14).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2218 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register13).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2217 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register12).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2216 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register11).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2215 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register10).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2214 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register9).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2213 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register8).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2212 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register7).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2211 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register6).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2210 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register5).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2209 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register4).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2208 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register3).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2207 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register2).
Adding EN signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2206 ($dff) from module top (D = \SOC.Core.RegisterBank.writeData, Q = \SOC.Core.RegisterBank.register1).
Adding SRST signal on $flatten\SOC.\Core.\RegisterBank.$procdff$2205 ($dff) from module top (D = $flatten\SOC.\Core.\RegisterBank.$procmux$1747_Y, Q = \SOC.Core.RegisterBank.register0, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2524 ($sdff) from module top (D = 0, Q = \SOC.Core.RegisterBank.register0).
Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$2237 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$1818_Y, Q = \SOC.Core.Pc.PC_Register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2530 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.PC_Register).
Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$2241 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 3'000).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2198 ($dff) from module top (D = \SOC.Bus.write_data, Q = \SOC.Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2197 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2196 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2195 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2194 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$966_Y, Q = \SOC.Core.instruction_register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2537 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2244 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2243 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2242 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Adding SRST signal on $flatten\ClkDivider.$procdff$2240 ($dff) from module top (D = $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:32$519_Y, Q = \ClkDivider.clk_counter, rval = 0).
Adding SRST signal on $flatten\ClkDivider.$procdff$2239 ($dff) from module top (D = $flatten\ClkDivider.$procmux$1854_Y, Q = \ClkDivider.clk_o_auto, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2565 ($sdff) from module top (D = $flatten\ClkDivider.$procmux$1854_Y, Q = \ClkDivider.clk_o_auto).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$2525 ($sdffe) from module top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$2358 ($sdffe) from module top.

21.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 136 unused cells and 137 unused wires.
<suppressed ~137 debug messages>

21.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6 debug messages>

21.13.9. Rerunning OPT passes. (Maybe there is more to do..)

21.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~51 debug messages>

21.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~93 debug messages>
Removed a total of 31 cells.

21.13.13. Executing OPT_DFF pass (perform DFF optimizations).

21.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 31 unused wires.
<suppressed ~1 debug messages>

21.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.13.16. Rerunning OPT passes. (Maybe there is more to do..)

21.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~51 debug messages>

21.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.13.20. Executing OPT_DFF pass (perform DFF optimizations).

21.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.13.23. Finished OPT passes. (There is nothing left to do.)

21.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 22 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2245 (SOC.Memory.memory).
Removed top 22 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$662 (SOC.Memory.memory).
Removed top 22 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:17$652 (SOC.Memory.memory).
Removed top 8 bits (of 32) from port B of cell top.$flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:40$525 ($ge).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:37$523 ($add).
Removed top 9 bits (of 32) from port B of cell top.$flatten\ClkDivider.$eq$Risco-5/debug/clk_divider.v:33$521 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$2123_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/fpga/ecp5/reset.v:38$509 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$508 ($add).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$508 ($add).
Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/fpga/ecp5/reset.v:36$507 ($lt).
Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:20$531 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:135$578 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$565 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$564 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$563 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$562 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:94$558 ($eq).
Removed top 1 bits (of 13) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:92$556 ($eq).
Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$162 ($mux).
Removed top 2 bits (of 8) from port Y of cell top.$flatten\SOC.\Leds.$not$Risco-5/src/peripheral/leds.v:31$165 ($not).
Removed top 2 bits (of 8) from port A of cell top.$flatten\SOC.\Leds.$not$Risco-5/src/peripheral/leds.v:31$165 ($not).
Removed top 20 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$74 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$77 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$78 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$85 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$86 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:66$97 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:67$98 ($le).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:75$116 ($mux).
Removed top 22 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$978 ($mux).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$eq$Risco-5/src/core/alu_control.v:34$46 ($eq).
Removed top 29 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$61 ($sub).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1826_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1826_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1816_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1815_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1814_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1813_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1812_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1811_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1810_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1809_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1808_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1807_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1806_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1805_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1804_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1803_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1802_CMP0 ($eq).
Removed top 4 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1783_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1782_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1781_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1780_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1779_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1778_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1777_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1776_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1775_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1774_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1773_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1772_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1771_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1770_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1769_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2550 ($ne).
Removed top 4 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1708_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1670_CMP0 ($eq).
Removed top 3 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1633_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1597_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1562_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1528_CMP0 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1495_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1463_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1432_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1402_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1373_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1345_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1318_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1292_CMP0 ($eq).
Removed top 1 bits (of 5) from port B of cell top.$flatten\SOC.\Core.\RegisterBank.$procmux$1267_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2041 ($mux).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1968_CMP0 ($eq).
Removed top 1 bits (of 2) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1965 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1904_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2545 ($ne).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1876_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1871_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1869_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1868_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1867_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1866_CMP0 ($eq).
Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:61$50 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2096_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2078_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2077_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2076_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2064 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2109_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2108_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2107_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2106_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$44 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:22$36 ($mux).
Removed top 29 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$62 ($sub).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$73 ($ge).
Removed top 20 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:80$124 ($mux).
Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$508_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$42_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:22$36_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$44_Y.
Removed top 1 bits (of 2) from wire top.$flatten\SOC.\Core.\Control_Unit.$2\alu_src_a[1:0].
Removed top 1 bits (of 3) from wire top.$flatten\SOC.\Core.\Control_Unit.$2\nextstate[2:0].
Removed top 22 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:33$650_ADDR[31:0]$655.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$562_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$563_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$564_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$565_Y.
Removed top 2 bits (of 8) from wire top.leds.

21.15. Executing PEEPOPT pass (run peephole optimizers).

21.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 14 unused wires.
<suppressed ~1 debug messages>

21.17. Executing SHARE pass (SAT-based resource sharing).
Found 3 cells in module top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:17$652 ($memrd):
    Found 1 activation_patterns using ctrl signal { $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$75_Y \SOC.Bus.slave_0_read }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:28$40 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2103_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:26$39 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2104_CMP.
    No candidates found.

21.18. Executing TECHMAP pass (map to technology primitives).

21.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

21.18.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~322 debug messages>

21.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.21. Executing TECHMAP pass (map to technology primitives).

21.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

21.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

21.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

21.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:37$523 ($add).
  creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$508 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$33 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34 ($sub).
  creating $macc model for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$61 ($sub).
  creating $macc model for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$62 ($sub).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$582 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$593 ($add).
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$593.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$582.
  creating $alu model for $macc $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$62.
  creating $alu model for $macc $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$61.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$33.
  creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$508.
  creating $alu model for $macc $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:37$523.
  creating $alu model for $flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:40$525 ($ge): new $alu
  creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/fpga/ecp5/reset.v:36$507 ($lt): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$73 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$77 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$85 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:66$97 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$74 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$78 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$86 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:67$98 ($le): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:34$43 ($ge): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34.
  creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:22$35 ($lt): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34.
  creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/fpga/ecp5/reset.v:38$509 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/fpga/ecp5/reset.v:36$507.
  creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$42 ($eq): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34.
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:67$98: $auto$alumacc.cc:485:replace_alu$2594
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$86: $auto$alumacc.cc:485:replace_alu$2607
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$78: $auto$alumacc.cc:485:replace_alu$2620
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$74: $auto$alumacc.cc:485:replace_alu$2633
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:66$97: $auto$alumacc.cc:485:replace_alu$2646
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$85: $auto$alumacc.cc:485:replace_alu$2655
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$77: $auto$alumacc.cc:485:replace_alu$2664
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$73: $auto$alumacc.cc:485:replace_alu$2673
  creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/fpga/ecp5/reset.v:36$507, $flatten\ResetBootSystem.$eq$Risco-5/fpga/ecp5/reset.v:38$509: $auto$alumacc.cc:485:replace_alu$2682
  creating $alu cell for $flatten\ClkDivider.$ge$Risco-5/debug/clk_divider.v:40$525: $auto$alumacc.cc:485:replace_alu$2693
  creating $alu cell for $flatten\ClkDivider.$add$Risco-5/debug/clk_divider.v:37$523: $auto$alumacc.cc:485:replace_alu$2702
  creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/fpga/ecp5/reset.v:37$508: $auto$alumacc.cc:485:replace_alu$2705
  creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:18$33: $auto$alumacc.cc:485:replace_alu$2708
  creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:20$34, $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:34$43, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:22$35, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:32$42: $auto$alumacc.cc:485:replace_alu$2711
  creating $alu cell for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:10$61: $auto$alumacc.cc:485:replace_alu$2724
  creating $alu cell for $flatten\SOC.\Core.\Immediate_Generator.$sub$Risco-5/src/core/immediate_generator.v:12$62: $auto$alumacc.cc:485:replace_alu$2727
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$582: $auto$alumacc.cc:485:replace_alu$2730
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$593: $auto$alumacc.cc:485:replace_alu$2733
  created 18 $alu and 0 $macc cells.

21.23. Executing OPT pass (performing simple optimizations).

21.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

21.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~51 debug messages>

21.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$2564: { $auto$rtlil.cc:2461:Not$2697 $auto$rtlil.cc:2464:ReduceAnd$2699 \reset }
  Optimizing cells in module \top.
Performed a total of 1 changes.

21.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.23.6. Executing OPT_DFF pass (perform DFF optimizations).

21.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 15 unused wires.
<suppressed ~2 debug messages>

21.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.23.9. Rerunning OPT passes. (Maybe there is more to do..)

21.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~51 debug messages>

21.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.23.13. Executing OPT_DFF pass (perform DFF optimizations).

21.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.23.16. Finished OPT passes. (There is nothing left to do.)

21.24. Executing MEMORY pass.

21.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

21.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

21.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing top.SOC.Memory.memory write port 0.

21.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

21.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found.
Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found.

21.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

21.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

21.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

21.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_
<suppressed ~68 debug messages>

21.27. Executing TECHMAP pass (map to technology primitives).

21.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

21.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

21.27.3. Continuing TECHMAP pass.
Using template $paramod$fb6ed8f936d3525780a052d218072c625795bc14\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$0eb199c7b2cea9c358f23ffe94c4548bdd802747\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b089c18cc881634130ec6d4716ef25d78c9d48c9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$731f2d82778baee6f78f5f3e0670a3ade61ac0d6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$48358c22c7a8e5b48ddefb8e14a8bb1f81de841f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5276274b86ff102139fbc8ae2dfc335d77b58a6a\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c75b2ca41d3ff8a2b5ad26d6a6ec321bb6e56448\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$315d0c5245324146665fc1ab307bed98cfcb6adf\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~634 debug messages>

21.28. Executing OPT pass (performing simple optimizations).

21.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~102 debug messages>

21.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

21.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$2539 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$2120_Y, Q = \ResetBootSystem.counter, rval = 6'000000).

21.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 27 unused cells and 3649 unused wires.
<suppressed ~28 debug messages>

21.28.5. Rerunning OPT passes. (Removed registers in this run.)

21.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

21.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$4009 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$2570 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).

21.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 4 unused wires.
<suppressed ~3 debug messages>

21.28.10. Rerunning OPT passes. (Removed registers in this run.)

21.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.28.13. Executing OPT_DFF pass (perform DFF optimizations).

21.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.28.15. Finished fast OPT passes.

21.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

21.30. Executing OPT pass (performing simple optimizations).

21.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~44 debug messages>

21.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2129: { $flatten\ResetBootSystem.$procmux$2124_CMP $flatten\ResetBootSystem.$procmux$2123_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2132:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2132_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2132_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2132_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2064:
      Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$2571 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$2571 [2]
      New connections: $auto$wreduce.cc:461:run$2571 [1:0] = 2'10
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2085:
      Old ports: A=4'0110, B=12'101101111110, Y=$flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0]
      New ports: A=3'010, B=9'101011110, Y={ $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [3:2] $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [0] }
      New connections: $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [1] = 1'1
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2033:
      Old ports: A=3'000, B=3'100, Y=$flatten\SOC.\Core.\Control_Unit.$3\nextstate[2:0]
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\Control_Unit.$3\nextstate[2:0] [2]
      New connections: $flatten\SOC.\Core.\Control_Unit.$3\nextstate[2:0] [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2041:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2576 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2576 [0]
      New connections: $auto$wreduce.cc:461:run$2576 [1] = $auto$wreduce.cc:461:run$2576 [0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$949:
      Old ports: A=3'000, B={ 2'00 \SOC.Uart.i_uart_tx.uart_tx_en 1'0 $auto$wreduce.cc:461:run$2579 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$2581 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \SOC.Uart.i_uart_tx.uart_tx_en $auto$wreduce.cc:461:run$2579 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$2581 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$565:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2581 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2581 [0]
      New connections: $auto$wreduce.cc:461:run$2581 [1] = $auto$wreduce.cc:461:run$2581 [0]
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2138:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2132_Y, Y=$flatten\ResetBootSystem.$procmux$2138_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2132_Y [1], Y=$flatten\ResetBootSystem.$procmux$2138_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2138_Y [0] = 1'0
  Optimizing cells in module \top.
Performed a total of 9 changes.

21.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.30.6. Executing OPT_DFF pass (perform DFF optimizations).

21.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.30.9. Rerunning OPT passes. (Maybe there is more to do..)

21.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~44 debug messages>

21.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.30.13. Executing OPT_DFF pass (perform DFF optimizations).

21.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.30.16. Finished OPT passes. (There is nothing left to do.)

21.31. Executing TECHMAP pass (map to technology primitives).

21.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

21.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $dff.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $mux.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $reduce_bool.
Using template $paramod$1c4a6e60ad8c85c8d80dadfee7b35034edee36a8\_80_ecp5_alu for cells of type $alu.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using template $paramod$861f5302217787cd55fd1a501bc728125f176580\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c96def1cdcef2eee3c62e5dfb7ba2dd09c9f74dd\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_or.
Using template $paramod$3111a1a8e90c88cc8c163ba5aed0203d96ddc46d\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $bmux.
Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $tribuf.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$215440792383f7884e57d9c95f84e9552d0bf4ac\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$41ef080258eed1ff8fcfbb7776f540ab469a3d7b\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c4ef20b21801b37ea2d65c32a05dfe56e84a870d\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$c83925f608704c3fa34790ddcfce9302bdcd7533\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $ne.
Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux.
Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_pmux for cells of type $pmux.
Using template $paramod$97565c3687be688407d1272a293bd9d0ae6852dc\_90_pmux for cells of type $pmux.
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
Using template $paramod$a13703aa027da371a1931fc542d213d7de559b19\_90_pmux for cells of type $pmux.
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $dlatch.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$56955d0f36f77738c952d3505dc563df3ee11b94\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$a5f0941832cc861549e29ccafffe20bfdf2e5528\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
Using template $paramod$5d1d2614b24accd0f9d06c4779fd9ef771faf494\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~3638 debug messages>

21.32. Executing OPT pass (performing simple optimizations).

21.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6078 debug messages>

21.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3699 debug messages>
Removed a total of 1233 cells.

21.32.3. Executing OPT_DFF pass (perform DFF optimizations).

21.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 328 unused cells and 3564 unused wires.
<suppressed ~329 debug messages>

21.32.5. Finished fast OPT passes.

21.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

21.35. Executing TECHMAP pass (map to technology primitives).

21.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

21.35.2. Continuing TECHMAP pass.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
No more expansions possible.
<suppressed ~1405 debug messages>

21.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~27 debug messages>

21.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

21.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in top.

21.39. Executing ATTRMVCP pass (move or copy attributes).

21.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 6640 unused wires.
<suppressed ~1 debug messages>

21.41. Executing TECHMAP pass (map to technology primitives).

21.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

21.41.2. Continuing TECHMAP pass.

21.41.3. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping \$_DLATCH_N_.$ternary$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$27709 ($mux).
Mapping \$_DLATCH_N_.$logic_not$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$27708 ($logic_not).
<suppressed ~4 debug messages>

21.41.4. Executing OPT pass (performing simple optimizations).

21.41.4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.
<suppressed ~1 debug messages>

21.41.4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

21.41.4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.41.4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

21.41.4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

21.41.4.6. Executing OPT_DFF pass (perform DFF optimizations).

21.41.4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..
Removed 1 unused cells and 2 unused wires.
<suppressed ~2 debug messages>

21.41.4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

21.41.4.9. Rerunning OPT passes. (Maybe there is more to do..)

21.41.4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.41.4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

21.41.4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

21.41.4.13. Executing OPT_DFF pass (perform DFF optimizations).

21.41.4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..

21.41.4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

21.41.4.16. Finished OPT passes. (There is nothing left to do.)
Using template \$_DLATCH_N_ for cells of type $_DLATCH_N_.
No more expansions possible.
<suppressed ~4 debug messages>

21.42. Executing ABC9 pass.

21.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.3. Executing PROC pass (convert processes to netlists).

21.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27804'.
Cleaned up 1 empty switch.

21.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27805 in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.3.4. Executing PROC_INIT pass (extract init attributes).

21.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27805'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27803_EN[3:0]$27811
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27803_DATA[3:0]$27810
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27803_ADDR[3:0]$27809
Creating decoders for process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27804'.

21.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.\i' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27801_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27795_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27789_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27790_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27791_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27792_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27796_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27797_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27787_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27798_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27802_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27788_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27793_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27794_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27799_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27800_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27803_ADDR' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27805'.
  created $dff cell `$procdff$27855' with positive edge clock.
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27803_DATA' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27805'.
  created $dff cell `$procdff$27856' with positive edge clock.
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27803_EN' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27805'.
  created $dff cell `$procdff$27857' with positive edge clock.
Creating register for signal `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.\muxwre' using process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27804'.
  created direct connection (no actual register cell created).

21.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27829'.
Found and cleaned up 1 empty switch in `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27805'.
Removing empty process `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27804'.
Cleaned up 1 empty switch.

21.42.3.12. Executing OPT_EXPR pass (perform const folding).

21.42.4. Executing PROC pass (convert processes to netlists).

21.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27875'.
Cleaned up 1 empty switch.

21.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27876 in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.4.4. Executing PROC_INIT pass (extract init attributes).

21.42.4.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27876'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27874_EN[3:0]$27880
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27874_DATA[3:0]$27882
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27874_ADDR[3:0]$27881
Creating decoders for process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27875'.

21.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.\i' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27871_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27866_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27861_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27858_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27862_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27863_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27867_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27859_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27868_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27872_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27864_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27873_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27860_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27869_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27865_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27870_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27874_EN' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27876'.
  created $dff cell `$procdff$27926' with positive edge clock.
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27874_ADDR' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27876'.
  created $dff cell `$procdff$27927' with positive edge clock.
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27874_DATA' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27876'.
  created $dff cell `$procdff$27928' with positive edge clock.
Creating register for signal `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27875'.
  created direct connection (no actual register cell created).

21.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27900'.
Found and cleaned up 1 empty switch in `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27876'.
Removing empty process `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27875'.
Cleaned up 1 empty switch.

21.42.4.12. Executing OPT_EXPR pass (perform const folding).

21.42.5. Executing PROC pass (convert processes to netlists).

21.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27946'.
Cleaned up 1 empty switch.

21.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27947 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.5.4. Executing PROC_INIT pass (extract init attributes).

21.42.5.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27947'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27945_EN[3:0]$27953
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27945_DATA[3:0]$27952
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27945_ADDR[3:0]$27951
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27946'.

21.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27944_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27939_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27934_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27929_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27930_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27931_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27935_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27936_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27940_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27932_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27941_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27937_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27933_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27942_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27938_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27943_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27945_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27947'.
  created $dff cell `$procdff$27997' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27945_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27947'.
  created $dff cell `$procdff$27998' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27945_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27947'.
  created $dff cell `$procdff$27999' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27946'.
  created direct connection (no actual register cell created).

21.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27971'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27947'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27946'.
Cleaned up 1 empty switch.

21.42.5.12. Executing OPT_EXPR pass (perform const folding).

21.42.6. Executing PROC pass (convert processes to netlists).

21.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28017'.
Cleaned up 1 empty switch.

21.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28018 in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.6.4. Executing PROC_INIT pass (extract init attributes).

21.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28018'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28016_EN[3:0]$28023
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28016_DATA[3:0]$28022
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28016_ADDR[3:0]$28024
Creating decoders for process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28017'.

21.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.\i' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28012_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28007_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28002_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28000_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28009_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28013_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28001_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28006_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28015_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28005_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28011_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28014_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28004_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28003_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28010_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28008_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28016_DATA' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28018'.
  created $dff cell `$procdff$28068' with positive edge clock.
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28016_EN' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28018'.
  created $dff cell `$procdff$28069' with positive edge clock.
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28016_ADDR' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28018'.
  created $dff cell `$procdff$28070' with positive edge clock.
Creating register for signal `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28017'.
  created direct connection (no actual register cell created).

21.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28042'.
Found and cleaned up 1 empty switch in `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28018'.
Removing empty process `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28017'.
Cleaned up 1 empty switch.

21.42.6.12. Executing OPT_EXPR pass (perform const folding).

21.42.7. Executing PROC pass (convert processes to netlists).

21.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28088'.
Cleaned up 1 empty switch.

21.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28089 in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.7.4. Executing PROC_INIT pass (extract init attributes).

21.42.7.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28089'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28087_EN[3:0]$28095
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28087_DATA[3:0]$28094
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28087_ADDR[3:0]$28093
Creating decoders for process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28088'.

21.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.\i' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28085_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28080_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28075_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28071_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28072_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28076_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28077_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28081_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28073_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28082_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28086_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28078_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28074_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28083_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28079_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28084_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28087_ADDR' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28089'.
  created $dff cell `$procdff$28139' with positive edge clock.
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28087_DATA' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28089'.
  created $dff cell `$procdff$28140' with positive edge clock.
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28087_EN' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28089'.
  created $dff cell `$procdff$28141' with positive edge clock.
Creating register for signal `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28088'.
  created direct connection (no actual register cell created).

21.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28113'.
Found and cleaned up 1 empty switch in `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28089'.
Removing empty process `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28088'.
Cleaned up 1 empty switch.

21.42.7.12. Executing OPT_EXPR pass (perform const folding).

21.42.8. Executing PROC pass (convert processes to netlists).

21.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28159'.
Cleaned up 1 empty switch.

21.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28160 in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.8.4. Executing PROC_INIT pass (extract init attributes).

21.42.8.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.8.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28160'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28158_EN[3:0]$28166
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28158_DATA[3:0]$28165
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28158_ADDR[3:0]$28164
Creating decoders for process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28159'.

21.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.\i' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28155_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28149_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28143_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28142_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28144_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28145_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28146_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28150_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28151_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28152_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28156_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28157_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28147_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28148_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28153_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28154_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28158_ADDR' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28160'.
  created $dff cell `$procdff$28210' with positive edge clock.
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28158_DATA' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28160'.
  created $dff cell `$procdff$28211' with positive edge clock.
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28158_EN' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28160'.
  created $dff cell `$procdff$28212' with positive edge clock.
Creating register for signal `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.\muxwre' using process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28159'.
  created direct connection (no actual register cell created).

21.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28184'.
Found and cleaned up 1 empty switch in `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28160'.
Removing empty process `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28159'.
Cleaned up 1 empty switch.

21.42.8.12. Executing OPT_EXPR pass (perform const folding).

21.42.9. Executing PROC pass (convert processes to netlists).

21.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28230'.
Cleaned up 1 empty switch.

21.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28231 in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.9.4. Executing PROC_INIT pass (extract init attributes).

21.42.9.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.9.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28231'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28229_EN[3:0]$28235
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28229_DATA[3:0]$28237
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28229_ADDR[3:0]$28236
Creating decoders for process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28230'.

21.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.\i' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28225_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28219_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28213_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28214_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28215_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28216_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28220_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28221_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28222_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28226_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28227_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28217_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28228_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28218_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28223_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28224_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28229_EN' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28231'.
  created $dff cell `$procdff$28281' with positive edge clock.
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28229_ADDR' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28231'.
  created $dff cell `$procdff$28282' with positive edge clock.
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28229_DATA' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28231'.
  created $dff cell `$procdff$28283' with positive edge clock.
Creating register for signal `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.\muxwre' using process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28230'.
  created direct connection (no actual register cell created).

21.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28255'.
Found and cleaned up 1 empty switch in `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28231'.
Removing empty process `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28230'.
Cleaned up 1 empty switch.

21.42.9.12. Executing OPT_EXPR pass (perform const folding).

21.42.10. Executing PROC pass (convert processes to netlists).

21.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28301'.
Cleaned up 1 empty switch.

21.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28302 in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.10.4. Executing PROC_INIT pass (extract init attributes).

21.42.10.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.10.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28302'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28300_EN[3:0]$28307
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28300_DATA[3:0]$28306
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28300_ADDR[3:0]$28308
Creating decoders for process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28301'.

21.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.\i' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28295_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28289_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28284_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28285_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28286_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28290_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28291_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28292_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28296_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28297_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28287_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28298_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28288_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28293_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28294_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28299_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28300_DATA' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28302'.
  created $dff cell `$procdff$28352' with positive edge clock.
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28300_EN' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28302'.
  created $dff cell `$procdff$28353' with positive edge clock.
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28300_ADDR' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28302'.
  created $dff cell `$procdff$28354' with positive edge clock.
Creating register for signal `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28301'.
  created direct connection (no actual register cell created).

21.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28326'.
Found and cleaned up 1 empty switch in `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28302'.
Removing empty process `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28301'.
Cleaned up 1 empty switch.

21.42.10.12. Executing OPT_EXPR pass (perform const folding).

21.42.11. Executing PROC pass (convert processes to netlists).

21.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28372'.
Cleaned up 1 empty switch.

21.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28373 in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.11.4. Executing PROC_INIT pass (extract init attributes).

21.42.11.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.11.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28373'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28371_EN[3:0]$28377
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28371_DATA[3:0]$28379
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28371_ADDR[3:0]$28378
Creating decoders for process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28372'.

21.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.\i' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28368_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28363_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28358_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28355_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28359_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28360_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28364_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28356_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28365_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28369_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28361_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28370_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28357_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28366_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28362_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$28367_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28371_EN' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28373'.
  created $dff cell `$procdff$28423' with positive edge clock.
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28371_ADDR' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28373'.
  created $dff cell `$procdff$28424' with positive edge clock.
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$28371_DATA' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28373'.
  created $dff cell `$procdff$28425' with positive edge clock.
Creating register for signal `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28372'.
  created direct connection (no actual register cell created).

21.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$28397'.
Found and cleaned up 1 empty switch in `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$28373'.
Removing empty process `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$28372'.
Cleaned up 1 empty switch.

21.42.11.12. Executing OPT_EXPR pass (perform const folding).

21.42.12. Executing SCC pass (detecting logic loops).
Found an SCC: $techmap$auto$ff.cc:266:slice$11836.$auto$simplemap.cc:267:simplemap_mux$27711
Found an SCC: $techmap$auto$ff.cc:266:slice$11835.$auto$simplemap.cc:267:simplemap_mux$27711
Found an SCC: $techmap$auto$ff.cc:266:slice$11834.$auto$simplemap.cc:267:simplemap_mux$27711
Found an SCC: $techmap$auto$ff.cc:266:slice$11833.$auto$simplemap.cc:267:simplemap_mux$27711
Found an SCC: $auto$simplemap.cc:38:simplemap_not$24226 $auto$ff.cc:266:slice$7624 $auto$simplemap.cc:126:simplemap_reduce$7787 $auto$simplemap.cc:126:simplemap_reduce$7802 $auto$ff.cc:266:slice$7625 $auto$ff.cc:266:slice$7626 $auto$opt_expr.cc:613:replace_const_cells$25847 $auto$simplemap.cc:225:simplemap_logbin$7777 $auto$simplemap.cc:196:simplemap_lognot$7792 $auto$simplemap.cc:126:simplemap_reduce$7790 $auto$simplemap.cc:126:simplemap_reduce$7788 $auto$opt_expr.cc:613:replace_const_cells$25661 $auto$simplemap.cc:267:simplemap_mux$15983 $auto$simplemap.cc:126:simplemap_reduce$15997 $auto$simplemap.cc:126:simplemap_reduce$15994 $auto$simplemap.cc:75:simplemap_bitop$15987 $auto$simplemap.cc:196:simplemap_lognot$7807 $auto$simplemap.cc:126:simplemap_reduce$7805 $auto$simplemap.cc:126:simplemap_reduce$7803 $auto$opt_expr.cc:613:replace_const_cells$25631 $auto$ff.cc:266:slice$7627 $auto$simplemap.cc:126:simplemap_reduce$4931 $auto$simplemap.cc:126:simplemap_reduce$4929 $auto$simplemap.cc:225:simplemap_logbin$7756 $auto$simplemap.cc:196:simplemap_lognot$7766 $auto$simplemap.cc:126:simplemap_reduce$7764 $auto$opt_expr.cc:613:replace_const_cells$25663 $auto$simplemap.cc:267:simplemap_mux$15984 $auto$simplemap.cc:126:simplemap_reduce$16002 $auto$simplemap.cc:126:simplemap_reduce$15999 $auto$simplemap.cc:75:simplemap_bitop$15985
Found an SCC: $auto$simplemap.cc:38:simplemap_not$16979 $auto$ff.cc:266:slice$4382 $auto$ff.cc:266:slice$4374 $auto$ff.cc:266:slice$4357 $auto$ff.cc:266:slice$4358 $auto$simplemap.cc:38:simplemap_not$16976 $auto$ff.cc:266:slice$4379 $auto$simplemap.cc:38:simplemap_not$16973 $auto$ff.cc:266:slice$4376 $auto$simplemap.cc:126:simplemap_reduce$7399 $auto$simplemap.cc:38:simplemap_not$16975 $auto$ff.cc:266:slice$4378 $auto$simplemap.cc:126:simplemap_reduce$7398 $auto$ff.cc:266:slice$4377 $auto$ff.cc:266:slice$4373 $auto$simplemap.cc:38:simplemap_not$16967 $auto$ff.cc:266:slice$4370 $auto$ff.cc:266:slice$4359 $auto$ff.cc:266:slice$4355 $auto$simplemap.cc:38:simplemap_not$16978 $auto$ff.cc:266:slice$4381 $auto$alumacc.cc:485:replace_alu$2693.slice[0].ccu2c_i $auto$simplemap.cc:38:simplemap_not$16957 $auto$ff.cc:266:slice$4360 $auto$simplemap.cc:126:simplemap_reduce$7396 $auto$ff.cc:266:slice$4372 $auto$simplemap.cc:126:simplemap_reduce$7401 $auto$simplemap.cc:38:simplemap_not$14288 $auto$ff.cc:266:slice$4383 $auto$simplemap.cc:126:simplemap_reduce$7408 $auto$simplemap.cc:126:simplemap_reduce$7395 $auto$ff.cc:266:slice$4371 $auto$ff.cc:266:slice$4367 $auto$simplemap.cc:38:simplemap_not$14289 $auto$ff.cc:266:slice$4384 $auto$ff.cc:266:slice$4369 $auto$simplemap.cc:126:simplemap_reduce$7415 $auto$simplemap.cc:126:simplemap_reduce$7409 $auto$simplemap.cc:126:simplemap_reduce$7397 $auto$ff.cc:266:slice$4375 $auto$ff.cc:266:slice$4364 $auto$simplemap.cc:126:simplemap_reduce$7392 $auto$ff.cc:266:slice$4365 $auto$simplemap.cc:126:simplemap_reduce$7393 $auto$ff.cc:266:slice$4366 $auto$simplemap.cc:126:simplemap_reduce$7388 $auto$ff.cc:266:slice$4356 $auto$simplemap.cc:38:simplemap_not$16959 $auto$ff.cc:266:slice$4362 $auto$simplemap.cc:126:simplemap_reduce$7407 $auto$simplemap.cc:126:simplemap_reduce$7394 $auto$simplemap.cc:38:simplemap_not$16965 $auto$ff.cc:266:slice$4368 $auto$simplemap.cc:126:simplemap_reduce$7410 $auto$simplemap.cc:126:simplemap_reduce$7400 $auto$simplemap.cc:38:simplemap_not$16977 $auto$ff.cc:266:slice$4380 $auto$simplemap.cc:126:simplemap_reduce$7419 $auto$simplemap.cc:126:simplemap_reduce$7416 $auto$simplemap.cc:126:simplemap_reduce$7411 $auto$simplemap.cc:126:simplemap_reduce$7402 $auto$simplemap.cc:38:simplemap_not$16982 $auto$ff.cc:266:slice$4385 $auto$simplemap.cc:126:simplemap_reduce$7414 $auto$simplemap.cc:126:simplemap_reduce$7406 $auto$simplemap.cc:126:simplemap_reduce$7391 $auto$simplemap.cc:38:simplemap_not$16960 $auto$ff.cc:266:slice$4363 $auto$simplemap.cc:38:simplemap_not$7422 $auto$simplemap.cc:225:simplemap_logbin$16911 $auto$alumacc.cc:485:replace_alu$2693.slice[24].ccu2c_i $auto$alumacc.cc:485:replace_alu$2693.slice[22].ccu2c_i $auto$alumacc.cc:485:replace_alu$2693.slice[20].ccu2c_i $auto$alumacc.cc:485:replace_alu$2693.slice[18].ccu2c_i $auto$alumacc.cc:485:replace_alu$2693.slice[16].ccu2c_i $auto$alumacc.cc:485:replace_alu$2693.slice[14].ccu2c_i $auto$alumacc.cc:485:replace_alu$2693.slice[12].ccu2c_i $auto$alumacc.cc:485:replace_alu$2693.slice[10].ccu2c_i $auto$alumacc.cc:485:replace_alu$2693.slice[8].ccu2c_i $auto$alumacc.cc:485:replace_alu$2693.slice[6].ccu2c_i $auto$alumacc.cc:485:replace_alu$2693.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$2693.slice[2].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7390 $auto$simplemap.cc:38:simplemap_not$16958 $auto$ff.cc:266:slice$4361 $auto$simplemap.cc:126:simplemap_reduce$7404 $auto$simplemap.cc:126:simplemap_reduce$7387 $auto$ff.cc:266:slice$4354 $auto$simplemap.cc:126:simplemap_reduce$10751 $auto$simplemap.cc:126:simplemap_reduce$10749 $auto$simplemap.cc:126:simplemap_reduce$7421 $auto$simplemap.cc:126:simplemap_reduce$7418 $auto$simplemap.cc:126:simplemap_reduce$7413 $auto$simplemap.cc:126:simplemap_reduce$7405 $auto$simplemap.cc:126:simplemap_reduce$7389 $auto$simplemap.cc:38:simplemap_not$16956
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$11739 $auto$simplemap.cc:38:simplemap_not$7423 $auto$opt_expr.cc:613:replace_const_cells$25639 $auto$ff.cc:266:slice$8116 $auto$ff.cc:479:convert_ce_over_srst$26395 $auto$alumacc.cc:485:replace_alu$2682.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7426 $auto$simplemap.cc:38:simplemap_not$14305 $auto$ff.cc:266:slice$8117 $auto$ff.cc:479:convert_ce_over_srst$26397 $auto$ff.cc:266:slice$8118 $auto$ff.cc:479:convert_ce_over_srst$26399 $auto$alumacc.cc:485:replace_alu$2682.slice[2].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7430 $auto$simplemap.cc:126:simplemap_reduce$7427 $auto$simplemap.cc:38:simplemap_not$14307 $auto$ff.cc:266:slice$8119 $auto$ff.cc:479:convert_ce_over_srst$26401 $auto$ff.cc:266:slice$8120 $auto$ff.cc:479:convert_ce_over_srst$26403 $auto$simplemap.cc:126:simplemap_reduce$10732 $auto$simplemap.cc:75:simplemap_bitop$7424 $auto$simplemap.cc:38:simplemap_not$7433 $auto$alumacc.cc:485:replace_alu$2682.slice[4].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$7428 $auto$simplemap.cc:38:simplemap_not$24259 $auto$ff.cc:266:slice$8121 $auto$ff.cc:479:convert_ce_over_srst$26405 $auto$simplemap.cc:126:simplemap_reduce$4153 $auto$simplemap.cc:126:simplemap_reduce$4151 $auto$simplemap.cc:126:simplemap_reduce$11741 $auto$simplemap.cc:126:simplemap_reduce$11738 $auto$simplemap.cc:126:simplemap_reduce$7432
Found an SCC: $auto$simplemap.cc:38:simplemap_not$14829 $auto$ff.cc:266:slice$7637 $auto$ff.cc:266:slice$7638 $auto$ff.cc:266:slice$7640 $auto$simplemap.cc:126:simplemap_reduce$7831 $auto$simplemap.cc:38:simplemap_not$14831 $auto$ff.cc:266:slice$7639 $auto$ff.cc:266:slice$7629 $auto$ff.cc:266:slice$7632 $auto$simplemap.cc:126:simplemap_reduce$7826 $auto$ff.cc:266:slice$7628 $auto$ff.cc:266:slice$7634 $auto$simplemap.cc:38:simplemap_not$14822 $auto$ff.cc:266:slice$7630 $auto$simplemap.cc:126:simplemap_reduce$7833 $auto$simplemap.cc:126:simplemap_reduce$7827 $auto$simplemap.cc:38:simplemap_not$14823 $auto$ff.cc:266:slice$7631 $auto$simplemap.cc:126:simplemap_reduce$7838 $auto$simplemap.cc:126:simplemap_reduce$7835 $auto$simplemap.cc:126:simplemap_reduce$7830 $auto$ff.cc:266:slice$7636 $auto$simplemap.cc:126:simplemap_reduce$7828 $auto$simplemap.cc:38:simplemap_not$14825 $auto$ff.cc:266:slice$7633 $auto$ff.cc:266:slice$7635 $auto$simplemap.cc:167:logic_reduce$4925 $auto$simplemap.cc:196:simplemap_lognot$7842 $auto$simplemap.cc:126:simplemap_reduce$7840 $auto$simplemap.cc:126:simplemap_reduce$7837 $auto$simplemap.cc:126:simplemap_reduce$7834 $auto$simplemap.cc:126:simplemap_reduce$7829
Found 8 SCCs in module top.
Found 8 SCCs.

21.42.13. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.14. Executing PROC pass (convert processes to netlists).

21.42.14.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

21.42.14.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

21.42.14.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

21.42.14.4. Executing PROC_INIT pass (extract init attributes).

21.42.14.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.14.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

21.42.14.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

21.42.14.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.14.9. Executing PROC_DFF pass (convert process syncs to FFs).

21.42.14.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.14.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

21.42.14.12. Executing OPT_EXPR pass (perform const folding).

21.42.15. Executing TECHMAP pass (map to technology primitives).

21.42.15.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.42.15.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~178 debug messages>

21.42.16. Executing OPT pass (performing simple optimizations).

21.42.16.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Optimizing module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Optimizing module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Optimizing module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Optimizing module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Optimizing module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Optimizing module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.

21.42.16.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

21.42.16.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.16.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Performed a total of 0 changes.

21.42.16.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

21.42.16.6. Executing OPT_DFF pass (perform DFF optimizations).

21.42.16.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4..

21.42.16.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Optimizing module $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Optimizing module $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Optimizing module $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Optimizing module $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Optimizing module $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Optimizing module $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Optimizing module $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.

21.42.16.9. Finished OPT passes. (There is nothing left to do.)

21.42.17. Executing TECHMAP pass (map to technology primitives).

21.42.17.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

21.42.17.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4 for cells of type $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Using template $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4 for cells of type $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Using template $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4 for cells of type $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Using template $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4 for cells of type $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Using template $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4 for cells of type $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Using template $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4 for cells of type $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Using template $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4 for cells of type $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Using template $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4 for cells of type $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~523 debug messages>

21.42.18. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

21.42.19. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

21.42.20. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.21. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

21.42.22. Executing TECHMAP pass (map to technology primitives).

21.42.22.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.42.22.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~217 debug messages>

21.42.23. Executing OPT pass (performing simple optimizations).

21.42.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~18 debug messages>

21.42.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

21.42.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.42.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.42.23.6. Executing OPT_DFF pass (perform DFF optimizations).

21.42.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

21.42.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.42.23.9. Rerunning OPT passes. (Maybe there is more to do..)

21.42.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.42.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.42.23.13. Executing OPT_DFF pass (perform DFF optimizations).

21.42.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.42.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.42.23.16. Finished OPT passes. (There is nothing left to do.)

21.42.24. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

21.42.25. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 5988 cells with 33342 new cells, skipped 5743 cells.
  replaced 3 cell types:
    2858 $_OR_
      67 $_XOR_
    3063 $_MUX_
  not replaced 24 cell types:
     366 $_NOT_
    2822 $_AND_
       5 $_TBUF_
    1301 TRELLIS_FF
       1 $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4
       1 $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4
       1 $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp
     504 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
     224 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
       1 $__ABC9_SCC_BREAKER
       1 $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4
       1 $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4
     504 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
       1 $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4
       1 $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4
       1 $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4
       1 $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4

21.42.25.1. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.25.2. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.25.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 15070 AND gates and 43058 wires from module `top' to a netlist network with 3365 inputs and 492 outputs.

21.42.25.4. Executing ABC9_EXE pass (technology mapping using ABC9).

21.42.25.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   3365/    492  and =   13829  lev =   47 (6.68)  mem = 0.35 MB  box = 736  bb = 512
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   3365/    492  and =   20175  lev =   62 (4.45)  mem = 0.41 MB  ch = 1472  box = 660  bb = 512
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   60. Obj =  140. Set =  636. CutMin = no
ABC: Node =   20175.  Ch =  1029.  Total mem =    4.75 MB. Peak cut mem =    0.20 MB.
ABC: P:  Del = 7030.00.  Ar =   22354.0.  Edge =    24274.  Cut =   302512.  T =     0.07 sec
ABC: P:  Del = 6782.00.  Ar =   22476.0.  Edge =    24230.  Cut =   279917.  T =     0.07 sec
ABC: P:  Del = 6782.00.  Ar =    9100.0.  Edge =    19449.  Cut =   654088.  T =     0.14 sec
ABC: F:  Del = 6782.00.  Ar =    6428.0.  Edge =    17021.  Cut =   498251.  T =     0.12 sec
ABC: A:  Del = 6782.00.  Ar =    5572.0.  Edge =    15651.  Cut =   492242.  T =     0.20 sec
ABC: A:  Del = 6782.00.  Ar =    5513.0.  Edge =    15575.  Cut =   488626.  T =     0.20 sec
ABC: Total time =     0.80 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   3365/    492  and =   12631  lev =   39 (3.73)  mem = 0.33 MB  box = 660  bb = 512
ABC: Mapping (K=7)  :  lut =   3808  edge =   15523  lev =   14 (2.00)  levB =   26  mem = 0.18 MB
ABC: LUT = 3808 : 2=224 5.9 %  3=312 8.2 %  4=2564 67.3 %  5=498 13.1 %  6=77 2.0 %  7=133 3.5 %  Ave = 4.08
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 4.84 seconds, total: 4.84 seconds

21.42.25.6. Executing AIGER frontend.
<suppressed ~7802 debug messages>
Removed 16031 unused cells and 29971 unused wires.

21.42.25.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     3826
ABC RESULTS:   $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:      504
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      148
ABC RESULTS:   $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:           input signals:      569
ABC RESULTS:          output signals:      107
Removing temp directory.

21.42.26. Executing TECHMAP pass (map to technology primitives).

21.42.26.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

21.42.26.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4 for cells of type $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4.
Using template $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$c796f3aafb530189a9e278fc2a97f2eb67116164\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4 for cells of type $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4.
Using template $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$b447c5bf95f0878bc4f7467b5129df7c93483367\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4 for cells of type $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4.
Using template $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$69dba5f79aae0a311e85b026f4073dd17694fb6c\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4 for cells of type $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4.
Using template $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4 for cells of type $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4.
Using template $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4 for cells of type $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4.
Using template $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4 for cells of type $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4.
Using template $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4 for cells of type $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4.
Using template $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$f5853d1b4efb2773c5c944aeb4de301e16ac158f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$31e6de5a51db3d33b0302c81374307268ef6d374\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$3da461b29bf2e0c9bee9e2bff1b2a3c21483ef68\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d04d37e33ac49ea6b46510304d7f1c64e446ba08\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001000 for cells of type $__ABC9_SCC_BREAKER.
Using template $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d4aa5571ba0b0cbe8b2c978f3e7f9f16122d0867\TRELLIS_DPR16X4_$abc9_byp.
No more expansions possible.
<suppressed ~1208 debug messages>
Removed 209 unused cells and 49180 unused wires.

21.43. Executing TECHMAP pass (map to technology primitives).

21.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

21.43.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$c1e03ad83f785f1cb08178836c284676a688a458\$lut for cells of type $lut.
Using template $paramod$874ccaa8ca7783774f35da6418d6fdb7651f35c0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$40bf400bfab4b5cf32dcfe01e14f0900ac7f6b1b\$lut for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod$35f1cf51add8f9ea7c3b0e13553ba1e7e1b636a2\$lut for cells of type $lut.
Using template $paramod$5e2c4e05bbdd2eaa20212f01bb8e88597c0f6680\$lut for cells of type $lut.
Using template $paramod$2c1875de701f39453798b76f5b327fe456cc0991\$lut for cells of type $lut.
Using template $paramod$a743caf801766df40bcc22d49baa12a0bdc2f7fe\$lut for cells of type $lut.
Using template $paramod$6c8df34f38f3bb4fc8db8d09eb9f20a15c6ee32e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$b4d0f4738a5ce50c7f36c2aa2ecc09cfb874f2b6\$lut for cells of type $lut.
Using template $paramod$7202672b7332febf25cdbe5424cf24593f5449be\$lut for cells of type $lut.
Using template $paramod$f28c2e49975958241d4d835ef97e799ed72256e5\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$8540495becc5977ef0ebaa7b0aa27d3683d9ed0c\$lut for cells of type $lut.
Using template $paramod$ac4554ffa35b9d2fa5b7348516757776a7a67f02\$lut for cells of type $lut.
Using template $paramod$a29dc9226a883358910d3758606f48686bda2689\$lut for cells of type $lut.
Using template $paramod$79c3d83d4871e26e96c90c891dc3096781d9df3e\$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$2a0fcf50e11f6cd8a2a8336669cf63de60636586\$lut for cells of type $lut.
Using template $paramod$5f301d4621548048d910116bcc8ed10e1833e08c\$lut for cells of type $lut.
Using template $paramod$b4b5740b5640612c1d89992d679c6c734bdba6f9\$lut for cells of type $lut.
Using template $paramod$803fb2e411cd759897bb32714c4cd91d7f11ca86\$lut for cells of type $lut.
Using template $paramod$f5d8233a2fdbec6a6ed40b4cfc6b7365fd4484fe\$lut for cells of type $lut.
Using template $paramod$cd4f4295f5084044560b62b49d805756222899b9\$lut for cells of type $lut.
Using template $paramod$67b1b761102ea2ed7f0f277d000c631a9072a22f\$lut for cells of type $lut.
Using template $paramod$08e0515b71182b69329467e1e009a2fd6b1d4c54\$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod$8829675bb8c52553aed9f101ec0d5ef0c865e5c7\$lut for cells of type $lut.
Using template $paramod$913f3e117e0a42cc17697f45936a362259569cfa\$lut for cells of type $lut.
Using template $paramod$5dec547b44f0cd5dfd621ba61a51196e0a8a0f35\$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$f34c9ba492480627f47d8dfcd782f1eaf78c7d94\$lut for cells of type $lut.
Using template $paramod$d255a4a46bd4a36a5790aca5d885d457f08599e2\$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod$88ed425d0071e87296cc9a8557e5b7dc89eaee12\$lut for cells of type $lut.
Using template $paramod$5d123e00fbda0ee68221352f0694a6049f7f183c\$lut for cells of type $lut.
Using template $paramod$130af793a2ec6ecceb3e0ef509cf6b180e856b6f\$lut for cells of type $lut.
Using template $paramod$becdf848295816388551cb2646615a33bdb04e11\$lut for cells of type $lut.
Using template $paramod$0f9a5ffb15c1e481b6b1d423325ea99a60119726\$lut for cells of type $lut.
Using template $paramod$7fc8544ffe292914f3b1ba5191dc3eedcc2e5a3f\$lut for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$eb910726ff5861dd9396a7c5aa886ad79576be97\$lut for cells of type $lut.
Using template $paramod$e5e84348467ecf6d5ce2b59f12a6096feab827b2\$lut for cells of type $lut.
Using template $paramod$7ee6c3286a349174c5e1aff5b6a17ba6deaea830\$lut for cells of type $lut.
Using template $paramod$4b23d751b3e1d7cde9cd1766bf20ceee12e38a3d\$lut for cells of type $lut.
Using template $paramod$429329241ae63682154f412c8b86b8896211705d\$lut for cells of type $lut.
Using template $paramod$09194da5f2c8e08bed8f609fd0e254d8629b24b3\$lut for cells of type $lut.
Using template $paramod$b2dba46aa2b0149f438da882ac896f20127f0b60\$lut for cells of type $lut.
Using template $paramod$fda4707794770d6f29932889cc489c0256b1ae48\$lut for cells of type $lut.
Using template $paramod$20b41872982a1d3a14464728d6f36ed06e69498a\$lut for cells of type $lut.
Using template $paramod$bc4a6b809cbbc009de87c18a1b6edb9ef520238c\$lut for cells of type $lut.
Using template $paramod$b2864c3206d4428f10766ba1966e24a61f1d027e\$lut for cells of type $lut.
Using template $paramod$0305e8e4c893d751520019ea9347bab68d22be05\$lut for cells of type $lut.
Using template $paramod$cfe658add7b49bc6805d629e0a88423d427de396\$lut for cells of type $lut.
Using template $paramod$f054a7d7ab239e8c6ce022005b59678182897bfe\$lut for cells of type $lut.
Using template $paramod$d39daf56a31b2e8ce06533aad96ed54894dfed59\$lut for cells of type $lut.
Using template $paramod$4ec858c47b7778c9131c4204cef9a039ed565428\$lut for cells of type $lut.
Using template $paramod$4dd4a9d54065b1696fc5e1c7ca18ff772310a315\$lut for cells of type $lut.
Using template $paramod$b8113752b08bd47f69a1c8c2bca1cfb157e800c9\$lut for cells of type $lut.
Using template $paramod$0d5a9938198c8aeef3d3ac7eddda9d177042e13c\$lut for cells of type $lut.
Using template $paramod$7a1718b26287c3698b1ec859c91817689dad72ff\$lut for cells of type $lut.
Using template $paramod$a88cbe275ca0f24a28b776a3819125328c2b6eb0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$01b636f2759ab594c2741266b3c22685988e291c\$lut for cells of type $lut.
Using template $paramod$6fc23ce09f2013cb9de2228dbcdda21841008f92\$lut for cells of type $lut.
Using template $paramod$2173de3b863bca56f7f65301b84bc178e6f2c71f\$lut for cells of type $lut.
Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut.
Using template $paramod$73b79051db5218b405f7c74f604647aed4aa0559\$lut for cells of type $lut.
Using template $paramod$607287ded17c450b8d4fc68174c254d5b5d55899\$lut for cells of type $lut.
Using template $paramod$30824f21a9f8bed38fce745c7e6310f57a7a6451\$lut for cells of type $lut.
Using template $paramod$a7dad16c080c08c1647c7e1b9706a59a123d8bcd\$lut for cells of type $lut.
Using template $paramod$3b374b0454c507d1efadee363d480c52c3b3f58f\$lut for cells of type $lut.
Using template $paramod$3f2c557865dd7ee52bf964f1d9c26774da90ebb5\$lut for cells of type $lut.
Using template $paramod$4900a2fac790e59cf03c38b46fe588aa052b7555\$lut for cells of type $lut.
Using template $paramod$b97dea647725901eed851280e5a3889ea3e50a3d\$lut for cells of type $lut.
Using template $paramod$cc2a095eb455a4b3d2a771dcc8d049b19888952d\$lut for cells of type $lut.
Using template $paramod$6b426eeaf6533b96f4b3c8e9ae3501bf492564c2\$lut for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut.
Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e\$lut for cells of type $lut.
Using template $paramod$d8acfcac714e132df9d74ab1f5732336bac5f56c\$lut for cells of type $lut.
Using template $paramod$56079f369d766181fb52d14b1ffc1de70ddb148d\$lut for cells of type $lut.
Using template $paramod$874323b1b03bdf604ef39a47eba69b0b6ac78f25\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$fb17a9732b22d43717c59597fcdf362ab87aef76\$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod$d700d5cc76f86490d99cc7f406eead77f4e1ae7b\$lut for cells of type $lut.
Using template $paramod$ddf5041833ca180cece5c04cc6c13097dee1dfee\$lut for cells of type $lut.
Using template $paramod$ec1ba13261471652a1600b57f1ebaf5eccb2b34a\$lut for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod$5f9b7bf48a6fadb9801093f0c05e10146ed56eaa\$lut for cells of type $lut.
Using template $paramod$7562579f4b6cddaf6813bdaed7637a5cce67162c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$7fc325150916e09e21db63cc9672b99a89ef9301\$lut for cells of type $lut.
Using template $paramod$587bb239a5a4de50b1b910a4448ecc99be745253\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut.
Using template $paramod$83821a066236f01fefdc8a5b6ba5f8c52084787b\$lut for cells of type $lut.
Using template $paramod$024e95241da3cebf78e228447139a39694a29c0a\$lut for cells of type $lut.
Using template $paramod$c5e9409d868ac22b0d04fa66386bddf5c7c8858c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$481d1baa81ed1e68962f554dca6895a6c4eed364\$lut for cells of type $lut.
Using template $paramod$89650da14f66821831b73df96caa126dfa6e9359\$lut for cells of type $lut.
Using template $paramod$26457813620ed8358013f1ae0e558890b7cacc4b\$lut for cells of type $lut.
Using template $paramod$f58e0d90afc57a738914697b6a4a7319b30d7e7e\$lut for cells of type $lut.
Using template $paramod$4d7dc822e6ac78c7574e16060f5e26124cddca40\$lut for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$be95f3a2132281eadd1adcfe6229e43dbc3353c9\$lut for cells of type $lut.
Using template $paramod$6ff81f730f8b59d892f57895d61776245fbfaaec\$lut for cells of type $lut.
Using template $paramod$6c1e00c0bc35cf54843f4c6c5256c8106cb8a199\$lut for cells of type $lut.
Using template $paramod$221832ea6a41a3208cd6f3411a952b5811695f4c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$a15fd389a2f54cb7b94707b25934d226e68d9e2e\$lut for cells of type $lut.
Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut.
Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0\$lut for cells of type $lut.
Using template $paramod$cb1cd89237f31f29c980d0ccd1a8936073e6db69\$lut for cells of type $lut.
Using template $paramod$aab54572d5ffecd31253b36e73e9cb718d05be34\$lut for cells of type $lut.
Using template $paramod$d546db88fc169832512e499a9cdf9a41b89ab74e\$lut for cells of type $lut.
Using template $paramod$0f891ee84fac320f890afcf9c994c53a24cd31f9\$lut for cells of type $lut.
Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$8075729953f49b6cb1b4d863b2fb20da9818d304\$lut for cells of type $lut.
Using template $paramod$4e0dac06d9d9602cfb659e01e0850b77eec5b798\$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$09deb89cf77b6e37f6ed7fef8d797dc05c0b2eee\$lut for cells of type $lut.
Using template $paramod$6023c671e114c4eb0467aa8a0b08e183f33ec2fd\$lut for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod$75ae9627805e0c99d176bdce0ae8ff0c02687aab\$lut for cells of type $lut.
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut.
Using template $paramod$f14392a4cc12ec2a0dfed843473b2f24e813a7e1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$b98c5cad3e4b1575461e7c6b454efd7b9d35666f\$lut for cells of type $lut.
Using template $paramod$3416dacc8eaab1f89b3d6b7398df3da766d29ef2\$lut for cells of type $lut.
Using template $paramod$5d9d4826b4537254130d485441e860419b94471b\$lut for cells of type $lut.
Using template $paramod$0331e023d83b8009e60defb446ce9fa640b122c7\$lut for cells of type $lut.
Using template $paramod$34cfe9df4430063fabfbb926faa11063185271c0\$lut for cells of type $lut.
Using template $paramod$75d5c453cca75cc7a7ca320c4fb7be0932b6aaa7\$lut for cells of type $lut.
Using template $paramod$7b2d37dcbd4fe2396b33c37902941f4dedd8caa3\$lut for cells of type $lut.
Using template $paramod$faa5f5f53ce5ce860523993b8c1bddf301af2da0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut.
Using template $paramod$adce9c89515a4e83641fc3471eb3c01ec7b082ff\$lut for cells of type $lut.
Using template $paramod$c880d3684c59d81463073c16ca802a92aca5f773\$lut for cells of type $lut.
Using template $paramod$302ba22a83dfb50189674147c5c2626b9e9dab7e\$lut for cells of type $lut.
Using template $paramod$1f0c66e0f7ce7f846ca5a58367480fa489a7b432\$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
Using template $paramod$808477eb524646d08acb16560b86b4ca0a09b975\$lut for cells of type $lut.
Using template $paramod$0c8ca179830091c5e617fa87fec5eda52bbb802e\$lut for cells of type $lut.
Using template $paramod$9a8142107e16b1af3b331cc683a28cc45dcf8f24\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$48c19eb209dd8ad2c18334e4df384d3b3b74d5ec\$lut for cells of type $lut.
Using template $paramod$5e3164a14b8375764d1831e48df8bc11c8d249e0\$lut for cells of type $lut.
Using template $paramod$9a6965d4f53d69e345bd8d48283856520a30225e\$lut for cells of type $lut.
Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut.
Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut.
Using template $paramod$27d1fd562eca397af0bcf374fcecce96bb10480e\$lut for cells of type $lut.
Using template $paramod$e332cff882edd417f410bab5fe07a0f88572cce3\$lut for cells of type $lut.
Using template $paramod$d68c955eab3e0ff857c6b60afe14ca397531beeb\$lut for cells of type $lut.
Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b\$lut for cells of type $lut.
Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut.
Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut.
Using template $paramod$f314abdbef3663f31659cf7a4e5e574a874f0912\$lut for cells of type $lut.
Using template $paramod$8e55a9cca77fc533dfed315558bf3940f6a7ff6b\$lut for cells of type $lut.
Using template $paramod$3d1fa0d0482416cda5738079edd18db672aaa8c6\$lut for cells of type $lut.
Using template $paramod$18df3812bc12364e5ebcb6c3ed05c0294e4c26fc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut.
Using template $paramod$af15d200e3605f2c4c42beab3430842bc93f1158\$lut for cells of type $lut.
Using template $paramod$697a84631830e9b01bebb09367dab1e66781e8bf\$lut for cells of type $lut.
Using template $paramod$16afe9d5e9122b91959c071e8099523dfb9b6a27\$lut for cells of type $lut.
Using template $paramod$5502a85110dbca29ac631107f0b0635e7fade476\$lut for cells of type $lut.
Using template $paramod$a6b2d4693fada6bebbe4480262641915d709d280\$lut for cells of type $lut.
Using template $paramod$312c8bab003b975d614e2bfaf49ff0fa7926f2d1\$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod$849d013d096d73269ca4beb768f8e399745d37f2\$lut for cells of type $lut.
Using template $paramod$84c5cfa8d7481774250caab0fcdd6d249a376a31\$lut for cells of type $lut.
Using template $paramod$4b9b235bc4444ff899bef0c648e4109b26737f1a\$lut for cells of type $lut.
Using template $paramod$4385b611926e5c0509dba4de58311d325da0ff0d\$lut for cells of type $lut.
Using template $paramod$7a9b7d7d96d5349b2a3f800b325795fd17e50692\$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$0d4742cff20cb0e0e40b9af6c0257e3a276c0c2b\$lut for cells of type $lut.
Using template $paramod$b50e5f97c781a8ec6c48e135f101d305962383a3\$lut for cells of type $lut.
Using template $paramod$15ac410ea5b84c303864da98179081473b96983a\$lut for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut.
Using template $paramod$20ae971f03a8aabd14bc9c90601f9bed8100c9da\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$ca2167e97c50792f5ced35a59198c1ac5e93e2b7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$973394a6f8c13a435c2fa950b3fc699e041032a1\$lut for cells of type $lut.
Using template $paramod$d82743395a00cb844fb11eee66626018a89da412\$lut for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$4e7d68feade07e1e4cdedf8dbc6372862bb719ed\$lut for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2\$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod$1fd0b2bb53030dfa0316858facfc5ad38eccbe20\$lut for cells of type $lut.
Using template $paramod$6f8c8cdc4b3e951baba96b2acd13eabbb5e850fe\$lut for cells of type $lut.
Using template $paramod$821faed1475c638687052ec0c9f7ab37407237cb\$lut for cells of type $lut.
Using template $paramod$4eb848e991ac2a992be9b4be01f278b220c0efac\$lut for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
Using template $paramod$97bfd0f207e3cd11e81dc81c48f8e4fa7fc28966\$lut for cells of type $lut.
Using template $paramod$4981294a7caafabf6d7b76c8e6721c70638ee4c2\$lut for cells of type $lut.
Using template $paramod$093ee58b0520130b1d178e0c5806216acfab2d05\$lut for cells of type $lut.
Using template $paramod$bccf6f63f1f947f8d5a8817f13336731e7c3d1df\$lut for cells of type $lut.
Using template $paramod$60b758fd5679f6508bff32bea2afedb4f329e5f9\$lut for cells of type $lut.
Using template $paramod$ddd8aa9e998ab3e5bfa937360ff448a2c3226527\$lut for cells of type $lut.
Using template $paramod$81e300b0819553138d2ee25e9a978cf155f03dec\$lut for cells of type $lut.
Using template $paramod$193d365ba3260f56de4ca734b1cedcf9dc72302b\$lut for cells of type $lut.
Using template $paramod$858fd097437a174e69b6ff17eb7313563a7ac284\$lut for cells of type $lut.
Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514\$lut for cells of type $lut.
Using template $paramod$bcdeb2d0c1ce828b183bf04b8f063d4aebab16c2\$lut for cells of type $lut.
Using template $paramod$215f3c9a8e515a7c9e993b2d4eacc6383ba99c06\$lut for cells of type $lut.
Using template $paramod$8a4e44d9835596f192869c8fa5e0d6fa9c5d03b3\$lut for cells of type $lut.
Using template $paramod$8b156142bc74ae9e700b3ef741666f2561ac80b2\$lut for cells of type $lut.
Using template $paramod$53a9ea82e33652755519285ec82d27911f670b9d\$lut for cells of type $lut.
Using template $paramod$89fdd3c167b1eba1ecebef1ca0a72787b3585ddd\$lut for cells of type $lut.
Using template $paramod$c4fe0d52e4fa3d649d75cb9587992cb08e44f263\$lut for cells of type $lut.
Using template $paramod$de2b92d66e62d2468c774d4959d51c030800288f\$lut for cells of type $lut.
Using template $paramod$21ae97a4a7b4150f4d543da554e192df87272b1f\$lut for cells of type $lut.
Using template $paramod$4fd3428c4b8b1accf8f8fb4bb88555a2b5fa688d\$lut for cells of type $lut.
Using template $paramod$96739b921f7d333732b159587c49a8cc425ef777\$lut for cells of type $lut.
Using template $paramod$3b38fe715e7d131a66cdb012c358fbc239b20dc3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut.
Using template $paramod$0079324da11d2f78abfe97890ea41133196e94ad\$lut for cells of type $lut.
Using template $paramod$09303e6d63eb89c5ed7e5f925ae8fe56f04db2a9\$lut for cells of type $lut.
Using template $paramod$f67222c0e07416e9f6125e442bf0a4814d347d89\$lut for cells of type $lut.
Using template $paramod$9d77f97e9de18393e01564b5895540804898ac1c\$lut for cells of type $lut.
Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut.
Using template $paramod$c7eaad6a588218ef0ba5a17502d003bdff2bbd3e\$lut for cells of type $lut.
Using template $paramod$1d976bc954653b91c2dfa54d38dd9f92125922d7\$lut for cells of type $lut.
Using template $paramod$5002424fb13e71fe3d63c5ae16358968d083bd9b\$lut for cells of type $lut.
Using template $paramod$8384e66d408d22ab39dfb451efb7879731befeb8\$lut for cells of type $lut.
Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut.
Using template $paramod$1578333f1a5078051b84dbcbad362e8087bf5284\$lut for cells of type $lut.
Using template $paramod$73bfab9a6a26309994bf03e2e1e427f44b9a29b0\$lut for cells of type $lut.
Using template $paramod$fba4f983b189d4159f79bc1a1f57acdfd13d8fba\$lut for cells of type $lut.
Using template $paramod$714d58867eda82040510534210d467a2ffbc8472\$lut for cells of type $lut.
Using template $paramod$ce2b82f44649b2d40566fcf109bb314976e721d0\$lut for cells of type $lut.
Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d\$lut for cells of type $lut.
Using template $paramod$10c453dda41015fc8865ebe53ca9e0fe5dc92360\$lut for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$76e7646ea01c89fc86af9fd5d41d1ae3236f4205\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
Using template $paramod$d8119e7cf18bdd1d72e1822e569d9c40a2fc5848\$lut for cells of type $lut.
Using template $paramod$8e39d7ff27cce668605d270a834d952933c18e0c\$lut for cells of type $lut.
Using template $paramod$baaf57d168a90541fcefc9da2063f810b0910fb2\$lut for cells of type $lut.
Using template $paramod$d419573a12191c9e0f79eec244cdb5f8f86363cc\$lut for cells of type $lut.
Using template $paramod$2521fbdd58bac2d4ed7fbf0439b5fbace74c1b9c\$lut for cells of type $lut.
Using template $paramod$c362ad8dedc7d166ed978091aca319ab1e81a2d4\$lut for cells of type $lut.
Using template $paramod$d315acbf930db7c20b3f4ac2dad3b7982b1f437c\$lut for cells of type $lut.
Using template $paramod$f1abc293f2e4aa48fcd9262ba190ff886479340e\$lut for cells of type $lut.
Using template $paramod$824ebdbfd4c90cb6f5290fb3b0198a4ac3354581\$lut for cells of type $lut.
Using template $paramod$c1a909080ec76944fa258a19c3ca35c98563249f\$lut for cells of type $lut.
Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut.
Using template $paramod$993a2044bae9e2f987bba692162e23bf80e406a7\$lut for cells of type $lut.
Using template $paramod$ac9c45fe379e76b7cc43d4826318b311b78fba58\$lut for cells of type $lut.
Using template $paramod$9cf976b4f3a576aa2cd6b51304cf5de7fc836fbd\$lut for cells of type $lut.
Using template $paramod$a91489f65ae3b4299f68fd72eb152638fdf6e03d\$lut for cells of type $lut.
Using template $paramod$de5d1812e8087669c4e10a59313e0bc878b774db\$lut for cells of type $lut.
Using template $paramod$1dbc005c3ca46176ed5f71d3318762a2498d170f\$lut for cells of type $lut.
Using template $paramod$7860a5985ef4c0c6d2245b486edd100073006d99\$lut for cells of type $lut.
Using template $paramod$643625f6f8b1d178181399ddc7e2ea926b651682\$lut for cells of type $lut.
Using template $paramod$2136fe914e3a1b381f420e8c69ca986e13870eaf\$lut for cells of type $lut.
Using template $paramod$142aa2d6e7bf19c7af854830ac7e5a07ffd992ab\$lut for cells of type $lut.
Using template $paramod$71715b752f6c6222735147a74a785ff930effad3\$lut for cells of type $lut.
Using template $paramod$7ffba39d59d0bf4bfd5964c51dd175c63cbc16c9\$lut for cells of type $lut.
Using template $paramod$8b433b6d0c67485e67cdd596bea43371aaf8099f\$lut for cells of type $lut.
Using template $paramod$3a2d5a98ab1592b96e36a874f2893a88b535b517\$lut for cells of type $lut.
Using template $paramod$dcf80d2c2ec10d6ba1e23d820880a8149a8ee2d7\$lut for cells of type $lut.
Using template $paramod$c9f18324b2c51d8938d61165353bfe926ae52628\$lut for cells of type $lut.
Using template $paramod$b3c64ca762d6c10a14cacd4fbc7bdd573adccf55\$lut for cells of type $lut.
Using template $paramod$a166001d0e359e7a09aae0628253b880bfd9fa21\$lut for cells of type $lut.
Using template $paramod$0f6a5b2d703b48519c07dd3bf95386222f32fadd\$lut for cells of type $lut.
Using template $paramod$2ec6422db00d358fc7469efce6208bffbc8521cd\$lut for cells of type $lut.
Using template $paramod$22ab56550807ac1ca0030e7dda21f0acdae3746b\$lut for cells of type $lut.
Using template $paramod$62e962fc19a04a2b4e4e7ccfa8219434c241cbdd\$lut for cells of type $lut.
Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut.
Using template $paramod$3170cf03349b88b5635e6c1c2df644e450ae489d\$lut for cells of type $lut.
Using template $paramod$2a3aee6f1b16b87fae5ad552f211bb1ef99dfafe\$lut for cells of type $lut.
Using template $paramod$ca148d02063486bb828be736c14b6d6ea10e1e2c\$lut for cells of type $lut.
Using template $paramod$e66ddd071de3be1d112de63078d882cb12c0fbe3\$lut for cells of type $lut.
Using template $paramod$70a6f8b5e7c26d543ee5df54b2e21d28a007a4bc\$lut for cells of type $lut.
Using template $paramod$2b0f161f27527f3c655ff8e9bb2bc8e3b0a61b9a\$lut for cells of type $lut.
Using template $paramod$6c325b1fe14ac6f3049a2e363bfa73d747c7127d\$lut for cells of type $lut.
Using template $paramod$7a815dc767089d4b9343c72ee0d0e2dfc028c784\$lut for cells of type $lut.
Using template $paramod$9becc6376cac3c55b34ebe436ca01b702d34d09e\$lut for cells of type $lut.
Using template $paramod$525091013e43abd6467037fb35116e65a26a5b11\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$e8b1383c6901b56df73ac402d78a5e0a42461be0\$lut for cells of type $lut.
Using template $paramod$c70b865141b31e676f7fbd7ee63b880eef8cb064\$lut for cells of type $lut.
Using template $paramod$1a570f7c4fa84211cd76bb231e4a70d524ba2b35\$lut for cells of type $lut.
Using template $paramod$edf930f53e90cacdbbfbc8ced817dd6ff9482247\$lut for cells of type $lut.
Using template $paramod$9a92da23c4e9c4048c7590dc07955b118f9b4d07\$lut for cells of type $lut.
Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut.
Using template $paramod$bb4dd11adcf72630fb0df3c35d1656661f4c36ad\$lut for cells of type $lut.
Using template $paramod$389e43ee14507e9d1ff41667d687299eeebb4e34\$lut for cells of type $lut.
Using template $paramod$bdc65f11200e9eefee8fbb35b2c23d18ffdf014a\$lut for cells of type $lut.
Using template $paramod$3548f6e93628807ae6cc989ec88fe8ae640cb47a\$lut for cells of type $lut.
Using template $paramod$b68f9800cc1bf69afcfbc0567a25e43ebb01456c\$lut for cells of type $lut.
Using template $paramod$8cac5452d526045503c5864c3a1dac0121c7053e\$lut for cells of type $lut.
Using template $paramod$9a0f106f21ca373340f504f33a8aa2f4540f751e\$lut for cells of type $lut.
Using template $paramod$a977fb3a4e30b200887394f8ff6c3df1befab9e3\$lut for cells of type $lut.
Using template $paramod$1408b386368bf5572c9daf8417b03ff048fc4a59\$lut for cells of type $lut.
Using template $paramod$769bdbbde83614df0f4ab5f54e777ded51bb10ce\$lut for cells of type $lut.
Using template $paramod$146d1e96dc4c9681b0c5558dc2dbbbbe4050c7ac\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
Using template $paramod$f0169807cabb208126f94e3f71552cc012e8013f\$lut for cells of type $lut.
Using template $paramod$51307cdec77060d17363ea3d60427c9afef1ddc2\$lut for cells of type $lut.
Using template $paramod$e3232e0a90c8340ac10328f8e4e3ccd56fa7779b\$lut for cells of type $lut.
Using template $paramod$6a2f8f32cd4db09920ea757d1b22604453df1e89\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$e906e72cbd10abfe84b88bb112d24de91dc6cf81\$lut for cells of type $lut.
Using template $paramod$243cc2cb1c2719c01ea62c217920ae3156ba74dc\$lut for cells of type $lut.
Using template $paramod$31ae08c40137bfb4d3c0a9dade880bc81658ad8f\$lut for cells of type $lut.
Using template $paramod$fc92c2d3f2dfb664cde88655ba8321787f976456\$lut for cells of type $lut.
Using template $paramod$73311b45afe783964b8a99b303013155bf535006\$lut for cells of type $lut.
Using template $paramod$223a1a0bfc3038108c8c5d096bc8fdc50fd540b0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$18e50808df562b188523e13714b96fedec6427c1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101110 for cells of type $lut.
Using template $paramod$651e836885d95717c36e69441422c3fe04ee5f4d\$lut for cells of type $lut.
Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26\$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$0328e568d609989242dcb98a1c5328d4372a6e9c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut.
Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a\$lut for cells of type $lut.
Using template $paramod$23c406d3302544ed79a645df17e697e360ff2a8d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut.
Using template $paramod$0ef0d5727b0805ddc8d3c9353111fc414a43a1ba\$lut for cells of type $lut.
Using template $paramod$833582361e14b3ee2e66ad676022ab35d7aa7e28\$lut for cells of type $lut.
Using template $paramod$2926b16e717affb5d0a151eb884ab0739856a29e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$0f19b1c588a47c675d00132b243b5e3308ffab5d\$lut for cells of type $lut.
Using template $paramod$b419810ab1d51da1962917a1949cecc5f27935eb\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~8878 debug messages>

21.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$9362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$9362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$9343.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$9228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9213.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$9188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$9133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$9133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$9093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96125.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$9056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$9036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9016.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8995.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8991.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8847.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8743.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8724.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8674.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8391.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8083.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7977.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7906.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$18314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$17678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17672.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17639.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16772.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$16706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$16212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$16010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15977.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15635.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$9238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$9238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$9238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7656.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7503.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7503.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7503.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7503.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7503.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96315.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96315.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96315.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7407.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7402.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7402.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7402.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7402.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7121.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7121.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7121.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96333.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96309.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$6754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96307.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$6731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$6712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$6635.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6598.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$6591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$6564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$6521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$6480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$6389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$6353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6250.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$6677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$6799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$6273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10457.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10508.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$10590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10684.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10712.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10752.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10907.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10923.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10955.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$10983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11189.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11335.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11543.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11654.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11665.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11867.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$11942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12543.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12753.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$12999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13089.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13179.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13245.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13401.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13469.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13485.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13633.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13701.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$13993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14204.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$14316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14449.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14756.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$14956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15015.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15349.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15439.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$15477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15543.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$15612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$15639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$15661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$15934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$15981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$16000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$16200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$16222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16245.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$16305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16439.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16488.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16495.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16509.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16541.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$16581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$16688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$16706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$16713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16739.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$16988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$17058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17081.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$17158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$17209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$17283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17412.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$17613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$17662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17691.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17752.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$17774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17851.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$17920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$17936.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18035.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$18131.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$18179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18251.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$18302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$18324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18347.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$18442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$18449.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$5878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$5893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$5909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6108.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$10568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6278.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$6365.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6404.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6419.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6511.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6645.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$6507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6705.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6677.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6664.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6705.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6731.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$6823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6903.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6931.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7085.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7121.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7169.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7277.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7462.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7503.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7711.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7753.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$7996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8013.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8340.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$8521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8535.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8579.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8637.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8644.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8661.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8750.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$8773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8910.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$7962.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$8972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$8979.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9024.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$9031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$9056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9061.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9085.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$9174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9193.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9221.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$9259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$9281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$9290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9305.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9351.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$9366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$9668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$9903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$auto$opt_dff.cc:219:make_patterns_logic$2546.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96131.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96151.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96160.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96171.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96195.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96251.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$96111$lut$aiger96110$6823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$6754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$96111$lut$aiger96110$7503.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96321.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$96111$lut$aiger96110$6526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$96111$lut$aiger96110$7018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$96333.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Removed 0 unused cells and 11034 unused wires.

21.45. Executing AUTONAME pass.
Renamed 341143 objects in module top (264 iterations).
<suppressed ~14759 debug messages>

21.46. Executing HIERARCHY pass (managing design hierarchy).

21.46.1. Analyzing design hierarchy..
Top module:  \top

21.46.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

21.47. Printing statistics.

=== top ===

   Number of wires:               6212
   Number of wire bits:          16625
   Number of public wires:        6212
   Number of public wire bits:   16625
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               9250
     $_TBUF_                         5
     CCU2C                         148
     L6MUX21                       501
     LUT4                         5562
     PFUMX                        1221
     TRELLIS_DPR16X4               512
     TRELLIS_FF                   1301

21.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

21.49. Executing JSON backend.

Warnings: 259 unique messages, 260 total
End of script. Logfile hash: b9e6dadfc9, CPU: user 8.55s system 0.13s, MEM: 241.04 MB peak
Yosys 0.36+8 (git sha1 fb4cbfa73, clang 10.0.0-4ubuntu1 -fPIC -Os)
Time spent: 36% 1x abc9_exe (4 sec), 13% 11x techmap (1 sec), ...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (NextPNR)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz
Warning: IO 'gpios[4]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[3]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[2]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[1]' is unconstrained in LPF and will be automatically placed
Warning: IO 'gpios[0]' is unconstrained in LPF and will be automatically placed

Info: Logic utilisation before packing:
Info:     Total LUT4s:      8930/43848    20%
Info:         logic LUTs:   5562/43848    12%
Info:         carry LUTs:    296/43848     0%
Info:           RAM LUTs:   2048/ 5481    37%
Info:          RAMW LUTs:   1024/10962     9%

Info:      Total DFFs:      1301/43848     2%

Info: Packing IOs..
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y.Y
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     276 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk_o to global network
Info:     promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x3ea99aae

Info: Device utilisation:
Info: 	          TRELLIS_IO:    17/  245     6%
Info: 	                DCCA:     2/   56     3%
Info: 	              DP16KD:     0/  108     0%
Info: 	          MULT18X18D:     0/   72     0%
Info: 	              ALU54B:     0/   36     0%
Info: 	             EHXPLLL:     0/    4     0%
Info: 	             EXTREFB:     0/    2     0%
Info: 	                DCUA:     0/    2     0%
Info: 	           PCSCLKDIV:     0/    2     0%
Info: 	             IOLOGIC:     0/  160     0%
Info: 	            SIOLOGIC:     0/   85     0%
Info: 	                 GSR:     0/    1     0%
Info: 	               JTAGG:     0/    1     0%
Info: 	                OSCG:     0/    1     0%
Info: 	               SEDGA:     0/    1     0%
Info: 	                 DTR:     0/    1     0%
Info: 	             USRMCLK:     0/    1     0%
Info: 	             CLKDIVF:     0/    4     0%
Info: 	           ECLKSYNCB:     0/   10     0%
Info: 	             DLLDELD:     0/    8     0%
Info: 	              DDRDLL:     0/    4     0%
Info: 	             DQSBUFM:     0/   10     0%
Info: 	     TRELLIS_ECLKBUF:     0/    8     0%
Info: 	        ECLKBRIDGECS:     0/    2     0%
Info: 	                DCSC:     0/    2     0%
Info: 	          TRELLIS_FF:  1301/43848     2%
Info: 	        TRELLIS_COMB:  8989/43848    20%
Info: 	        TRELLIS_RAMW:   512/ 5481     9%

Info: Placed 12 cells based on constraints.
Info: Creating initial analytic placement for 5397 cells, random placement wirelen = 456859.
Info:     at initial placer iter 0, wirelen = 2210
Info:     at initial placer iter 1, wirelen = 2219
Info:     at initial placer iter 2, wirelen = 2000
Info:     at initial placer iter 3, wirelen = 1920
Info: Running main analytical placer, max placement attempts per cell = 14636755.
Info:     at iteration #1, type ALL: wirelen solved = 1907, spread = 64977, legal = 65872; time = 0.27s
Info:     at iteration #2, type ALL: wirelen solved = 6941, spread = 46134, legal = 47227; time = 0.27s
Info:     at iteration #3, type ALL: wirelen solved = 13303, spread = 43687, legal = 44857; time = 0.26s
Info:     at iteration #4, type ALL: wirelen solved = 15340, spread = 44718, legal = 45448; time = 0.26s
Info:     at iteration #5, type ALL: wirelen solved = 16947, spread = 42044, legal = 42961; time = 0.26s
Info:     at iteration #6, type ALL: wirelen solved = 18202, spread = 39703, legal = 41014; time = 0.25s
Info:     at iteration #7, type ALL: wirelen solved = 18225, spread = 38270, legal = 39449; time = 0.25s
Info:     at iteration #8, type ALL: wirelen solved = 19188, spread = 39043, legal = 40011; time = 0.25s
Info:     at iteration #9, type ALL: wirelen solved = 20411, spread = 41888, legal = 42503; time = 0.25s
Info:     at iteration #10, type ALL: wirelen solved = 23068, spread = 40157, legal = 41081; time = 0.24s
Info:     at iteration #11, type ALL: wirelen solved = 22444, spread = 40902, legal = 41396; time = 0.24s
Info:     at iteration #12, type ALL: wirelen solved = 23390, spread = 39643, legal = 40444; time = 0.24s
Info: HeAP Placer Time: 5.12s
Info:   of which solving equations: 3.20s
Info:   of which spreading cells: 0.39s
Info:   of which strict legalisation: 0.12s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 16804, wirelen = 39449
Info:   at iteration #5: temp = 0.000000, timing cost = 9903, wirelen = 32365
Info:   at iteration #10: temp = 0.000000, timing cost = 12787, wirelen = 30612
Info:   at iteration #15: temp = 0.000000, timing cost = 14452, wirelen = 29790
Info:   at iteration #20: temp = 0.000000, timing cost = 13972, wirelen = 29038
Info:   at iteration #25: temp = 0.000000, timing cost = 13786, wirelen = 28787
Info:   at iteration #30: temp = 0.000000, timing cost = 13664, wirelen = 28663
Info:   at iteration #35: temp = 0.000000, timing cost = 13554, wirelen = 28626
Info:   at iteration #40: temp = 0.000000, timing cost = 13566, wirelen = 28598
Info:   at iteration #41: temp = 0.000000, timing cost = 13562, wirelen = 28594 
Info: SA placement time 39.36s

Info: Max frequency for clock             '$glbnet$clk_o': 29.17 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 142.80 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.82 ns
Info: Max delay <async>                           -> posedge $glbnet$clk_o            : 10.84 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 13.96 ns
Info: Max delay posedge $glbnet$clk_o             -> <async>                          : 12.52 ns

Info: Slack histogram:
Info:  legend: * represents 98 endpoint(s)
Info:          + represents [1,98) endpoint(s)
Info: [ 32997,  35476) |+
Info: [ 35476,  37955) |+
Info: [ 37955,  40434) |+
Info: [ 40434,  42913) | 
Info: [ 42913,  45392) | 
Info: [ 45392,  47871) | 
Info: [ 47871,  50350) |+
Info: [ 50350,  52829) |+
Info: [ 52829,  55308) |+
Info: [ 55308,  57787) |****+
Info: [ 57787,  60266) |***************+
Info: [ 60266,  62745) |***********************************************+
Info: [ 62745,  65224) |************************************************************ 
Info: [ 65224,  67703) |******+
Info: [ 67703,  70182) |*+
Info: [ 70182,  72661) |+
Info: [ 72661,  75140) |****+
Info: [ 75140,  77619) |******+
Info: [ 77619,  80098) |**+
Info: [ 80098,  82577) |+
Info: Checksum: 0xf3f19479
Info: Routing globals...
Info:     routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info:     routing clock net $glbnet$clk_o using global 1

Info: Routing..
Info: Setting up routing queue.
Info: Routing 43150 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |      122        877 |  122   877 |     42885|       0.62       0.62|
Info:       2000 |      337       1662 |  215   785 |     42456|       0.15       0.77|
Info:       3000 |      551       2448 |  214   786 |     41986|       0.17       0.94|
Info:       4000 |      654       3345 |  103   897 |     42090|       0.13       1.07|
Info:       5000 |      734       4265 |   80   920 |     41829|       0.13       1.20|
Info:       6000 |      915       5084 |  181   819 |     41615|       0.19       1.38|
Info:       7000 |     1155       5844 |  240   760 |     41197|       0.17       1.55|
Info:       8000 |     1325       6674 |  170   830 |     40828|       0.16       1.71|
Info:       9000 |     1572       7427 |  247   753 |     40422|       0.17       1.88|
Info:      10000 |     1785       8214 |  213   787 |     39925|       0.17       2.05|
Info:      11000 |     1919       9080 |  134   866 |     39737|       0.16       2.21|
Info:      12000 |     2112       9887 |  193   807 |     39373|       0.16       2.37|
Info:      13000 |     2354      10645 |  242   758 |     39051|       0.18       2.55|
Info:      14000 |     2446      11553 |   92   908 |     38579|       0.16       2.72|
Info:      15000 |     2632      12367 |  186   814 |     38177|       0.18       2.89|
Info:      16000 |     2841      13158 |  209   791 |     37730|       0.18       3.07|
Info:      17000 |     3040      13959 |  199   801 |     37421|       0.18       3.25|
Info:      18000 |     3263      14736 |  223   777 |     37660|       0.18       3.43|
Info:      19000 |     3279      15720 |   16   984 |     37541|       0.14       3.56|
Info:      20000 |     3296      16703 |   17   983 |     37301|       0.13       3.69|
Info:      21000 |     3356      17643 |   60   940 |     37087|       0.14       3.83|
Info:      22000 |     3547      18452 |  191   809 |     37346|       0.18       4.02|
Info:      23000 |     3686      19313 |  139   861 |     36883|       0.15       4.17|
Info:      24000 |     3911      20088 |  225   775 |     36567|       0.18       4.34|
Info:      25000 |     4074      20925 |  163   837 |     36320|       0.17       4.52|
Info:      26000 |     4247      21752 |  173   827 |     36064|       0.18       4.70|
Info:      27000 |     4380      22619 |  133   867 |     35766|       0.15       4.85|
Info:      28000 |     4565      23434 |  185   815 |     35395|       0.19       5.04|
Info:      29000 |     4819      24180 |  254   746 |     37085|       0.18       5.22|
Info:      30000 |     4873      25126 |   54   946 |     36311|       0.14       5.36|
Info:      31000 |     4903      26096 |   30   970 |     35358|       0.15       5.51|
Info:      32000 |     5042      26957 |  139   861 |     37174|       0.18       5.69|
Info:      33000 |     5198      27801 |  156   844 |     36619|       0.17       5.87|
Info:      34000 |     5287      28712 |   89   911 |     35945|       0.19       6.06|
Info:      35000 |     5384      29615 |   97   903 |     35266|       0.18       6.24|
Info:      36000 |     5521      30478 |  137   863 |     35320|       0.19       6.43|
Info:      37000 |     5797      31202 |  276   724 |     34987|       0.19       6.62|
Info:      38000 |     6023      31976 |  226   774 |     34652|       0.19       6.81|
Info:      39000 |     6205      32794 |  182   818 |     34205|       0.18       6.98|
Info:      40000 |     6440      33559 |  235   765 |     33640|       0.19       7.17|
Info:      41000 |     6710      34289 |  270   730 |     33480|       0.20       7.38|
Info:      42000 |     6963      35036 |  253   747 |     33110|       0.20       7.58|
Info:      43000 |     7240      35759 |  277   723 |     32654|       0.21       7.78|
Info:      44000 |     7471      36528 |  231   769 |     32067|       0.20       7.98|
Info:      45000 |     7749      37250 |  278   722 |     31638|       0.20       8.19|
Info:      46000 |     7996      38003 |  247   753 |     31197|       0.20       8.39|
Info:      47000 |     8281      38718 |  285   715 |     30856|       0.21       8.60|
Info:      48000 |     8580      39419 |  299   701 |     30542|       0.21       8.81|
Info:      49000 |     8861      40138 |  281   719 |     30085|       0.21       9.02|
Info:      50000 |     9158      40841 |  297   703 |     29594|       0.22       9.24|
Info:      51000 |     9386      41613 |  228   772 |     29276|       0.21       9.44|
Info:      52000 |     9699      42300 |  313   687 |     28887|       0.21       9.65|
Info:      53000 |     9945      43054 |  246   754 |     28365|       0.20       9.86|
Info:      54000 |    10260      43739 |  315   685 |     28231|       0.22      10.08|
Info:      55000 |    10483      44516 |  223   777 |     27940|       0.21      10.28|
Info:      56000 |    10738      45261 |  255   745 |     27523|       0.22      10.50|
Info:      57000 |    11036      45963 |  298   702 |     27112|       0.25      10.75|
Info:      58000 |    11341      46658 |  305   695 |     26660|       0.23      10.98|
Info:      59000 |    11624      47375 |  283   717 |     26358|       0.21      11.18|
Info:      60000 |    11924      48075 |  300   700 |     26026|       0.23      11.42|
Info:      61000 |    12279      48720 |  355   645 |     25627|       0.22      11.64|
Info:      62000 |    12553      49446 |  274   726 |     25313|       0.23      11.86|
Info:      63000 |    12849      50150 |  296   704 |     25140|       0.25      12.11|
Info:      64000 |    13125      50874 |  276   724 |     24872|       0.24      12.35|
Info:      65000 |    13396      51603 |  271   729 |     24586|       0.22      12.57|
Info:      66000 |    13758      52241 |  362   638 |     24253|       0.24      12.81|
Info:      67000 |    14104      52895 |  346   654 |     23820|       0.23      13.04|
Info:      68000 |    14423      53576 |  319   681 |     23531|       0.24      13.29|
Info:      69000 |    14784      54215 |  361   639 |     23220|       0.23      13.52|
Info:      70000 |    15118      54881 |  334   666 |     22933|       0.24      13.76|
Info:      71000 |    15354      55645 |  236   764 |     23200|       0.22      13.98|
Info:      72000 |    15512      56487 |  158   842 |     22697|       0.23      14.21|
Info:      73000 |    15901      57098 |  389   611 |     22436|       0.24      14.46|
Info:      74000 |    16259      57740 |  358   642 |     22149|       0.25      14.71|
Info:      75000 |    16660      58339 |  401   599 |     21868|       0.25      14.96|
Info:      76000 |    16963      59036 |  303   697 |     21659|       0.24      15.20|
Info:      77000 |    17281      59718 |  318   682 |     21526|       0.26      15.45|
Info:      78000 |    17684      60315 |  403   597 |     21548|       0.24      15.70|
Info:      79000 |    17961      61038 |  277   723 |     21308|       0.24      15.94|
Info:      80000 |    18329      61670 |  368   632 |     20926|       0.24      16.18|
Info:      81000 |    18753      62246 |  424   576 |     20611|       0.24      16.42|
Info:      82000 |    19193      62806 |  440   560 |     20352|       0.25      16.67|
Info:      83000 |    19674      63325 |  481   519 |     20077|       0.26      16.93|
Info:      84000 |    20107      63892 |  433   567 |     19981|       0.26      17.19|
Info:      85000 |    20517      64482 |  410   590 |     19657|       0.26      17.45|
Info:      86000 |    21002      64997 |  485   515 |     19521|       0.26      17.72|
Info:      87000 |    21451      65548 |  449   551 |     19395|       0.24      17.96|
Info:      88000 |    21808      66191 |  357   643 |     19296|       0.23      18.19|
Info:      89000 |    22194      66805 |  386   614 |     19033|       0.26      18.45|
Info:      90000 |    22621      67378 |  427   573 |     18858|       0.27      18.72|
Info:      91000 |    23072      67927 |  451   549 |     18616|       0.25      18.96|
Info:      92000 |    23557      68442 |  485   515 |     18356|       0.26      19.23|
Info:      93000 |    23866      69133 |  309   691 |     19706|       0.24      19.47|
Info:      94000 |    24078      69921 |  212   788 |     19329|       0.26      19.73|
Info:      95000 |    24307      70692 |  229   771 |     18764|       0.26      19.99|
Info:      96000 |    24561      71438 |  254   746 |     18811|       0.26      20.25|
Info:      97000 |    24801      72198 |  240   760 |     18644|       0.25      20.51|
Info:      98000 |    25160      72839 |  359   641 |     18661|       0.25      20.76|
Info:      99000 |    25249      73750 |   89   911 |     19097|       0.22      20.98|
Info:     100000 |    25312      74687 |   63   937 |     18769|       0.23      21.21|
Info:     101000 |    25611      75388 |  299   701 |     18376|       0.26      21.47|
Info:     102000 |    26055      75944 |  444   556 |     18540|       0.27      21.74|
Info:     103000 |    26311      76688 |  256   744 |     18120|       0.23      21.97|
Info:     104000 |    26912      77087 |  601   399 |     17970|       0.26      22.23|
Info:     105000 |    27482      77517 |  570   430 |     17787|       0.27      22.50|
Info:     106000 |    28055      77944 |  573   427 |     17572|       0.24      22.74|
Info:     107000 |    28562      78437 |  507   493 |     17443|       0.25      23.00|
Info:     108000 |    29119      78880 |  557   443 |     17174|       0.26      23.25|
Info:     109000 |    29666      79333 |  547   453 |     16984|       0.26      23.51|
Info:     110000 |    30213      79786 |  547   453 |     16735|       0.24      23.75|
Info:     111000 |    30735      80264 |  522   478 |     16560|       0.26      24.01|
Info:     112000 |    31291      80708 |  556   444 |     16317|       0.25      24.26|
Info:     113000 |    31691      81308 |  400   600 |     16211|       0.25      24.51|
Info:     114000 |    32172      81827 |  481   519 |     15951|       0.24      24.76|
Info:     115000 |    32687      82312 |  515   485 |     15716|       0.26      25.02|
Info:     116000 |    33201      82775 |  514   463 |     15496|       0.28      25.30|
Info:     117000 |    33656      83252 |  455   477 |     15185|       0.24      25.53|
Info:     118000 |    34253      83601 |  597   349 |     14891|       0.24      25.77|
Info:     119000 |    34771      84030 |  518   429 |     14653|       0.25      26.03|
Info:     120000 |    35289      84454 |  518   424 |     14525|       0.25      26.28|
Info:     121000 |    35748      84946 |  459   492 |     14254|       0.26      26.54|
Info:     122000 |    36290      85377 |  542   431 |     14070|       0.25      26.79|
Info:     123000 |    36722      85886 |  432   509 |     13849|       0.24      27.03|
Info:     124000 |    37235      86326 |  513   440 |     13549|       0.24      27.27|
Info:     125000 |    37732      86794 |  497   468 |     13335|       0.26      27.53|
Info:     126000 |    38248      87248 |  516   454 |     13193|       0.26      27.79|
Info:     127000 |    38765      87677 |  517   429 |     12917|       0.25      28.04|
Info:     128000 |    39331      88045 |  566   368 |     12597|       0.29      28.33|
Info:     129000 |    39849      88490 |  518   445 |     12414|       0.27      28.60|
Info:     130000 |    40303      89018 |  454   528 |     12269|       0.28      28.88|
Info:     131000 |    40815      89464 |  512   446 |     11951|       0.25      29.13|
Info:     132000 |    41146      90037 |  331   573 |     11599|       0.25      29.39|
Info:     133000 |    41410      90721 |  264   684 |     10934|       0.22      29.60|
Info:     134000 |    41510      91608 |  100   887 |     10056|       0.13      29.73|
Info:     135000 |    41566      92551 |   56   943 |      9129|       0.10      29.83|
Info:     136000 |    41605      93511 |   39   960 |      8171|       0.09      29.92|
Info:     137000 |    41639      94473 |   34   962 |      7208|       0.09      30.01|
Info:     138000 |    41683      95426 |   44   953 |      6262|       0.10      30.12|
Info:     139000 |    41787      96317 |  104   891 |      5426|       0.14      30.26|
Info:     140000 |    41921      97175 |  134   858 |      4575|       0.14      30.40|
Info:     141000 |    42271      97821 |  350   646 |      4079|       0.24      30.64|
Info:     142000 |    42669      98418 |  398   597 |      3612|       0.28      30.92|
Info:     143000 |    43062      99008 |  393   590 |      3146|       0.27      31.20|
Info:     144000 |    43527      99533 |  465   525 |      2772|       0.33      31.52|
Info:     145000 |    43996     100055 |  469   522 |      2378|       0.30      31.82|
Info:     146000 |    44420     100608 |  424   553 |      1993|       0.29      32.11|
Info:     147000 |    44834     101188 |  414   580 |      1564|       0.31      32.42|
Info:     148000 |    45327     101693 |  493   505 |      1211|       0.32      32.74|
Info:     149000 |    45858     102162 |  531   469 |       919|       0.33      33.08|
Info:     150000 |    46389     102622 |  531   460 |       802|       0.35      33.43|
Info:     151000 |    46676     103062 |  287   440 |       191|       0.34      33.77|
Info:     151244 |    46712     103137 |   36    75 |         0|       0.11      33.88|
Info: Routing complete.
Info: Router1 time 33.88s
Info: Checksum: 0x1a82f7e6

Info: Critical path report for clock '$glbnet$clk_o' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_2.Q
Info:  0.8  1.4    Net SOC.Core.Control_Unit.state[0] (46,29) -> (46,29)
Info:                Sink SOC.Bus.slave_1_write_LUT4_Z_B_PFUMX_Z_C0_LUT4_Z_1.D
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/core/core.v:97.14-113.2
Info:                  Risco-5/src/core/control_unit.v:25.11-25.16
Info:                  Risco-5/src/peripheral/soc.v:28.3-36.2
Info:  0.2  1.6  Source SOC.Bus.slave_1_write_LUT4_Z_B_PFUMX_Z_C0_LUT4_Z_1.F
Info:  1.0  2.6    Net SOC.Bus.slave_1_write_LUT4_Z_B_PFUMX_Z_C0[4] (46,29) -> (47,23)
Info:                Sink SOC.Bus.slave_1_write_LUT4_Z_B_PFUMX_Z_C0_LUT4_C.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  2.9  Source SOC.Bus.slave_1_write_LUT4_Z_B_PFUMX_Z_C0_LUT4_C.F
Info:  1.9  4.8    Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D[1] (47,23) -> (43,12)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  5.0  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_LUT4_Z.F
Info:  1.5  6.5    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0 (43,12) -> (42,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.B
Info:  0.4  7.0  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  7.0    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (42,16) -> (42,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  7.0  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  7.0    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (42,16) -> (42,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.0  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  7.0    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (42,16) -> (42,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  7.0  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  7.0    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (42,16) -> (42,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.1  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  7.1    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (42,16) -> (42,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  7.1  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  7.1    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (42,16) -> (43,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.2  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  7.2    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (43,16) -> (43,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  7.2  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  7.2    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (43,16) -> (43,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.2  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  7.2    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (43,16) -> (43,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  7.2  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  7.2    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (43,16) -> (43,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.3  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  7.3    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (43,16) -> (43,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  7.3  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  7.3    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (43,16) -> (43,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.4  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  7.4    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (43,16) -> (43,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  7.4  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  7.4    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (43,16) -> (44,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.5  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  7.5    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (44,16) -> (44,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  7.5  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  7.5    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (44,16) -> (44,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.5  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  7.5    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (44,16) -> (44,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  7.5  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  7.5    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (44,16) -> (44,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  Risco-5/src/peripheral/soc.v:51.5-81.2
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.6  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  7.6    Net SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (44,16) -> (44,16)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  7.6  Source SOC.GPIOS.write_data_LUT4_Z_B_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  7.6    Net $nextpnr_CCU2C_15$CIN (44,16) -> (44,16)
Info:                Sink $nextpnr_CCU2C_15$CCU2_COMB0.FCI
Info:  0.4  8.0  Source $nextpnr_CCU2C_15$CCU2_COMB0.F
Info:  1.8  9.9    Net SOC.Bus.slave_1_write_LUT4_Z_B[1] (44,16) -> (25,17)
Info:                Sink SOC.Memory.address_LUT4_Z_2.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 10.1  Source SOC.Memory.address_LUT4_Z_2.F
Info:  2.0 12.1    Net SOC.slave_address[3] (25,17) -> (15,16)
Info:                Sink SOC.Memory.memory.0.174$DPRAM_COMB1.B
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/soc.v:21.5-21.18
Info:  0.2 12.3  Source SOC.Memory.memory.0.174$DPRAM_COMB1.F
Info:  0.9 13.2    Net SOC.Memory.memory.0.158_DO[2] (15,16) -> (14,16)
Info:                Sink SOC.Memory.memory.0.150_DO_2_LUT4_Z.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 13.4  Source SOC.Memory.memory.0.150_DO_2_LUT4_Z.F
Info:  0.7 14.2    Net SOC.Memory.memory.0.150_DO_2[4] (14,16) -> (14,15)
Info:                Sink SOC.Memory.memory.0.190_DO_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 14.4  Source SOC.Memory.memory.0.190_DO_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.6 15.0    Net SOC.Memory.memory.0.190_DO[3] (14,15) -> (13,15)
Info:                Sink SOC.Memory.memory.0.134_DO_2_LUT4_Z_1.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 15.3  Source SOC.Memory.memory.0.134_DO_2_LUT4_Z_1.F
Info:  0.5 15.7    Net SOC.Memory.memory.0.134_DO_2[3] (13,15) -> (13,14)
Info:                Sink SOC.Memory.memory.0.134_DO_2_LUT4_B.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 16.0  Source SOC.Memory.memory.0.134_DO_2_LUT4_B.F
Info:  1.1 17.0    Net SOC.Memory.memory.0.126_DO_LUT4_B_Z[4] (13,14) -> (17,13)
Info:                Sink SOC.Core.read_data_LUT4_Z_16_D_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 17.3  Source SOC.Core.read_data_LUT4_Z_16_D_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.0 17.3    Net SOC.Core.read_data_LUT4_Z_16_D_L6MUX21_Z_SD_L6MUX21_Z_D1 (17,13) -> (17,13)
Info:                Sink SOC.Core.read_data_LUT4_Z_16_D_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info:  0.2 17.5  Source SOC.Core.read_data_LUT4_Z_16_D_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  1.5 19.0    Net SOC.Core.read_data_LUT4_Z_16_D_L6MUX21_Z_SD[5] (17,13) -> (21,17)
Info:                Sink SOC.Core.read_data_LUT4_Z_16_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 19.3  Source SOC.Core.read_data_LUT4_Z_16_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  2.1 21.4    Net SOC.Core.read_data_LUT4_Z_16_D[2] (21,17) -> (42,21)
Info:                Sink SOC.Core.read_data_LUT4_Z_16.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 21.7  Source SOC.Core.read_data_LUT4_Z_16.F
Info:  1.3 22.9    Net SOC.read_data[25] (42,21) -> (42,27)
Info:                Sink SOC.Core.instruction_register_TRELLIS_FF_Q_6.M
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/soc.v:20.34-20.43
Info:  0.0 22.9  Setup SOC.Core.instruction_register_TRELLIS_FF_Q_6.M
Info: 5.2 ns logic, 17.7 ns routing

Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source ClkDivider.clk_counter_TRELLIS_FF_Q_26.Q
Info:  1.1  1.7    Net reset_LUT4_B_C_LUT4_Z_1_D_PFUMX_Z_C0[0] (17,3) -> (18,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.4  2.1  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.1    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (18,2) -> (18,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.1  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.1    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (18,2) -> (18,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.2  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.2    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (18,2) -> (18,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.2  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.2    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (18,2) -> (18,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.3  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.3    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (18,2) -> (18,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.3  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.3    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (18,2) -> (19,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.3  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.3    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (19,2) -> (19,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.3  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.3    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (19,2) -> (19,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.4  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.4    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (19,2) -> (19,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.4  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.4    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (19,2) -> (19,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.5  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.5    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (19,2) -> (19,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.5  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.5    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (19,2) -> (19,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.5  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.5    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (19,2) -> (19,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.5  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.5    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (19,2) -> (20,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.6  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.6    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (20,2) -> (20,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.6  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.6    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (20,2) -> (20,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.7  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.7    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (20,2) -> (20,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.7  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.7    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (20,2) -> (20,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.8  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.8    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (20,2) -> (20,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.8  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.8    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (20,2) -> (20,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.8  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.8    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (20,2) -> (20,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.8  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.8    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (20,2) -> (21,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  2.9  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  2.9    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (21,2) -> (21,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  2.9  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  2.9    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT_CIN (21,2) -> (21,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:15.3-23.2
Info:                  Risco-5/debug/clk_divider.v:40.12-40.38
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  3.0  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
Info:  0.0  3.0    Net reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (21,2) -> (21,2)
Info:                Sink reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
Info:  0.0  3.0  Source reset_LUT4_B_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
Info:  0.0  3.0    Net $nextpnr_CCU2C_1$CIN (21,2) -> (21,2)
Info:                Sink $nextpnr_CCU2C_1$CCU2_COMB0.FCI
Info:  0.4  3.4  Source $nextpnr_CCU2C_1$CCU2_COMB0.F
Info:  0.9  4.3    Net reset_LUT4_B_C_LUT4_Z_D[1] (21,2) -> (21,3)
Info:                Sink reset_LUT4_B_C_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  4.5  Source reset_LUT4_B_C_LUT4_Z.F
Info:  0.9  5.5    Net reset_LUT4_B_C[1] (21,3) -> (19,4)
Info:                Sink reset_LUT4_B.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  5.7  Source reset_LUT4_B.F
Info:  0.9  6.6    Net reset_LUT4_B_Z (19,4) -> (16,3)
Info:                Sink ClkDivider.clk_counter_TRELLIS_FF_Q_31.LSR
Info:  0.4  7.0  Setup ClkDivider.clk_counter_TRELLIS_FF_Q_31.LSR
Info: 3.2 ns logic, 3.8 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source reset$tr_io.O
Info:  2.6  2.6    Net reset$TRELLIS_IO_IN (0,29) -> (19,4)
Info:                Sink reset_LUT4_B.B
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  2.8  Source reset_LUT4_B.F
Info:  0.9  3.7    Net reset_LUT4_B_Z (19,4) -> (16,3)
Info:                Sink ClkDivider.clk_counter_TRELLIS_FF_Q_31.LSR
Info:  0.4  4.1  Setup ClkDivider.clk_counter_TRELLIS_FF_Q_31.LSR
Info: 0.7 ns logic, 3.5 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk_o':
Info: curr total
Info:  0.0  0.0  Source gpios[3]$tr_io.O
Info:  1.8  1.8    Net gpios[3]$TRELLIS_IO_IN (56,0) -> (44,7)
Info:                Sink SOC.GPIOS.Gpios[3].direction_LUT4_B.A
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:7.16-7.21
Info:  0.2  2.1  Source SOC.GPIOS.Gpios[3].direction_LUT4_B.F
Info:  0.0  2.1    Net SOC.GPIOS.Gpios[3].direction_LUT4_B_Z (44,7) -> (44,7)
Info:                Sink SOC.GPIOS.Gpios[3].direction_LUT4_B_Z_PFUMX_ALUT_BLUT_LUT4_Z.F1
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info:  0.2  2.2  Source SOC.GPIOS.Gpios[3].direction_LUT4_B_Z_PFUMX_ALUT_BLUT_LUT4_Z.OFX
Info:  1.4  3.6    Net SOC.GPIOS.Gpios[3].direction_LUT4_B_Z_PFUMX_ALUT_Z[1] (44,7) -> (39,8)
Info:                Sink SOC.Core.read_data_LUT4_Z_2.B
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  3.9  Source SOC.Core.read_data_LUT4_Z_2.F
Info:  2.2  6.1    Net SOC.read_data[3] (39,8) -> (42,29)
Info:                Sink SOC.Core.instruction_register_TRELLIS_FF_Q_28.M
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/soc.v:20.34-20.43
Info:  0.0  6.1  Setup SOC.Core.instruction_register_TRELLIS_FF_Q_28.M
Info: 0.6 ns logic, 5.5 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source ClkDivider.clk_o_auto_TRELLIS_FF_Q.Q
Info:  3.5  4.0    Net clk_o (20,4) -> (64,7)
Info:                Sink led_LUT4_Z_1.D
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:10.6-10.11
Info:  0.2  4.3  Source led_LUT4_Z_1.F
Info:  2.5  6.8    Net led[7]$TRELLIS_IO_OUT (64,7) -> (90,20)
Info:                Sink led[7]$tr_io.I
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 6.0 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk_o' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source SOC.Leds.data_TRELLIS_FF_Q_31.Q
Info:  2.3  2.8    Net SOC.Leds.data[0] (42,28) -> (17,32)
Info:                Sink led_LUT4_Z_3.D
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:42.3-49.2
Info:                  Risco-5/src/peripheral/leds.v:15.12-15.16
Info:                  Risco-5/src/peripheral/soc.v:83.6-92.2
Info:  0.2  3.1  Source led_LUT4_Z_3.F
Info:  3.4  6.5    Net led[0]$TRELLIS_IO_OUT (17,32) -> (0,59)
Info:                Sink led[0]$tr_io.I
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.7 ns routing

Info: Max frequency for clock             '$glbnet$clk_o': 43.63 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 143.12 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.11 ns
Info: Max delay <async>                           -> posedge $glbnet$clk_o            : 6.11 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 6.76 ns
Info: Max delay posedge $glbnet$clk_o             -> <async>                          : 6.49 ns

Info: Slack histogram:
Info:  legend: * represents 164 endpoint(s)
Info:          + represents [1,164) endpoint(s)
Info: [ 33013,  35474) |+
Info: [ 35474,  37935) |+
Info: [ 37935,  40396) |+
Info: [ 40396,  42857) | 
Info: [ 42857,  45318) | 
Info: [ 45318,  47779) | 
Info: [ 47779,  50240) | 
Info: [ 50240,  52701) | 
Info: [ 52701,  55162) | 
Info: [ 55162,  57623) | 
Info: [ 57623,  60084) | 
Info: [ 60084,  62545) |+
Info: [ 62545,  65006) |+
Info: [ 65006,  67467) |+
Info: [ 67467,  69928) |***************+
Info: [ 69928,  72389) |************************************************************ 
Info: [ 72389,  74850) |*****+
Info: [ 74850,  77311) |*+
Info: [ 77311,  79772) |******+
Info: [ 79772,  82233) |+

5 warnings, 0 errors

Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (openFPGAloader)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
Found 1 compatible device:
	0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE

Loading: [=====                                             ] 9.45%
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Loading: [=============================                     ] 56.71%
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Done
Disable configuration: DONE
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS