Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Risco_5
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -Rf Risco-5/ build/
[Pipeline] sh
+ git clone https://github.com/JN513/Risco-5
Cloning into 'Risco-5'...
[Pipeline] sh
+ cd Risco-5
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (IVerilog)
[Pipeline] sh
+ mkdir -p build
[Pipeline] sh
+ cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/csr_unit.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/fifo.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v
[Pipeline] sh
+ /eda/oss-cad-suite/bin/vvp build/soc_test.o
ERROR: Risco-5/src/peripheral/memory.v:29: $readmemh: Unable to open software/memory/generic.hex for reading.
VCD info: dumpfile build/soc.vcd opened for output.
Risco-5/tests/soc_test.v:34: $finish called at 1206 (1s)
[Pipeline] sh
+ rm -f Risco-5/software/memory/generic.hex
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Síntese)
[Pipeline] parallel
[Pipeline] { (Branch: OSS-Cad-Suite)
[Pipeline] { (Branch: Gowin)
[Pipeline] { (Branch: Vivado)
[Pipeline] stage
[Pipeline] { (OSS-Cad-Suite)
[Pipeline] stage
[Pipeline] { (Gowin)
[Pipeline] stage
[Pipeline] { (Vivado)
[Pipeline] stage
[Pipeline] { (Yosys)
[Pipeline] sh
[Pipeline] sh
+ rm -rf Risco-5/impl/pnr
[Pipeline] sh
+ cd Risco-5/fpga/nexys4_ddr
+ mkdir build
+ /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source run.tcl
[Pipeline] sh
+ mkdir -p Risco-5/impl/pnr
+ /eda/oss-cad-suite/bin/yosys -p                                          read_verilog Risco-5/fpga/ecp5/*.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)

-- Running command `                                         read_verilog Risco-5/fpga/ecp5/*.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     ' --

1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v
Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: Risco-5/debug/reset.v
Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v
Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation.
Generating RTLIL representation for module `\Alu'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v
Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation.
Generating RTLIL representation for module `\ALU_Control'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v
Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: Risco-5/src/core/core.v
Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation.
Generating RTLIL representation for module `\Core'.
Risco-5/src/core/core.v:112: Warning: Identifier `\pc_source' is implicitly declared.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: Risco-5/src/core/csr_unit.v
Parsing Verilog input from `Risco-5/src/core/csr_unit.v' to AST representation.
Generating RTLIL representation for module `\CSR_Unit'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v
Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation.
Generating RTLIL representation for module `\Immediate_Generator'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v
Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation.
Generating RTLIL representation for module `\MUX'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v
Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation.
Generating RTLIL representation for module `\PC'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v
Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation.
Generating RTLIL representation for module `\Registers'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v
Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation.
Generating RTLIL representation for module `\BUS'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/fifo.v
Parsing Verilog input from `Risco-5/src/peripheral/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v
Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9)
Generating RTLIL representation for module `\GPIO'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v
Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation.
Generating RTLIL representation for module `\GPIOS'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v
Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation.
Generating RTLIL representation for module `\LEDs'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v
Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v
Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation.
Generating RTLIL representation for module `\Risco_5_SOC'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v
Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_rx'.
Successfully finished Verilog frontend.

21. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_tx'.
Successfully finished Verilog frontend.

22. Executing SYNTH_ECP5 pass.

22.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

22.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

22.3. Executing HIERARCHY pass (managing design hierarchy).

22.3.1. Finding top of design hierarchy..
root of   0 design levels: uart_tool_tx        
root of   0 design levels: uart_tool_rx        
root of   1 design levels: UART                
root of   2 design levels: Risco_5_SOC         
root of   0 design levels: Memory              
root of   0 design levels: LEDs                
root of   1 design levels: GPIOS               
root of   0 design levels: GPIO                
root of   0 design levels: FIFO                
root of   0 design levels: BUS                 
root of   0 design levels: Registers           
root of   0 design levels: PC                  
root of   0 design levels: MUX                 
root of   0 design levels: Immediate_Generator 
root of   0 design levels: CSR_Unit            
root of   1 design levels: Core                
root of   0 design levels: Control_Unit        
root of   0 design levels: ALU_Control         
root of   0 design levels: Alu                 
root of   0 design levels: ResetBootSystem     
root of   3 design levels: top                 
Automatically selected top as design top module.

22.3.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     \ResetBootSystem
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \MEMORY_SIZE = 2048
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6

22.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \MEMORY_SIZE = 2048
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6
Generating RTLIL representation for module `$paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC'.
Parameter \CYCLES = 20

22.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \WIDHT = 5

22.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 5
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600

22.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Generating RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

22.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \BOOT_ADDRESS = 0

22.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'.
Parameter \BOOT_ADDRESS = 0
Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.
Risco-5/src/core/core.v:112: Warning: Identifier `\pc_source' is implicitly declared.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

22.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

22.3.12. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \WIDHT = 6

22.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 6
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200

22.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Generating RTLIL representation for module `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART'.
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 2048

22.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 2048
Generating RTLIL representation for module `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory'.
Parameter \BOOT_ADDRESS = 0
Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.

22.3.16. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

22.3.19. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100

22.3.20. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Removing unused module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Removing unused module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Removing unused module `\uart_tool_tx'.
Removing unused module `\uart_tool_rx'.
Removing unused module `\UART'.
Removing unused module `\Risco_5_SOC'.
Removing unused module `\Memory'.
Removing unused module `\GPIOS'.
Removing unused module `\FIFO'.
Removing unused module `\Core'.
Removing unused module `\ResetBootSystem'.
Removed 14 unused modules.

22.4. Executing PROC pass (convert processes to netlists).

22.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$495'.
Found and cleaned up 1 empty switch in `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:0$883'.
Removing empty process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:0$883'.
Cleaned up 2 empty switches.

22.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$602 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496 in module TRELLIS_DPR16X4.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/fifo.v:24$794 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:197$976 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:186$974 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:171$966 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:160$963 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:148$957 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:133$952 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:116$947 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:97$938 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:173$925 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:162$923 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:147$915 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:130$901 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:115$895 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:98$890 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:190$684 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:45$881 in module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:33$844 in module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$215 in module LEDs.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:76$834 in module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:41$820 in module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:29$818 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:22$73 in module Registers.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:15$63 in module PC.
Removed 1 dead cases from process $proc$Risco-5/src/core/mux.v:10$62 in module MUX.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/mux.v:10$62 in module MUX.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:18$60 in module Immediate_Generator.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:187$58 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:178$54 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:164$52 in module CSR_Unit.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:118$45 in module CSR_Unit.
Marked 5 switch rules as full_case in process $proc$Risco-5/debug/reset.v:24$605 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Removed 1 dead cases from process $proc$Risco-5/src/core/control_unit.v:122$33 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:122$33 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/control_unit.v:80$31 in module Control_Unit.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:80$31 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:72$30 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:9$26 in module ALU_Control.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:9$26 in module ALU_Control.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:23$11 in module Alu.
Removed a total of 4 dead cases.

22.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 11 redundant assignments.
Promoted 146 assignments to connections.

22.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$603'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$978'.
  Set init value: \i = 0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$931'.
  Set init value: \i = 0
Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$687'.
  Set init value: \instruction_register = 0
  Set init value: \memory_register = 0
  Set init value: \alu_out_register = 0
  Set init value: \register_data_1 = 0
  Set init value: \register_data_2 = 0
  Set init value: \pc_old = 0
Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$218'.
  Set init value: \data = 33'000000000000000000000000000000000
Found init rule in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$837'.
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \buffer_full = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$66'.
  Set init value: \Output = 0
Found init rule in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'.
  Set init value: \csr_mcause = 0
  Set init value: \csr_mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \csr_mepc = 0
  Set init value: \csr_mie_mfie = 16'0000000000000000
  Set init value: \csr_mie_meie = 1'0
  Set init value: \csr_mie_msie = 1'0
  Set init value: \csr_mie_mtie = 1'0
  Set init value: \csr_mip_mfip = 16'0000000000000000
  Set init value: \csr_mip_meip = 1'0
  Set init value: \csr_mip_mtip = 1'0
  Set init value: \csr_mip_msip = 1'0
  Set init value: \csr_minstret = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \csr_mscratch = 0
  Set init value: \csr_mstatus_mie = 1'0
  Set init value: \csr_mstatus_mpie = 1'0
  Set init value: \csr_mtvec = 0
  Set init value: \csr_mtval = 0
  Set init value: \csr_write_data = 0
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$611'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000
Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$34'.
  Set init value: \state = 4'0000
  Set init value: \is_immediate = 1'0
  Set init value: \lorD = 1'0
  Set init value: \pc_write = 1'0
  Set init value: \ir_write = 1'0
  Set init value: \pc_source = 1'0
  Set init value: \reg_write = 1'0
  Set init value: \memory_read = 1'0
  Set init value: \memory_write = 1'0
  Set init value: \pc_write_cond = 1'0
  Set init value: \csr_write_enable = 1'0
  Set init value: \aluop = 2'00
  Set init value: \alu_src_a = 2'00
  Set init value: \alu_src_b = 2'00
  Set init value: \memory_to_reg = 2'00
  Set init value: \nextstate = 4'0000

22.4.5. Executing PROC_ARST pass (detect async resets in processes).

22.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 1 switch.
<suppressed ~88 debug messages>

22.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$603'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$602'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_EN[3:0]$560
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_DATA[3:0]$559
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_ADDR[3:0]$558
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_EN[3:0]$502
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_DATA[3:0]$501
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_ADDR[3:0]$500
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$495'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'.
     1/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$806
     2/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_DATA[7:0]$805
     3/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$804
     4/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$801
     5/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_DATA[7:0]$800
     6/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$799
     7/8: $0\write_ptr[5:0]
     8/8: $0\read_ptr[5:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$978'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$976'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$974'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$966'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$963'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$957'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$952'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$947'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$938'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$931'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$925'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$923'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$915'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$901'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$895'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$890'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$687'.
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
     1/6: $0\alu_out_register[31:0]
     2/6: $0\register_data_2[31:0]
     3/6: $0\register_data_1[31:0]
     4/6: $0\memory_register[31:0]
     5/6: $0\pc_old[31:0]
     6/6: $0\instruction_register[31:0]
Creating decoders for process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$881'.
     1/1: $1\read_data[31:0]
Creating decoders for process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
     1/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$877
     2/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_DATA[31:0]$876
     3/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$875
     4/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$880
     5/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_DATA[31:0]$879
     6/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$878
     7/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$867
     8/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_DATA[31:0]$866
     9/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_ADDR[31:0]$865
    10/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$873
    11/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_DATA[31:0]$872
    12/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$871
    13/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$870
    14/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_DATA[31:0]$869
    15/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$868
    16/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$863
    17/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_DATA[31:0]$862
    18/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$861
    19/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$860
    20/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_DATA[31:0]$859
    21/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$858
    22/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$857
    23/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_DATA[31:0]$856
    24/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_ADDR[31:0]$855
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$218'.
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$215'.
     1/1: $0\data[32:0]
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$837'.
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$834'.
     1/1: $1\read_data[31:0]
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
     1/9: $0\rx_fifo_write[0:0]
     2/9: $0\rx_fifo_read[0:0]
     3/9: $0\tx_fifo_write[0:0]
     4/9: $0\tx_fifo_read[0:0]
     5/9: $0\uart_tx_en[0:0]
     6/9: $0\rx_fifo_write_data[7:0]
     7/9: $0\tx_fifo_write_data[7:0]
     8/9: $0\uart_tx_data[7:0]
     9/9: $0\buffer_full[0:0]
Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$818'.
     1/2: $0\gpio_value[5:0]
     2/2: $0\gpio_direction[5:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$91'.
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'.
     1/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$88
     2/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$69_DATA[31:0]$87
     3/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$69_ADDR[4:0]$86
     4/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$89
     5/9: $1$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$80
     6/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$84
     7/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$83
     8/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$69_DATA[31:0]$82
     9/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$69_ADDR[4:0]$81
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$66'.
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:15$63'.
     1/1: $0\Output[31:0]
Creating decoders for process `\MUX.$proc$Risco-5/src/core/mux.v:10$62'.
     1/1: $1\S[31:0]
Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$60'.
     1/4: $4\immediate[31:0]
     2/4: $3\immediate[31:0]
     3/4: $2\immediate[31:0]
     4/4: $1\immediate[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'.
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$58'.
     1/1: $1\csr_data_out[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54'.
     1/1: $1\csr_write_data[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$52'.
     1/4: $0\csr_mip_msip[0:0]
     2/4: $0\csr_mip_mtip[0:0]
     3/4: $0\csr_mip_meip[0:0]
     4/4: $0\csr_mip_mfip[15:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
     1/13: $0\csr_mtval[31:0]
     2/13: $0\csr_mtvec[31:0]
     3/13: $0\csr_mstatus_mpie[0:0]
     4/13: $0\csr_mstatus_mie[0:0]
     5/13: $0\csr_mscratch[31:0]
     6/13: $0\csr_minstret[63:0]
     7/13: $0\csr_mie_mtie[0:0]
     8/13: $0\csr_mie_msie[0:0]
     9/13: $0\csr_mie_meie[0:0]
    10/13: $0\csr_mie_mfie[15:0]
    11/13: $0\csr_mepc[31:0]
    12/13: $0\csr_mcycle[63:0]
    13/13: $0\csr_mcause[31:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$611'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$34'.
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
     1/1: { $1\pc_write[0:0] $1\alu_src_b[1:0] $1\ir_write[0:0] $1\memory_read[0:0] $1\memory_to_reg[1:0] $1\alu_src_a[1:0] $1\aluop[1:0] $1\csr_write_enable[0:0] $1\pc_write_cond[0:0] $1\memory_write[0:0] $1\reg_write[0:0] $1\pc_source[0:0] $1\lorD[0:0] $1\is_immediate[0:0] }
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31'.
     1/3: $3\nextstate[3:0]
     2/3: $2\nextstate[3:0]
     3/3: $1\nextstate[3:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$30'.
     1/1: $0\state[3:0]
Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'.
     1/4: $4\aluop_out[3:0]
     2/4: $3\aluop_out[3:0]
     3/4: $2\aluop_out[3:0]
     4/4: $1\aluop_out[3:0]
Creating decoders for process `\Alu.$proc$Risco-5/src/core/alu.v:23$11'.
     1/1: $1\ALU_out_S[31:0]

22.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$947'.
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$890'.
No latch inferred for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.\read_data' from process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$881'.
No latch inferred for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\read_data' from process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$834'.
No latch inferred for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:16$67_EN' from process `\Registers.$proc$Risco-5/src/core/registers.v:0$91'.
No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$Risco-5/src/core/mux.v:10$62'.
No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$60'.
No latch inferred for signal `\CSR_Unit.\csr_mcause_code' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'.
No latch inferred for signal `\CSR_Unit.\csr_mcause_interrupt_flag' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'.
No latch inferred for signal `\CSR_Unit.\csr_utime' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'.
No latch inferred for signal `\CSR_Unit.\csr_data_out' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$58'.
No latch inferred for signal `\CSR_Unit.\csr_write_data' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54'.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [0]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [1]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [2]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [3]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [4]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [5]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [6]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [7]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [8]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [9]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [10]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [11]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [12]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [13]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [14]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [15]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [16]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [17]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [18]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [19]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [20]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [21]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [22]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [23]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [24]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [25]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [26]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [27]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [28]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [29]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [30]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [31]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\csr_write_enable` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31`.
Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26': $auto$proc_dlatch.cc:433:proc_dlatch$2031
No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$Risco-5/src/core/alu.v:23$11'.

22.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$602'.
  created $dff cell `$procdff$2054' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$538_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$539_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$540_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$541_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$542_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$543_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$544_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$545_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$546_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$547_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$548_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$549_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$550_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$551_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$552_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554'.
  created $dff cell `$procdff$2055' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554'.
  created $dff cell `$procdff$2056' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554'.
  created $dff cell `$procdff$2057' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$478_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$479_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$480_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$481_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$482_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$483_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$484_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$485_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$486_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$487_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$488_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$489_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$490_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$491_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$492_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$493_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496'.
  created $dff cell `$procdff$2058' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496'.
  created $dff cell `$procdff$2059' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496'.
  created $dff cell `$procdff$2060' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$495'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'.
  created $dff cell `$procdff$2061' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'.
  created $dff cell `$procdff$2062' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'.
  created $dff cell `$procdff$2063' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'.
  created $dff cell `$procdff$2064' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'.
  created $dff cell `$procdff$2065' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$976'.
  created $dff cell `$procdff$2066' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$976'.
  created $dff cell `$procdff$2067' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$974'.
  created $dff cell `$procdff$2068' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$966'.
  created $dff cell `$procdff$2069' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$963'.
  created $dff cell `$procdff$2070' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$957'.
  created $dff cell `$procdff$2071' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$952'.
  created $dff cell `$procdff$2072' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$952'.
  created $dff cell `$procdff$2073' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$938'.
  created $dff cell `$procdff$2074' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$925'.
  created $dff cell `$procdff$2075' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$923'.
  created $dff cell `$procdff$2076' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$915'.
  created $dff cell `$procdff$2077' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$901'.
  created $dff cell `$procdff$2078' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$895'.
  created $dff cell `$procdff$2079' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$895'.
  created $dff cell `$procdff$2080' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
  created $dff cell `$procdff$2081' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
  created $dff cell `$procdff$2082' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
  created $dff cell `$procdff$2083' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
  created $dff cell `$procdff$2084' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
  created $dff cell `$procdff$2085' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
  created $dff cell `$procdff$2086' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_ADDR' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2087' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_DATA' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2088' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2089' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2090' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_DATA' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2091' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2092' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2093' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_DATA' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2094' with positive edge clock.
Creating register for signal `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN' using process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2095' with positive edge clock.
Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$215'.
  created $dff cell `$procdff$2096' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\uart_tx_en' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2097' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_read' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2098' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_write' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2099' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_read' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2100' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_write' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2101' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\buffer_full' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2102' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\uart_tx_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2103' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_write_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2104' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_write_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2105' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$818'.
  created $dff cell `$procdff$2106' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$818'.
  created $dff cell `$procdff$2107' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'.
  created $dff cell `$procdff$2108' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$69_ADDR' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'.
  created $dff cell `$procdff$2109' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$69_DATA' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'.
  created $dff cell `$procdff$2110' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'.
  created $dff cell `$procdff$2111' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'.
  created $dff cell `$procdff$2112' with positive edge clock.
Creating register for signal `\PC.\Output' using process `\PC.$proc$Risco-5/src/core/pc.v:15$63'.
  created $dff cell `$procdff$2113' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_mfip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$52'.
  created $dff cell `$procdff$2114' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_meip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$52'.
  created $dff cell `$procdff$2115' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_mtip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$52'.
  created $dff cell `$procdff$2116' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_msip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$52'.
  created $dff cell `$procdff$2117' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mcause' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2118' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mcycle' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2119' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mepc' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2120' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_mfie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2121' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_meie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2122' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_msie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2123' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_mtie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2124' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_minstret' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2125' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mscratch' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2126' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mstatus_mie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2127' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mstatus_mpie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2128' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mtvec' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2129' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mtval' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2130' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'.
  created $dff cell `$procdff$2131' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'.
  created $dff cell `$procdff$2132' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'.
  created $dff cell `$procdff$2133' with positive edge clock.
Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$30'.
  created $dff cell `$procdff$2134' with positive edge clock.

22.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$603'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$602'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$602'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$495'.
Found and cleaned up 3 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$978'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$976'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$976'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$974'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$974'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$966'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$966'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$963'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$963'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$957'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$957'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$952'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$952'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$947'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$947'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$938'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$938'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$931'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$925'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$925'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$923'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$923'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$915'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$915'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$901'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$901'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$895'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$895'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$890'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$890'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$687'.
Found and cleaned up 2 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
Found and cleaned up 1 empty switch in `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$881'.
Removing empty process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:45$881'.
Found and cleaned up 3 empty switches in `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
Removing empty process `$paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$218'.
Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$215'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$215'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$837'.
Found and cleaned up 1 empty switch in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$834'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$834'.
Found and cleaned up 5 empty switches in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$818'.
Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$818'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$91'.
Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:22$73'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:22$73'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$66'.
Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:15$63'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:15$63'.
Found and cleaned up 1 empty switch in `\MUX.$proc$Risco-5/src/core/mux.v:10$62'.
Removing empty process `MUX.$proc$Risco-5/src/core/mux.v:10$62'.
Found and cleaned up 4 empty switches in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$60'.
Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$60'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$58'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$58'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$52'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$52'.
Found and cleaned up 3 empty switches in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$611'.
Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$34'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Found and cleaned up 3 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$30'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$30'.
Found and cleaned up 4 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'.
Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'.
Found and cleaned up 1 empty switch in `\Alu.$proc$Risco-5/src/core/alu.v:23$11'.
Removing empty process `Alu.$proc$Risco-5/src/core/alu.v:23$11'.
Cleaned up 89 empty switches.

22.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
<suppressed ~4 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
<suppressed ~4 debug messages>
Optimizing module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.
<suppressed ~5 debug messages>
Optimizing module LEDs.
<suppressed ~3 debug messages>
Optimizing module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
<suppressed ~9 debug messages>
Optimizing module GPIO.
<suppressed ~3 debug messages>
Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
<suppressed ~4 debug messages>
Optimizing module BUS.
Optimizing module Registers.
<suppressed ~2 debug messages>
Optimizing module PC.
<suppressed ~2 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module Immediate_Generator.
<suppressed ~1 debug messages>
Optimizing module CSR_Unit.
<suppressed ~2 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~7 debug messages>
Optimizing module Control_Unit.
<suppressed ~1 debug messages>
Optimizing module ALU_Control.
<suppressed ~15 debug messages>
Optimizing module Alu.
<suppressed ~1 debug messages>
Optimizing module $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC.
Optimizing module top.

22.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Deleting now unused module $paramod$f1ddc2afd36a607d96067303fa2301dbcd06b4af\Memory.
Deleting now unused module LEDs.
Deleting now unused module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Deleting now unused module GPIO.
Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Deleting now unused module BUS.
Deleting now unused module Registers.
Deleting now unused module PC.
Deleting now unused module MUX.
Deleting now unused module Immediate_Generator.
Deleting now unused module CSR_Unit.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module Control_Unit.
Deleting now unused module ALU_Control.
Deleting now unused module Alu.
Deleting now unused module $paramod$66096ff13eca93a7f6af61f22fabcd62b4edd5e6\Risco_5_SOC.
<suppressed ~30 debug messages>

22.6. Executing TRIBUF pass.

22.7. Executing DEMINOUT pass (demote inout ports to input or output).

22.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~47 debug messages>

22.9. Executing OPT_CLEAN pass (remove unused cells and wires).
[Pipeline] sh
Finding unused cells or wires in module \top..
Removed 64 unused cells and 730 unused wires.
<suppressed ~84 debug messages>

22.10. Executing CHECK pass (checking for obvious problems).
Checking module top...
Warning: Wire top.\SOC.Core.PCSourceMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [15] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [14] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [13] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [12] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [11] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [10] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [9] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [8] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [7] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [6] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [5] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [4] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [3] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [2] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [1] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [0] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_external is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_timer is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_software is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [0] is used but has no driver.
Found and reported 211 problems.

22.11. Executing OPT pass (performing simple optimizations).

22.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6 debug messages>

22.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~351 debug messages>
Removed a total of 117 cells.

22.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1925.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1953.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1601.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1603.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1614.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1629.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1588.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1588.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1588.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1588.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1548.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1554.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1560.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1566.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1345.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1347.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1354.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1356.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1363.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1365.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1372.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1374.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1381.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1383.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1390.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1392.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1398.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1404.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1410.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1416.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1422.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1428.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1434.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1440.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1446.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1010.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1016.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1022.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1010.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1016.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1022.
Removed 41 multiplexer ports.
<suppressed ~120 debug messages>

22.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1643: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1664_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1663_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1656_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1655_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1654_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1653_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1652_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1651_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1650_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1649_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1648_CMP $auto$opt_reduce.cc:134:opt_pmux$2191 $auto$opt_reduce.cc:134:opt_pmux$2189 $auto$opt_reduce.cc:134:opt_pmux$2187 $auto$opt_reduce.cc:134:opt_pmux$2185 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1942: { $auto$opt_reduce.cc:134:opt_pmux$2193 $flatten\SOC.\Core.\Control_Unit.$procmux$1950_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1949_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1948_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1947_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1946_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1945_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1944_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1943_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1955: { $flatten\SOC.\Core.\Control_Unit.$procmux$1971_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1954_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1926_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1968_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1960_CMP $auto$opt_reduce.cc:134:opt_pmux$2197 $auto$opt_reduce.cc:134:opt_pmux$2195 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1991: { $flatten\SOC.\Core.\ALU_Control.$procmux$1998_CMP $auto$opt_reduce.cc:134:opt_pmux$2199 $flatten\SOC.\Core.\ALU_Control.$procmux$1995_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1994_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1993_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1992_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1626: $auto$opt_reduce.cc:134:opt_pmux$2201
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1632: { $flatten\SOC.\Core.\Control_Unit.$procmux$1947_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1948_CMP $auto$opt_reduce.cc:134:opt_pmux$2205 $flatten\SOC.\Core.\Control_Unit.$procmux$1949_CMP $auto$opt_reduce.cc:134:opt_pmux$2203 $flatten\SOC.\Core.\Control_Unit.$procmux$1943_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1951_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1545:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1563:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1569:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1342:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1342_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1342_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1342_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2005: { $auto$opt_reduce.cc:134:opt_pmux$2209 $auto$opt_reduce.cc:134:opt_pmux$2207 $flatten\SOC.\Core.\ALU_Control.$procmux$1998_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1369:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Memory.$procmux$1369_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Memory.$procmux$1369_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1369_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2014: { $flatten\SOC.\Core.\ALU_Control.$procmux$2016_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2015_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1396:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1396_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1396_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1396_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0]
      New connections: $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1572:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$89, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1575:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$88, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1414:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$880, B=0, Y=$flatten\SOC.\Memory.$procmux$1414_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1369_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1414_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1414_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1432:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$877, B=0, Y=$flatten\SOC.\Memory.$procmux$1432_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1342_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1432_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1432_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1467:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$867, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1396_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1025:
      Old ports: A=$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$806, B=8'00000000, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797
      New ports: A=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1025:
      Old ports: A=$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$806, B=8'00000000, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797
      New ports: A=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0]
      New connections: $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1449:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$873, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1414_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1458:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$870, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1432_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] }
  Optimizing cells in module \top.
Performed a total of 25 changes.

22.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

22.11.6. Executing OPT_DFF pass (perform DFF optimizations).

22.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 3 unused cells and 169 unused wires.
<suppressed ~8 debug messages>

22.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.11.9. Rerunning OPT passes. (Maybe there is more to do..)

22.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~119 debug messages>

22.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.11.13. Executing OPT_DFF pass (perform DFF optimizations).
+ cd Risco-5/fpga/tangnano20k/
+ /eda/gowin/IDE/bin/gw_sh run.tcl
*** GOWIN Tcl Command Line Console  *** 
current device: GW2AR-18C  GW2AR-LV18QN88C8/I7
add new file: "pinout.cst"
add new file: "top.sdc"
add new file: "main.v"
add new file: "../../debug/reset.v"
add new file: "../../src/core/alu_control.v"
add new file: "../../src/core/alu.v"
add new file: "../../src/core/control_unit.v"
add new file: "../../src/core/core.v"
add new file: "../../src/core/immediate_generator.v"
add new file: "../../src/core/mux.v"
add new file: "../../src/core/pc.v"
add new file: "../../src/core/registers.v"
add new file: "../../src/core/csr_unit.v"
add new file: "../../src/peripheral/bus.v"
add new file: "../../src/peripheral/gpio.v"
add new file: "../../src/peripheral/gpios.v"
add new file: "../../src/peripheral/leds.v"
add new file: "../../src/peripheral/memory.v"
add new file: "../../src/peripheral/soc.v"
add new file: "../../src/peripheral/uart_rx.v"
add new file: "../../src/peripheral/uart_tx.v"
add new file: "../../src/peripheral/uart.v"
add new file: "../../src/peripheral/fifo.v"
GowinSynthesis start
Running parser ...
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v'
Undeclared symbol 'pc_source', assumed default net type 'wire'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":112)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v'
WARN  (EX3801) : Parameter 'SET_DIRECTION' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":17)
WARN  (EX3801) : Parameter 'READ' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":18)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v'
WARN  (EX3012) : Empty statement in sequential block("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":40)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v'
WARN  (EX3073) : Port 'resetn_o' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":18)
Compiling module 'top'("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":1)
Compiling module 'ResetBootSystem'("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":1)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":37)
Compiling module 'Risco_5_SOC(CLOCK_FREQ=27000000,MEMORY_SIZE=2048,MEMORY_FILE="../../software/memory/fpga_test_3.hex")'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":1)
WARN  (EX3073) : Port 'C' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX3073) : Port 'D' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX3073) : Port 'D' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX3073) : Port 'C' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX3073) : Port 'interrupt_on_hold' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":188)
Compiling module 'Core(BOOT_ADDRESS=32'b00000000000000000000000000000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":1)
Compiling module 'PC'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v":1)
Compiling module 'MUX'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v":1)
Compiling module 'Registers'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v":1)
Compiling module 'Control_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":1)
Compiling module 'ALU_Control'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":1)
WARN  (EX2420) : Latch inferred for net 'aluop_out[3]'; We do not recommend the use of latches in FPGA designs, as they may lead to timing problems("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":57)
Compiling module 'Alu'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v":1)
Compiling module 'Immediate_Generator'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v":1)
Compiling module 'CSR_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":1)
WARN  (EX3780) : Using initial value of 'csr_utime' since it is never assigned("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":114)
WARN  (EX2565) : Input 'C[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'C[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'save_pc' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":188)
Compiling module 'Memory(MEMORY_FILE="../../software/memory/fpga_test_3.hex",MEMORY_SIZE=2048)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":1)
Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":15)
Compiling module 'BUS'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v":1)
Compiling module 'LEDs'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":1)
WARN  (EX3791) : Expression size 33 truncated to fit in target size 32("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":21)
Compiling module 'UART(CLOCK_FREQ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v":1)
Compiling module 'FIFO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":1)
Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":15)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":35)
Compiling module 'uart_tool_rx(CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v":10)

22.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.11.16. Finished OPT passes. (There is nothing left to do.)

22.12. Executing FSM pass (extract and optimize FSM).

22.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.
Not marking top.SOC.Core.CSR_Unit.csr_mip_mfip as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Not marking top.SOC.Core.Control_Unit.state as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state.
Not marking top.SOC.Uart.i_uart_tx.fsm_state as FSM state register:
    Users of register don't seem to benefit from recoding.

22.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'.
  found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$2068
  root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$940_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$955_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$968_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$954_Y
  found state code: 3'000
  found ctrl input: \SOC.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \SOC.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$968_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$959_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$955_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$954_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$940_Y
  ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o }
  ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$940_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$954_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$955_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$959_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$968_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'0--0 ->      3'001 8'01010001
  transition:      3'000 4'1--0 ->      3'000 8'01010000
  transition:      3'000 4'---1 ->      3'000 8'01010000
  transition:      3'010 4'--00 ->      3'010 8'00100010
  transition:      3'010 4'--10 ->      3'011 8'00100011
  transition:      3'010 4'---1 ->      3'000 8'00100000
  transition:      3'001 4'-0-0 ->      3'001 8'00011001
  transition:      3'001 4'-1-0 ->      3'010 8'00011010
  transition:      3'001 4'---1 ->      3'000 8'00011000
  transition:      3'011 4'-0-0 ->      3'011 8'10010011
  transition:      3'011 4'-1-0 ->      3'000 8'10010000
  transition:      3'011 4'---1 ->      3'000 8'10010000

22.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2210' from module `\top'.

22.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 7 unused cells and 7 unused wires.
<suppressed ~8 debug messages>

22.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2210' from module `\top'.
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].

22.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2210' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---

22.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2210' from module `top':
-------------------------------------

  Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$2210 (\SOC.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \ResetBootSystem.reset_o
    1: \SOC.Uart.i_uart_rx.payload_done
    2: \SOC.Uart.i_uart_rx.next_bit
    3: \SOC.Uart.i_uart_rx.rxd_reg

  Output signals:
    0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$968_Y
    1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$959_Y
    2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$955_Y
    3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$954_Y
    4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$940_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'1--0   ->     0 5'01010
      1:     0 4'---1   ->     0 5'01010
      2:     0 4'0--0   ->     2 5'01010
      3:     1 4'---1   ->     0 5'00100
      4:     1 4'--00   ->     1 5'00100
      5:     1 4'--10   ->     3 5'00100
      6:     2 4'---1   ->     0 5'00011
      7:     2 4'-1-0   ->     1 5'00011
      8:     2 4'-0-0   ->     2 5'00011
      9:     3 4'-1-0   ->     0 5'10010
     10:     3 4'---1   ->     0 5'10010
     11:     3 4'-0-0   ->     3 5'10010

-------------------------------------

22.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2210' from module `\top'.

22.13. Executing OPT pass (performing simple optimizations).

22.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

22.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

22.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~118 debug messages>

22.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2080 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1291_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1285_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1276_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1267_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1258_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1249_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1231_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1240_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2260 ($sdff) from module top (D = \SOC.Uart.uart_tx_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$2260 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1285_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1276_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1267_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1258_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1249_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1231_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1240_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2078 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1207_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$2265 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1207_Y, Q = \SOC.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2077 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1196_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$2271 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$922_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2076 ($dff) from module top (D = \SOC.Uart.i_uart_tx.n_fsm_state, Q = \SOC.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2075 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1185_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$2276 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1185_Y, Q = \SOC.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2074 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1174_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2282 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2073 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$1151_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1142_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1133_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1124_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1115_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1106_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1088_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1097_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2284 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2071 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1070_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$2288 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$962_Y, Q = \SOC.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2070 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1065_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2292 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2069 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1057_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$2294 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$973_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2067 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2066 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$2062 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1034_Y, Q = \SOC.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2300 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$809_Y, Q = \SOC.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$2061 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1039_Y, Q = \SOC.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2302 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814_Y [5:0], Q = \SOC.Uart.TX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$2062 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1034_Y, Q = \SOC.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2304 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$809_Y, Q = \SOC.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$2061 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1039_Y, Q = \SOC.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2306 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814_Y [5:0], Q = \SOC.Uart.RX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2105 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1510_Y, Q = \SOC.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2308 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.uart_rx_data, Q = \SOC.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2104 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1515_Y, Q = \SOC.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2310 ($sdff) from module top (D = \SOC.Uart.write_data [7:0], Q = \SOC.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2103 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1520_Y, Q = \SOC.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2312 ($sdff) from module top (D = \SOC.Uart.tx_fifo_read_data, Q = \SOC.Uart.uart_tx_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2101 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1485_Y, Q = \SOC.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2100 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1490_Y, Q = \SOC.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2099 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1495_Y, Q = \SOC.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2097 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1500_Y, Q = \SOC.Uart.uart_tx_en, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Leds.$procdff$2096 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$1475_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2318 ($sdff) from module top (D = { 1'0 \SOC.Leds.write_data }, Q = \SOC.Leds.data).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2107 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1531_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2320 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_value).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2106 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1539_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2324 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_direction).
Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$2113 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$1583_Y, Q = \SOC.Core.Pc.Output, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2330 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.Output).
Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$2134 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 4'0000).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2130 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1687_Y, Q = \SOC.Core.CSR_Unit.csr_mtval, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2333 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mtval).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2129 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 1'0 \SOC.Core.CSR_Unit.csr_write_data [0] }, Q = \SOC.Core.CSR_Unit.csr_mtvec).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2128 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1713_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$2342 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2127 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1730_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2346 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mstatus_mie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2126 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1746_Y, Q = \SOC.Core.CSR_Unit.csr_mscratch, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2350 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mscratch).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2125 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1759_Y, Q = \SOC.Core.CSR_Unit.csr_minstret, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2354 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1759_Y, Q = \SOC.Core.CSR_Unit.csr_minstret).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2124 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1777_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mtie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2358 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mie_mtie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2123 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1795_Y, Q = \SOC.Core.CSR_Unit.csr_mie_msie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2362 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mie_msie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2122 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1813_Y, Q = \SOC.Core.CSR_Unit.csr_mie_meie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2366 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [11], Q = \SOC.Core.CSR_Unit.csr_mie_meie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2121 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1831_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mfie, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2370 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [31:16], Q = \SOC.Core.CSR_Unit.csr_mie_mfie).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2120 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 2'00 }, Q = \SOC.Core.CSR_Unit.csr_mepc).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2119 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1854_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2379 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1854_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2118 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1865_Y, Q = \SOC.Core.CSR_Unit.csr_mcause, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2383 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mcause).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2117 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_software, Q = \SOC.Core.CSR_Unit.csr_mip_msip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2116 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_timer, Q = \SOC.Core.CSR_Unit.csr_mip_mtip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2115 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_external, Q = \SOC.Core.CSR_Unit.csr_mip_meip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2114 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_fast, Q = \SOC.Core.CSR_Unit.csr_mip_mfip, rval = 16'0000000000000000).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2086 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1323_Y, Q = \SOC.Core.pc_old, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2391 ($sdff) from module top (D = \SOC.Core.Pc.Output, Q = \SOC.Core.pc_old).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2085 ($dff) from module top (D = \SOC.Bus.write_data, Q = \SOC.Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2084 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2083 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2082 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2081 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1328_Y, Q = \SOC.Core.instruction_register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2397 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2133 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2132 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2131 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2374 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2374 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2337 ($dffe) from module top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$2319 ($sdffe) from module top.

22.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 130 unused cells and 126 unused wires.
<suppressed ~131 debug messages>

22.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

22.13.9. Rerunning OPT passes. (Maybe there is more to do..)

22.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~76 debug messages>

22.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$2290: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o }
  Optimizing cells in module \top.
Performed a total of 1 changes.

22.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~15 debug messages>
Removed a total of 5 cells.

22.13.13. Executing OPT_DFF pass (perform DFF optimizations).

22.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 6 unused wires.
<suppressed ~2 debug messages>

22.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.13.16. Rerunning OPT passes. (Maybe there is more to do..)

22.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Compiling module 'uart_tool_tx(CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v":10)
Compiling module 'GPIOS(WIDHT=5)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":1)
Compiling module 'GPIO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v":1)
WARN  (EX2565) : Input 'instruction_request_external' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_timer' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_software' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
NOTE  (EX0101) : Current top module is "top"
WARN  (EX0211) : The output port "interrupt_on_hold" of module "CSR_Unit" has no driver, assigning undriven bits to Z, simulation mismatch possible("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":20)
[5%] Running netlist conversion ...
WARN  (CV0016) : Input reset is unused("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":3)
Running device independent optimization ...
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~76 debug messages>

22.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.20. Executing OPT_DFF pass (perform DFF optimizations).

22.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.13.23. Finished OPT passes. (There is nothing left to do.)

22.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 28 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\Control_Unit.$auto$mem.cc:328:emit$982 ($flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2139 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2141 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$meminit$\registers$Risco-5/src/core/registers.v:16$90 (SOC.Core.RegisterBank.registers).
Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2136 (SOC.Memory.memory).
Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2137 (SOC.Memory.memory).
Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2138 (SOC.Memory.memory).
Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$882 (SOC.Memory.memory).
Removed top 23 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$842 (SOC.Memory.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2135 (SOC.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$793 (SOC.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2135 (SOC.Uart.TX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\TX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$793 (SOC.Uart.TX_FIFO.memory).
Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$1882_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$609 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608 ($add).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608 ($add).
Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$607 ($lt).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2405 ($ne).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2410 ($ne).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:20$817 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$1482_CMP0 ($eq).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Uart.$procmux$1481 ($pmux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1031 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1019 ($mux).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$807 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$789 ($eq).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1031 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1019 ($mux).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$807 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$789 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$951 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$950 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$949 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$948 ($mux).
Removed top 2 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:111$943 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:109$941 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$917 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$909 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:135$907 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$904 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$903 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$899 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$894 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$893 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$892 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$891 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:94$887 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:92$885 ($eq).
Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$214 ($mux).
Removed top 20 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$94 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$97 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$98 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$101 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$102 ($le).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$105 ($ge).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$106 ($le).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:75$136 ($mux).
Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:84$152 ($mux).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$166 ($mux).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Memory.$procmux$1338_CMP0 ($eq).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1455 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1464 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1473 ($mux).
Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:100$32 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1591_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1591_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1591_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1968_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1967_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1966_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1965_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1964_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1954_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1951_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1950_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1949_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1946_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1945_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1926_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1923 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2016_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1998_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1997_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1996_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1984 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2029_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2028_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2027_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2026_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$25 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$17 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1669_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1656_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1655_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1654_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1653_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1652_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1651_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1650_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1649_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1648_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$51 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$49 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$48 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$93 ($ge).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1408 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1426 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1444 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1360 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1387 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:80$144 ($mux).
Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608_Y.
Removed top 24 bits (of 32) from wire top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$166_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$17_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$25_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\Control_Unit.$3\nextstate[3:0].
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_ADDR[31:0]$845.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$848.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$851.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_ADDR[31:0]$865.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$868.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$871.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$875.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$878.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$795.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$804.
Removed top 1 bits (of 8) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_DATA[7:0]$805.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814_Y.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$795.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$804.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$948_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$949_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$950_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$951_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$891_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$892_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$893_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$894_Y.

22.15. Executing PEEPOPT pass (run peephole optimizers).

22.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 33 unused wires.
<suppressed ~1 debug messages>

22.17. Executing SHARE pass (SAT-based resource sharing).
Found 4 cells in module top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$793 ($memrd):
    Found 1 activation_patterns using ctrl signal { $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:57$103_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:55$99_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$95_Y $flatten\SOC.\Uart.$procmux$1484_CMP $flatten\SOC.\Uart.$procmux$1483_CMP $flatten\SOC.\Uart.$procmux$1482_CMP }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$842 ($memrd):
    Found 7 activation_patterns using ctrl signal { $flatten\SOC.\Memory.$procmux$1339_CMP $flatten\SOC.\Memory.$procmux$1338_CMP $flatten\SOC.\Memory.$procmux$1337_CMP $flatten\SOC.\Memory.$procmux$1336_CMP \SOC.Memory.option [1:0] $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$95_Y \SOC.Bus.slave_0_write \SOC.Bus.slave_0_read }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:44$23 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2021_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:42$22 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2022_CMP.
    No candidates found.

22.18. Executing TECHMAP pass (map to technology primitives).

22.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

22.18.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~296 debug messages>

22.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.21. Executing TECHMAP pass (map to technology primitives).

22.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

22.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

22.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

22.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15 ($sub).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$46 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$47 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$48 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$49 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$50 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$51 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$962 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$973 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$911 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$922 ($add).
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$922.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$911.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$973.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$962.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$51.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$50.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$49.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$48.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$47.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$46.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14.
  creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608.
  creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$607 ($lt): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$93 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$97 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$101 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$105 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$94 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$98 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$102 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$106 ($le): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24 ($ge): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
  creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$16 ($lt): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
  creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$609 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$607.
  creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21 ($eq): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$106: $auto$alumacc.cc:485:replace_alu$2467
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$102: $auto$alumacc.cc:485:replace_alu$2480
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$98: $auto$alumacc.cc:485:replace_alu$2493
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$94: $auto$alumacc.cc:485:replace_alu$2506
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$105: $auto$alumacc.cc:485:replace_alu$2519
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$101: $auto$alumacc.cc:485:replace_alu$2528
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$97: $auto$alumacc.cc:485:replace_alu$2537
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$93: $auto$alumacc.cc:485:replace_alu$2546
  creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$607, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$609: $auto$alumacc.cc:485:replace_alu$2555
  creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608: $auto$alumacc.cc:485:replace_alu$2566
  creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14: $auto$alumacc.cc:485:replace_alu$2569
  creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15, $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$16, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21: $auto$alumacc.cc:485:replace_alu$2572
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$46: $auto$alumacc.cc:485:replace_alu$2585
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$47: $auto$alumacc.cc:485:replace_alu$2588
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$48: $auto$alumacc.cc:485:replace_alu$2591
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$49: $auto$alumacc.cc:485:replace_alu$2594
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$50: $auto$alumacc.cc:485:replace_alu$2597
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$51: $auto$alumacc.cc:485:replace_alu$2600
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808: $auto$alumacc.cc:485:replace_alu$2603
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786: $auto$alumacc.cc:485:replace_alu$2606
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813: $auto$alumacc.cc:485:replace_alu$2609
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808: $auto$alumacc.cc:485:replace_alu$2612
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786: $auto$alumacc.cc:485:replace_alu$2615
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813: $auto$alumacc.cc:485:replace_alu$2618
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$962: $auto$alumacc.cc:485:replace_alu$2621
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$973: $auto$alumacc.cc:485:replace_alu$2624
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$911: $auto$alumacc.cc:485:replace_alu$2627
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$922: $auto$alumacc.cc:485:replace_alu$2630
  created 28 $alu and 0 $macc cells.

22.23. Executing OPT pass (performing simple optimizations).

22.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

22.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~10 debug messages>
Removed a total of 2 cells.

22.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~76 debug messages>

22.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.23.6. Executing OPT_DFF pass (perform DFF optimizations).

22.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 19 unused wires.
<suppressed ~1 debug messages>

22.23.8. Executing OPT_EXPR pass (perform const folding).
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
Optimizing module top.

22.23.9. Rerunning OPT passes. (Maybe there is more to do..)

22.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~76 debug messages>

22.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.23.13. Executing OPT_DFF pass (perform DFF optimizations).

22.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.23.16. Finished OPT passes. (There is nothing left to do.)

22.24. Executing MEMORY pass.

22.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

22.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

22.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing top.SOC.Core.RegisterBank.registers write port 0.
  Analyzing top.SOC.Core.RegisterBank.registers write port 1.
  Analyzing top.SOC.Core.RegisterBank.registers write port 2.
  Analyzing top.SOC.Memory.memory write port 0.
  Analyzing top.SOC.Memory.memory write port 1.
  Analyzing top.SOC.Memory.memory write port 2.
  Analyzing top.SOC.Uart.RX_FIFO.memory write port 0.
  Analyzing top.SOC.Uart.TX_FIFO.memory write port 0.

22.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

22.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980'[0] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[0] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[1] in module `\top': merging output FF to cell.
    Write port 0: don't care on collision.
    Write port 1: non-transparent.
    Write port 2: non-transparent.
Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found.
Checking read port `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': no output FF found.
Checking read port `\SOC.Uart.TX_FIFO.memory'[0] in module `\top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port address `$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980'[0] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Core.RegisterBank.registers'[0] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found.
Checking read port address `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': merged address FF to cell.

22.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 44 unused wires.
<suppressed ~7 debug messages>

22.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
  Merging ports 0, 2 (address 5'00000).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Memory.memory by address:
  Merging ports 0, 1 (address \SOC.Memory.address [10:2]).
  Merging ports 0, 2 (address \SOC.Memory.address [10:2]).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers using sat-based resource sharing:
  Checking group clocked with posedge \clk, width 32: ports 0, 1.
  Common input cone for all EN signals: 6 cells.
  Size of unconstrained SAT problem: 40 variables, 98 clauses
  Merging port 1 into port 0.

22.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

22.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 8 unused cells and 8 unused wires.
<suppressed ~9 debug messages>

22.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

22.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
using FF mapping for memory top.$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980
mapping memory top.SOC.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_
Extracted data FF from read port 1 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[1]
mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory top.SOC.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted addr FF from read port 0 of top.SOC.Uart.RX_FIFO.memory: $\SOC.Uart.RX_FIFO.memory$rdreg[0]
mapping memory top.SOC.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of top.SOC.Uart.TX_FIFO.memory: $\SOC.Uart.TX_FIFO.memory$rdreg[0]
<suppressed ~1100 debug messages>

22.27. Executing TECHMAP pass (map to technology primitives).

22.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

22.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

22.27.3. Continuing TECHMAP pass.
Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$1f7528d846def63a25ef79a14688e75507487b07\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$16483afc93766dfb5fb1eddfd226d96b3663d59c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$aaadea22aebcd84c93bb9858adaa720cf09b082d\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$4732e8e929fe8d0a57a6c959ddfc52773439ff42\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5b36af983a34dea819263d47bd985c03f062c03b\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5f84a8dd211265fde0680d1329e0aeb011857798\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$65b5a9049f0a0f5b9de58368be8ce2821f51e438\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5a90b288fb430e0f24af5f61ee43ef935b86341e\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$58ddad20e9ef77e6675ec0a973f6df52cac15605\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$569f3b21b6212e6a0e436dd55c34df99d3696e0b\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c21745a1d1b8202233eb4fd671436aaa3b71d7e7\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$eabd6f8a46e61d81805337b1dc746bfd80802602\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$98f4fff52781fee114365d416fa097fc5bdcc5a1\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$ef9fccd6f2ebbfd2f9ea51ad76fcd229dd950af9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$f05333f47f0fac035d1d00a83ba1f91fba94d570\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$e060b64551c3d3977f3359c6d9cbc2f183f778aa\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5e6f6332f5b0abb114a71354918e4077127fc51f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$04114c6daf9b714920df2338bb84f1d824cfb28f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$df0229c2445eb19cad504fc663c8894a4b8ad2c2\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$82cf4a0fd82546fec0e453cb163e0b57b514e109\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$05123d0bc673513b0e5ab3de2414f4ca493424ef\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$3d62e89fd9fe82123196169686b7825d33b36c84\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$413228b6beffb528da7ce6c18481e68814727c46\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$74d116fba5fc319cbe4b4ef6fabb137b2ff9e708\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~635 debug messages>

22.28. Executing OPT pass (performing simple optimizations).

22.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~140 debug messages>

22.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~21 debug messages>
Removed a total of 7 cells.

22.28.3. Executing OPT_DFF pass (perform DFF optimizations).
[55%] Inferring Phase 3 completed
Running technical mapping ...
Adding SRST signal on $\SOC.Uart.RX_FIFO.memory$rdreg[0] ($dff) from module top (D = $auto$rtlil.cc:2582:Mux$2684, Q = $\SOC.Uart.RX_FIFO.memory$rdreg[0]$q, rval = 3'000).
Adding SRST signal on $auto$ff.cc:266:slice$2399 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$1879_Y, Q = \ResetBootSystem.counter, rval = 6'000000).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2387 ($sdff) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.

22.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 20 unused cells and 2124 unused wires.
<suppressed ~21 debug messages>

22.28.5. Rerunning OPT passes. (Removed registers in this run.)

22.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

22.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$3499 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$2425 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).

22.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 3 unused cells and 3 unused wires.
<suppressed ~4 debug messages>

22.28.10. Rerunning OPT passes. (Removed registers in this run.)

22.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.28.13. Executing OPT_DFF pass (perform DFF optimizations).

22.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.28.15. Finished fast OPT passes.

22.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
Mapping memory $flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980 in module \top:
  created 16 $dff cells and 0 static cells of width 18.
  read interface: 0 $dff and 15 $mux cells.
  write interface: 0 write mux blocks.

22.30. Executing OPT pass (performing simple optimizations).

22.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$2706: $auto$rtlil.cc:2489:ReduceOr$2700 -> 1'1
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~59 debug messages>

22.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][6]$3544:
      Old ports: A=18'010000010000000000, B=18'010000011000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$3524
      New ports: A=1'0, B=1'1, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$3524 [9]
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$3524 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$3524 [8:0] } = 17'01000001000000000
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][5]$3541:
      Old ports: A=18'000000001010100100, B=18'101000010000000101, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3522
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3522 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3522 [0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3522 [17:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3522 [4:1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3522 [0] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3522 [0] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3522 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3522 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3522 [5] 5'00010 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][4]$3538:
      Old ports: A=18'010000001100000001, B=18'101000010000000100, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3521
      New ports: A=2'01, B=2'10, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3521 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3521 [0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3521 [17:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3521 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3521 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3521 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3521 [2] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3521 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3521 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3521 [0] 6'000000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][3]$3535:
      Old ports: A=18'000000001100000000, B=18'000000000000001000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3519
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3519 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3519 [3] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3519 [17:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3519 [7:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3519 [2:0] } = { 8'00000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3519 [8] 7'0000000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][2]$3532:
      Old ports: A=18'000000100000001000, B=18'000000000000010010, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3518
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3518 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3518 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3518 [17:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3518 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3518 [0] } = { 6'000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3518 [3] 6'000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3518 [1] 2'00 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][1]$3529:
      Old ports: A=18'010000001000000000, B=18'000010000000000010, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3516
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3516 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3516 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3516 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3516 [8:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3516 [0] } = { 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3516 [9] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3516 [1] 11'00000000000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][0]$3526:
      Old ports: A=18'101110000000000000, B=18'010000010000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3515
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3515 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3515 [10] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3515 [17:14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3515 [12:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3515 [9:0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3515 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3515 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3515 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3515 [13] 12'000000000000 }
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$2691:
      Old ports: A={ \SOC.Memory.buffer [31:16] \SOC.Memory.write_data [15:0] }, B=\SOC.Memory.write_data, Y=$auto$rtlil.cc:2582:Mux$2692
      New ports: A=\SOC.Memory.buffer [31:16], B=\SOC.Memory.write_data [31:16], Y=$auto$rtlil.cc:2582:Mux$2692 [31:16]
      New connections: $auto$rtlil.cc:2582:Mux$2692 [15:0] = \SOC.Memory.write_data [15:0]
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$1888: { $flatten\ResetBootSystem.$procmux$1883_CMP $flatten\ResetBootSystem.$procmux$1882_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1891:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$1891_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$1891_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$1891_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1984:
      Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$2427 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$2427 [2]
      New connections: $auto$wreduce.cc:461:run$2427 [1:0] = 2'10
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2005:
      Old ports: A=4'0110, B=12'101101111110, Y=$flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0]
      New ports: A=3'010, B=9'101011110, Y={ $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [3:2] $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [0] }
      New connections: $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [1] = 1'1
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1643: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1664_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1663_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1656_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1655_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1654_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1653_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1652_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1651_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1650_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1649_CMP $auto$opt_reduce.cc:134:opt_pmux$2191 $auto$opt_reduce.cc:134:opt_pmux$2189 $auto$opt_reduce.cc:134:opt_pmux$2187 $auto$opt_reduce.cc:134:opt_pmux$2185 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][7]$3547:
      Old ports: A=18'010000001000000000, B=18'000001000001001000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3525
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3525 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3525 [3] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3525 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3525 [8:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3525 [2:0] } = { 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3525 [9] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3525 [3] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3525 [3] 5'00000 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1923:
      Old ports: A=3'101, B=3'011, Y=$auto$wreduce.cc:461:run$2431 [2:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$2431 [2:1]
      New connections: $auto$wreduce.cc:461:run$2431 [0] = 1'1
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1599:
      Old ports: A={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] }, B={ 27'000000000000000000000000000 \SOC.Core.instruction_register [24:20] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0]
      New ports: A=\SOC.Core.instruction_register [24], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [31:6] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] \SOC.Core.instruction_register [24:20] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1626:
      Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, B={ 19'0000000000000000000 \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0]
      New ports: A=\SOC.Core.instruction_register [31], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [31:14] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Memory.$procmux$1335:
      Old ports: A=\SOC.Memory.buffer, B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7:0] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:0] 24'000000000000000000000000 \SOC.Memory.buffer [7:0] 16'0000000000000000 \SOC.Memory.buffer [15:0] }, Y=\SOC.Bus.slave_0_read_data
      New ports: A=\SOC.Memory.buffer [31:8], B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:8] 40'0000000000000000000000000000000000000000 \SOC.Memory.buffer [15:8] }, Y=\SOC.Bus.slave_0_read_data [31:8]
      New connections: \SOC.Bus.slave_0_read_data [7:0] = \SOC.Memory.buffer [7:0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_rx.$procmux$1169:
      Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$2449 [0] 1'0 $auto$wreduce.cc:461:run$2450 [1:0] 2'01 \SOC.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$2452 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$2449 [0] $auto$wreduce.cc:461:run$2450 [1:0] 1'1 \SOC.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$2452 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$951:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2452 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2452 [0]
      New connections: $auto$wreduce.cc:461:run$2452 [1] = $auto$wreduce.cc:461:run$2452 [0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$1306:
      Old ports: A=3'000, B={ 2'00 \SOC.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$2454 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$2456 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \SOC.Uart.uart_tx_en $auto$wreduce.cc:461:run$2454 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$2456 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$894:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2456 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2456 [0]
      New connections: $auto$wreduce.cc:461:run$2456 [1] = $auto$wreduce.cc:461:run$2456 [0]
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$3523:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$3524, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3525, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3513
      New ports: A={ 2'11 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$3524 [9] 1'0 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3525 [9] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3525 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$3525 [3] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3513 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3513 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3513 [3] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3513 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3513 [15:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3513 [8:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3513 [2:0] } = { 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3513 [3] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3513 [3] 5'00000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$3520:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3521, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3522, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3521 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3521 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3521 [0] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3521 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$3521 [0] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3522 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3522 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3522 [5] 1'1 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$3522 [0] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [17:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [7:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [4:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [10] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [5] 4'0000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$3517:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3518, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3519, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3518 [3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3518 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$3518 [1] }, B={ 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3519 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$3519 [3] 1'0 }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510 [11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510 [17:12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510 [7:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510 [0] } = { 7'0000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510 [8] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510 [1] 2'00 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$3514:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3515, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3516, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3509
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3515 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3515 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3515 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$3515 [10] 2'00 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3516 [9] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3516 [1] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3516 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$3516 [1] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3509 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3509 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3509 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3509 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3509 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3509 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3509 [12:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3509 [8:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3509 [0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3509 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3509 [14] 10'0000000000 }
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$2695:
      Old ports: A=$auto$rtlil.cc:2582:Mux$2692, B={ \SOC.Memory.buffer [31:8] \SOC.Memory.write_data [7:0] }, Y=$auto$rtlil.cc:2582:Mux$2696
      New ports: A={ $auto$rtlil.cc:2582:Mux$2692 [31:16] \SOC.Memory.write_data [15:8] }, B=\SOC.Memory.buffer [31:8], Y=$auto$rtlil.cc:2582:Mux$2696 [31:8]
      New connections: $auto$rtlil.cc:2582:Mux$2696 [7:0] = \SOC.Memory.write_data [7:0]
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1897:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$1891_Y, Y=$flatten\ResetBootSystem.$procmux$1897_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$1891_Y [1], Y=$flatten\ResetBootSystem.$procmux$1897_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$1897_Y [0] = 1'0
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1610:
      Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:20] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] 20'00000000000000000000 \SOC.Core.instruction_register [31:20] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0]
      New ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:25] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] 1'0 \SOC.Core.instruction_register [31:25] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12:5]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [31:13] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] \SOC.Core.instruction_register [24:20] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$3511:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3513, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$3512 [0] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3513 [16] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3513 [10:9] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$3513 [3] 2'00 }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [16:15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [3:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [14:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [7:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [15] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [3] 2'00 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$3508:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3509, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3509 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3509 [14:13] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3509 [10:9] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$3509 [1] }, B={ 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510 [11] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510 [1] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$3510 [1] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [11:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [4:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [7:5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [14] 6'000000 }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$3505:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507, Y={ \SOC.Core.pc_write \SOC.Core.AluInputBMUX.option \SOC.Core.Control_Unit.ir_write \SOC.Bus.read \SOC.Core.MemoryDataMUX.option \SOC.Core.AluInputAMUX.option \SOC.Core.ALU_Control.aluop_in \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond \SOC.Bus.write \SOC.Core.Control_Unit.reg_write \SOC.Core.PCSourceMUX.option [0] \SOC.Core.MemoryAddressMUX.option [0] \SOC.Core.ALU_Control.is_immediate }
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [11:8] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [4:3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$3506 [1] 1'0 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [16:15] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [3:2] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$3507 [0] }, Y={ \SOC.Core.AluInputBMUX.option \SOC.Core.Control_Unit.ir_write \SOC.Bus.read \SOC.Core.MemoryDataMUX.option [0] \SOC.Core.AluInputAMUX.option \SOC.Core.ALU_Control.aluop_in [1] \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond \SOC.Bus.write \SOC.Core.Control_Unit.reg_write \SOC.Core.PCSourceMUX.option [0] \SOC.Core.MemoryAddressMUX.option [0] \SOC.Core.ALU_Control.is_immediate }
      New connections: { \SOC.Core.pc_write \SOC.Core.MemoryDataMUX.option [1] \SOC.Core.ALU_Control.aluop_in [0] } = { \SOC.Core.AluInputBMUX.option [0] \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond }
  Optimizing cells in module \top.
Performed a total of 34 changes.

22.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~15 debug messages>
Removed a total of 5 cells.

22.30.6. Executing OPT_DFF pass (perform DFF optimizations).

22.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 22 unused wires.
<suppressed ~2 debug messages>

22.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~1 debug messages>

22.30.9. Rerunning OPT passes. (Maybe there is more to do..)

22.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~62 debug messages>

22.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.30.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2275 ($sdff) from module top.

22.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

22.30.16. Rerunning OPT passes. (Maybe there is more to do..)

22.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~62 debug messages>

22.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.30.20. Executing OPT_DFF pass (perform DFF optimizations).

22.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
[60%] Tech-Mapping Phase 0 completed

22.30.23. Finished OPT passes. (There is nothing left to do.)

22.31. Executing TECHMAP pass (map to technology primitives).

22.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

22.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

22.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $sdffce.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $dffe.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $logic_not.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux.
Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $sdffe.
Using template $paramod$3111a1a8e90c88cc8c163ba5aed0203d96ddc46d\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $bmux.
Using extmapper simplemap for cells of type $tribuf.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu.
Using template $paramod$41ef080258eed1ff8fcfbb7776f540ab469a3d7b\_80_ecp5_alu for cells of type $alu.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c4ef20b21801b37ea2d65c32a05dfe56e84a870d\_80_ecp5_alu for cells of type $alu.
Using template $paramod$2407ada40cc3dda6c6015be2b49b748cddb5a800\_90_demux for cells of type $demux.
Using template $paramod$19e9557905baa9d3741d0daa66e2ef076e9bab7d\_90_pmux for cells of type $pmux.
Using template $paramod$f1fc4bc1d42e857fca43ce0fdd0da6ff25c612c4\_90_pmux for cells of type $pmux.
Using template $paramod$4d45682f6d5f8751d24fc75184ef72226da353f7\_90_pmux for cells of type $pmux.
Using template $paramod$a13703aa027da371a1931fc542d213d7de559b19\_90_pmux for cells of type $pmux.
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $dlatch.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$56955d0f36f77738c952d3505dc563df3ee11b94\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$a5f0941832cc861549e29ccafffe20bfdf2e5528\_90_pmux for cells of type $pmux.
Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~4187 debug messages>

22.32. Executing OPT pass (performing simple optimizations).

22.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6077 debug messages>

22.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~4284 debug messages>
Removed a total of 1428 cells.

22.32.3. Executing OPT_DFF pass (perform DFF optimizations).

22.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 631 unused cells and 3988 unused wires.
<suppressed ~632 debug messages>

22.32.5. Finished fast OPT passes.

22.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

22.35. Executing TECHMAP pass (map to technology primitives).

22.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

22.35.2. Continuing TECHMAP pass.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_.
No more expansions possible.
<suppressed ~817 debug messages>

22.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~31 debug messages>

22.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

22.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in top.

22.39. Executing ATTRMVCP pass (move or copy attributes).

22.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3995 unused wires.
<suppressed ~1 debug messages>

22.41. Executing TECHMAP pass (map to technology primitives).

22.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

22.41.2. Continuing TECHMAP pass.

22.41.3. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping \$_DLATCH_N_.$ternary$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$22283 ($mux).
Mapping \$_DLATCH_N_.$logic_not$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$22282 ($logic_not).
<suppressed ~4 debug messages>

22.41.4. Executing OPT pass (performing simple optimizations).

22.41.4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.
<suppressed ~1 debug messages>

22.41.4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

22.41.4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.41.4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

22.41.4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

22.41.4.6. Executing OPT_DFF pass (perform DFF optimizations).

22.41.4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..
Removed 1 unused cells and 2 unused wires.
<suppressed ~2 debug messages>

22.41.4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

22.41.4.9. Rerunning OPT passes. (Maybe there is more to do..)

22.41.4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.41.4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

22.41.4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

22.41.4.13. Executing OPT_DFF pass (perform DFF optimizations).

22.41.4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..

22.41.4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

22.41.4.16. Finished OPT passes. (There is nothing left to do.)
Using template \$_DLATCH_N_ for cells of type $_DLATCH_N_.
No more expansions possible.
<suppressed ~4 debug messages>

22.42. Executing ABC9 pass.

22.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.3. Executing PROC pass (convert processes to netlists).

22.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22387'.
Cleaned up 1 empty switch.

22.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22388 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.3.4. Executing PROC_INIT pass (extract init attributes).

22.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22388'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22386_EN[3:0]$22394
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22386_DATA[3:0]$22392
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22386_ADDR[3:0]$22393
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22387'.

22.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22371_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22380_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22384_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22376_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22385_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22377_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22382_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22374_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22375_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22370_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22379_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22372_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22381_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22383_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22378_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22373_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22386_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22388'.
  created $dff cell `$procdff$22438' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22386_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22388'.
  created $dff cell `$procdff$22439' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22386_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22388'.
  created $dff cell `$procdff$22440' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22387'.
  created direct connection (no actual register cell created).

22.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22412'.
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22388'.
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22387'.
Cleaned up 1 empty switch.

22.42.3.12. Executing OPT_EXPR pass (perform const folding).

22.42.4. Executing PROC pass (convert processes to netlists).

22.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22458'.
Cleaned up 1 empty switch.

22.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22459 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.4.4. Executing PROC_INIT pass (extract init attributes).

22.42.4.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22459'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22457_EN[3:0]$22465
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22457_DATA[3:0]$22464
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22457_ADDR[3:0]$22463
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22458'.

22.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22450_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22449_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22447_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22448_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22452_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22443_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22445_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22455_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22454_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22453_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22444_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22441_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22442_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22456_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22451_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22446_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22457_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22459'.
  created $dff cell `$procdff$22509' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22457_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22459'.
  created $dff cell `$procdff$22510' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22457_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22459'.
  created $dff cell `$procdff$22511' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22458'.
  created direct connection (no actual register cell created).

22.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22483'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22459'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22458'.
Cleaned up 1 empty switch.

22.42.4.12. Executing OPT_EXPR pass (perform const folding).

22.42.5. Executing PROC pass (convert processes to netlists).

22.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22529'.
Cleaned up 1 empty switch.

22.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22530 in module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.5.4. Executing PROC_INIT pass (extract init attributes).

22.42.5.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
Creating decoders for process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22530'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22528_EN[3:0]$22536
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22528_DATA[3:0]$22534
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22528_ADDR[3:0]$22535
Creating decoders for process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22529'.

22.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.\i' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22518_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22520_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22517_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22525_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22526_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22523_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22521_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22527_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22522_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22513_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22516_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22515_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22524_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22519_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22514_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22512_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22528_DATA' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22530'.
  created $dff cell `$procdff$22580' with positive edge clock.
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22528_ADDR' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22530'.
  created $dff cell `$procdff$22581' with positive edge clock.
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22528_EN' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22530'.
  created $dff cell `$procdff$22582' with positive edge clock.
Creating register for signal `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.\muxwre' using process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22529'.
  created direct connection (no actual register cell created).

22.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22554'.
Found and cleaned up 1 empty switch in `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22530'.
Removing empty process `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22529'.
Cleaned up 1 empty switch.

22.42.5.12. Executing OPT_EXPR pass (perform const folding).

22.42.6. Executing PROC pass (convert processes to netlists).

22.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22600'.
Cleaned up 1 empty switch.

22.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22601 in module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.6.4. Executing PROC_INIT pass (extract init attributes).

22.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
Creating decoders for process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22601'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22599_EN[3:0]$22605
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22599_DATA[3:0]$22607
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22599_ADDR[3:0]$22606
Creating decoders for process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22600'.

22.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.\i' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22583_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22585_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22589_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22595_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22591_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22590_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22587_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22597_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22596_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22592_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22598_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22593_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22586_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22584_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22594_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22588_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22599_EN' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22601'.
  created $dff cell `$procdff$22651' with positive edge clock.
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22599_ADDR' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22601'.
  created $dff cell `$procdff$22652' with positive edge clock.
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22599_DATA' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22601'.
  created $dff cell `$procdff$22653' with positive edge clock.
Creating register for signal `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22600'.
  created direct connection (no actual register cell created).

22.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22625'.
Found and cleaned up 1 empty switch in `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22601'.
Removing empty process `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22600'.
Cleaned up 1 empty switch.

22.42.6.12. Executing OPT_EXPR pass (perform const folding).

22.42.7. Executing PROC pass (convert processes to netlists).

22.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22671'.
Cleaned up 1 empty switch.

22.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22672 in module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.7.4. Executing PROC_INIT pass (extract init attributes).

22.42.7.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
Creating decoders for process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22672'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22670_EN[3:0]$22677
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22670_DATA[3:0]$22676
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22670_ADDR[3:0]$22678
Creating decoders for process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22671'.

22.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.\i' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22659_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22655_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22665_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22661_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22660_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22657_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22667_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22666_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22663_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22669_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22668_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22662_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22656_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22654_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22664_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22658_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22670_DATA' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22672'.
  created $dff cell `$procdff$22722' with positive edge clock.
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22670_EN' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22672'.
  created $dff cell `$procdff$22723' with positive edge clock.
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22670_ADDR' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22672'.
  created $dff cell `$procdff$22724' with positive edge clock.
Creating register for signal `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22671'.
  created direct connection (no actual register cell created).

22.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22696'.
Found and cleaned up 1 empty switch in `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22672'.
Removing empty process `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22671'.
Cleaned up 1 empty switch.

22.42.7.12. Executing OPT_EXPR pass (perform const folding).

22.42.8. Executing PROC pass (convert processes to netlists).

22.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22742'.
Cleaned up 1 empty switch.

22.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22743 in module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.8.4. Executing PROC_INIT pass (extract init attributes).

22.42.8.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.8.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
Creating decoders for process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22743'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22741_EN[3:0]$22749
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22741_DATA[3:0]$22747
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22741_ADDR[3:0]$22748
Creating decoders for process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22742'.

22.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.\i' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22725_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22730_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22729_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22736_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22735_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22726_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22727_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22732_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22733_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22738_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22739_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22737_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22731_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22740_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22734_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22728_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22741_DATA' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22743'.
  created $dff cell `$procdff$22793' with positive edge clock.
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22741_ADDR' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22743'.
  created $dff cell `$procdff$22794' with positive edge clock.
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22741_EN' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22743'.
  created $dff cell `$procdff$22795' with positive edge clock.
Creating register for signal `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.\muxwre' using process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22742'.
  created direct connection (no actual register cell created).

22.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22767'.
Found and cleaned up 1 empty switch in `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22743'.
Removing empty process `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22742'.
Cleaned up 1 empty switch.

22.42.8.12. Executing OPT_EXPR pass (perform const folding).

22.42.9. Executing PROC pass (convert processes to netlists).

22.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22813'.
Cleaned up 1 empty switch.

22.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22814 in module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.9.4. Executing PROC_INIT pass (extract init attributes).

22.42.9.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.9.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
Creating decoders for process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22814'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22812_EN[3:0]$22820
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22812_DATA[3:0]$22818
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22812_ADDR[3:0]$22819
Creating decoders for process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22813'.

22.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.\i' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22808_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22807_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22801_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22800_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22799_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22806_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22805_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22797_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22811_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22802_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22803_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22809_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22810_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22804_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22798_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22796_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22812_DATA' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22814'.
  created $dff cell `$procdff$22864' with positive edge clock.
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22812_ADDR' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22814'.
  created $dff cell `$procdff$22865' with positive edge clock.
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22812_EN' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22814'.
  created $dff cell `$procdff$22866' with positive edge clock.
Creating register for signal `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.\muxwre' using process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22813'.
  created direct connection (no actual register cell created).

22.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22838'.
Found and cleaned up 1 empty switch in `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22814'.
Removing empty process `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22813'.
Cleaned up 1 empty switch.

22.42.9.12. Executing OPT_EXPR pass (perform const folding).

22.42.10. Executing PROC pass (convert processes to netlists).

22.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22884'.
Cleaned up 1 empty switch.

22.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22885 in module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.10.4. Executing PROC_INIT pass (extract init attributes).

22.42.10.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.10.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
Creating decoders for process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22885'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22883_EN[3:0]$22891
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22883_DATA[3:0]$22890
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22883_ADDR[3:0]$22889
Creating decoders for process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22884'.

22.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.\i' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22867_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22869_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22870_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22871_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22875_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22876_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22877_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22881_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22882_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22872_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22873_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22878_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22879_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22880_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22874_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22868_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22883_ADDR' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22885'.
  created $dff cell `$procdff$22935' with positive edge clock.
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22883_DATA' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22885'.
  created $dff cell `$procdff$22936' with positive edge clock.
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22883_EN' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22885'.
  created $dff cell `$procdff$22937' with positive edge clock.
Creating register for signal `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.\muxwre' using process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22884'.
  created direct connection (no actual register cell created).

22.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22909'.
Found and cleaned up 1 empty switch in `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22885'.
Removing empty process `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22884'.
Cleaned up 1 empty switch.

22.42.10.12. Executing OPT_EXPR pass (perform const folding).

22.42.11. Executing PROC pass (convert processes to netlists).

22.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22955'.
Cleaned up 1 empty switch.

22.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22956 in module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.11.4. Executing PROC_INIT pass (extract init attributes).

22.42.11.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.11.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
Creating decoders for process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22956'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22954_EN[3:0]$22962
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22954_DATA[3:0]$22961
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22954_ADDR[3:0]$22960
Creating decoders for process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22955'.

22.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.\i' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22953_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22940_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22938_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22945_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22947_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22946_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22951_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22952_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22942_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22943_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22948_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22949_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22939_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22941_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22950_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$22944_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22954_ADDR' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22956'.
  created $dff cell `$procdff$23006' with positive edge clock.
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22954_DATA' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22956'.
  created $dff cell `$procdff$23007' with positive edge clock.
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$22954_EN' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22956'.
  created $dff cell `$procdff$23008' with positive edge clock.
Creating register for signal `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22955'.
  created direct connection (no actual register cell created).

22.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$22980'.
Found and cleaned up 1 empty switch in `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$22956'.
Removing empty process `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$22955'.
Cleaned up 1 empty switch.

22.42.11.12. Executing OPT_EXPR pass (perform const folding).

22.42.12. Executing PROC pass (convert processes to netlists).

22.42.12.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23026'.
Cleaned up 1 empty switch.

22.42.12.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23027 in module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.12.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.12.4. Executing PROC_INIT pass (extract init attributes).

22.42.12.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.12.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.12.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
Creating decoders for process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23027'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23025_EN[3:0]$23032
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23025_DATA[3:0]$23033
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23025_ADDR[3:0]$23031
Creating decoders for process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23026'.

22.42.12.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.12.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23021_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23016_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23024_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23017_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.\i' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23019_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23018_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23013_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23023_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23012_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23010_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23009_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23022_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23015_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23011_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23020_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23014_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23025_ADDR' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23027'.
  created $dff cell `$procdff$23077' with positive edge clock.
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23025_EN' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23027'.
  created $dff cell `$procdff$23078' with positive edge clock.
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23025_DATA' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23027'.
  created $dff cell `$procdff$23079' with positive edge clock.
Creating register for signal `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.\muxwre' using process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23026'.
  created direct connection (no actual register cell created).

22.42.12.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.12.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23051'.
Found and cleaned up 1 empty switch in `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23027'.
Removing empty process `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23026'.
Cleaned up 1 empty switch.

22.42.12.12. Executing OPT_EXPR pass (perform const folding).

22.42.13. Executing PROC pass (convert processes to netlists).

22.42.13.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23097'.
Cleaned up 1 empty switch.

22.42.13.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23098 in module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.13.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.13.4. Executing PROC_INIT pass (extract init attributes).

22.42.13.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.13.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.13.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
Creating decoders for process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23098'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23096_EN[3:0]$23102
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23096_DATA[3:0]$23103
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23096_ADDR[3:0]$23104
Creating decoders for process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23097'.

22.42.13.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.13.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23095_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23083_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23093_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23082_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.\i' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23094_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23089_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23092_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23091_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23087_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23086_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23085_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23081_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23080_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23088_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23090_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23084_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23096_EN' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23098'.
  created $dff cell `$procdff$23148' with positive edge clock.
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23096_DATA' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23098'.
  created $dff cell `$procdff$23149' with positive edge clock.
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23096_ADDR' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23098'.
  created $dff cell `$procdff$23150' with positive edge clock.
Creating register for signal `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.\muxwre' using process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23097'.
  created direct connection (no actual register cell created).

22.42.13.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.13.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23122'.
Found and cleaned up 1 empty switch in `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23098'.
Removing empty process `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23097'.
Cleaned up 1 empty switch.

22.42.13.12. Executing OPT_EXPR pass (perform const folding).

22.42.14. Executing PROC pass (convert processes to netlists).

22.42.14.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23168'.
Cleaned up 1 empty switch.

22.42.14.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23169 in module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.14.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.14.4. Executing PROC_INIT pass (extract init attributes).

22.42.14.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.14.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.14.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
Creating decoders for process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23169'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23167_EN[3:0]$23175
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23167_DATA[3:0]$23174
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23167_ADDR[3:0]$23173
Creating decoders for process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23168'.

22.42.14.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.14.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23159_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23164_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23158_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23153_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23163_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.\i' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23161_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23157_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23162_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23156_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23155_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23151_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23165_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23152_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23166_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23160_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23154_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23167_ADDR' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23169'.
  created $dff cell `$procdff$23219' with positive edge clock.
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23167_DATA' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23169'.
  created $dff cell `$procdff$23220' with positive edge clock.
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23167_EN' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23169'.
  created $dff cell `$procdff$23221' with positive edge clock.
Creating register for signal `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.\muxwre' using process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23168'.
  created direct connection (no actual register cell created).

22.42.14.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.14.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23193'.
Found and cleaned up 1 empty switch in `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23169'.
Removing empty process `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23168'.
Cleaned up 1 empty switch.

22.42.14.12. Executing OPT_EXPR pass (perform const folding).

22.42.15. Executing PROC pass (convert processes to netlists).

22.42.15.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23239'.
Cleaned up 1 empty switch.

22.42.15.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23240 in module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.15.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.15.4. Executing PROC_INIT pass (extract init attributes).

22.42.15.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.15.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.15.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
Creating decoders for process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23240'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23238_EN[3:0]$23244
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23238_DATA[3:0]$23245
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23238_ADDR[3:0]$23246
Creating decoders for process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23239'.

22.42.15.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.15.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23235_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23234_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23229_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23228_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23223_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23237_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.\i' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23233_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23226_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23225_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23227_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23231_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23232_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23236_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23230_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23224_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23222_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23238_EN' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23240'.
  created $dff cell `$procdff$23290' with positive edge clock.
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23238_DATA' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23240'.
  created $dff cell `$procdff$23291' with positive edge clock.
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23238_ADDR' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23240'.
  created $dff cell `$procdff$23292' with positive edge clock.
Creating register for signal `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.\muxwre' using process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23239'.
  created direct connection (no actual register cell created).

22.42.15.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.15.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23264'.
Found and cleaned up 1 empty switch in `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23240'.
Removing empty process `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23239'.
Cleaned up 1 empty switch.

22.42.15.12. Executing OPT_EXPR pass (perform const folding).

22.42.16. Executing PROC pass (convert processes to netlists).

22.42.16.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23310'.
Cleaned up 1 empty switch.

22.42.16.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23311 in module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.16.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.16.4. Executing PROC_INIT pass (extract init attributes).

22.42.16.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.16.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.16.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
Creating decoders for process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23311'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23309_EN[3:0]$23315
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23309_DATA[3:0]$23316
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23309_ADDR[3:0]$23317
Creating decoders for process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23310'.

22.42.16.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.16.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23293_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23308_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23307_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23303_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23302_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23301_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23297_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23296_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23295_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.\i' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23305_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23304_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23299_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23298_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23306_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23300_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23294_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23309_EN' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23311'.
  created $dff cell `$procdff$23361' with positive edge clock.
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23309_DATA' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23311'.
  created $dff cell `$procdff$23362' with positive edge clock.
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23309_ADDR' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23311'.
  created $dff cell `$procdff$23363' with positive edge clock.
Creating register for signal `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.\muxwre' using process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23310'.
  created direct connection (no actual register cell created).

22.42.16.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.16.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23335'.
Found and cleaned up 1 empty switch in `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23311'.
Removing empty process `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23310'.
Cleaned up 1 empty switch.

22.42.16.12. Executing OPT_EXPR pass (perform const folding).

22.42.17. Executing PROC pass (convert processes to netlists).

22.42.17.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23381'.
Cleaned up 1 empty switch.

22.42.17.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23382 in module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.17.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.17.4. Executing PROC_INIT pass (extract init attributes).

22.42.17.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.17.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.17.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
Creating decoders for process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23382'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23380_EN[3:0]$23388
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23380_DATA[3:0]$23386
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23380_ADDR[3:0]$23387
Creating decoders for process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23381'.

22.42.17.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.17.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.\i' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23375_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23374_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23369_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23379_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23368_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23378_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23377_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23373_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23372_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23371_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23367_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23366_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23365_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23364_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23376_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23370_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23380_DATA' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23382'.
  created $dff cell `$procdff$23432' with positive edge clock.
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23380_ADDR' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23382'.
  created $dff cell `$procdff$23433' with positive edge clock.
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23380_EN' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23382'.
  created $dff cell `$procdff$23434' with positive edge clock.
Creating register for signal `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.\muxwre' using process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23381'.
  created direct connection (no actual register cell created).

22.42.17.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.17.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23406'.
Found and cleaned up 1 empty switch in `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23382'.
Removing empty process `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23381'.
Cleaned up 1 empty switch.

22.42.17.12. Executing OPT_EXPR pass (perform const folding).

22.42.18. Executing PROC pass (convert processes to netlists).

22.42.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23452'.
Cleaned up 1 empty switch.

22.42.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23453 in module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.18.4. Executing PROC_INIT pass (extract init attributes).

22.42.18.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.18.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
Creating decoders for process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23453'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23451_EN[3:0]$23458
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23451_DATA[3:0]$23459
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23451_ADDR[3:0]$23457
Creating decoders for process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23452'.

22.42.18.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.18.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.\i' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23450_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23445_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23444_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23439_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23449_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23438_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23441_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23442_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23437_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23443_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23436_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23447_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23435_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23448_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23446_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23440_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23451_ADDR' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23453'.
  created $dff cell `$procdff$23503' with positive edge clock.
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23451_EN' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23453'.
  created $dff cell `$procdff$23504' with positive edge clock.
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23451_DATA' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23453'.
  created $dff cell `$procdff$23505' with positive edge clock.
Creating register for signal `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.\muxwre' using process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23452'.
  created direct connection (no actual register cell created).

22.42.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23477'.
Found and cleaned up 1 empty switch in `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23453'.
Removing empty process `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23452'.
Cleaned up 1 empty switch.

22.42.18.12. Executing OPT_EXPR pass (perform const folding).

22.42.19. Executing PROC pass (convert processes to netlists).

22.42.19.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23523'.
Cleaned up 1 empty switch.

22.42.19.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23524 in module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.19.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.19.4. Executing PROC_INIT pass (extract init attributes).

22.42.19.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.19.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.19.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
Creating decoders for process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23524'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23522_EN[3:0]$23528
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23522_DATA[3:0]$23529
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23522_ADDR[3:0]$23530
Creating decoders for process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23523'.

22.42.19.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.19.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23517_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23519_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23508_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.\i' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23518_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23513_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23509_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23514_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23511_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23512_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23507_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23506_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23521_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23520_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23515_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23516_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23510_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23522_EN' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23524'.
  created $dff cell `$procdff$23574' with positive edge clock.
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23522_DATA' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23524'.
  created $dff cell `$procdff$23575' with positive edge clock.
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23522_ADDR' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23524'.
  created $dff cell `$procdff$23576' with positive edge clock.
Creating register for signal `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.\muxwre' using process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23523'.
  created direct connection (no actual register cell created).

22.42.19.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.19.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23548'.
Found and cleaned up 1 empty switch in `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23524'.
Removing empty process `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23523'.
Cleaned up 1 empty switch.

22.42.19.12. Executing OPT_EXPR pass (perform const folding).

22.42.20. Executing PROC pass (convert processes to netlists).

22.42.20.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23594'.
Cleaned up 1 empty switch.

22.42.20.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23595 in module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.20.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.20.4. Executing PROC_INIT pass (extract init attributes).

22.42.20.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.20.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.20.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
Creating decoders for process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23595'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23593_EN[3:0]$23599
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23593_DATA[3:0]$23600
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23593_ADDR[3:0]$23601
Creating decoders for process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23594'.

22.42.20.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.20.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.\i' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23591_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23584_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23585_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23579_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23590_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23589_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23578_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23588_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23587_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23583_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23582_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23581_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23577_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23592_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23586_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23580_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23593_EN' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23595'.
  created $dff cell `$procdff$23645' with positive edge clock.
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23593_DATA' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23595'.
  created $dff cell `$procdff$23646' with positive edge clock.
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23593_ADDR' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23595'.
  created $dff cell `$procdff$23647' with positive edge clock.
Creating register for signal `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23594'.
  created direct connection (no actual register cell created).

22.42.20.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.20.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23619'.
Found and cleaned up 1 empty switch in `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23595'.
Removing empty process `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23594'.
Cleaned up 1 empty switch.

22.42.20.12. Executing OPT_EXPR pass (perform const folding).

22.42.21. Executing PROC pass (convert processes to netlists).

22.42.21.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23665'.
Cleaned up 1 empty switch.

22.42.21.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23666 in module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.21.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.21.4. Executing PROC_INIT pass (extract init attributes).

22.42.21.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.21.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.21.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
Creating decoders for process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23666'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23664_EN[3:0]$23671
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23664_DATA[3:0]$23670
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23664_ADDR[3:0]$23672
Creating decoders for process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23665'.

22.42.21.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.21.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.\i' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23660_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23655_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23661_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23654_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23649_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23663_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23659_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23658_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23657_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23653_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23652_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23651_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23662_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23656_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23650_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23648_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23664_DATA' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23666'.
  created $dff cell `$procdff$23716' with positive edge clock.
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23664_EN' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23666'.
  created $dff cell `$procdff$23717' with positive edge clock.
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23664_ADDR' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23666'.
  created $dff cell `$procdff$23718' with positive edge clock.
Creating register for signal `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.\muxwre' using process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23665'.
  created direct connection (no actual register cell created).

22.42.21.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.21.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23690'.
Found and cleaned up 1 empty switch in `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23666'.
Removing empty process `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23665'.
Cleaned up 1 empty switch.

22.42.21.12. Executing OPT_EXPR pass (perform const folding).

22.42.22. Executing PROC pass (convert processes to netlists).

22.42.22.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23736'.
Cleaned up 1 empty switch.

22.42.22.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23737 in module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.22.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.22.4. Executing PROC_INIT pass (extract init attributes).

22.42.22.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.22.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.22.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
Creating decoders for process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23737'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23735_EN[3:0]$23741
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23735_DATA[3:0]$23743
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23735_ADDR[3:0]$23742
Creating decoders for process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23736'.

22.42.22.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.22.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.\i' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23729_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23734_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23720_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23721_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23725_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23726_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23727_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23731_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23732_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23722_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23733_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23723_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23728_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23719_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23730_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23724_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23735_EN' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23737'.
  created $dff cell `$procdff$23787' with positive edge clock.
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23735_ADDR' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23737'.
  created $dff cell `$procdff$23788' with positive edge clock.
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23735_DATA' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23737'.
  created $dff cell `$procdff$23789' with positive edge clock.
Creating register for signal `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.\muxwre' using process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23736'.
  created direct connection (no actual register cell created).

22.42.22.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.22.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23761'.
Found and cleaned up 1 empty switch in `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23737'.
Removing empty process `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23736'.
Cleaned up 1 empty switch.

22.42.22.12. Executing OPT_EXPR pass (perform const folding).

22.42.23. Executing PROC pass (convert processes to netlists).

22.42.23.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23807'.
Cleaned up 1 empty switch.

22.42.23.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23808 in module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.23.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.23.4. Executing PROC_INIT pass (extract init attributes).

22.42.23.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.23.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.23.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
Creating decoders for process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23808'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23806_EN[3:0]$23814
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23806_DATA[3:0]$23812
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23806_ADDR[3:0]$23813
Creating decoders for process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23807'.

22.42.23.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.23.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.\i' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23803_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23798_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23791_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23792_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23802_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23793_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23796_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23801_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23797_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23790_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23804_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23794_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23799_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23805_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23800_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23795_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23806_DATA' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23808'.
  created $dff cell `$procdff$23858' with positive edge clock.
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23806_ADDR' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23808'.
  created $dff cell `$procdff$23859' with positive edge clock.
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23806_EN' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23808'.
  created $dff cell `$procdff$23860' with positive edge clock.
Creating register for signal `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.\muxwre' using process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23807'.
  created direct connection (no actual register cell created).

22.42.23.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.23.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23832'.
Found and cleaned up 1 empty switch in `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23808'.
Removing empty process `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23807'.
Cleaned up 1 empty switch.

22.42.23.12. Executing OPT_EXPR pass (perform const folding).

22.42.24. Executing PROC pass (convert processes to netlists).

22.42.24.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23878'.
Cleaned up 1 empty switch.

22.42.24.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23879 in module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.24.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.24.4. Executing PROC_INIT pass (extract init attributes).

22.42.24.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.24.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.24.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
Creating decoders for process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23879'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23877_EN[3:0]$23885
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23877_DATA[3:0]$23884
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23877_ADDR[3:0]$23883
Creating decoders for process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23878'.

22.42.24.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.24.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.\i' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23876_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23869_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23873_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23868_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23867_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23866_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23862_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23861_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23871_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23865_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23872_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23863_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23874_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23870_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23864_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23875_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23877_ADDR' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23879'.
  created $dff cell `$procdff$23929' with positive edge clock.
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23877_DATA' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23879'.
  created $dff cell `$procdff$23930' with positive edge clock.
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23877_EN' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23879'.
  created $dff cell `$procdff$23931' with positive edge clock.
Creating register for signal `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.\muxwre' using process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23878'.
  created direct connection (no actual register cell created).

22.42.24.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.24.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23903'.
Found and cleaned up 1 empty switch in `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23879'.
Removing empty process `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23878'.
Cleaned up 1 empty switch.

22.42.24.12. Executing OPT_EXPR pass (perform const folding).

22.42.25. Executing PROC pass (convert processes to netlists).

22.42.25.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23949'.
Cleaned up 1 empty switch.

22.42.25.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23950 in module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.25.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.25.4. Executing PROC_INIT pass (extract init attributes).

22.42.25.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.25.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.25.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
Creating decoders for process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23950'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23948_EN[3:0]$23955
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23948_DATA[3:0]$23954
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23948_ADDR[3:0]$23956
Creating decoders for process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23949'.

22.42.25.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.25.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23937_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.\i' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23943_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23944_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23934_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23945_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23935_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23940_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23941_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23939_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23946_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23947_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23938_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23933_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23942_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23936_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23932_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23948_DATA' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23950'.
  created $dff cell `$procdff$24000' with positive edge clock.
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23948_EN' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23950'.
  created $dff cell `$procdff$24001' with positive edge clock.
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23948_ADDR' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23950'.
  created $dff cell `$procdff$24002' with positive edge clock.
Creating register for signal `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.\muxwre' using process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23949'.
  created direct connection (no actual register cell created).

22.42.25.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.25.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23974'.
Found and cleaned up 1 empty switch in `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23950'.
Removing empty process `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23949'.
Cleaned up 1 empty switch.

22.42.25.12. Executing OPT_EXPR pass (perform const folding).

22.42.26. Executing PROC pass (convert processes to netlists).

22.42.26.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24020'.
Cleaned up 1 empty switch.

22.42.26.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24021 in module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.26.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.26.4. Executing PROC_INIT pass (extract init attributes).

22.42.26.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.26.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.26.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
Creating decoders for process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24021'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24019_EN[3:0]$24026
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24019_DATA[3:0]$24025
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24019_ADDR[3:0]$24027
Creating decoders for process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24020'.

22.42.26.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.26.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.\i' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24005_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24017_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24013_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24014_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24004_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24015_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24011_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24016_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24008_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24009_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24003_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24007_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24018_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24012_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24006_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24010_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24019_DATA' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24021'.
  created $dff cell `$procdff$24071' with positive edge clock.
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24019_EN' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24021'.
  created $dff cell `$procdff$24072' with positive edge clock.
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24019_ADDR' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24021'.
  created $dff cell `$procdff$24073' with positive edge clock.
Creating register for signal `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.\muxwre' using process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24020'.
  created direct connection (no actual register cell created).

22.42.26.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.26.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24045'.
Found and cleaned up 1 empty switch in `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24021'.
Removing empty process `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24020'.
Cleaned up 1 empty switch.

22.42.26.12. Executing OPT_EXPR pass (perform const folding).

22.42.27. Executing PROC pass (convert processes to netlists).

22.42.27.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24091'.
Cleaned up 1 empty switch.

22.42.27.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24092 in module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.27.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.27.4. Executing PROC_INIT pass (extract init attributes).

22.42.27.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.27.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.27.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
Creating decoders for process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24092'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24090_EN[3:0]$24098
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24090_DATA[3:0]$24097
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24090_ADDR[3:0]$24096
Creating decoders for process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24091'.

22.42.27.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.27.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24074_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.\i' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24084_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24079_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24083_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24075_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24076_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24080_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24081_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24085_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24086_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24077_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24087_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24082_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24078_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24088_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24089_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24090_ADDR' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24092'.
  created $dff cell `$procdff$24142' with positive edge clock.
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24090_DATA' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24092'.
  created $dff cell `$procdff$24143' with positive edge clock.
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24090_EN' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24092'.
  created $dff cell `$procdff$24144' with positive edge clock.
Creating register for signal `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.\muxwre' using process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24091'.
  created direct connection (no actual register cell created).

22.42.27.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.27.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24116'.
Found and cleaned up 1 empty switch in `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24092'.
Removing empty process `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24091'.
Cleaned up 1 empty switch.

22.42.27.12. Executing OPT_EXPR pass (perform const folding).

22.42.28. Executing PROC pass (convert processes to netlists).

22.42.28.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24162'.
Cleaned up 1 empty switch.

22.42.28.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24163 in module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.28.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.28.4. Executing PROC_INIT pass (extract init attributes).

22.42.28.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.28.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.28.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
Creating decoders for process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24163'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24161_EN[3:0]$24168
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24161_DATA[3:0]$24169
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24161_ADDR[3:0]$24167
Creating decoders for process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24162'.

22.42.28.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.28.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.\i' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24160_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24154_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24148_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24149_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24153_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24145_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24150_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24151_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24155_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24156_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24146_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24157_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24147_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24152_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24158_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24159_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24161_ADDR' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24163'.
  created $dff cell `$procdff$24213' with positive edge clock.
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24161_EN' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24163'.
  created $dff cell `$procdff$24214' with positive edge clock.
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24161_DATA' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24163'.
  created $dff cell `$procdff$24215' with positive edge clock.
Creating register for signal `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24162'.
  created direct connection (no actual register cell created).

22.42.28.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.28.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24187'.
Found and cleaned up 1 empty switch in `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24163'.
Removing empty process `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24162'.
Cleaned up 1 empty switch.

22.42.28.12. Executing OPT_EXPR pass (perform const folding).

22.42.29. Executing SCC pass (detecting logic loops).
Found an SCC: $techmap$auto$ff.cc:266:slice$8061.$auto$simplemap.cc:267:simplemap_mux$22285
Found an SCC: $techmap$auto$ff.cc:266:slice$8060.$auto$simplemap.cc:267:simplemap_mux$22285
Found an SCC: $techmap$auto$ff.cc:266:slice$8059.$auto$simplemap.cc:267:simplemap_mux$22285
Found an SCC: $techmap$auto$ff.cc:266:slice$8058.$auto$simplemap.cc:267:simplemap_mux$22285
Found an SCC: $auto$ff.cc:266:slice$6125 $auto$simplemap.cc:126:simplemap_reduce$6246 $auto$simplemap.cc:126:simplemap_reduce$6231 $auto$simplemap.cc:38:simplemap_not$12923 $auto$ff.cc:266:slice$6124 $auto$opt_expr.cc:613:replace_const_cells$21168 $auto$ff.cc:266:slice$6127 $auto$simplemap.cc:75:simplemap_bitop$12933 $auto$simplemap.cc:196:simplemap_lognot$6251 $auto$simplemap.cc:126:simplemap_reduce$6249 $auto$simplemap.cc:126:simplemap_reduce$6247 $auto$opt_expr.cc:613:replace_const_cells$21204 $auto$simplemap.cc:267:simplemap_mux$12921 $auto$simplemap.cc:126:simplemap_reduce$13017 $auto$simplemap.cc:126:simplemap_reduce$13014 $auto$simplemap.cc:126:simplemap_reduce$13022 $auto$simplemap.cc:126:simplemap_reduce$13019 $auto$simplemap.cc:75:simplemap_bitop$12932 $auto$simplemap.cc:267:simplemap_mux$6212 $auto$simplemap.cc:225:simplemap_logbin$6221 $auto$simplemap.cc:196:simplemap_lognot$6236 $auto$simplemap.cc:126:simplemap_reduce$6234 $auto$simplemap.cc:126:simplemap_reduce$6232 $auto$ff.cc:266:slice$6126 $auto$simplemap.cc:126:simplemap_reduce$4257 $auto$simplemap.cc:126:simplemap_reduce$4255 $auto$simplemap.cc:225:simplemap_logbin$6171 $auto$simplemap.cc:196:simplemap_lognot$6181 $auto$simplemap.cc:126:simplemap_reduce$6179 $auto$opt_expr.cc:613:replace_const_cells$21202 $auto$simplemap.cc:267:simplemap_mux$12922
Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$21206 $auto$ff.cc:266:slice$5984 $auto$simplemap.cc:38:simplemap_not$11219 $auto$ff.cc:266:slice$5986 $auto$ff.cc:266:slice$5989 $auto$simplemap.cc:126:simplemap_reduce$6108 $auto$simplemap.cc:38:simplemap_not$11221 $auto$ff.cc:266:slice$5988 $auto$simplemap.cc:126:simplemap_reduce$6107 $auto$simplemap.cc:126:simplemap_reduce$6080 $auto$simplemap.cc:38:simplemap_not$11220 $auto$ff.cc:266:slice$5987 $auto$simplemap.cc:38:simplemap_not$11223 $auto$ff.cc:266:slice$5990 $auto$simplemap.cc:126:simplemap_reduce$6082 $auto$simplemap.cc:126:simplemap_reduce$6112 $auto$simplemap.cc:126:simplemap_reduce$6109 $auto$simplemap.cc:38:simplemap_not$11224 $auto$ff.cc:266:slice$5991 $auto$ff.cc:266:slice$5992 $auto$simplemap.cc:196:simplemap_lognot$6118 $auto$simplemap.cc:126:simplemap_reduce$6116 $auto$simplemap.cc:126:simplemap_reduce$6114 $auto$simplemap.cc:126:simplemap_reduce$6111 $auto$simplemap.cc:126:simplemap_reduce$6106 $auto$simplemap.cc:126:simplemap_reduce$6084 $auto$simplemap.cc:126:simplemap_reduce$6079 $auto$ff.cc:266:slice$5985 $auto$simplemap.cc:167:logic_reduce$4236 $auto$simplemap.cc:225:simplemap_logbin$6063 $auto$simplemap.cc:225:simplemap_logbin$6064 $auto$simplemap.cc:196:simplemap_lognot$6091 $auto$simplemap.cc:126:simplemap_reduce$6089 $auto$simplemap.cc:126:simplemap_reduce$6087 $auto$simplemap.cc:126:simplemap_reduce$6085 $auto$simplemap.cc:126:simplemap_reduce$6081 $auto$simplemap.cc:38:simplemap_not$11222
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$4435 $auto$simplemap.cc:38:simplemap_not$4144 $auto$simplemap.cc:38:simplemap_not$15116 $auto$ff.cc:266:slice$3658 $auto$ff.cc:479:convert_ce_over_srst$21570 $auto$ff.cc:266:slice$3659 $auto$ff.cc:479:convert_ce_over_srst$21572 $auto$simplemap.cc:126:simplemap_reduce$4138 $auto$ff.cc:266:slice$3657 $auto$ff.cc:479:convert_ce_over_srst$21568 $auto$simplemap.cc:38:simplemap_not$15114 $auto$ff.cc:266:slice$3656 $auto$ff.cc:479:convert_ce_over_srst$21566 $auto$simplemap.cc:38:simplemap_not$4051 $auto$alumacc.cc:485:replace_alu$2555.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$2555.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$2555.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$4141 $auto$simplemap.cc:126:simplemap_reduce$4137 $auto$simplemap.cc:38:simplemap_not$20096 $auto$ff.cc:266:slice$3655 $auto$ff.cc:479:convert_ce_over_srst$21564 $auto$simplemap.cc:126:simplemap_reduce$4413 $auto$simplemap.cc:75:simplemap_bitop$4135 $auto$simplemap.cc:126:simplemap_reduce$4437 $auto$simplemap.cc:126:simplemap_reduce$4434 $auto$simplemap.cc:126:simplemap_reduce$4143 $auto$simplemap.cc:126:simplemap_reduce$4139 $auto$simplemap.cc:38:simplemap_not$20101 $auto$ff.cc:266:slice$3660 $auto$ff.cc:479:convert_ce_over_srst$21574 $auto$simplemap.cc:126:simplemap_reduce$4389 $auto$simplemap.cc:126:simplemap_reduce$4387
Found an SCC: $auto$simplemap.cc:38:simplemap_not$12860 $auto$ff.cc:266:slice$6135 $auto$opt_expr.cc:613:replace_const_cells$21396 $auto$ff.cc:266:slice$6128 $auto$ff.cc:266:slice$6130 $auto$simplemap.cc:126:simplemap_reduce$6266 $auto$ff.cc:266:slice$6129 $auto$simplemap.cc:126:simplemap_reduce$6271 $auto$simplemap.cc:126:simplemap_reduce$6267 $auto$simplemap.cc:38:simplemap_not$12856 $auto$ff.cc:266:slice$6131 $auto$simplemap.cc:126:simplemap_reduce$6269 $auto$simplemap.cc:38:simplemap_not$12859 $auto$ff.cc:266:slice$6134 $auto$ff.cc:266:slice$6132 $auto$ff.cc:266:slice$6133 $auto$ff.cc:266:slice$6136 $auto$simplemap.cc:126:simplemap_reduce$4284 $auto$simplemap.cc:196:simplemap_lognot$6278 $auto$simplemap.cc:126:simplemap_reduce$6276 $auto$simplemap.cc:126:simplemap_reduce$6274 $auto$simplemap.cc:126:simplemap_reduce$6272 $auto$simplemap.cc:126:simplemap_reduce$6268 $auto$simplemap.cc:38:simplemap_not$12857
Found 8 SCCs in module top.
Found 8 SCCs.

22.42.30. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.31. Executing PROC pass (convert processes to netlists).

22.42.31.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

22.42.31.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

22.42.31.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

22.42.31.4. Executing PROC_INIT pass (extract init attributes).

22.42.31.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.31.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

22.42.31.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

22.42.31.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.31.9. Executing PROC_DFF pass (convert process syncs to FFs).

22.42.31.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.31.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

22.42.31.12. Executing OPT_EXPR pass (perform const folding).

22.42.32. Executing TECHMAP pass (map to technology primitives).

22.42.32.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

22.42.32.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~212 debug messages>

22.42.33. Executing OPT pass (performing simple optimizations).

22.42.33.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
Optimizing module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
Optimizing module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
Optimizing module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
Optimizing module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
Optimizing module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
Optimizing module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
Optimizing module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
Optimizing module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
Optimizing module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
Optimizing module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
Optimizing module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
Optimizing module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
Optimizing module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
Optimizing module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
Optimizing module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
Optimizing module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
Optimizing module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
Optimizing module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.
Optimizing module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
Optimizing module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
Optimizing module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
Optimizing module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
Optimizing module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.

22.42.33.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

22.42.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.42.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.
Performed a total of 0 changes.

22.42.33.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

22.42.33.6. Executing OPT_DFF pass (perform DFF optimizations).

22.42.33.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4..

22.42.33.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
Optimizing module $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
Optimizing module $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
Optimizing module $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
Optimizing module $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
Optimizing module $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
Optimizing module $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
Optimizing module $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
Optimizing module $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.
Optimizing module $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
Optimizing module $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
Optimizing module $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
Optimizing module $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
Optimizing module $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
Optimizing module $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
Optimizing module $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
Optimizing module $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
Optimizing module $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
Optimizing module $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
Optimizing module $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
Optimizing module $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
Optimizing module $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.

22.42.33.9. Finished OPT passes. (There is nothing left to do.)

22.42.34. Executing TECHMAP pass (map to technology primitives).

22.42.34.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

22.42.34.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4 for cells of type $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
Using template $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4 for cells of type $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
Using template $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4 for cells of type $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
Using template $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4 for cells of type $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
Using template $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4 for cells of type $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.
Using template $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4 for cells of type $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
Using template $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4 for cells of type $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
Using template $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4 for cells of type $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
Using template $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4 for cells of type $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
Using template $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4 for cells of type $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.
Using template $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4 for cells of type $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
Using template $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4 for cells of type $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
Using template $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4 for cells of type $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
Using template $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4 for cells of type $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
Using template $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4 for cells of type $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
Using template $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4 for cells of type $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
Using template $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4 for cells of type $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
Using template $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4 for cells of type $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
Using template $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4 for cells of type $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
Using template $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4 for cells of type $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
Using template $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4 for cells of type $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
Using template $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4 for cells of type $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
Using template $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4 for cells of type $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
Using template $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4 for cells of type $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~320 debug messages>

22.42.35. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

22.42.36. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

22.42.37. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.38. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

22.42.39. Executing TECHMAP pass (map to technology primitives).

22.42.39.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

22.42.39.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $or.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~251 debug messages>

22.42.40. Executing OPT pass (performing simple optimizations).

22.42.40.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~18 debug messages>

22.42.40.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

22.42.40.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.42.40.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.42.40.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.42.40.6. Executing OPT_DFF pass (perform DFF optimizations).

22.42.40.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

22.42.40.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.42.40.9. Rerunning OPT passes. (Maybe there is more to do..)

22.42.40.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.42.40.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.42.40.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.42.40.13. Executing OPT_DFF pass (perform DFF optimizations).

22.42.40.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.42.40.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.42.40.16. Finished OPT passes. (There is nothing left to do.)

22.42.41. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

22.42.42. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 4011 cells with 24012 new cells, skipped 3322 cells.
  replaced 3 cell types:
    1355 $_OR_
      94 $_XOR_
    2562 $_MUX_
  not replaced 59 cell types:
      30 $scopeinfo
     363 $_NOT_
    1264 $_AND_
       6 $_TBUF_
       1 $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4
       1 $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4
       1 $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4
     702 TRELLIS_FF
       1 $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4
       1 $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4
       1 $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4
       1 $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4
       1 $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4
       1 $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4
       1 $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4
       1 $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4
       1 $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4
       1 $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4
     252 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4
       1 $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4
       1 $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4
       1 $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4
       1 $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp
      16 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp
      16 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4
       1 $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp
     252 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
       1 $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4
       1 $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4
       1 $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4
       1 $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4
       1 $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4
       1 $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4
       1 $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4
       1 $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp
     372 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
       1 $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp
       1 $__ABC9_SCC_BREAKER
       1 $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp

22.42.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.42.3. Executing XAIGER backend.

****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

source run.tcl
# read_verilog "main.v"
<suppressed ~11 debug messages>
Extracted 10587 AND gates and 30468 wires from module `top' to a netlist network with 1887 inputs and 733 outputs.

22.42.42.4. Executing ABC9_EXE pass (technology mapping using ABC9).

22.42.42.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   1887/    733  and =    9193  lev =   46 (5.17)  mem = 0.27 MB  box = 664  bb = 292
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   1887/    733  and =   12597  lev =   62 (3.15)  mem = 0.30 MB  ch = 1425  box = 602  bb = 292
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   60. Obj =  140. Set =  636. CutMin = no
ABC: Node =   12597.  Ch =  1271.  Total mem =    3.34 MB. Peak cut mem =    0.28 MB.
ABC: P:  Del = 6939.00.  Ar =   11740.0.  Edge =    14342.  Cut =   175064.  T =     0.04 sec
ABC: P:  Del = 6898.00.  Ar =   12362.0.  Edge =    14809.  Cut =   175992.  T =     0.05 sec
ABC: P:  Del = 6898.00.  Ar =    7040.0.  Edge =    13101.  Cut =   367829.  T =     0.09 sec
ABC: F:  Del = 6898.00.  Ar =    4690.0.  Edge =    11589.  Cut =   316983.  T =     0.08 sec
ABC: A:  Del = 6898.00.  Ar =    4118.0.  Edge =    10136.  Cut =   296447.  T =     0.12 sec
ABC: A:  Del = 6898.00.  Ar =    4057.0.  Edge =    10101.  Cut =   318979.  T =     0.12 sec
ABC: Total time =     0.50 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   1887/    733  and =    8605  lev =   40 (3.32)  mem = 0.25 MB  box = 602  bb = 292
ABC: Mapping (K=7)  :  lut =   2585  edge =   10045  lev =   14 (1.46)  levB =   41  mem = 0.13 MB
ABC: LUT = 2585 : 2=259 10.0 %  3=648 25.1 %  4=1124 43.5 %  5=359 13.9 %  6=73 2.8 %  7=122 4.7 %  Ave = 3.89
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 4.71 seconds, total: 4.71 seconds

22.42.42.6. Executing AIGER frontend.
<suppressed ~5314 debug messages>
Removed 11754 unused cells and 23048 unused wires.

22.42.42.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     2610
ABC RESULTS:   $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:      252
ABC RESULTS:   $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells:       16
ABC RESULTS:   $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      310
ABC RESULTS:   $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:           input signals:      337
ABC RESULTS:          output signals:      131
Removing temp directory.

22.42.43. Executing TECHMAP pass (map to technology primitives).

22.42.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

22.42.43.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4 for cells of type $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4.
Using template $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$598ce05fbd37fda01d101fd892de3eb358d9030a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4 for cells of type $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4.
Using template $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$87af9f65391a9c7ce2f35545a9a53dd5d7380fa9\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4 for cells of type $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4.
Using template $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$766efdf0501607f5e6ecbdedf2c7fde9a94e17aa\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4 for cells of type $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4.
Using template $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$381f808ef29a7c65dfad9f9e1e8feeda302271da\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4 for cells of type $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4.
Using template $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4 for cells of type $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4.
Using template $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4 for cells of type $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4.
Using template $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4 for cells of type $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4.
Using template $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4 for cells of type $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4.
Using template $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4 for cells of type $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4.
Using template $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4 for cells of type $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4.
Using template $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4 for cells of type $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4.
Using template $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4 for cells of type $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4.
Using template $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4 for cells of type $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4.
Using template $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4 for cells of type $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4.
Using template $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4 for cells of type $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4.
Using template $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4 for cells of type $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4.
Using template $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4 for cells of type $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4.
Using template $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4 for cells of type $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4.
Using template $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4 for cells of type $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4.
Using template $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4 for cells of type $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4.
Using template $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4 for cells of type $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4.
Using template $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4 for cells of type $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4.
Using template $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4 for cells of type $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4.
Using template $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$3309091ca88249c445a5f94b6f088cdc1eb868a6\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$5916f855b650b7013038fefba9684572c8d4de97\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$eedbc18eacbaed098ee523909435286fcf027a52\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$b4bc996bd4a735c5ef8e51c6b0ad6053b9058eff\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$e1da505f92887594bd5563495c38a6327e1fcf07\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$00e85defa119d0774f6bf9400906f8cdc6ae5ee4\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$6bada7a0c6ef941ac68caf12c410a076242d3d5c\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$283afb6b17035820eaab9102c1c16e32f4f68760\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$660170032aee85531a5c0ffee10c6c1371e076ab\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$9f485c16d89188be0b17fc08f32db69cd0def929\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$25310fd776b08deeb7587ef3c2abbf354a987588\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$788e6d943c5aaa2e18a07bf4dd60b1d3dd04e14c\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$592b353a3566933225eeed97359281426bd39ec0\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$6fb47d1aaaef8fbd1a9baec297b90fb7f6c0874b\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$309f683a9939f2cdb60e3e0c1a14eccc70517117\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$ea201580bd49b6cbe90f9c035681dc57af1c87c9\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$c903eb84eee9f27a8c5d16e6ed13f2c0afe01ef4\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d387786f1c1232a861a1abfa48e4752dc47c4d16\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$67cb7fa26e940e53e06bb51018fbde2e9a166e28\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$1b2f2fd4b0e2e37c3784ce108bc56711a65c53df\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001000 for cells of type $__ABC9_SCC_BREAKER.
No more expansions possible.
<suppressed ~964 debug messages>
Removed 325 unused cells and 36554 unused wires.

22.43. Executing TECHMAP pass (map to technology primitives).

22.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

22.43.2. Continuing TECHMAP pass.
Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$6e46ec5a196ba1a24b8e69ab094cadc07c13ac1f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$633ae299df262467973f925d88826d85d4a12fb4\$lut for cells of type $lut.
Using template $paramod$052ca015f1400ebf950f85d5f181f7a5865c336c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$d2d50fced6e06d123321409eee0a12cd3b79fb8c\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$ccd3e15dc00d71b9284dff48e88ccef5be7362c8\$lut for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod$b97ff285770a798ba31d840db2ce52fdc36910ae\$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut.
Using template $paramod$fb7bbfbe62f17d1abd6f8eaee546f5a966c46c29\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$df5c8730c0a53792c3f54c2192a2221c27162fb5\$lut for cells of type $lut.
Using template $paramod$b18a3edb490ff3a49fefc94182a05f36efbdbba2\$lut for cells of type $lut.
Using template $paramod$56d1a78632b07077a5fde81946aeef0a806ae664\$lut for cells of type $lut.
Using template $paramod$6a41bdd44258a75b5d355eacbb4989b590f9a720\$lut for cells of type $lut.
Using template $paramod$73168779d124d0e86f3f4da4f351086f6646bb40\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$e0b4add7490d32b93d44906688455f3c7729d0a3\$lut for cells of type $lut.
Using template $paramod$877859204cc06b766f4cb38f89dea559af1e3734\$lut for cells of type $lut.
Using template $paramod$05402c79be82cc63a2eaed19f98c2af9df54d241\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod$63114da772fb28945ba24699e32f1e30ca7142f4\$lut for cells of type $lut.
Using template $paramod$c20bb0ec9b7ffe048b440bc5b52865dca055e17d\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod$ec6bb3db7c80c492ce6110718f99328a4ab7f019\$lut for cells of type $lut.
Using template $paramod$717dae7a4b4d98fb824634d546043d165e3cf20a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$23ba03b3f106a8b0f20f18bfebd862b419996ddc\$lut for cells of type $lut.
Using template $paramod$7202672b7332febf25cdbe5424cf24593f5449be\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011111 for cells of type $lut.
Using template $paramod$5400b6807adef39a9693b2fbff17f8c0ab116b66\$lut for cells of type $lut.
Using template $paramod$ce44877a8aba311086973ef3ef648b154684306e\$lut for cells of type $lut.
Using template $paramod$f28a4401e00366386f5c9da01093cb438d2ef37a\$lut for cells of type $lut.
Using template $paramod$173257c402a3003de28bff8c2a49d358e5f4004c\$lut for cells of type $lut.
Using template $paramod$9c6e6a10ea00e5b0682f6243b802d7839a398197\$lut for cells of type $lut.
Using template $paramod$a743caf801766df40bcc22d49baa12a0bdc2f7fe\$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$bde6c96e44b0f8e6d9db97eafdf28d77ceaa9a96\$lut for cells of type $lut.
Using template $paramod$4e45a60feb8bbe3cabd280417c9ffbefad6f6ef3\$lut for cells of type $lut.
Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut.
Using template $paramod$0fe8fbf45fc9407b7d9f6cdf3b662e78e91e9b55\$lut for cells of type $lut.
Using template $paramod$d7a87ca2ecbda1d431eb014d7af4b3bc1067b28d\$lut for cells of type $lut.
Using template $paramod$08466811901d5e03ed77c75ae1ee4f324a7c22b7\$lut for cells of type $lut.
Using template $paramod$b2b362fa866354d5936edc937d825ffc48772447\$lut for cells of type $lut.
Using template $paramod$3cc80e2a63856e1f46075e358d1c072c35cc4ca8\$lut for cells of type $lut.
Using template $paramod$f9c55c999dcf6c87c8508a041c8b2e28738fa25d\$lut for cells of type $lut.
Using template $paramod$ee3ba3939f6ccdb74bf420a252d58cdb86511937\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod$c3602c5fd8b16f64e0416a32652da97d6f1efbf9\$lut for cells of type $lut.
Using template $paramod$b2b8f14c1dc45737f0261c4484079d734f30d41f\$lut for cells of type $lut.
Using template $paramod$c19ac226b2328a9dc00b76bc0a6d1e025c6f4fca\$lut for cells of type $lut.
Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut.
Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut.
Using template $paramod$38400b76de2b00d7d5f8f09de118b82fd1b8be0a\$lut for cells of type $lut.
Using template $paramod$48f2db66c872c1f64faeb797c1719c912a15a86f\$lut for cells of type $lut.
Using template $paramod$35e780f9333f3666b86f6bdeb5e6c5f65477f87e\$lut for cells of type $lut.
Using template $paramod$1df6d41de86e48fa0e114cfe35ac61195abc3952\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut.
Using template $paramod$cf48b29332194ed05b4e63a678acb5324e9f6648\$lut for cells of type $lut.
Using template $paramod$83c1b6108170249166239e09804c5f4542556524\$lut for cells of type $lut.
Using template $paramod$5748393b45210a1c62ecef4cc17023a4fc1dc09a\$lut for cells of type $lut.
Using template $paramod$88af067e5d7a87415e359e1eb0f295b619d047cd\$lut for cells of type $lut.
Using template $paramod$db8547c0ce3f404162c765a55df5db805b4e10bc\$lut for cells of type $lut.
Using template $paramod$7aa8140c7d6de3160b21e7ff84e0f93f69f7fcc6\$lut for cells of type $lut.
Using template $paramod$2e6f7636c4430e71acfafacf89034290c19a68d2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut.
Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$b8113752b08bd47f69a1c8c2bca1cfb157e800c9\$lut for cells of type $lut.
Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290\$lut for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
Using template $paramod$9b444505f3a8d856cee3b7ca9d0a263c9da4fb6e\$lut for cells of type $lut.
Using template $paramod$2e0fd651ab536ddf2afd30af26b1a2532281e83a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$ae6a86c125757108324af5e1de1be0d15f94f76e\$lut for cells of type $lut.
Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
Using template $paramod$a18efd9245448b0a198b87f7e710a6a1c17ab9de\$lut for cells of type $lut.
Using template $paramod$3b374b0454c507d1efadee363d480c52c3b3f58f\$lut for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod$c35ad3063d5038410210ddc72c1fd5fed46413b4\$lut for cells of type $lut.
Using template $paramod$7f88ae8b0ca78f7b736f446522956805c49fb79f\$lut for cells of type $lut.
Using template $paramod$6fc23ce09f2013cb9de2228dbcdda21841008f92\$lut for cells of type $lut.
Using template $paramod$0331e023d83b8009e60defb446ce9fa640b122c7\$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod$bb59da4933702bb82ef3226e214fb972ba5089dd\$lut for cells of type $lut.
Using template $paramod$fbace1c5af8b8efd1c625bd9d47d8b080aa709a4\$lut for cells of type $lut.
Using template $paramod$f62bf7b9bf368c5a044dd284e6192cdfb023ea0f\$lut for cells of type $lut.
Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod$26d876869d6ab003366d0470e095daef2ccfcbd7\$lut for cells of type $lut.
Using template $paramod$4c0221505c29b55a66f4801128a7e9ab143964dc\$lut for cells of type $lut.
Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut.
Using template $paramod$8c11a155773d2e4aba9b1022fc059160b55313e8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$7ab9990e447a92f0817942e45bfb8b646848e027\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$98da953dac84989c1dec711ba4d909885d65c4dd\$lut for cells of type $lut.
Using template $paramod$d08ae3e2fee668f1a68bd32fd012d46d229cb782\$lut for cells of type $lut.
Using template $paramod$c79aec6bf66334ca918f85c196e004c918c371ef\$lut for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod$7e9df0afb32b76fe5fce0691b8752aca650057fa\$lut for cells of type $lut.
Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0\$lut for cells of type $lut.
Using template $paramod$2b47d6f0645f6c0eac4d0fed1097d370ff2ad02d\$lut for cells of type $lut.
Using template $paramod$aa398ad9f45fcec98f268eb4eebf93ce5a3a396a\$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod$70a934594406e8042bf2854c778fef542ef3ea5f\$lut for cells of type $lut.
Using template $paramod$58d49ffbb43fac74e1430ef7dfa6e760bbd204ab\$lut for cells of type $lut.
Using template $paramod$f7a897257decedfb6cc642e53d65fef7fc0df390\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut.
Using template $paramod$fdb7d2f78b1b1d86177579c82e917e4e8af6f77d\$lut for cells of type $lut.
Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc\$lut for cells of type $lut.
Using template $paramod$c8c2f45d9083177b70913b41d4370d01f048f309\$lut for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut.
Using template $paramod$16894c241be5ea1f024e9339dea788b4dbe184ae\$lut for cells of type $lut.
Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut.
Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut.
Using template $paramod$8d6b1427c6cef4584f3b541903b0dee036dd5787\$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod$f8e8e1e1389c03e530e143893bb2f66bbf48cb04\$lut for cells of type $lut.
Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut.
Using template $paramod$723be7177967d6866729df0ff463a602326a012e\$lut for cells of type $lut.
Using template $paramod$ec77ef2f39e0c5347eaada9711f26fca6a276050\$lut for cells of type $lut.
Using template $paramod$47a326ee296feaca60c97add5a2f7670de259bd9\$lut for cells of type $lut.
Using template $paramod$302ba22a83dfb50189674147c5c2626b9e9dab7e\$lut for cells of type $lut.
Using template $paramod$c039f15592dbb863a55cd28cd138649990f0aecd\$lut for cells of type $lut.
Using template $paramod$d2cb21e990ed09a64a77c05577a016c435aa6c26\$lut for cells of type $lut.
Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut.
Using template $paramod$bf6add2967325c59b1cc62393b93e39c101df9d8\$lut for cells of type $lut.
Using template $paramod$df29fe9e6d6d694a9cc5697e4251bf7d8cd4d8e4\$lut for cells of type $lut.
Using template $paramod$f546bd96bcec6e3bf1b78bdea64b0f5bbbaff6df\$lut for cells of type $lut.
Using template $paramod$4db3f0d067a6794efd5979ea33ffc0ce06e2e75c\$lut for cells of type $lut.
Using template $paramod$d9c249f7cd5fb5f45e81da04b06adf97422cf801\$lut for cells of type $lut.
Using template $paramod$ea718eeb98c809ba5abcd0d342cca6190319badd\$lut for cells of type $lut.
Using template $paramod$e445d7d281fdedd2d7ecb859493aac14908829c6\$lut for cells of type $lut.
Using template $paramod$6fc2d22b16acbc3c0d1ab4810a22084b2df32ef5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut.
Using template $paramod$be95f3a2132281eadd1adcfe6229e43dbc3353c9\$lut for cells of type $lut.
Using template $paramod$e0a16b39d62021fbd2d1c105eda1b9c3b86f8b30\$lut for cells of type $lut.
Using template $paramod$acf008c194939dd533849530b1ab63c5c671b3d9\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut.
Using template $paramod$f672f1e5ea7eaf40630014635549af40fc023a51\$lut for cells of type $lut.
Using template $paramod$77b67ef20c955093353b18505577135db4a47988\$lut for cells of type $lut.
Using template $paramod$791ae37bef671b724edae9f13d094dc39cd7c8cb\$lut for cells of type $lut.
Using template $paramod$3e7360796ac608ec9e808c79d6b1f4bc43c69d15\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod$a05170b3f2d3fcb0bf88d37e810984e864962880\$lut for cells of type $lut.
Using template $paramod$1ae2b86b41d612949835304cb76e044b333c87cd\$lut for cells of type $lut.
Using template $paramod$924b39a5781143b3d97abceead32dfebbce1809b\$lut for cells of type $lut.
Using template $paramod$e96913eb14d58c1ec1047a1c7e88dc30cc0422b6\$lut for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut.
Using template $paramod$3936055e449a2cdc57e98561af0e93c9694640dd\$lut for cells of type $lut.
Using template $paramod$96f192fe57fb80f8bbb71e5e3be3610ca5a5c1e7\$lut for cells of type $lut.
Using template $paramod$3ec6ca53c095953c6afa3941bf19e515191d6f97\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod$41dc53b6a844fec3122a407b3df5a74e50a81c22\$lut for cells of type $lut.
Using template $paramod$47d363ae7b1a0e81207e02fe31af85b6bf36a2ac\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod$e4b832d686d12318ec0715f027fe549b42e45c20\$lut for cells of type $lut.
Using template $paramod$75ae9627805e0c99d176bdce0ae8ff0c02687aab\$lut for cells of type $lut.
Using template $paramod$682dcf7a44e09cdf417bc55247ac658426f4c8e6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut.
Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut.
Using template $paramod$e50929688d8319f8cd7bdd627065cd59d2e91fe4\$lut for cells of type $lut.
Using template $paramod$d8119e7cf18bdd1d72e1822e569d9c40a2fc5848\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod$f109125ffdede8321ac65719b1066c75ff1eaef0\$lut for cells of type $lut.
Using template $paramod$193d365ba3260f56de4ca734b1cedcf9dc72302b\$lut for cells of type $lut.
Using template $paramod$56c6fc98268f6966dd23dcb4af9b8f5298fa7ead\$lut for cells of type $lut.
Using template $paramod$28a43eafd9c70d95e52b2418cf601e2e6b0411d3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$240e171f8bae87a2fe4bee672a3055fa35afe320\$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$18b66a2dc66be2a0d172c3d50ba03932f5924e22\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$2ca5a8bf2a853a223fe0e0148e443d1b7e1e37b1\$lut for cells of type $lut.
Using template $paramod$3f9a3800e34bd795630a4eaf44b2e1d4a7f48a74\$lut for cells of type $lut.
Using template $paramod$5b4991ef8e215d9f18839630c2afa21273bf9421\$lut for cells of type $lut.
Using template $paramod$21a1ca6f9f5c15b304c8c46ce6cda8b91e063cf1\$lut for cells of type $lut.
Using template $paramod$6e3a03c79073e44642e8ed2dab4ee82dfd40dfba\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$4b9b235bc4444ff899bef0c648e4109b26737f1a\$lut for cells of type $lut.
Using template $paramod$7a73f9756d5c153bcd3667a54c2eeb22386fe779\$lut for cells of type $lut.
Using template $paramod$3fccf73a6622f7944be221edcc506b675d995c35\$lut for cells of type $lut.
Using template $paramod$bd47da135cd12bfe4c19544ec47f66e7653b78d9\$lut for cells of type $lut.
Using template $paramod$a81cf453a316218febe7a33c0cf3157f69dfa7dc\$lut for cells of type $lut.
Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut.
Using template $paramod$1ec3fb8fd1fa98216cb96b4422de32c4ba5f6c9c\$lut for cells of type $lut.
Using template $paramod$60b99ddfae8ffcebbb1fe7f9e676a60f7472edd5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut.
Using template $paramod$c064d9f267b09049d631f66733af1b91c12aa819\$lut for cells of type $lut.
Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut.
Using template $paramod$29e6d4598488760861f6b73d2b7f65cb302fdcde\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
Using template $paramod$858b99bd4565f7bb7e8795cb31e914dcba0acf94\$lut for cells of type $lut.
Using template $paramod$4173305553201c5217b90f49a21a6e867b6c27f9\$lut for cells of type $lut.
Using template $paramod$f8569ddbb66107feb983739693963bb01d3743c0\$lut for cells of type $lut.
Using template $paramod$eaddf175cbf0f357c5cc21e4dcb779376e653604\$lut for cells of type $lut.
Using template $paramod$ea8c3614309befced1c4cfc4249e324e2d77ca4c\$lut for cells of type $lut.
Using template $paramod$4d5484c3a11571ca87761881538ce835bb16c82a\$lut for cells of type $lut.
Using template $paramod$8e7b1ec7df4c8852d827365421a6d41e55bd7752\$lut for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$e6062a78edaf68ec0dbea59d4c8352dcb2ce0366\$lut for cells of type $lut.
Using template $paramod$2b73665e68c50148227a7aa3d8edf599547c15fa\$lut for cells of type $lut.
Using template $paramod$0e7ce19e5da99c6675c7a5220f7cc55270b24ac0\$lut for cells of type $lut.
Using template $paramod$7a9b7d7d96d5349b2a3f800b325795fd17e50692\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut.
Using template $paramod$39825c5ed3d135e502be79829033166f1762d78b\$lut for cells of type $lut.
Using template $paramod$f24ba3ced4b870f8e829f5ac5a8af88573350e6f\$lut for cells of type $lut.
Using template $paramod$e8ba44e4a3ee29c32776f6151b0293be3e5fa416\$lut for cells of type $lut.
Using template $paramod$08c74d7002e4f691d402539d3a18282d00068c65\$lut for cells of type $lut.
Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut.
Using template $paramod$5c76169916ad2852767adcbddee054887cf9226f\$lut for cells of type $lut.
Using template $paramod$6d64ca8087b2277f29d14a24ca6148e7bee3bdb7\$lut for cells of type $lut.
Using template $paramod$793fc28cf61120083daef76d0ad6adfe307204e0\$lut for cells of type $lut.
Using template $paramod$183ec76ed3429a430a8be24b57f3de734985f568\$lut for cells of type $lut.
Using template $paramod$32abbd1d449a67fb913b4733374e345d4c17175b\$lut for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut.
Using template $paramod$ac9e3968766d438b96ef7a04264cc79d386f7658\$lut for cells of type $lut.
Using template $paramod$3b56205e0e57b3ea26d80fc7983017f83663129e\$lut for cells of type $lut.
Using template $paramod$7c085cdbf0919cd3ad402d9495d97f0d71e4db93\$lut for cells of type $lut.
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$6e4a86e6f1a5dc8f826898a131e83cdba4a4fc9e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut.
Using template $paramod$d80c9b99dacb354fa564a6fcc23ca30753bf6623\$lut for cells of type $lut.
Using template $paramod$9268d3e71d862575019400bdb92f213f3c7800df\$lut for cells of type $lut.
Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e\$lut for cells of type $lut.
Using template $paramod$023d9d13c9ddd8e6cbda8fa49753038bbbacbfa4\$lut for cells of type $lut.
Using template $paramod$f00c0376cdf8518a9288594305173c177a0a27e2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut.
Using template $paramod$a849ee1488f722579445e96622b562c1f7e4892a\$lut for cells of type $lut.
Using template $paramod$7b88379b9b1290ff52d08a7a46291c233168d810\$lut for cells of type $lut.
Using template $paramod$91fea5a86bb871ddff3e42ed708d9d17d58909a2\$lut for cells of type $lut.
Using template $paramod$9e1755e3954600257bb9b9ab192e2c0243b0f35a\$lut for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$3c113f47a14d3df8f2933a6990f1690802de34db\$lut for cells of type $lut.
Using template $paramod$dd9047df8afc1543e47f4200533bb1ad5f56e5fc\$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$f258f431a7c2fc52205873e71cd6683fdc689824\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut.
Using template $paramod$6d05ee5be4fbc817e6482b590e1831ddde15ffbe\$lut for cells of type $lut.
Using template $paramod$256f3f936b752cf569dca900ae92c3ac452c7e57\$lut for cells of type $lut.
Using template $paramod$94cc9dc7ba20eb6ef27973e1d776ca04cbc15deb\$lut for cells of type $lut.
Using template $paramod$e8eec22f7ab1c445e827b93eab3af19e4901a17c\$lut for cells of type $lut.
Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4\$lut for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut.
Using template $paramod$2d52a1d6cf603c98ba7b908cd4e344a0536dbeca\$lut for cells of type $lut.
Using template $paramod$abd231a9afd33693694c463e09ff8fa65f6852cf\$lut for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$fd5f2940fdf150ba6a50d81069ec7f6163ced647\$lut for cells of type $lut.
Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut.
Using template $paramod$0b411b7d1762b79400c7b7e65303823d9a001f59\$lut for cells of type $lut.
Using template $paramod$93ad38b3182088363c1d57e8aced3320193160f8\$lut for cells of type $lut.
Using template $paramod$51307cdec77060d17363ea3d60427c9afef1ddc2\$lut for cells of type $lut.
Using template $paramod$ca009e911508f27903ef81bdd82bfd594b87e190\$lut for cells of type $lut.
Using template $paramod$695ac4bb7ce2388a8f35ce70ce66ecb0c4b116e3\$lut for cells of type $lut.
Using template $paramod$6382f7860648fdb6f8a8dc690c25a62882cc501b\$lut for cells of type $lut.
Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut.
Using template $paramod$98183b99bd47ccfeaad74233c7680ec0f898f2bf\$lut for cells of type $lut.
Using template $paramod$932c11a3bc9d7be3a59b6ef1077a519829f68519\$lut for cells of type $lut.
Using template $paramod$c8ae41cb26add4dd428560b3921241f1a4e3f96e\$lut for cells of type $lut.
Using template $paramod$6565e92242a21f5338d449de809baa175c228bcf\$lut for cells of type $lut.
Using template $paramod$30ccc2d02d561628bd3e8ba21431cf11015685a5\$lut for cells of type $lut.
Using template $paramod$a48d96b3084901aac1f541d9be59ab6aad37df36\$lut for cells of type $lut.
Using template $paramod$5d9d4826b4537254130d485441e860419b94471b\$lut for cells of type $lut.
Using template $paramod$891991ae1dfac12f87edb9dbdb503babd1fae1a1\$lut for cells of type $lut.
Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514\$lut for cells of type $lut.
Using template $paramod$3a313ff02d51d1203c8a57fd50d2cde2804e4da1\$lut for cells of type $lut.
Using template $paramod$eed9c772f48174b821d5da17f5569e9e4d05ed0a\$lut for cells of type $lut.
Using template $paramod$97bfd0f207e3cd11e81dc81c48f8e4fa7fc28966\$lut for cells of type $lut.
Using template $paramod$99bea6b1a6bfc821c80186f7c0bda101c86a5f38\$lut for cells of type $lut.
Using template $paramod$440c55e9b86a4d19d2d9af4513ac1f3c626292af\$lut for cells of type $lut.
Using template $paramod$31387621d1610a0290872bbf4d90a41c51f62d2e\$lut for cells of type $lut.
Using template $paramod$afbb78ea2f898aa3cffa65de18f43b6b53d33ce1\$lut for cells of type $lut.
Using template $paramod$d37d41a2c800c320b9c689e7a39b8112b7b9b133\$lut for cells of type $lut.
Using template $paramod$757c055b2d591f99a56beeb4bd1bdff266f67334\$lut for cells of type $lut.
Using template $paramod$81f38dbe34c0131668a5f4192c3c2c07e8338073\$lut for cells of type $lut.
Using template $paramod$dad840480f91b70228c2a78ee1410000f2c8899f\$lut for cells of type $lut.
Using template $paramod$e8ac95798b71c13c567fa6ba269261811f4a3442\$lut for cells of type $lut.
Using template $paramod$6023c671e114c4eb0467aa8a0b08e183f33ec2fd\$lut for cells of type $lut.
Using template $paramod$1f2c31d6f9d5076de53559ae8a054e1c27e3a8e2\$lut for cells of type $lut.
Using template $paramod$8833253c105c1f3ff9a03a20302d6d0a2f4d9c5b\$lut for cells of type $lut.
Using template $paramod$5afdc7428159757eedf89ce514f7efa32b31c8e7\$lut for cells of type $lut.
Using template $paramod$89ca3723ebb4dfdb3c4024f3f04b784a3e88f188\$lut for cells of type $lut.
Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut.
Using template $paramod$1c06568dc8dcaed2cf74acfa7f8e37c7cbb3da0f\$lut for cells of type $lut.
Using template $paramod$c386cd9f25d73bb5d158b73cec1ee0ebc10a8383\$lut for cells of type $lut.
Using template $paramod$36e7cbd3745d1b2929f2c4c704d52f177ee43c3b\$lut for cells of type $lut.
Using template $paramod$4d1533dad4814c51bde53f9a378e78c03dd47a9f\$lut for cells of type $lut.
Using template $paramod$8504d86f1088c038cefc453338e6ce07c755faf4\$lut for cells of type $lut.
Using template $paramod$c4a57735f68dea791563158e71e652a9ee523b9b\$lut for cells of type $lut.
Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut.
Using template $paramod$5b5abc946fe8633f86011bdbfff6ace0c780305a\$lut for cells of type $lut.
Using template $paramod$511751daf715d05fd95961e12a405417b374e12a\$lut for cells of type $lut.
Using template $paramod$04378ff5de74dcc5e8256236add5995200f72e4d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut.
Using template $paramod$e174607312e7b90c79c85571daf8b9fa2341a07d\$lut for cells of type $lut.
Using template $paramod$72148f3545efac6f48701d6c21ae5eeb7a5f865b\$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod$40f50322426372d948aaadc2f14dc77fbf5a9200\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut.
Using template $paramod$d0e42eec83ea592bf45e9ec906447f1ed04bd355\$lut for cells of type $lut.
Using template $paramod$d9922e15eb5da1acc26e937540cc16b16c2ad42c\$lut for cells of type $lut.
Using template $paramod$8075729953f49b6cb1b4d863b2fb20da9818d304\$lut for cells of type $lut.
Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut.
Using template $paramod$729ae2031cbf0cda63bd85f6a99c83a10255533e\$lut for cells of type $lut.
Using template $paramod$dfdac05721588b0ddfd873da6a994c6e2917618b\$lut for cells of type $lut.
Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut.
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut.
Using template $paramod$1b53a9695a0f80de7517b50863b438fd2b7f56da\$lut for cells of type $lut.
Using template $paramod$4ebbf381cf64b08e3304ae8194da41d0cd1eaa92\$lut for cells of type $lut.
Using template $paramod$7ce7683c590e6b9a2ebd543a8f468551f1af24cf\$lut for cells of type $lut.
Using template $paramod$e4165147566e3bf81fd9d0710a5c0c3f92a62036\$lut for cells of type $lut.
Using template $paramod$05f66240810e81b1a2e698a1f280f5252768dc46\$lut for cells of type $lut.
Using template $paramod$d4649ab668a85d4687d7924713da2ad248493b9e\$lut for cells of type $lut.
Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut.
Using template $paramod$ac151cb38c7ba6525bd1253e43cd4c9cbab24bcf\$lut for cells of type $lut.
Using template $paramod$90dc599eed99da511e64ad217d69e7ff2c1e56cc\$lut for cells of type $lut.
Using template $paramod$a0977411bdac40d44233adbcbc81a939f81eb479\$lut for cells of type $lut.
Using template $paramod$30d0a2190ad4c97308be50f413b03ae693dcb1d5\$lut for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod$cba7d4f63aea5e4b3faf052f9f9805e0c6d202cb\$lut for cells of type $lut.
Using template $paramod$26918802e6ed329b7afdcbcae3efbad76693779f\$lut for cells of type $lut.
Using template $paramod$68cb09a5d00037369a2af39e1778bf17484c020a\$lut for cells of type $lut.
Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut.
Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120\$lut for cells of type $lut.
Using template $paramod$ba8dec50293bd4fff7afb084857c0abb583edca0\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$90418f71a1b3e98f36d147df874dd839b0e31579\$lut for cells of type $lut.
Using template $paramod$2a4b250d89be3556c74aa0e719a4f6242369d42f\$lut for cells of type $lut.
Using template $paramod$f399c645759b462c6951b29e9c70b00f6c71f1c7\$lut for cells of type $lut.
Using template $paramod$542e2fdf39f66ee0d9684372297ec1f9c72087d5\$lut for cells of type $lut.
Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f\$lut for cells of type $lut.
Using template $paramod$34e326867bb04eb7166eb385de03f3f07fdc4c23\$lut for cells of type $lut.
Using template $paramod$037be5c00d8a02858cdb1ab049b58a0133287ff1\$lut for cells of type $lut.
Using template $paramod$af9afa97a86ed965cd3ddb88f85a3c26bc8c150b\$lut for cells of type $lut.
Using template $paramod$120c20f632ce45d8913b24863643696ec017df28\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$4f6ef5838c139220e91b3d9534b74e9d61193cac\$lut for cells of type $lut.
Using template $paramod$d657361b360a152b4018b0283df55e5626273e96\$lut for cells of type $lut.
Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut.
Using template $paramod$263b613d26e59958a0d1e36903a2016b82f2f359\$lut for cells of type $lut.
Using template $paramod$39fecdaa624309b39c1f847c4e14205177fabf73\$lut for cells of type $lut.
Using template $paramod$00dfa99b7aecc2e72490719b192118cbd6549a2c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$769bdbbde83614df0f4ab5f54e777ded51bb10ce\$lut for cells of type $lut.
Using template $paramod$e934877433e628b9aa4b7cb2bee8957bca3e1db5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod$14e62338c0694b7d80cbb5d0fd29f7c0d24a02a6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$de5328836923c44c99600bcab852423201246f91\$lut for cells of type $lut.
Using template $paramod$95f9b81027e0efcb4250de73f2fadc287f9fe7c2\$lut for cells of type $lut.
Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut.
Using template $paramod$179bbca2dd7fa841ad12e8b0327ef61d6e9a7bc3\$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$70f68cc10fbeada9b6fa90c3bb75475e348ca467\$lut for cells of type $lut.
Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26\$lut for cells of type $lut.
Using template $paramod$b574c1df31b19134bcccccd0450f90abe2dd8f26\$lut for cells of type $lut.
Using template $paramod$71b6d833a4170eede1dcc8409c3fc7460c2df8d9\$lut for cells of type $lut.
Using template $paramod$4d673f44384ebded9d542bceabb0e9271e6f9336\$lut for cells of type $lut.
Using template $paramod$32f6e6f07642dc22c5cc1d998ff4e38e22c3119d\$lut for cells of type $lut.
Using template $paramod$432f26b811c14bf54c5e87c8670ec65cbcaf38ac\$lut for cells of type $lut.
Using template $paramod$f94cf08026d21db794b98b1a8efaec5f34ff8975\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~8065 debug messages>

22.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73295.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73308.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73246.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73281.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73273.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$9493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$9322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$9322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$9322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$9305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$9054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$9002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$8672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$8396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8384.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$8359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$8359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$8130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$8080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$8068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$7770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$7770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$7764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$7227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$7077.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7077.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7077.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7077.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7077.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7077.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$7022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$7022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$7022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$7022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$6830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$6652.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$6373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$5971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$5532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$5447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$5447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$5447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$5244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$5244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$5244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4344.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4340.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$4293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6021.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6579.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$5985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7090.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6952.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6952.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$5978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$7366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$7366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$7366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$7366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$7254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$7254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$7254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$6524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$5996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10277.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7297.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$7292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6716.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$5719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$5662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$5752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$5752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$4898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$4756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$4811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73344.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$4837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4832.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$4933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$4694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$4073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4068.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$4038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$10014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$10075.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10115.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$10292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$10470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7393.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10777.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$10795.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$10818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$10934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10941.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$10994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11090.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11095.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$11283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11375.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$12053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$12060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$12105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$12142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$12149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$12160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$12167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$4002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$4013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$4060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$4068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$4073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$4096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$4096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$4106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$4085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$10070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$4282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$4658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4725.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$4749.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$4756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4767.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4785.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4811.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4841.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$4886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4881.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4890.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73364.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$4921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$4944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$5603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$5054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$5298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$5315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7292.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$5462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$5532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$5586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5586.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5756.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$5764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5816.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$5860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$5860.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$5872.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5909.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5955.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$5978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6099.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6217.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6233.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6284.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6353.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6361.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6428.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$5920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$6490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$6549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6553.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6571.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6587.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$6821.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$5648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$5627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$6958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$6964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6972.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7022.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$7026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$7040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7077.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7125.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$7214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$7260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$5689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$5703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$7372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$6004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7471.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$7733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73135.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$8068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8072.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$8120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$8130.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$8348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8384.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$8384.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$8396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$8653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$8672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$8990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$9042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9258.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$9305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9309.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$9322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9493.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$9497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$9506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$9934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$73072$lut$auto$fsm_map.cc:170:map_fsm$2217[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$auto$fsm_map.cc:170:map_fsm$2217[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$7688.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$auto$rtlil.cc:2582:Mux$2704[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$auto$opt_dff.cc:219:make_patterns_logic$2406.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73290.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$11185.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73072$lut$aiger73071$12068.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$73072$lut\SOC.Core.CSR_Unit.csr_write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73072$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73072$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73072$lut\SOC.Core.CSR_Unit.csr_write_data[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73072$lut\SOC.Core.CSR_Unit.csr_write_data[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73072$lut\SOC.Core.CSR_Unit.csr_write_data[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73072$lut\SOC.Core.CSR_Unit.csr_write_data[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$73072$lut\SOC.Core.CSR_Unit.csr_write_data[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73161.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$73072$lut$auto$fsm_map.cc:170:map_fsm$2217[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73285.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73124.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73133.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73145.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73151.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73247.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73262.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73267.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73269.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73299.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73300.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73317.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73319.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73321.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73324.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73325.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73326.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73332.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$73072$lut$aiger73071$5739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$73072$lut$aiger73071$7366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$73372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$73072$lut$aiger73071$4736.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Removed 0 unused cells and 7157 unused wires.

22.45. Executing AUTONAME pass.
Renamed 346821 objects in module top (333 iterations).
<suppressed ~11588 debug messages>

22.46. Executing HIERARCHY pass (managing design hierarchy).

22.46.1. Analyzing design hierarchy..
Top module:  \top

22.46.2. Analyzing design hierarchy..
read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1317.094 ; gain = 0.023 ; free physical = 10194 ; free virtual = 30007
# read_verilog ../../debug/reset.v
# read_verilog ../../src/core/alu_control.v
# read_verilog ../../src/core/alu.v
# read_verilog ../../src/core/control_unit.v
# read_verilog ../../src/core/core.v
# read_verilog ../../src/core/immediate_generator.v
# read_verilog ../../src/core/mux.v
# read_verilog ../../src/core/pc.v
# read_verilog ../../src/core/registers.v
# read_verilog ../../src/core/csr_unit.v
# read_verilog ../../src/peripheral/bus.v
# read_verilog ../../src/peripheral/gpio.v
# read_verilog ../../src/peripheral/gpios.v
# read_verilog ../../src/peripheral/leds.v
# read_verilog ../../src/peripheral/memory.v
# read_verilog ../../src/peripheral/soc.v
# read_verilog ../../src/peripheral/uart_rx.v
# read_verilog ../../src/peripheral/uart_tx.v
# read_verilog ../../src/peripheral/uart.v
# read_verilog ../../src/peripheral/fifo.v
# read_xdc "digilent_nexys4_ddr.xdc"
# set_property PROCESSING_ORDER EARLY [get_files digilent_nexys4_ddr.xdc]
# synth_design -top "top" -part "xc7a100tcsg324-1"
Command: synth_design -top top -part xc7a100tcsg324-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
Top module:  \top
Removed 0 unused modules.

22.47. Printing statistics.

=== top ===

   Number of wires:               5316
   Number of wire bits:          13298
   Number of public wires:        5316
   Number of public wire bits:   13298
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               6815
     $_TBUF_                         6
     $scopeinfo                     30
     CCU2C                         310
     L6MUX21                       439
     LUT4                         4043
     PFUMX                         993
     TRELLIS_DPR16X4               292
     TRELLIS_FF                    702

22.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

22.49. Executing JSON backend.

Warnings: 213 unique messages, 214 total
End of script. Logfile hash: bb1755d072, CPU: user 8.29s system 0.11s, MEM: 214.87 MB peak
Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)
Time spent: 36% 1x abc9_exe (4 sec), 11% 11x techmap (1 sec), ...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (NextPNR)
[Pipeline] sh
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:      6415/43848    14%
Info:         logic LUTs:   4043/43848     9%
Info:         carry LUTs:    620/43848     1%
Info:           RAM LUTs:   1168/ 5481    21%
Info:          RAMW LUTs:    584/10962     5%

Info:      Total DFFs:       702/43848     1%

Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     323 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x76ac17df

Info: Device utilisation:
Info: 	          TRELLIS_IO:    18/  245     7%
Info: 	                DCCA:     1/   56     1%
Info: 	              DP16KD:     0/  108     0%
Info: 	          MULT18X18D:     0/   72     0%
Info: 	              ALU54B:     0/   36     0%
Info: 	             EHXPLLL:     0/    4     0%
Info: 	             EXTREFB:     0/    2     0%
Info: 	                DCUA:     0/    2     0%
Info: 	           PCSCLKDIV:     0/    2     0%
Info: 	             IOLOGIC:     0/  160     0%
Info: 	            SIOLOGIC:     0/   85     0%
Info: 	                 GSR:     0/    1     0%
Info: 	               JTAGG:     0/    1     0%
Info: 	                OSCG:     0/    1     0%
Info: 	               SEDGA:     0/    1     0%
Info: 	                 DTR:     0/    1     0%
Info: 	             USRMCLK:     0/    1     0%
Info: 	             CLKDIVF:     0/    4     0%
Info: 	           ECLKSYNCB:     0/   10     0%
Info: 	             DLLDELD:     0/    8     0%
Info: 	              DDRDLL:     0/    4     0%
Info: 	             DQSBUFM:     0/   10     0%
Info: 	     TRELLIS_ECLKBUF:     0/    8     0%
Info: 	        ECLKBRIDGECS:     0/    2     0%
Info: 	                DCSC:     0/    2     0%
Info: 	          TRELLIS_FF:   702/43848     1%
Info: 	        TRELLIS_COMB:  6503/43848    14%
Info: 	        TRELLIS_RAMW:   292/ 5481     5%

Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 3310 cells, random placement wirelen = 304995.
Info:     at initial placer iter 0, wirelen = 2824
Info:     at initial placer iter 1, wirelen = 2825
Info:     at initial placer iter 2, wirelen = 2921
Info:     at initial placer iter 3, wirelen = 2935
Info: Running main analytical placer, max placement attempts per cell = 7061282.
Info:     at iteration #1, type ALL: wirelen solved = 2928, spread = 46307, legal = 46730; time = 0.17s
Info:     at iteration #2, type ALL: wirelen solved = 4604, spread = 38466, legal = 38935; time = 0.17s
Info:     at iteration #3, type ALL: wirelen solved = 5739, spread = 39707, legal = 40490; time = 0.17s
Info:     at iteration #4, type ALL: wirelen solved = 7789, spread = 39597, legal = 40113; time = 0.17s
Info:     at iteration #5, type ALL: wirelen solved = 9242, spread = 35652, legal = 36440; time = 0.17s
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 1081497
Info:     at iteration #6, type ALL: wirelen solved = 9933, spread = 35531, legal = 36039; time = 0.21s
Info:     at iteration #7, type ALL: wirelen solved = 10659, spread = 34497, legal = 35188; time = 0.23s
Info:     at iteration #8, type ALL: wirelen solved = 10946, spread = 32101, legal = 33033; time = 0.23s
Info:     at iteration #9, type ALL: wirelen solved = 12586, spread = 30763, legal = 31724; time = 0.24s
Info:     at iteration #10, type ALL: wirelen solved = 13131, spread = 29770, legal = 30840; time = 0.22s
Info:     at iteration #11, type ALL: wirelen solved = 14304, spread = 29919, legal = 30874; time = 0.25s
Info:     at iteration #12, type ALL: wirelen solved = 14433, spread = 29866, legal = 30605; time = 0.22s
Info:     at iteration #13, type ALL: wirelen solved = 14419, spread = 30800, legal = 31456; time = 0.23s
Info:     at iteration #14, type ALL: wirelen solved = 15538, spread = 28751, legal = 29730; time = 0.23s
Info:     at iteration #15, type ALL: wirelen solved = 15411, spread = 29377, legal = 30058; time = 0.22s
Info:     at iteration #16, type ALL: wirelen solved = 16159, spread = 27454, legal = 28529; time = 0.21s
Info:     at iteration #17, type ALL: wirelen solved = 16014, spread = 28182, legal = 28895; time = 0.16s
Info:     at iteration #18, type ALL: wirelen solved = 17749, spread = 26827, legal = 27675; time = 0.15s
Info:     at iteration #19, type ALL: wirelen solved = 16441, spread = 27193, legal = 28168; time = 0.20s
Info:     at iteration #20, type ALL: wirelen solved = 16736, spread = 25676, legal = 27504; time = 0.22s
Info:     at iteration #21, type ALL: wirelen solved = 16885, spread = 27577, legal = 28496; time = 0.22s
Info:     at iteration #22, type ALL: wirelen solved = 17516, spread = 25782, legal = 27840; time = 0.16s
Info:     at iteration #23, type ALL: wirelen solved = 17640, spread = 28054, legal = 29124; time = 0.16s
Info:     at iteration #24, type ALL: wirelen solved = 18265, spread = 26696, legal = 27593; time = 0.16s
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2028.816 ; gain = 404.715 ; free physical = 9176 ; free virtual = 28997
---------------------------------------------------------------------------------
Info:     at iteration #25, type ALL: wirelen solved = 18028, spread = 26288, legal = 27838; time = 0.16s
Info: HeAP Placer Time: 7.63s
Info:   of which solving equations: 4.72s
Info:   of which spreading cells: 0.56s
Info:   of which strict legalisation: 0.22s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 6647, wirelen = 27504
INFO: [Synth 8-11241] undeclared symbol 'pc_source', assumed default net type 'wire' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:112]
WARNING: [Synth 8-11065] parameter 'SET_DIRECTION' becomes localparam in 'GPIOS' with formal parameter declaration list [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:17]
WARNING: [Synth 8-11065] parameter 'READ' becomes localparam in 'GPIOS' with formal parameter declaration list [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:18]
WARNING: [Synth 8-9400] empty statement in sequential block [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:40]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:17]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:16]
INFO: [Synth 8-6157] synthesizing module 'top' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1]
	Parameter CYCLES bound to: 20 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1]
WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:17]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 3 connections declared, but only 2 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:17]
INFO: [Synth 8-6157] synthesizing module 'Risco_5_SOC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
	Parameter CLOCK_FREQ bound to: 100000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter MEMORY_SIZE bound to: 2048 - type: integer 
	Parameter MEMORY_FILE bound to: ../../software/memory/fpga_test_3.hex - type: string 
	Parameter GPIO_WIDHT bound to: 8 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:1]
	Parameter BOOT_ADDRESS bound to: 0 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'PC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'PC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6157] synthesizing module 'MUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:11]
INFO: [Synth 8-6155] done synthesizing module 'MUX' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1]
WARNING: [Synth 8-7071] port 'C' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:79]
WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:79]
WARNING: [Synth 8-7023] instance 'MemoryAddressMUX' of module 'MUX' has 6 connections declared, but only 4 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:79]
WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'MemoryDataMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:86]
WARNING: [Synth 8-7023] instance 'MemoryDataMUX' of module 'MUX' has 6 connections declared, but only 5 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:86]
WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'AluInputBMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:103]
WARNING: [Synth 8-7023] instance 'AluInputBMUX' of module 'MUX' has 6 connections declared, but only 5 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:103]
WARNING: [Synth 8-7071] port 'C' of module 'MUX' is unconnected for instance 'PCSourceMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:111]
WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'PCSourceMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:111]
WARNING: [Synth 8-7023] instance 'PCSourceMUX' of module 'MUX' has 6 connections declared, but only 4 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:111]
INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1]
INFO: [Synth 8-6157] synthesizing module 'Control_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:1]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:82]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:86]
INFO: [Synth 8-6155] done synthesizing module 'Control_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:1]
INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:33]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:10]
INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6157] synthesizing module 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:132]
INFO: [Synth 8-6155] done synthesizing module 'CSR_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
WARNING: [Synth 8-7071] port 'save_pc' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:174]
WARNING: [Synth 8-7071] port 'interrupt_on_hold' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:174]
WARNING: [Synth 8-7023] instance 'CSR_Unit' of module 'CSR_Unit' has 15 connections declared, but only 13 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:174]
INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:1]
WARNING: [Synth 8-7071] port 'instruction_request_external' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:29]
WARNING: [Synth 8-7071] port 'instruction_request_timer' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:29]
WARNING: [Synth 8-7071] port 'instruction_request_software' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:29]
WARNING: [Synth 8-7071] port 'instruction_request_fast' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:29]
WARNING: [Synth 8-7023] instance 'Core' of module 'Core' has 12 connections declared, but only 8 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:29]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
	Parameter MEMORY_FILE bound to: ../../software/memory/fpga_test_3.hex - type: string 
	Parameter MEMORY_SIZE bound to: 2048 - type: integer 
INFO: [Synth 8-3876] $readmem data file '../../software/memory/fpga_test_3.hex' is read successfully [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:29]
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
INFO: [Synth 8-6157] synthesizing module 'BUS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6155] done synthesizing module 'BUS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6157] synthesizing module 'LEDs' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6155] done synthesizing module 'LEDs' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
	Parameter CLOCK_FREQ bound to: 100000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
	Parameter DEPTH bound to: 8 - type: integer 
	Parameter WIDTH bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_rx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 100000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_rx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_tx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 100000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_tx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'GPIOS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
	Parameter WIDHT bound to: 8 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'GPIO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIOS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Risco_5_SOC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
WARNING: [Synth 8-3848] Net interrupt_on_hold in module/entity CSR_Unit does not have driver. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:20]
WARNING: [Synth 8-6014] Unused sequential element buffer_full_reg was removed.  [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:49]
WARNING: [Synth 8-6014] Unused sequential element tx_fifo_read_reg was removed.  [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:43]
WARNING: [Synth 8-7129] Port address[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[4] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[3] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[2] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[16] in module UART is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2113.785 ; gain = 489.684 ; free physical = 9035 ; free virtual = 28857
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2131.598 ; gain = 507.496 ; free physical = 9037 ; free virtual = 28859
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2131.598 ; gain = 507.496 ; free physical = 9037 ; free virtual = 28859
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2131.598 ; gain = 0.000 ; free physical = 9037 ; free virtual = 28859
Info:   at iteration #5: temp = 0.000000, timing cost = 4484, wirelen = 23904
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2280.348 ; gain = 0.000 ; free physical = 9020 ; free virtual = 28841
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2280.383 ; gain = 0.000 ; free physical = 9013 ; free virtual = 28834
Info:   at iteration #10: temp = 0.000000, timing cost = 4682, wirelen = 22935
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 9006 ; free virtual = 28828
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 9006 ; free virtual = 28828
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 9006 ; free virtual = 28828
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
           RESET_COUNTER |                               00 |                               01
                    IDLE |                               01 |                               10
                    INIT |                               10 |                               00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                   FETCH |                 0000000000000001 |                             0000
                  DECODE |                 0000000000000010 |                             0001
                  MEMADR |                 0000000000000100 |                             0010
                 MEMREAD |                 0000000000001000 |                             0011
                   MEMWB |                 0000000000010000 |                             0100
                MEMWRITE |                 0000000000100000 |                             0101
                EXECUTER |                 0000000001000000 |                             0110
                EXECUTEI |                 0000000010000000 |                             1000
                     JAL |                 0000000100000000 |                             1001
                     BEQ |                 0000001000000000 |                             1010
                   AUIPC |                 0000010000000000 |                             1100
                     LUI |                 0000100000000000 |                             1101
                 JALR_PC |                 0001000000000000 |                             1110
                    JALR |                 0010000000000000 |                             1011
                   ALUWB |                 0100000000000000 |                             0111
              EXECUTECSR |                 1000000000000000 |                             1111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
WARNING: [Synth 8-327] inferring latch for variable 'aluop_out_reg' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:12]
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_RECV |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_SEND |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 9002 ; free virtual = 28825
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input   32 Bit       Adders := 1     
	   3 Input   32 Bit       Adders := 1     
	   2 Input   11 Bit       Adders := 2     
	   2 Input    6 Bit       Adders := 4     
	   2 Input    5 Bit       Adders := 1     
	   2 Input    4 Bit       Adders := 2     
+---XORs : 
	   2 Input     32 Bit         XORs := 1     
+---Registers : 
	               33 Bit    Registers := 1     
	               32 Bit    Registers := 44    
	               16 Bit    Registers := 2     
	               11 Bit    Registers := 2     
	                8 Bit    Registers := 8     
	                6 Bit    Registers := 1     
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 17    
+---RAMs : 
	              16K Bit	(512 X 32 bit)          RAMs := 1     
	               64 Bit	(8 X 8 bit)          RAMs := 2     
+---Muxes : 
	   3 Input   33 Bit        Muxes := 1     
	   4 Input   32 Bit        Muxes := 18    
	   2 Input   32 Bit        Muxes := 36    
	   8 Input   32 Bit        Muxes := 1     
	  16 Input   32 Bit        Muxes := 1     
	   6 Input   32 Bit        Muxes := 1     
	  16 Input   16 Bit        Muxes := 1     
	  11 Input   16 Bit        Muxes := 1     
	   2 Input   16 Bit        Muxes := 1     
	   2 Input    8 Bit        Muxes := 3     
	   5 Input    8 Bit        Muxes := 1     
	   3 Input    6 Bit        Muxes := 1     
	   2 Input    6 Bit        Muxes := 4     
	   2 Input    5 Bit        Muxes := 1     
	  10 Input    4 Bit        Muxes := 1     
	   8 Input    4 Bit        Muxes := 1     
	  23 Input    4 Bit        Muxes := 1     
	  10 Input    3 Bit        Muxes := 1     
	   2 Input    3 Bit        Muxes := 1     
	   3 Input    2 Bit        Muxes := 1     
	   2 Input    2 Bit        Muxes := 14    
	  16 Input    2 Bit        Muxes := 3     
	   4 Input    2 Bit        Muxes := 4     
	   3 Input    1 Bit        Muxes := 6     
	   2 Input    1 Bit        Muxes := 49    
	  16 Input    1 Bit        Muxes := 6     
	   4 Input    1 Bit        Muxes := 2     
	  13 Input    1 Bit        Muxes := 2     
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
[80%] Tech-Mapping Phase 3 completed
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
[90%] Tech-Mapping Phase 4 completed
WARN  (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":172)
WARN  (NL0002) : The module "MUX" instantiated to "MemoryAddressMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
[95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Info:   at iteration #15: temp = 0.000000, timing cost = 4741, wirelen = 22302
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template. 
[100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg"
Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Processing netlist completed
Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst"
Physical Constraint parsed completed
Running placement......
Info:   at iteration #20: temp = 0.000000, timing cost = 4374, wirelen = 22072
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
Info:   at iteration #25: temp = 0.000000, timing cost = 3684, wirelen = 21996
Info:   at iteration #27: temp = 0.000000, timing cost = 3720, wirelen = 22001 
Info: SA placement time 21.67s

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 39.09 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 9.43 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 10.36 ns

Info: Slack histogram:
Info:  legend: * represents 44 endpoint(s)
Info:          + represents [1,44) endpoint(s)
Info: [ 14421,  15662) |+
Info: [ 15662,  16903) |+
Info: [ 16903,  18144) |**+
Info: [ 18144,  19385) |******+
Info: [ 19385,  20626) |****+
Info: [ 20626,  21867) |***+
Info: [ 21867,  23108) |**+
Info: [ 23108,  24349) |****+
Info: [ 24349,  25590) |******************+
Info: [ 25590,  26831) |********************************+
Info: [ 26831,  28072) |************************************************************ 
Info: [ 28072,  29313) |****************************+
Info: [ 29313,  30554) |********+
Info: [ 30554,  31795) |*+
Info: [ 31795,  33036) |+
Info: [ 33036,  34277) |**+
Info: [ 34277,  35518) |******+
Info: [ 35518,  36759) |******+
Info: [ 36759,  38000) |*****+
Info: [ 38000,  39241) |**+
Info: Checksum: 0x7f300386
Info: Routing globals...
Info:     routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0

Info: Routing..
Info: Setting up routing queue.
Info: Routing 28866 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |      156        843 |  156   843 |     28076|       0.62       0.62|
Info:       2000 |      293       1706 |  137   863 |     27463|       0.27       0.89|
Info:       3000 |      410       2589 |  117   883 |     26810|       0.28       1.18|
Info:       4000 |      541       3458 |  131   869 |     26023|       0.26       1.44|
Info:       5000 |      683       4316 |  142   858 |     25401|       0.26       1.70|
Info:       6000 |      764       5235 |   81   919 |     25148|       0.27       1.96|
Info:       7000 |      981       6018 |  217   783 |     24587|       0.23       2.20|
Info:       8000 |     1115       6884 |  134   866 |     24220|       0.23       2.42|
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8824 ; free virtual = 28656
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object                  | Inference | Size (Depth x Width) | Primitives      | 
+------------+-----------------------------+-----------+----------------------+-----------------+
|top         | SOC/Memory/memory_reg       | Implied   | 512 x 32             | RAM256X1S x 64  | 
|top         | SOC/Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
|top         | SOC/Uart/TX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
+------------+-----------------------------+-----------+----------------------+-----------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Info:       9000 |     1311       7688 |  196   804 |     23535|       0.26       2.68|
Info:      10000 |     1509       8490 |  198   802 |     22788|       0.24       2.92|
Info:      11000 |     1717       9282 |  208   792 |     22149|       0.25       3.17|
Info:      12000 |     1951      10048 |  234   766 |     21445|       0.25       3.42|
Info:      13000 |     2090      10909 |  139   861 |     21145|       0.25       3.67|
Info:      14000 |     2246      11753 |  156   844 |     20645|       0.28       3.95|
Info:      15000 |     2480      12519 |  234   766 |     19951|       0.28       4.23|
Info:      16000 |     2635      13364 |  155   845 |     19367|       0.28       4.51|
Info:      17000 |     2844      14155 |  209   791 |     18853|       0.30       4.81|
Info:      18000 |     3078      14921 |  234   766 |     18470|       0.37       5.18|
Info:      19000 |     3331      15668 |  253   747 |     17824|       0.28       5.46|
Info:      20000 |     3614      16385 |  283   717 |     17320|       0.30       5.76|
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8815 ; free virtual = 28647
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
Info:      21000 |     3926      17073 |  312   688 |     16836|       0.31       6.07|
Info:      22000 |     4240      17759 |  314   686 |     16273|       0.32       6.38|
Info:      23000 |     4574      18425 |  334   666 |     15727|       0.34       6.73|
Info:      24000 |     4931      19068 |  357   643 |     15192|       0.33       7.06|
Info:      25000 |     5312      19687 |  381   619 |     14761|       0.33       7.39|
Info:      26000 |     5628      20371 |  316   684 |     14163|       0.31       7.70|
Info:      27000 |     6016      20983 |  388   612 |     13675|       0.33       8.03|
Info:      28000 |     6387      21612 |  371   629 |     13159|       0.30       8.33|
Info:      29000 |     6819      22180 |  432   568 |     12732|       0.33       8.66|
Info:      30000 |     7265      22734 |  446   554 |     12282|       0.33       8.99|
Info:      31000 |     7664      23335 |  399   601 |     11936|       0.33       9.33|
Info:      32000 |     8097      23902 |  433   567 |     11474|       0.33       9.66|
[30%] Placement Phase 2 completed
Info:      33000 |     8494      24483 |  397   581 |     10957|       0.32       9.98|
Info:      34000 |     8902      24990 |  408   507 |     10465|       0.29      10.27|
Info:      35000 |     9145      25575 |  243   585 |      9745|       0.21      10.47|
Info:      36000 |     9523      26090 |  378   515 |      9240|       0.29      10.76|
Info:      37000 |     9880      26621 |  357   531 |      8696|       0.27      11.03|
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8813 ; free virtual = 28645
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object                  | Inference | Size (Depth x Width) | Primitives      | 
+------------+-----------------------------+-----------+----------------------+-----------------+
|top         | SOC/Memory/memory_reg       | Implied   | 512 x 32             | RAM256X1S x 64  | 
|top         | SOC/Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
|top         | SOC/Uart/TX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
+------------+-----------------------------+-----------+----------------------+-----------------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
Info:      38000 |    10158      27257 |  278   636 |      8000|       0.20      11.24|
Info:      39000 |    10473      27871 |  315   614 |      7540|       0.28      11.51|
Info:      40000 |    10768      28477 |  295   606 |      6899|       0.25      11.76|
Info:      41000 |    11111      29085 |  343   608 |      6262|       0.30      12.06|
Info:      42000 |    11357      29807 |  246   722 |      5596|       0.32      12.38|
Info:      43000 |    11399      30752 |   42   945 |      4691|       0.12      12.50|
Info:      44000 |    11431      31697 |   32   945 |      3723|       0.08      12.58|
Info:      45000 |    11454      32671 |   23   974 |      2748|       0.08      12.66|
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8733 ; free virtual = 28565
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
Info:      46000 |    11636      33482 |  182   811 |      1959|       0.24      12.90|
Info:      47000 |    11752      34250 |  116   768 |      1085|       0.28      13.18|
Info:      48000 |    11791      34933 |   39   683 |       148|       0.22      13.40|
Info:      48147 |    11791      35013 |    0    80 |         0|       0.08      13.49|
Info: Routing complete.
Info: Router1 time 13.49s
Info: Checksum: 0xab8aa729

Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q.Q
Info:  1.5  2.0    Net SOC.Core.Control_Unit.nextstate_PFUMX_Z_2_C0[0] (19,21) -> (21,25)
Info:                Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.A
Info:                Defined in:
Info:                  Risco-5/src/core/control_unit.v:51.11-51.16
Info:  0.2  2.3  Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F
Info:  1.4  3.6    Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D[2] (21,25) -> (21,14)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  3.9  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.F
Info:  1.8  5.7    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1 (21,14) -> (21,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.B
Info:  0.4  6.1  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.1    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (21,26) -> (21,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.2  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.2    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (21,26) -> (21,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.2  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.2    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (21,26) -> (21,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.2  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.2    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (21,26) -> (21,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.2  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.2    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (21,26) -> (22,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.3  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.3    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (22,26) -> (22,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.3  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.3    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (22,26) -> (22,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.4  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.4    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (22,26) -> (22,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.4  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.4    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (22,26) -> (22,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.5  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.5    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (22,26) -> (22,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.5  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.5    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (22,26) -> (22,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.5  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.5    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (22,26) -> (22,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.5  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.5    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (22,26) -> (23,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.6  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.6    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (23,26) -> (23,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.6  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.6    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (23,26) -> (23,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.7  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.7    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (23,26) -> (23,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.7  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.7    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (23,26) -> (23,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.7  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.7    Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (23,26) -> (23,26)
Info:                Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.7  Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.7    Net $nextpnr_CCU2C_29$CIN (23,26) -> (23,26)
Info:                Sink $nextpnr_CCU2C_29$CCU2_COMB0.FCI
Info:  0.4  7.2  Source $nextpnr_CCU2C_29$CCU2_COMB0.F
Info:  1.4  8.6    Net SOC.Bus.slave_1_write_LUT4_Z_C[3] (23,26) -> (13,29)
Info:                Sink SOC.Memory.address_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  8.8  Source SOC.Memory.address_LUT4_Z.F
Info:  1.9 10.7    Net SOC.slave_address[5] (13,29) -> (3,32)
Info:                Sink SOC.Memory.memory.0.121$DPRAM_COMB3.A
Info:                Defined in:
Info:                  Risco-5/src/peripheral/soc.v:22.5-22.18
Info:  0.2 10.9  Source SOC.Memory.memory.0.121$DPRAM_COMB3.F
Info:  0.6 11.6    Net SOC.Memory.memory.0.97_DO[2] (3,32) -> (4,32)
Info:                Sink SOC.Memory.memory.0.97_DO_LUT4_C.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 11.8  Source SOC.Memory.memory.0.97_DO_LUT4_C.F
Info:  0.9 12.7    Net SOC.Memory.memory.0.97_DO_LUT4_C_Z[0] (4,32) -> (4,33)
Info:                Sink SOC.Memory.memory.0.41_DO_LUT4_C_Z_LUT4_Z.B
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 12.9  Source SOC.Memory.memory.0.41_DO_LUT4_C_Z_LUT4_Z.F
Info:  0.7 13.6    Net SOC.Memory.memory.0.41_DO_LUT4_C_Z[3] (4,33) -> (3,33)
Info:                Sink SOC.Memory.memory.0.73_DO_LUT4_C_Z_LUT4_Z_1.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 13.8  Source SOC.Memory.memory.0.73_DO_LUT4_C_Z_LUT4_Z_1.F
Info:  0.7 14.6    Net SOC.Memory.memory.0.73_DO_LUT4_C_Z[4] (3,33) -> (3,31)
Info:                Sink SOC.Memory.memory.0.9_DO_LUT4_C_Z_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 14.8  Source SOC.Memory.memory.0.9_DO_LUT4_C_Z_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.7 15.5    Net SOC.Memory.memory.0.9_DO_LUT4_C_Z_LUT4_A_Z[3] (3,31) -> (5,30)
Info:                Sink SOC.Memory.memory.0.9_DO_LUT4_C_Z_LUT4_A_Z_LUT4_B.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 15.7  Source SOC.Memory.memory.0.9_DO_LUT4_C_Z_LUT4_A_Z_LUT4_B.F
Info:  1.6 17.4    Net SOC.Core.read_data_LUT4_Z_7_C[3] (5,30) -> (19,26)
Info:                Sink SOC.Memory.memory.0.175_DO_PFUMX_C0_Z_LUT4_C_Z_PFUMX_C0_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 17.6  Source SOC.Memory.memory.0.175_DO_PFUMX_C0_Z_LUT4_C_Z_PFUMX_C0_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  1.3 19.0    Net SOC.Core.read_data_PFUMX_Z_10_BLUT_LUT4_Z_D[4] (19,26) -> (24,33)
Info:                Sink SOC.Core.read_data_PFUMX_Z_8_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 19.2  Source SOC.Core.read_data_PFUMX_Z_8_BLUT_LUT4_Z.OFX
Info:  1.6 20.8    Net SOC.read_data[24] (24,33) -> (17,23)
Info:                Sink SOC.Core.instruction_register_TRELLIS_FF_Q_7.M
Info:                Defined in:
Info:                  Risco-5/src/peripheral/soc.v:21.34-21.43
Info:  0.0 20.8  Setup SOC.Core.instruction_register_TRELLIS_FF_Q_7.M
Info: 4.7 ns logic, 16.1 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source gpios[2]$tr_io.O
Info:  4.7  4.7    Net gpios[2]$TRELLIS_IO_IN (90,23) -> (14,23)
Info:                Sink SOC.GPIOS.Gpios[2].direction_LUT4_C.B
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:7.16-7.21
Info:  0.2  4.9  Source SOC.GPIOS.Gpios[2].direction_LUT4_C.F
Info:  0.6  5.5    Net SOC.GPIOS.Gpios[2].direction_LUT4_C_Z[2] (14,23) -> (14,23)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_1_LUT4_Z.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  5.8  Source SOC.Uart.RX_FIFO.memory.0.0_DO_1_LUT4_Z.F
Info:  1.0  6.8    Net SOC.Uart.RX_FIFO.memory.0.0_DO_1[3] (14,23) -> (15,19)
Info:                Sink SOC.Core.read_data_LUT4_Z_2.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  7.0  Source SOC.Core.read_data_LUT4_Z_2.F
Info:  0.4  7.4    Net SOC.read_data[2] (15,19) -> (15,19)
Info:                Sink SOC.Core.memory_register_TRELLIS_FF_Q_29.M
Info:                Defined in:
Info:                  Risco-5/src/peripheral/soc.v:21.34-21.43
Info:  0.0  7.4  Setup SOC.Core.memory_register_TRELLIS_FF_Q_29.M
Info: 0.7 ns logic, 6.7 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source SOC.GPIOS.Gpios[2].direction_TRELLIS_FF_Q.Q
Info:  4.0  4.6    Net SOC.GPIOS.gpio_direction[2] (13,23) -> (74,23)
Info:                Sink SOC.GPIOS.Gpios[2].direction_LUT4_D.D
Info:                Defined in:
Info:                  Risco-5/src/peripheral/gpios.v:14.19-14.33
Info:  0.2  4.8  Source SOC.GPIOS.Gpios[2].direction_LUT4_D.F
Info:  1.0  5.8    Net gpios_$_TBUF__Y_3_E (74,23) -> (83,23)
Info:                Sink gpios[2]$tr_io$invert_T.A
Info:  0.2  6.0  Source gpios[2]$tr_io$invert_T.F
Info:  1.3  7.3    Net gpios[2]$tr_io$invert_T$conn$Z (83,23) -> (90,23)
Info:                Sink gpios[2]$tr_io.T
Info: 1.0 ns logic, 6.3 ns routing

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 48.00 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.42 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 7.27 ns

Info: Slack histogram:
Info:  legend: * represents 50 endpoint(s)
Info:          + represents [1,50) endpoint(s)
Info: [ 19168,  20163) |+
Info: [ 20163,  21158) |+
Info: [ 21158,  22153) |******+
Info: [ 22153,  23148) |*****+
Info: [ 23148,  24143) |*+
Info: [ 24143,  25138) |*+
Info: [ 25138,  26133) |***+
Info: [ 26133,  27128) |**************+
Info: [ 27128,  28123) |**********+
Info: [ 28123,  29118) |*********************************+
Info: [ 29118,  30113) |************************************************************ 
Info: [ 30113,  31108) |****+
Info: [ 31108,  32103) |**+
Info: [ 32103,  33098) |*******+
Info: [ 33098,  34093) |***+
Info: [ 34093,  35088) |*+
Info: [ 35088,  36083) |***+
Info: [ 36083,  37078) |******+
Info: [ 37078,  38073) |******+
Info: [ 38073,  39068) |*** 

Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8983 ; free virtual = 28834
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8983 ; free virtual = 28834
---------------------------------------------------------------------------------
[Pipeline] // stage
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8983 ; free virtual = 28834
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8983 ; free virtual = 28834
---------------------------------------------------------------------------------
[Pipeline] }
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8978 ; free virtual = 28830
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8977 ; free virtual = 28829
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+----------+------+
|      |Cell      |Count |
+------+----------+------+
|1     |BUFG      |     1|
|2     |CARRY4    |    55|
|3     |LUT1      |    11|
|4     |LUT2      |   150|
|5     |LUT3      |    68|
|6     |LUT4      |   140|
|7     |LUT5      |   380|
|8     |LUT6      |  1376|
|9     |MUXF7     |   256|
|10    |RAM256X1S |    64|
|11    |RAM32M    |     2|
|12    |RAM32X1D  |     4|
|13    |FDRE      |  1739|
|14    |FDSE      |     5|
|15    |LD        |     4|
|16    |IBUF      |     2|
|17    |IOBUF     |     8|
|18    |OBUF      |     9|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8983 ; free virtual = 28835
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 43 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2280.383 ; gain = 507.496 ; free physical = 8982 ; free virtual = 28833
Synthesis Optimization Complete : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8982 ; free virtual = 28833
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2280.383 ; gain = 0.000 ; free physical = 9256 ; free virtual = 29108
INFO: [Netlist 29-17] Analyzing 393 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2352.379 ; gain = 0.000 ; free physical = 9255 ; free virtual = 29107
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 82 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 8 instances
  LD => LDCE: 4 instances
  RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances

Synth Design complete | Checksum: 5bd2eccb
INFO: [Common 17-83] Releasing license: Synthesis
75 Infos, 130 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:55 ; elapsed = 00:00:52 . Memory (MB): peak = 2352.414 ; gain = 1035.320 ; free physical = 9255 ; free virtual = 29106
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2054.456; main = 1778.755; forked = 422.401
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3225.988; main = 2352.383; forked = 969.652
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2416.410 ; gain = 63.996 ; free physical = 9254 ; free virtual = 29106

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: c8f6debf

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2519.238 ; gain = 102.828 ; free physical = 9215 ; free virtual = 29067

Starting Logic Optimization Task

Phase 1 Initialization

Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: c8f6debf

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794

Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: c8f6debf

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794
Phase 1 Initialization | Checksum: c8f6debf

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794

Phase 2 Timer Update And Timing Data Collection

Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: c8f6debf

Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794

Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: c8f6debf

Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794
Phase 2 Timer Update And Timing Data Collection | Checksum: c8f6debf

Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794

Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 3 inverters resulting in an inversion of 9 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 8eda6a4f

Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794
Retarget | Checksum: 8eda6a4f
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 3 cells

Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 8eda6a4f

Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794
Constant propagation | Checksum: 8eda6a4f
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 5 Sweep
Phase 5 Sweep | Checksum: 15094a4a4

Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794
Sweep | Checksum: 15094a4a4
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 0 cells

Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 15094a4a4

Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2802.160 ; gain = 32.016 ; free physical = 8942 ; free virtual = 28794
BUFG optimization | Checksum: 15094a4a4
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 15094a4a4

Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2802.160 ; gain = 32.016 ; free physical = 8942 ; free virtual = 28794
Shift Register Optimization | Checksum: 15094a4a4
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 905269d5

Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2802.160 ; gain = 32.016 ; free physical = 8942 ; free virtual = 28794
Post Processing Netlist | Checksum: 905269d5
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells

Phase 9 Finalization

Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: cad3eec1

Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2802.160 ; gain = 32.016 ; free physical = 8942 ; free virtual = 28793

Phase 9.2 Verifying Netlist Connectivity

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2802.160 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28793
Phase 9.2 Verifying Netlist Connectivity | Checksum: cad3eec1

Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2802.160 ; gain = 32.016 ; free physical = 8942 ; free virtual = 28793
Phase 9 Finalization | Checksum: cad3eec1

Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2802.160 ; gain = 32.016 ; free physical = 8942 ; free virtual = 28793
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |               3  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               8  |               0  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------


Ending Logic Optimization Task | Checksum: cad3eec1

Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2802.160 ; gain = 32.016 ; free physical = 8942 ; free virtual = 28793
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2802.160 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28793
[50%] Placement Phase 3 completed
Running routing......

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: cad3eec1

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2802.160 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28793

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: cad3eec1

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.160 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28793

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.160 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28793
Ending Netlist Obfuscation Task | Checksum: cad3eec1

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.160 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28793
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2802.160 ; gain = 449.746 ; free physical = 8942 ; free virtual = 28793
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2834.176 ; gain = 0.000 ; free physical = 8941 ; free virtual = 28793
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 7ffa9969

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2834.176 ; gain = 0.000 ; free physical = 8941 ; free virtual = 28793
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2834.176 ; gain = 0.000 ; free physical = 8941 ; free virtual = 28793

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 851f817e

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.52 . Memory (MB): peak = 2834.176 ; gain = 0.000 ; free physical = 8932 ; free virtual = 28784

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: ec301d64

Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8935 ; free virtual = 28787

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: ec301d64

Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8935 ; free virtual = 28787
Phase 1 Placer Initialization | Checksum: ec301d64

Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8935 ; free virtual = 28787

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: db2775b0

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8931 ; free virtual = 28783

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1580cb01c

Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8929 ; free virtual = 28781

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1580cb01c

Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8929 ; free virtual = 28781

Phase 2.4 Global Placement Core
[60%] Routing Phase 0 completed

Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: ed4fdaab

Time (s): cpu = 00:00:26 ; elapsed = 00:00:07 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8862 ; free virtual = 28713

Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 39 LUTNM shape to break, 40 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 13, two critical 26, total 39, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 54 nets or LUTs. Breaked 39 LUTs, combined 15 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 8862 ; free virtual = 28713

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |           39  |             15  |                    54  |           0  |           1  |  00:00:00  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |           39  |             15  |                    54  |           0  |           9  |  00:00:00  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.2 Physical Synthesis In Placer | Checksum: 127c78cd0

Time (s): cpu = 00:00:27 ; elapsed = 00:00:08 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8862 ; free virtual = 28713
Phase 2.4 Global Placement Core | Checksum: 136b43015

Time (s): cpu = 00:00:32 ; elapsed = 00:00:08 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8862 ; free virtual = 28714
Phase 2 Global Placement | Checksum: 136b43015

Time (s): cpu = 00:00:32 ; elapsed = 00:00:08 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8862 ; free virtual = 28714

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: e9b42c39

Time (s): cpu = 00:00:33 ; elapsed = 00:00:09 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8862 ; free virtual = 28714

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: f6e766f4

Time (s): cpu = 00:00:35 ; elapsed = 00:00:09 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8859 ; free virtual = 28711

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 159da352b

Time (s): cpu = 00:00:35 ; elapsed = 00:00:09 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8857 ; free virtual = 28709

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 13a8d2123

Time (s): cpu = 00:00:35 ; elapsed = 00:00:09 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8855 ; free virtual = 28707

Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: dc99ae94

Time (s): cpu = 00:00:39 ; elapsed = 00:00:11 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8852 ; free virtual = 28704

Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 1b604b750

Time (s): cpu = 00:00:41 ; elapsed = 00:00:13 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8861 ; free virtual = 28712

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 18ac65933

Time (s): cpu = 00:00:41 ; elapsed = 00:00:13 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8861 ; free virtual = 28712

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 1b15bcf4f

Time (s): cpu = 00:00:41 ; elapsed = 00:00:13 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8861 ; free virtual = 28712

Phase 3.9 Fast Optimization
[70%] Routing Phase 1 completed
Phase 3.9 Fast Optimization | Checksum: 1a52de3d5

Time (s): cpu = 00:00:47 ; elapsed = 00:00:16 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8858 ; free virtual = 28709
Phase 3 Detail Placement | Checksum: 1a52de3d5

Time (s): cpu = 00:00:47 ; elapsed = 00:00:16 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8858 ; free virtual = 28709

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 21ff37f8e

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.027 | TNS=-40.611 |
Phase 1 Physical Synthesis Initialization | Checksum: 1c032e1c9

Time (s): cpu = 00:00:00.71 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 8877 ; free virtual = 28729
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 1c032e1c9

Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 8877 ; free virtual = 28729
Phase 4.1.1.1 BUFG Insertion | Checksum: 21ff37f8e

Time (s): cpu = 00:00:51 ; elapsed = 00:00:18 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8874 ; free virtual = 28726

Phase 4.1.1.2 Post Placement Timing Optimization
[80%] Routing Phase 2 completed
WARN  (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.176. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1a34d6670

Time (s): cpu = 00:01:16 ; elapsed = 00:00:39 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8842 ; free virtual = 28700

Time (s): cpu = 00:01:16 ; elapsed = 00:00:39 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8842 ; free virtual = 28700
Phase 4.1 Post Commit Optimization | Checksum: 1a34d6670

Time (s): cpu = 00:01:16 ; elapsed = 00:00:39 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8842 ; free virtual = 28700

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1a34d6670

Time (s): cpu = 00:01:17 ; elapsed = 00:00:40 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8844 ; free virtual = 28701

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                8x8|
|___________|___________________|___________________|
|      South|                1x1|                2x2|
|___________|___________________|___________________|
|       East|                2x2|                4x4|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 1a34d6670

Time (s): cpu = 00:01:17 ; elapsed = 00:00:40 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8844 ; free virtual = 28701
Phase 4.3 Placer Reporting | Checksum: 1a34d6670

Time (s): cpu = 00:01:17 ; elapsed = 00:00:40 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8842 ; free virtual = 28700

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 8841 ; free virtual = 28699

Time (s): cpu = 00:01:17 ; elapsed = 00:00:40 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8841 ; free virtual = 28699
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 19ff18b3e

Time (s): cpu = 00:01:17 ; elapsed = 00:00:40 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8844 ; free virtual = 28701
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Sun Apr 14 02:07:00 2024

Ending Placer Task | Checksum: 10983f1f3

Time (s): cpu = 00:01:17 ; elapsed = 00:00:40 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8844 ; free virtual = 28701
37 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:01:18 ; elapsed = 00:00:40 . Memory (MB): peak = 2841.203 ; gain = 39.043 ; free physical = 8844 ; free virtual = 28701
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
[Pipeline] }
# report_io -file digilent_nexys4ddr_io.rpt
[Pipeline] // stage
[Pipeline] }
report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9160 ; free virtual = 29018
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9159 ; free virtual = 29017
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs

Phase 1 Build RT Design
Checksum: PlaceDB: 8d76f748 ConstDB: 0 ShapeSum: 7c0cfaab RouteDB: 0
Post Restoration Checksum: NetGraph: 618cf839 | NumContArr: cdc5ae4e | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2b4a49bc1

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9153 ; free virtual = 29011

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2b4a49bc1

Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9153 ; free virtual = 29011

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2b4a49bc1

Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9153 ; free virtual = 29011
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 22c5afb3d

Time (s): cpu = 00:00:36 ; elapsed = 00:00:28 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9132 ; free virtual = 28991
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.183  | TNS=0.000  | WHS=-0.203 | THS=-11.695|


Router Utilization Summary
  Global Vertical Routing Utilization    = 0.00130565 %
  Global Horizontal Routing Utilization  = 0.00269963 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 3402
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 3399
  Number of Partially Routed Nets     = 3
  Number of Node Overlaps             = 2

Phase 2 Router Initialization | Checksum: 204d1efb4

Time (s): cpu = 00:00:39 ; elapsed = 00:00:28 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9130 ; free virtual = 28988

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 204d1efb4

Time (s): cpu = 00:00:39 ; elapsed = 00:00:28 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9130 ; free virtual = 28988

Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 1c658fb38

Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9130 ; free virtual = 28988
Phase 3 Initial Routing | Checksum: 1c658fb38

Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9130 ; free virtual = 28988

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 1976
 Number of Nodes with overlaps = 844
 Number of Nodes with overlaps = 465
 Number of Nodes with overlaps = 296
 Number of Nodes with overlaps = 219
 Number of Nodes with overlaps = 126
 Number of Nodes with overlaps = 87
 Number of Nodes with overlaps = 60
 Number of Nodes with overlaps = 42
 Number of Nodes with overlaps = 32
 Number of Nodes with overlaps = 9
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.944 | TNS=-43.454| WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 136f795a3

Time (s): cpu = 00:01:23 ; elapsed = 00:00:44 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9104 ; free virtual = 28962

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 496
 Number of Nodes with overlaps = 405
 Number of Nodes with overlaps = 284
 Number of Nodes with overlaps = 187
 Number of Nodes with overlaps = 79
 Number of Nodes with overlaps = 56
 Number of Nodes with overlaps = 33
 Number of Nodes with overlaps = 24
 Number of Nodes with overlaps = 10
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.655 | TNS=-65.213| WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 301d176df

Time (s): cpu = 00:01:46 ; elapsed = 00:00:54 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9113 ; free virtual = 28971
Phase 4 Rip-up And Reroute | Checksum: 301d176df

Time (s): cpu = 00:01:46 ; elapsed = 00:00:54 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9113 ; free virtual = 28971

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 2a1f5a147

Time (s): cpu = 00:01:47 ; elapsed = 00:00:54 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9113 ; free virtual = 28972
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.930 | TNS=-40.340| WHS=N/A    | THS=N/A    |

 Number of Nodes with overlaps = 0
Phase 5.1 Delay CleanUp | Checksum: 1c3fe5053

Time (s): cpu = 00:01:48 ; elapsed = 00:00:54 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9111 ; free virtual = 28970

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1c3fe5053

Time (s): cpu = 00:01:48 ; elapsed = 00:00:54 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9111 ; free virtual = 28970
Phase 5 Delay and Skew Optimization | Checksum: 1c3fe5053

Time (s): cpu = 00:01:48 ; elapsed = 00:00:54 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9111 ; free virtual = 28970

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 2008ed711

Time (s): cpu = 00:01:49 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.930 | TNS=-34.680| WHS=0.037  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 28b474cb6

Time (s): cpu = 00:01:49 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977
Phase 6 Post Hold Fix | Checksum: 28b474cb6

Time (s): cpu = 00:01:49 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 1.07116 %
  Global Horizontal Routing Utilization  = 1.42917 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0


--GLOBAL Congestion:
Utilization threshold used for congestion level computation: 0.85
Congestion Report
North Dir 1x1 Area, Max Cong = 61.2613%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 78.3784%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 79.4118%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 77.9412%, No Congested Regions.

------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0

Phase 7 Route finalize | Checksum: 28b474cb6

Time (s): cpu = 00:01:49 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 28b474cb6

Time (s): cpu = 00:01:49 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 31934ba8b

Time (s): cpu = 00:01:50 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.930 | TNS=-34.680| WHS=0.037  | THS=0.000  |

WARNING: [Route 35-328] Router estimated timing not met.
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
Phase 10 Post Router Timing | Checksum: 31934ba8b

Time (s): cpu = 00:01:51 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977
INFO: [Route 35-16] Router Completed Successfully

Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 10c07316a

Time (s): cpu = 00:01:51 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977
Ending Routing Task | Checksum: 10c07316a

Time (s): cpu = 00:01:51 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
13 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:52 ; elapsed = 00:00:56 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (12)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (4)
5. checking no_input_delay (9)
6. checking no_output_delay (17)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (12)
-------------------------
 There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[6]/Q (HIGH)

 There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[7]/Q (HIGH)

 There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[9]/Q (HIGH)


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (4)
------------------------------------------------
 There are 4 pins that are not constrained for maximum delay. (HIGH)

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (9)
------------------------------
 There are 9 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (17)
--------------------------------
 There are 17 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
     -0.931      -34.505                     97                 6709        0.037        0.000                      0                 6709        3.750        0.000                       0                  2033  


Timing constraints are not met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock        Waveform(ns)       Period(ns)      Frequency(MHz)
-----        ------------       ----------      --------------
sys_clk_pin  {0.000 5.000}      10.000          100.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
sys_clk_pin        -0.931      -34.505                     97                 6709        0.037        0.000                      0                 6709        3.750        0.000                       0                  2033  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
WARNING: [DRC PDRC-153] Gated clock check: Net SOC/Core/Control_Unit/FSM_onehot_state_reg[9]_0[0] is a gated clock net sourced by a combinational pin SOC/Core/Control_Unit/aluop_out_reg[3]_i_2/O, cell SOC/Core/Control_Unit/aluop_out_reg[3]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./build/out.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 3152.492 ; gain = 229.363 ; free physical = 8771 ; free virtual = 28636
INFO: [Common 17-206] Exiting Vivado at Sun Apr 14 02:08:20 2024...
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
The resource [ecp5] is locked by build SERV #75 #75 since Apr 14, 2024, 2:08 AM.
[ecp5] is not free, waiting for execution ...
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [nexys4]
Lock acquired on [ecp5]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
[Pipeline] echo
+ echo gravando na tang nano
gravando na tang nano
FPGA Nexys 4 Broqueada
[Pipeline] sh
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz   -> real 6.00MHz  
Open file DONE
Parse file DONE
load program
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh

Load SRAM: [=========                                         ] 18.00%+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
	0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
[Pipeline] }
Lock released on resource [tangnano20k]

Load SRAM: [===================                               ] 38.00%[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }

Loading: [======                                            ] 11.11%[Pipeline] // stage
[Pipeline] }

Load SRAM: [=============================                     ] 58.00%
Loading: [============                                      ] 22.22%
Load SRAM: [=======================================           ] 78.00%
Loading: [=================                                 ] 33.33%
Load SRAM: [================================================= ] 98.00%
Load SRAM: [===================================================] 100.00%
Done
[Pipeline] }

Loading: [=======================                           ] 44.45%Lock released on resource [nexys4]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }

Loading: [============================                      ] 55.56%
Loading: [==================================                ] 66.67%
Loading: [=======================================           ] 77.78%
Loading: [=============================================     ] 88.89%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
Rodando teste na Nexys 4
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ echo testando na ecp5
testando na ecp5
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo testando na tang nano
testando na tang nano
[Pipeline] sh
[Pipeline] }
+ echo testando na tang nano
testando na tang nano
Lock released on resource [ecp5]
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // script
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS