Console Output

Download View as plain text
Started by user Julio Nunes Avelar
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Risco_5
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -Rf Risco-5/ build/
[Pipeline] sh
+ git clone https://github.com/JN513/Risco-5
Cloning into 'Risco-5'...
[Pipeline] sh
+ cd Risco-5
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (IVerilog)
[Pipeline] sh
+ mkdir -p build
[Pipeline] sh
+ cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/csr_unit.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/fifo.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v
[Pipeline] sh
+ /eda/oss-cad-suite/bin/vvp build/soc_test.o
ERROR: Risco-5/src/peripheral/memory.v:29: $readmemh: Unable to open software/memory/generic.hex for reading.
VCD info: dumpfile build/soc.vcd opened for output.
Risco-5/tests/soc_test.v:34: $finish called at 3606 (1s)
[Pipeline] sh
+ rm -f Risco-5/software/memory/generic.hex
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Síntese)
[Pipeline] parallel
[Pipeline] { (Branch: OSS-Cad-Suite)
[Pipeline] { (Branch: Gowin)
[Pipeline] { (Branch: Vivado)
[Pipeline] stage
[Pipeline] { (OSS-Cad-Suite)
[Pipeline] stage
[Pipeline] { (Gowin)
[Pipeline] stage
[Pipeline] { (Vivado)
[Pipeline] stage
[Pipeline] { (Yosys)
[Pipeline] sh
[Pipeline] sh
+ rm -rf Risco-5/impl/pnr
+ cd Risco-5/fpga/nexys4_ddr
+ mkdir build
+ /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source run.tcl
[Pipeline] sh
+ mkdir -p Risco-5/impl/pnr
[Pipeline] sh
+ /eda/oss-cad-suite/bin/yosys -p                                          read_verilog Risco-5/fpga/ecp5/*.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)

-- Running command `                                         read_verilog Risco-5/fpga/ecp5/*.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     ' --

1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v
Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: Risco-5/debug/reset.v
Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v
Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation.
Generating RTLIL representation for module `\Alu'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v
Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation.
Generating RTLIL representation for module `\ALU_Control'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v
Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: Risco-5/src/core/core.v
Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation.
Generating RTLIL representation for module `\Core'.
Risco-5/src/core/core.v:112: Warning: Identifier `\pc_source' is implicitly declared.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: Risco-5/src/core/csr_unit.v
Parsing Verilog input from `Risco-5/src/core/csr_unit.v' to AST representation.
Generating RTLIL representation for module `\CSR_Unit'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v
Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation.
Generating RTLIL representation for module `\Immediate_Generator'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v
Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation.
Generating RTLIL representation for module `\MUX'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v
Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation.
Generating RTLIL representation for module `\PC'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v
Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation.
Generating RTLIL representation for module `\Registers'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v
Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation.
Generating RTLIL representation for module `\BUS'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/fifo.v
Parsing Verilog input from `Risco-5/src/peripheral/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v
Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9)
Generating RTLIL representation for module `\GPIO'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v
Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation.
Generating RTLIL representation for module `\GPIOS'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v
Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation.
Generating RTLIL representation for module `\LEDs'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v
Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v
Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation.
Generating RTLIL representation for module `\Risco_5_SOC'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v
Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_rx'.
Successfully finished Verilog frontend.

21. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_tx'.
Successfully finished Verilog frontend.

22. Executing SYNTH_ECP5 pass.

22.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

22.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

22.3. Executing HIERARCHY pass (managing design hierarchy).

22.3.1. Finding top of design hierarchy..
root of   0 design levels: uart_tool_tx        
root of   0 design levels: uart_tool_rx        
root of   1 design levels: UART                
root of   2 design levels: Risco_5_SOC         
root of   0 design levels: Memory              
root of   0 design levels: LEDs                
root of   1 design levels: GPIOS               
root of   0 design levels: GPIO                
root of   0 design levels: FIFO                
root of   0 design levels: BUS                 
root of   0 design levels: Registers           
root of   0 design levels: PC                  
root of   0 design levels: MUX                 
root of   0 design levels: Immediate_Generator 
root of   0 design levels: CSR_Unit            
root of   1 design levels: Core                
root of   0 design levels: Control_Unit        
root of   0 design levels: ALU_Control         
root of   0 design levels: Alu                 
root of   0 design levels: ResetBootSystem     
root of   3 design levels: top                 
Automatically selected top as design top module.

22.3.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     \ResetBootSystem
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \MEMORY_SIZE = 8192
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6

22.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \MEMORY_SIZE = 8192
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6
Generating RTLIL representation for module `$paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC'.
Parameter \CYCLES = 20

22.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \WIDHT = 5

22.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 5
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600

22.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Generating RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

22.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \BOOT_ADDRESS = 0

22.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'.
Parameter \BOOT_ADDRESS = 0
Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.
Risco-5/src/core/core.v:112: Warning: Identifier `\pc_source' is implicitly declared.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

22.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

22.3.12. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \WIDHT = 6

22.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 6
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200

22.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Generating RTLIL representation for module `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART'.
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 8192

22.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 8192
Generating RTLIL representation for module `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory'.
Parameter \BOOT_ADDRESS = 0
Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.

22.3.16. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

22.3.19. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100

22.3.20. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Removing unused module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Removing unused module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Removing unused module `\uart_tool_tx'.
Removing unused module `\uart_tool_rx'.
Removing unused module `\UART'.
Removing unused module `\Risco_5_SOC'.
Removing unused module `\Memory'.
Removing unused module `\GPIOS'.
Removing unused module `\FIFO'.
Removing unused module `\Core'.
Removing unused module `\ResetBootSystem'.
Removed 14 unused modules.

22.4. Executing PROC pass (convert processes to netlists).

22.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$495'.
Found and cleaned up 1 empty switch in `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:0$883'.
Removing empty process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:0$883'.
Cleaned up 2 empty switches.

22.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$602 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496 in module TRELLIS_DPR16X4.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/fifo.v:24$794 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:197$976 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:186$974 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:171$966 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:160$963 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:148$957 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:133$952 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:116$947 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:97$938 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:173$925 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:162$923 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:147$915 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:130$901 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:115$895 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:98$890 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:190$684 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:45$881 in module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:33$844 in module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$215 in module LEDs.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:76$834 in module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:41$820 in module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:29$818 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:22$73 in module Registers.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:15$63 in module PC.
Removed 1 dead cases from process $proc$Risco-5/src/core/mux.v:10$62 in module MUX.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/mux.v:10$62 in module MUX.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:18$60 in module Immediate_Generator.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:187$58 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:178$54 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:164$52 in module CSR_Unit.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:118$45 in module CSR_Unit.
Marked 5 switch rules as full_case in process $proc$Risco-5/debug/reset.v:24$605 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Removed 1 dead cases from process $proc$Risco-5/src/core/control_unit.v:122$33 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:122$33 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/control_unit.v:80$31 in module Control_Unit.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:80$31 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:72$30 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:9$26 in module ALU_Control.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:9$26 in module ALU_Control.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:23$11 in module Alu.
Removed a total of 4 dead cases.

22.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 11 redundant assignments.
Promoted 146 assignments to connections.

22.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$603'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$978'.
  Set init value: \i = 0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$931'.
  Set init value: \i = 0
Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$687'.
  Set init value: \instruction_register = 0
  Set init value: \memory_register = 0
  Set init value: \alu_out_register = 0
  Set init value: \register_data_1 = 0
  Set init value: \register_data_2 = 0
  Set init value: \pc_old = 0
Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$218'.
  Set init value: \data = 33'000000000000000000000000000000000
Found init rule in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$837'.
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \buffer_full = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$66'.
  Set init value: \Output = 0
Found init rule in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'.
  Set init value: \csr_mcause = 0
  Set init value: \csr_mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \csr_mepc = 0
  Set init value: \csr_mie_mfie = 16'0000000000000000
  Set init value: \csr_mie_meie = 1'0
  Set init value: \csr_mie_msie = 1'0
  Set init value: \csr_mie_mtie = 1'0
  Set init value: \csr_mip_mfip = 16'0000000000000000
  Set init value: \csr_mip_meip = 1'0
  Set init value: \csr_mip_mtip = 1'0
  Set init value: \csr_mip_msip = 1'0
  Set init value: \csr_minstret = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \csr_mscratch = 0
  Set init value: \csr_mstatus_mie = 1'0
  Set init value: \csr_mstatus_mpie = 1'0
  Set init value: \csr_mtvec = 0
  Set init value: \csr_mtval = 0
  Set init value: \csr_write_data = 0
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$611'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000
Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$34'.
  Set init value: \state = 4'0000
  Set init value: \is_immediate = 1'0
  Set init value: \lorD = 1'0
  Set init value: \pc_write = 1'0
  Set init value: \ir_write = 1'0
  Set init value: \pc_source = 1'0
  Set init value: \reg_write = 1'0
  Set init value: \memory_read = 1'0
  Set init value: \memory_write = 1'0
  Set init value: \pc_write_cond = 1'0
  Set init value: \csr_write_enable = 1'0
  Set init value: \aluop = 2'00
  Set init value: \alu_src_a = 2'00
  Set init value: \alu_src_b = 2'00
  Set init value: \memory_to_reg = 2'00
  Set init value: \nextstate = 4'0000

22.4.5. Executing PROC_ARST pass (detect async resets in processes).

22.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 1 switch.
<suppressed ~88 debug messages>

22.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$603'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$602'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_EN[3:0]$560
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_DATA[3:0]$559
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_ADDR[3:0]$558
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_EN[3:0]$502
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_DATA[3:0]$501
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_ADDR[3:0]$500
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$495'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'.
     1/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$806
     2/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_DATA[7:0]$805
     3/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$804
     4/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$801
     5/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_DATA[7:0]$800
     6/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$799
     7/8: $0\write_ptr[5:0]
     8/8: $0\read_ptr[5:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$978'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$976'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$974'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$966'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$963'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$957'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$952'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$947'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$938'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$931'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$925'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$923'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$915'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$901'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$895'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$890'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$687'.
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
     1/6: $0\alu_out_register[31:0]
     2/6: $0\register_data_2[31:0]
     3/6: $0\register_data_1[31:0]
     4/6: $0\memory_register[31:0]
     5/6: $0\pc_old[31:0]
     6/6: $0\instruction_register[31:0]
Creating decoders for process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:45$881'.
     1/1: $1\read_data[31:0]
Creating decoders for process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
     1/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$877
     2/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_DATA[31:0]$876
     3/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$875
     4/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$880
     5/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_DATA[31:0]$879
     6/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$878
     7/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$867
     8/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_DATA[31:0]$866
     9/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_ADDR[31:0]$865
    10/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$873
    11/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_DATA[31:0]$872
    12/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$871
    13/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$870
    14/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_DATA[31:0]$869
    15/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$868
    16/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$863
    17/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_DATA[31:0]$862
    18/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$861
    19/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$860
    20/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_DATA[31:0]$859
    21/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$858
    22/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$857
    23/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_DATA[31:0]$856
    24/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_ADDR[31:0]$855
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$218'.
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$215'.
     1/1: $0\data[32:0]
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$837'.
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$834'.
     1/1: $1\read_data[31:0]
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
     1/9: $0\rx_fifo_write[0:0]
     2/9: $0\rx_fifo_read[0:0]
     3/9: $0\tx_fifo_write[0:0]
     4/9: $0\tx_fifo_read[0:0]
     5/9: $0\uart_tx_en[0:0]
     6/9: $0\rx_fifo_write_data[7:0]
     7/9: $0\tx_fifo_write_data[7:0]
     8/9: $0\uart_tx_data[7:0]
     9/9: $0\buffer_full[0:0]
Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$818'.
     1/2: $0\gpio_value[5:0]
     2/2: $0\gpio_direction[5:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$91'.
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'.
     1/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$88
     2/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$69_DATA[31:0]$87
     3/9: $2$memwr$\registers$Risco-5/src/core/registers.v:26$69_ADDR[4:0]$86
     4/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$89
     5/9: $1$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$80
     6/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$84
     7/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$83
     8/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$69_DATA[31:0]$82
     9/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$69_ADDR[4:0]$81
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$66'.
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:15$63'.
     1/1: $0\Output[31:0]
Creating decoders for process `\MUX.$proc$Risco-5/src/core/mux.v:10$62'.
     1/1: $1\S[31:0]
Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$60'.
     1/4: $4\immediate[31:0]
     2/4: $3\immediate[31:0]
     3/4: $2\immediate[31:0]
     4/4: $1\immediate[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'.
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$58'.
     1/1: $1\csr_data_out[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54'.
     1/1: $1\csr_write_data[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$52'.
     1/4: $0\csr_mip_msip[0:0]
     2/4: $0\csr_mip_mtip[0:0]
     3/4: $0\csr_mip_meip[0:0]
     4/4: $0\csr_mip_mfip[15:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
     1/13: $0\csr_mtval[31:0]
     2/13: $0\csr_mtvec[31:0]
     3/13: $0\csr_mstatus_mpie[0:0]
     4/13: $0\csr_mstatus_mie[0:0]
     5/13: $0\csr_mscratch[31:0]
     6/13: $0\csr_minstret[63:0]
     7/13: $0\csr_mie_mtie[0:0]
     8/13: $0\csr_mie_msie[0:0]
     9/13: $0\csr_mie_meie[0:0]
    10/13: $0\csr_mie_mfie[15:0]
    11/13: $0\csr_mepc[31:0]
    12/13: $0\csr_mcycle[63:0]
    13/13: $0\csr_mcause[31:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$611'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$34'.
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
     1/1: { $1\pc_write[0:0] $1\alu_src_b[1:0] $1\ir_write[0:0] $1\memory_read[0:0] $1\memory_to_reg[1:0] $1\alu_src_a[1:0] $1\aluop[1:0] $1\csr_write_enable[0:0] $1\pc_write_cond[0:0] $1\memory_write[0:0] $1\reg_write[0:0] $1\pc_source[0:0] $1\lorD[0:0] $1\is_immediate[0:0] }
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31'.
     1/3: $3\nextstate[3:0]
     2/3: $2\nextstate[3:0]
     3/3: $1\nextstate[3:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$30'.
     1/1: $0\state[3:0]
Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'.
     1/4: $4\aluop_out[3:0]
     2/4: $3\aluop_out[3:0]
     3/4: $2\aluop_out[3:0]
     4/4: $1\aluop_out[3:0]
Creating decoders for process `\Alu.$proc$Risco-5/src/core/alu.v:23$11'.
     1/1: $1\ALU_out_S[31:0]

22.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$947'.
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$890'.
No latch inferred for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.\read_data' from process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:45$881'.
No latch inferred for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\read_data' from process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$834'.
No latch inferred for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:16$67_EN' from process `\Registers.$proc$Risco-5/src/core/registers.v:0$91'.
No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$Risco-5/src/core/mux.v:10$62'.
No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$60'.
No latch inferred for signal `\CSR_Unit.\csr_mcause_code' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'.
No latch inferred for signal `\CSR_Unit.\csr_mcause_interrupt_flag' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'.
No latch inferred for signal `\CSR_Unit.\csr_utime' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'.
No latch inferred for signal `\CSR_Unit.\csr_data_out' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$58'.
No latch inferred for signal `\CSR_Unit.\csr_write_data' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54'.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [0]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [1]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [2]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [3]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [4]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [5]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [6]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [7]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [8]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [9]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [10]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [11]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [12]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [13]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [14]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [15]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [16]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [17]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [18]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [19]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [20]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [21]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [22]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [23]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [24]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [25]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [26]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [27]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [28]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [29]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [30]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [31]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54`.
No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\csr_write_enable` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33`.
No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31`.
Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26': $auto$proc_dlatch.cc:433:proc_dlatch$2031
No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$Risco-5/src/core/alu.v:23$11'.

22.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$602'.
  created $dff cell `$procdff$2054' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$538_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$539_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$540_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$541_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$542_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$543_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$544_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$545_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$546_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$547_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$548_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$549_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$550_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$551_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$552_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554'.
  created $dff cell `$procdff$2055' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554'.
  created $dff cell `$procdff$2056' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$553_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554'.
  created $dff cell `$procdff$2057' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$478_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$479_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$480_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$481_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$482_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$483_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$484_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$485_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$486_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$487_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$488_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$489_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$490_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$491_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$492_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$493_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496'.
  created $dff cell `$procdff$2058' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496'.
  created $dff cell `$procdff$2059' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$494_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496'.
  created $dff cell `$procdff$2060' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$495'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'.
  created $dff cell `$procdff$2061' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'.
  created $dff cell `$procdff$2062' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'.
  created $dff cell `$procdff$2063' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'.
  created $dff cell `$procdff$2064' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'.
  created $dff cell `$procdff$2065' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$976'.
  created $dff cell `$procdff$2066' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$976'.
  created $dff cell `$procdff$2067' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$974'.
  created $dff cell `$procdff$2068' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$966'.
  created $dff cell `$procdff$2069' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$963'.
  created $dff cell `$procdff$2070' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$957'.
  created $dff cell `$procdff$2071' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$952'.
  created $dff cell `$procdff$2072' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$952'.
  created $dff cell `$procdff$2073' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$938'.
  created $dff cell `$procdff$2074' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$925'.
  created $dff cell `$procdff$2075' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$923'.
  created $dff cell `$procdff$2076' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$915'.
  created $dff cell `$procdff$2077' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$901'.
  created $dff cell `$procdff$2078' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$895'.
  created $dff cell `$procdff$2079' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$895'.
  created $dff cell `$procdff$2080' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
  created $dff cell `$procdff$2081' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
  created $dff cell `$procdff$2082' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
  created $dff cell `$procdff$2083' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
  created $dff cell `$procdff$2084' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
  created $dff cell `$procdff$2085' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
  created $dff cell `$procdff$2086' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_ADDR' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2087' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_DATA' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2088' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2089' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2090' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_DATA' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2091' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2092' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2093' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_DATA' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2094' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
  created $dff cell `$procdff$2095' with positive edge clock.
Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$215'.
  created $dff cell `$procdff$2096' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\uart_tx_en' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2097' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_read' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2098' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_write' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2099' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_read' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2100' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_write' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2101' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\buffer_full' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2102' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\uart_tx_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2103' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_write_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2104' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_write_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
  created $dff cell `$procdff$2105' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$818'.
  created $dff cell `$procdff$2106' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$818'.
  created $dff cell `$procdff$2107' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'.
  created $dff cell `$procdff$2108' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$69_ADDR' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'.
  created $dff cell `$procdff$2109' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$69_DATA' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'.
  created $dff cell `$procdff$2110' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'.
  created $dff cell `$procdff$2111' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:22$73'.
  created $dff cell `$procdff$2112' with positive edge clock.
Creating register for signal `\PC.\Output' using process `\PC.$proc$Risco-5/src/core/pc.v:15$63'.
  created $dff cell `$procdff$2113' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_mfip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$52'.
  created $dff cell `$procdff$2114' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_meip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$52'.
  created $dff cell `$procdff$2115' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_mtip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$52'.
  created $dff cell `$procdff$2116' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_msip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$52'.
  created $dff cell `$procdff$2117' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mcause' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2118' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mcycle' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2119' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mepc' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2120' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_mfie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2121' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_meie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2122' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_msie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2123' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_mtie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2124' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_minstret' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2125' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mscratch' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2126' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mstatus_mie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2127' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mstatus_mpie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2128' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mtvec' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2129' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mtval' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
  created $dff cell `$procdff$2130' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'.
  created $dff cell `$procdff$2131' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'.
  created $dff cell `$procdff$2132' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'.
  created $dff cell `$procdff$2133' with positive edge clock.
Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$30'.
  created $dff cell `$procdff$2134' with positive edge clock.

22.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$603'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$602'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$602'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$577'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$554'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$520'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$496'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$495'.
Found and cleaned up 3 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$794'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$978'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$976'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$976'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$974'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$974'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$966'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$966'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$963'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$963'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$957'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$957'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$952'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$952'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$947'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$947'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$938'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$938'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$931'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$925'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$925'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$923'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$923'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$915'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$915'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$901'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$901'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$895'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$895'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$890'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$890'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$687'.
Found and cleaned up 2 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:190$684'.
Found and cleaned up 1 empty switch in `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:45$881'.
Removing empty process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:45$881'.
Found and cleaned up 3 empty switches in `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
Removing empty process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$844'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$218'.
Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$215'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$215'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$837'.
Found and cleaned up 1 empty switch in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$834'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$834'.
Found and cleaned up 5 empty switches in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$820'.
Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$818'.
Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$818'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$91'.
Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:22$73'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:22$73'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$66'.
Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:15$63'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:15$63'.
Found and cleaned up 1 empty switch in `\MUX.$proc$Risco-5/src/core/mux.v:10$62'.
Removing empty process `MUX.$proc$Risco-5/src/core/mux.v:10$62'.
Found and cleaned up 4 empty switches in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$60'.
Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$60'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$59'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$58'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$58'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$54'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$52'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$52'.
Found and cleaned up 3 empty switches in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$45'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$611'.
Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$605'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$34'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:122$33'.
Found and cleaned up 3 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:80$31'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$30'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:72$30'.
Found and cleaned up 4 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'.
Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'.
Found and cleaned up 1 empty switch in `\Alu.$proc$Risco-5/src/core/alu.v:23$11'.
Removing empty process `Alu.$proc$Risco-5/src/core/alu.v:23$11'.
Cleaned up 89 empty switches.

22.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
<suppressed ~4 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
<suppressed ~4 debug messages>
Optimizing module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.
<suppressed ~5 debug messages>
Optimizing module LEDs.
<suppressed ~3 debug messages>
Optimizing module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
<suppressed ~9 debug messages>
Optimizing module GPIO.
<suppressed ~3 debug messages>
Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
<suppressed ~4 debug messages>
Optimizing module BUS.
Optimizing module Registers.
<suppressed ~2 debug messages>
Optimizing module PC.
<suppressed ~2 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module Immediate_Generator.
<suppressed ~1 debug messages>
Optimizing module CSR_Unit.
<suppressed ~2 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~7 debug messages>
Optimizing module Control_Unit.
<suppressed ~1 debug messages>
Optimizing module ALU_Control.
<suppressed ~15 debug messages>
Optimizing module Alu.
<suppressed ~1 debug messages>
Optimizing module $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC.
Optimizing module top.

22.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Deleting now unused module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.
Deleting now unused module LEDs.
Deleting now unused module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Deleting now unused module GPIO.
Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Deleting now unused module BUS.
Deleting now unused module Registers.
Deleting now unused module PC.
Deleting now unused module MUX.
Deleting now unused module Immediate_Generator.
Deleting now unused module CSR_Unit.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module Control_Unit.
Deleting now unused module ALU_Control.
Deleting now unused module Alu.
Deleting now unused module $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC.
<suppressed ~30 debug messages>

22.6. Executing TRIBUF pass.

22.7. Executing DEMINOUT pass (demote inout ports to input or output).

22.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~47 debug messages>

22.9. Executing OPT_CLEAN pass (remove unused cells and wires).
[Pipeline] sh
Finding unused cells or wires in module \top..
Removed 64 unused cells and 730 unused wires.
<suppressed ~84 debug messages>

22.10. Executing CHECK pass (checking for obvious problems).
Checking module top...
Warning: Wire top.\SOC.Core.PCSourceMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.PCSourceMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryDataMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.C [0] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.MemoryAddressMUX.D [0] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [15] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [14] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [13] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [12] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [11] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [10] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [9] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [8] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [7] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [6] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [5] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [4] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [3] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [2] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [1] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [0] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_external is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_timer is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_software is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [31] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [30] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [29] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [28] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [27] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [26] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [25] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [24] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [23] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [22] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [21] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [20] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [19] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [18] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [17] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [16] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [15] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [14] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [13] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [12] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [11] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [10] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [9] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [8] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [7] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [6] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [5] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [4] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [3] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [2] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [1] is used but has no driver.
Warning: Wire top.\SOC.Core.AluInputBMUX.D [0] is used but has no driver.
Found and reported 211 problems.

22.11. Executing OPT pass (performing simple optimizations).

22.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6 debug messages>

22.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~351 debug messages>
Removed a total of 117 cells.

22.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1925.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$1953.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1601.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1603.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1614.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1629.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1588.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1588.
    dead port 1/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1588.
    dead port 2/5 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1588.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1548.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1554.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1560.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1566.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1345.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1347.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1354.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1356.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1363.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1365.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1372.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1374.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1381.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1383.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1390.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1392.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1398.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1404.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1410.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1416.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1422.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1428.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1434.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1440.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1446.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1010.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1016.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1022.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1010.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1016.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1022.
Removed 41 multiplexer ports.
<suppressed ~120 debug messages>

22.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1643: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1664_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1663_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1656_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1655_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1654_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1653_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1652_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1651_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1650_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1649_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1648_CMP $auto$opt_reduce.cc:134:opt_pmux$2191 $auto$opt_reduce.cc:134:opt_pmux$2189 $auto$opt_reduce.cc:134:opt_pmux$2187 $auto$opt_reduce.cc:134:opt_pmux$2185 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1942: { $auto$opt_reduce.cc:134:opt_pmux$2193 $flatten\SOC.\Core.\Control_Unit.$procmux$1950_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1949_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1948_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1947_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1946_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1945_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1944_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1943_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1955: { $flatten\SOC.\Core.\Control_Unit.$procmux$1971_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1954_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1926_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1968_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1960_CMP $auto$opt_reduce.cc:134:opt_pmux$2197 $auto$opt_reduce.cc:134:opt_pmux$2195 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1991: { $flatten\SOC.\Core.\ALU_Control.$procmux$1998_CMP $auto$opt_reduce.cc:134:opt_pmux$2199 $flatten\SOC.\Core.\ALU_Control.$procmux$1995_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1994_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1993_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$1992_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1626: $auto$opt_reduce.cc:134:opt_pmux$2201
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1632: { $flatten\SOC.\Core.\Control_Unit.$procmux$1947_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1948_CMP $auto$opt_reduce.cc:134:opt_pmux$2205 $flatten\SOC.\Core.\Control_Unit.$procmux$1949_CMP $auto$opt_reduce.cc:134:opt_pmux$2203 $flatten\SOC.\Core.\Control_Unit.$procmux$1943_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1951_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1545:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1563:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1569:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:24$68_EN[31:0]$74 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1342:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1342_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1342_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1342_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] $flatten\SOC.\Memory.$procmux$1342_Y [0] }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2005: { $auto$opt_reduce.cc:134:opt_pmux$2209 $auto$opt_reduce.cc:134:opt_pmux$2207 $flatten\SOC.\Core.\ALU_Control.$procmux$1998_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1369:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Memory.$procmux$1369_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Memory.$procmux$1369_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1369_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] $flatten\SOC.\Memory.$procmux$1369_Y [0] }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2014: { $flatten\SOC.\Core.\ALU_Control.$procmux$2016_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$2015_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1396:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1396_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1396_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1396_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] $flatten\SOC.\Memory.$procmux$1396_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0]
      New connections: $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1572:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$89, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1563_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$70_EN[31:0]$78 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1575:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$88, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1545_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$69_EN[31:0]$77 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1414:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$880, B=0, Y=$flatten\SOC.\Memory.$procmux$1414_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1369_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1414_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1414_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] $flatten\SOC.\Memory.$procmux$1414_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1432:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$877, B=0, Y=$flatten\SOC.\Memory.$procmux$1432_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1342_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1432_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1432_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] $flatten\SOC.\Memory.$procmux$1432_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1467:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$867, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1396_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_EN[31:0]$847 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1025:
      Old ports: A=$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$806, B=8'00000000, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797
      New ports: A=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1007_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1025:
      Old ports: A=$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$806, B=8'00000000, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797
      New ports: A=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1007_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0]
      New connections: $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_EN[7:0]$797 [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1449:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$873, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1414_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_EN[31:0]$853 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1458:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$870, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1432_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_EN[31:0]$850 [0] }
  Optimizing cells in module \top.
Performed a total of 25 changes.

22.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

22.11.6. Executing OPT_DFF pass (perform DFF optimizations).

22.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 3 unused cells and 169 unused wires.
<suppressed ~8 debug messages>

22.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.11.9. Rerunning OPT passes. (Maybe there is more to do..)

22.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~119 debug messages>

22.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.11.13. Executing OPT_DFF pass (perform DFF optimizations).

22.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.11.16. Finished OPT passes. (There is nothing left to do.)

22.12. Executing FSM pass (extract and optimize FSM).

22.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.
Not marking top.SOC.Core.CSR_Unit.csr_mip_mfip as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Not marking top.SOC.Core.Control_Unit.state as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state.
Not marking top.SOC.Uart.i_uart_tx.fsm_state as FSM state register:
    Users of register don't seem to benefit from recoding.

22.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'.
  found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$2068
  root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$940_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$955_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$968_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$954_Y
  found state code: 3'000
  found ctrl input: \SOC.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \SOC.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$968_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$959_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$955_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$954_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$940_Y
  ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o }
  ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$940_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$954_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$955_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$959_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$968_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'0--0 ->      3'001 8'01010001
  transition:      3'000 4'1--0 ->      3'000 8'01010000
  transition:      3'000 4'---1 ->      3'000 8'01010000
  transition:      3'010 4'--00 ->      3'010 8'00100010
  transition:      3'010 4'--10 ->      3'011 8'00100011
  transition:      3'010 4'---1 ->      3'000 8'00100000
  transition:      3'001 4'-0-0 ->      3'001 8'00011001
  transition:      3'001 4'-1-0 ->      3'010 8'00011010
  transition:      3'001 4'---1 ->      3'000 8'00011000
  transition:      3'011 4'-0-0 ->      3'011 8'10010011
  transition:      3'011 4'-1-0 ->      3'000 8'10010000
  transition:      3'011 4'---1 ->      3'000 8'10010000

22.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2210' from module `\top'.

22.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 7 unused cells and 7 unused wires.
<suppressed ~8 debug messages>

22.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2210' from module `\top'.
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].

22.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2210' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---

22.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2210' from module `top':
-------------------------------------

  Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$2210 (\SOC.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \ResetBootSystem.reset_o
    1: \SOC.Uart.i_uart_rx.payload_done
    2: \SOC.Uart.i_uart_rx.next_bit
    3: \SOC.Uart.i_uart_rx.rxd_reg

  Output signals:
    0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$968_Y
    1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$959_Y
    2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$955_Y
    3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$954_Y
    4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$940_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'1--0   ->     0 5'01010
      1:     0 4'---1   ->     0 5'01010
      2:     0 4'0--0   ->     2 5'01010
      3:     1 4'---1   ->     0 5'00100
      4:     1 4'--00   ->     1 5'00100
      5:     1 4'--10   ->     3 5'00100
      6:     2 4'---1   ->     0 5'00011
      7:     2 4'-1-0   ->     1 5'00011
      8:     2 4'-0-0   ->     2 5'00011
      9:     3 4'-1-0   ->     0 5'10010
     10:     3 4'---1   ->     0 5'10010
     11:     3 4'-0-0   ->     3 5'10010

-------------------------------------

22.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$2210' from module `\top'.

22.13. Executing OPT pass (performing simple optimizations).

22.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

22.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

22.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~118 debug messages>

22.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2080 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1291_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1285_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1276_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1267_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1258_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1249_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1231_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1240_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2260 ($sdff) from module top (D = \SOC.Uart.uart_tx_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$2260 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1285_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1276_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1267_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1258_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1249_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1231_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1240_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2078 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1207_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$2265 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1207_Y, Q = \SOC.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2077 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1196_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$2271 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$922_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2076 ($dff) from module top (D = \SOC.Uart.i_uart_tx.n_fsm_state, Q = \SOC.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$2075 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1185_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$2276 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1185_Y, Q = \SOC.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2074 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1174_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2282 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2073 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$1151_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1142_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1133_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1124_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1115_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1106_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1088_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1097_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2284 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2071 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1070_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$2288 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$962_Y, Q = \SOC.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2070 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1065_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2292 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2069 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1057_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$2294 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$973_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2067 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$2066 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$2062 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1034_Y, Q = \SOC.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2300 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$809_Y, Q = \SOC.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$2061 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1039_Y, Q = \SOC.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2302 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814_Y [5:0], Q = \SOC.Uart.TX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$2062 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1034_Y, Q = \SOC.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2304 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$809_Y, Q = \SOC.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$2061 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1039_Y, Q = \SOC.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2306 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814_Y [5:0], Q = \SOC.Uart.RX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2105 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1510_Y, Q = \SOC.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2308 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.uart_rx_data, Q = \SOC.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2104 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1515_Y, Q = \SOC.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2310 ($sdff) from module top (D = \SOC.Uart.write_data [7:0], Q = \SOC.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2103 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1520_Y, Q = \SOC.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$2312 ($sdff) from module top (D = \SOC.Uart.tx_fifo_read_data, Q = \SOC.Uart.uart_tx_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2101 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1485_Y, Q = \SOC.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2100 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1490_Y, Q = \SOC.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2099 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1495_Y, Q = \SOC.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$2097 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1500_Y, Q = \SOC.Uart.uart_tx_en, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Leds.$procdff$2096 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$1475_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2318 ($sdff) from module top (D = { 1'0 \SOC.Leds.write_data }, Q = \SOC.Leds.data).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2107 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1531_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2320 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_value).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$2106 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1539_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$2324 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_direction).
Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$2113 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$1583_Y, Q = \SOC.Core.Pc.Output, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2330 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.Output).
Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$2134 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 4'0000).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2130 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1687_Y, Q = \SOC.Core.CSR_Unit.csr_mtval, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2333 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mtval).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2129 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 1'0 \SOC.Core.CSR_Unit.csr_write_data [0] }, Q = \SOC.Core.CSR_Unit.csr_mtvec).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2128 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1713_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$2342 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2127 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1730_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2346 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mstatus_mie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2126 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1746_Y, Q = \SOC.Core.CSR_Unit.csr_mscratch, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2350 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mscratch).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2125 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1759_Y, Q = \SOC.Core.CSR_Unit.csr_minstret, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2354 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1759_Y, Q = \SOC.Core.CSR_Unit.csr_minstret).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2124 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1777_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mtie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2358 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mie_mtie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2123 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1795_Y, Q = \SOC.Core.CSR_Unit.csr_mie_msie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2362 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mie_msie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2122 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1813_Y, Q = \SOC.Core.CSR_Unit.csr_mie_meie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$2366 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [11], Q = \SOC.Core.CSR_Unit.csr_mie_meie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2121 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1831_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mfie, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2370 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [31:16], Q = \SOC.Core.CSR_Unit.csr_mie_mfie).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2120 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 2'00 }, Q = \SOC.Core.CSR_Unit.csr_mepc).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2119 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1854_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$2379 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1854_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2118 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1865_Y, Q = \SOC.Core.CSR_Unit.csr_mcause, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2383 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mcause).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2117 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_software, Q = \SOC.Core.CSR_Unit.csr_mip_msip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2116 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_timer, Q = \SOC.Core.CSR_Unit.csr_mip_mtip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2115 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_external, Q = \SOC.Core.CSR_Unit.csr_mip_meip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$2114 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_fast, Q = \SOC.Core.CSR_Unit.csr_mip_mfip, rval = 16'0000000000000000).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2086 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1323_Y, Q = \SOC.Core.pc_old, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2391 ($sdff) from module top (D = \SOC.Core.Pc.Output, Q = \SOC.Core.pc_old).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2085 ($dff) from module top (D = \SOC.Bus.write_data, Q = \SOC.Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2084 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2083 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2082 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$2081 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1328_Y, Q = \SOC.Core.instruction_register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$2397 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2133 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2132 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2131 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2374 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2374 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2337 ($dffe) from module top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$2319 ($sdffe) from module top.

22.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 130 unused cells and 126 unused wires.
<suppressed ~131 debug messages>

22.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

22.13.9. Rerunning OPT passes. (Maybe there is more to do..)

22.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~76 debug messages>

22.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$2290: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o }
  Optimizing cells in module \top.
Performed a total of 1 changes.

22.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~15 debug messages>
Removed a total of 5 cells.

22.13.13. Executing OPT_DFF pass (perform DFF optimizations).

22.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 6 unused wires.
<suppressed ~2 debug messages>

22.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.13.16. Rerunning OPT passes. (Maybe there is more to do..)

22.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+ cd Risco-5/fpga/tangnano20k/
+ /eda/gowin/IDE/bin/gw_sh run.tcl
*** GOWIN Tcl Command Line Console  *** 
current device: GW2AR-18C  GW2AR-LV18QN88C8/I7
add new file: "pinout.cst"
add new file: "top.sdc"
add new file: "main.v"
add new file: "../../debug/reset.v"
add new file: "../../src/core/alu_control.v"
add new file: "../../src/core/alu.v"
add new file: "../../src/core/control_unit.v"
add new file: "../../src/core/core.v"
add new file: "../../src/core/immediate_generator.v"
add new file: "../../src/core/mux.v"
add new file: "../../src/core/pc.v"
add new file: "../../src/core/registers.v"
add new file: "../../src/core/csr_unit.v"
add new file: "../../src/peripheral/bus.v"
add new file: "../../src/peripheral/gpio.v"
add new file: "../../src/peripheral/gpios.v"
add new file: "../../src/peripheral/leds.v"
add new file: "../../src/peripheral/memory.v"
add new file: "../../src/peripheral/soc.v"
add new file: "../../src/peripheral/uart_rx.v"
add new file: "../../src/peripheral/uart_tx.v"
add new file: "../../src/peripheral/uart.v"
add new file: "../../src/peripheral/fifo.v"
GowinSynthesis start
Running parser ...
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v'
Undeclared symbol 'pc_source', assumed default net type 'wire'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":112)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v'
WARN  (EX3801) : Parameter 'SET_DIRECTION' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":17)
WARN  (EX3801) : Parameter 'READ' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":18)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v'
WARN  (EX3012) : Empty statement in sequential block("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":40)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v'
WARN  (EX3073) : Port 'resetn_o' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":18)
Compiling module 'top'("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":1)
Compiling module 'ResetBootSystem'("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":1)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":37)
Compiling module 'Risco_5_SOC(CLOCK_FREQ=27000000,MEMORY_SIZE=2048,MEMORY_FILE="../../software/memory/fpga_test_3.hex")'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":1)
WARN  (EX3073) : Port 'C' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX3073) : Port 'D' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX3073) : Port 'D' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX3073) : Port 'C' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX3073) : Port 'interrupt_on_hold' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":188)
Compiling module 'Core(BOOT_ADDRESS=32'b00000000000000000000000000000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":1)
Compiling module 'PC'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v":1)
Compiling module 'MUX'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v":1)
Compiling module 'Registers'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v":1)
Compiling module 'Control_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":1)
Compiling module 'ALU_Control'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":1)
WARN  (EX2420) : Latch inferred for net 'aluop_out[3]'; We do not recommend the use of latches in FPGA designs, as they may lead to timing problems("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":57)
Compiling module 'Alu'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v":1)
Compiling module 'Immediate_Generator'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v":1)
Compiling module 'CSR_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":1)
WARN  (EX3780) : Using initial value of 'csr_utime' since it is never assigned("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":114)
WARN  (EX2565) : Input 'C[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'C[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (EX2565) : Input 'D[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":92)
WARN  (EX2565) : Input 'D[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'D[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":109)
WARN  (EX2565) : Input 'C[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'C[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[31]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[30]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[29]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[28]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[27]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[26]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[25]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[24]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[23]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[22]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[21]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[20]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[19]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[18]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[17]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[16]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'D[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":116)
WARN  (EX2565) : Input 'save_pc' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":188)
Compiling module 'Memory(MEMORY_FILE="../../software/memory/fpga_test_3.hex",MEMORY_SIZE=2048)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":1)
Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":15)
Compiling module 'BUS'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v":1)
Compiling module 'LEDs'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":1)
WARN  (EX3791) : Expression size 33 truncated to fit in target size 32("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":21)
Compiling module 'UART(CLOCK_FREQ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v":1)
Compiling module 'FIFO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":1)
Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":15)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":35)
Compiling module 'uart_tool_rx(CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v":10)
Compiling module 'uart_tool_tx(CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v":10)
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~76 debug messages>

22.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.20. Executing OPT_DFF pass (perform DFF optimizations).

22.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.13.23. Finished OPT passes. (There is nothing left to do.)

22.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 28 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\Control_Unit.$auto$mem.cc:328:emit$982 ($flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2139 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$2141 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$meminit$\registers$Risco-5/src/core/registers.v:16$90 (SOC.Core.RegisterBank.registers).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2136 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2137 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2138 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$882 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$842 (SOC.Memory.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2135 (SOC.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$793 (SOC.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2135 (SOC.Uart.TX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\TX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$793 (SOC.Uart.TX_FIFO.memory).
Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$1882_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$609 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608 ($add).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608 ($add).
Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$607 ($lt).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2405 ($ne).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$2410 ($ne).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:20$817 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$1482_CMP0 ($eq).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Uart.$procmux$1481 ($pmux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1031 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1019 ($mux).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$807 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$789 ($eq).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1031 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1019 ($mux).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$807 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$789 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$951 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$950 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$949 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$948 ($mux).
Removed top 2 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:111$943 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:109$941 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$917 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$909 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:135$907 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$904 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$903 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$899 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$894 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$893 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$892 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$891 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:94$887 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:92$885 ($eq).
Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$214 ($mux).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$94 ($le).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$97 ($ge).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$98 ($le).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$101 ($ge).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$102 ($le).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$105 ($ge).
Removed top 22 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$106 ($le).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:75$136 ($mux).
Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:84$152 ($mux).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$166 ($mux).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Memory.$procmux$1338_CMP0 ($eq).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1455 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1464 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1473 ($mux).
Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:100$32 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1591_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1591_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1591_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1968_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1967_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1966_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1965_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1964_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1954_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1951_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1950_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1949_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1946_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1945_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1926_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1923 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$2016_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1998_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1997_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1996_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$1984 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2029_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2028_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2027_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$2026_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$25 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$17 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1669_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1656_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1655_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1654_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1653_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1652_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1651_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1650_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1649_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1648_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$51 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$49 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$48 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$93 ($ge).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1408 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1426 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1444 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1360 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1387 ($mux).
Removed top 19 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:80$144 ($mux).
Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608_Y.
Removed top 24 bits (of 32) from wire top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$166_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$17_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$25_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\Control_Unit.$3\nextstate[3:0].
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_ADDR[31:0]$845.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$848.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$851.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$838_ADDR[31:0]$865.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$868.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$871.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$839_ADDR[31:0]$875.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$840_ADDR[31:0]$878.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$795.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$804.
Removed top 1 bits (of 8) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_DATA[7:0]$805.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814_Y.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$795.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$783_ADDR[5:0]$804.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$814_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$948_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$949_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$950_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$951_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$891_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$892_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$893_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$894_Y.

22.15. Executing PEEPOPT pass (run peephole optimizers).

22.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 33 unused wires.
<suppressed ~1 debug messages>

22.17. Executing SHARE pass (SAT-based resource sharing).
Found 4 cells in module top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$793 ($memrd):
    Found 1 activation_patterns using ctrl signal { $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:57$103_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:55$99_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$95_Y $flatten\SOC.\Uart.$procmux$1484_CMP $flatten\SOC.\Uart.$procmux$1483_CMP $flatten\SOC.\Uart.$procmux$1482_CMP }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$842 ($memrd):
    Found 7 activation_patterns using ctrl signal { $flatten\SOC.\Memory.$procmux$1339_CMP $flatten\SOC.\Memory.$procmux$1338_CMP $flatten\SOC.\Memory.$procmux$1337_CMP $flatten\SOC.\Memory.$procmux$1336_CMP \SOC.Memory.option [1:0] $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$95_Y \SOC.Bus.slave_0_write \SOC.Bus.slave_0_read }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:44$23 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2021_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:42$22 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$2022_CMP.
    No candidates found.

22.18. Executing TECHMAP pass (map to technology primitives).

22.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

22.18.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~296 debug messages>

22.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.21. Executing TECHMAP pass (map to technology primitives).

22.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

22.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

22.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

22.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15 ($sub).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$46 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$47 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$48 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$49 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$50 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$51 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$962 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$973 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$911 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$922 ($add).
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$922.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$911.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$973.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$962.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$51.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$50.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$49.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$48.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$47.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$46.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14.
  creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608.
  creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$607 ($lt): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$93 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$97 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$101 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$105 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$94 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$98 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$102 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$106 ($le): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24 ($ge): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
  creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$16 ($lt): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
  creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$609 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$607.
  creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21 ($eq): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$106: $auto$alumacc.cc:485:replace_alu$2467
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$102: $auto$alumacc.cc:485:replace_alu$2480
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$98: $auto$alumacc.cc:485:replace_alu$2493
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$94: $auto$alumacc.cc:485:replace_alu$2506
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$105: $auto$alumacc.cc:485:replace_alu$2519
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$101: $auto$alumacc.cc:485:replace_alu$2528
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$97: $auto$alumacc.cc:485:replace_alu$2537
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$93: $auto$alumacc.cc:485:replace_alu$2546
  creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$607, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$609: $auto$alumacc.cc:485:replace_alu$2555
  creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$608: $auto$alumacc.cc:485:replace_alu$2566
  creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14: $auto$alumacc.cc:485:replace_alu$2569
  creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15, $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$16, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21: $auto$alumacc.cc:485:replace_alu$2572
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$46: $auto$alumacc.cc:485:replace_alu$2585
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$47: $auto$alumacc.cc:485:replace_alu$2588
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$48: $auto$alumacc.cc:485:replace_alu$2591
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$49: $auto$alumacc.cc:485:replace_alu$2594
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$50: $auto$alumacc.cc:485:replace_alu$2597
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$51: $auto$alumacc.cc:485:replace_alu$2600
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808: $auto$alumacc.cc:485:replace_alu$2603
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786: $auto$alumacc.cc:485:replace_alu$2606
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813: $auto$alumacc.cc:485:replace_alu$2609
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$808: $auto$alumacc.cc:485:replace_alu$2612
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$786: $auto$alumacc.cc:485:replace_alu$2615
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$813: $auto$alumacc.cc:485:replace_alu$2618
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$962: $auto$alumacc.cc:485:replace_alu$2621
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$973: $auto$alumacc.cc:485:replace_alu$2624
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$911: $auto$alumacc.cc:485:replace_alu$2627
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$922: $auto$alumacc.cc:485:replace_alu$2630
  created 28 $alu and 0 $macc cells.

22.23. Executing OPT pass (performing simple optimizations).

22.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

22.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~10 debug messages>
Removed a total of 2 cells.

22.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~76 debug messages>

22.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.23.6. Executing OPT_DFF pass (perform DFF optimizations).

22.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 19 unused wires.
<suppressed ~1 debug messages>

22.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.23.9. Rerunning OPT passes. (Maybe there is more to do..)

22.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~76 debug messages>

22.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.23.13. Executing OPT_DFF pass (perform DFF optimizations).
Compiling module 'GPIOS(WIDHT=5)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":1)
Compiling module 'GPIO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v":1)
WARN  (EX2565) : Input 'instruction_request_external' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_timer' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_software' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
WARN  (EX2565) : Input 'instruction_request_fast[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":38)
NOTE  (EX0101) : Current top module is "top"
WARN  (EX0211) : The output port "interrupt_on_hold" of module "CSR_Unit" has no driver, assigning undriven bits to Z, simulation mismatch possible("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":20)
[5%] Running netlist conversion ...
WARN  (CV0016) : Input reset is unused("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":3)
Running device independent optimization ...

22.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.23.16. Finished OPT passes. (There is nothing left to do.)

22.24. Executing MEMORY pass.

22.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

22.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

22.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing top.SOC.Core.RegisterBank.registers write port 0.
  Analyzing top.SOC.Core.RegisterBank.registers write port 1.
  Analyzing top.SOC.Core.RegisterBank.registers write port 2.
  Analyzing top.SOC.Memory.memory write port 0.
  Analyzing top.SOC.Memory.memory write port 1.
  Analyzing top.SOC.Memory.memory write port 2.
  Analyzing top.SOC.Uart.RX_FIFO.memory write port 0.
  Analyzing top.SOC.Uart.TX_FIFO.memory write port 0.

22.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

22.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980'[0] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[0] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[1] in module `\top': merging output FF to cell.
    Write port 0: don't care on collision.
    Write port 1: non-transparent.
    Write port 2: non-transparent.
Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found.
Checking read port `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': no output FF found.
Checking read port `\SOC.Uart.TX_FIFO.memory'[0] in module `\top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port address `$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980'[0] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Core.RegisterBank.registers'[0] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found.
Checking read port address `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': merged address FF to cell.

22.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 44 unused wires.
<suppressed ~7 debug messages>

22.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
  Merging ports 0, 2 (address 5'00000).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Memory.memory by address:
  Merging ports 0, 1 (address \SOC.Memory.address [12:2]).
  Merging ports 0, 2 (address \SOC.Memory.address [12:2]).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers using sat-based resource sharing:
  Checking group clocked with posedge \clk, width 32: ports 0, 1.
  Common input cone for all EN signals: 6 cells.
  Size of unconstrained SAT problem: 40 variables, 98 clauses
  Merging port 1 into port 0.

22.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

22.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 8 unused cells and 8 unused wires.
<suppressed ~9 debug messages>

22.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

22.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
using FF mapping for memory top.$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980
mapping memory top.SOC.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_
Extracted data FF from read port 1 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[1]
mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory top.SOC.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted addr FF from read port 0 of top.SOC.Uart.RX_FIFO.memory: $\SOC.Uart.RX_FIFO.memory$rdreg[0]
mapping memory top.SOC.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of top.SOC.Uart.TX_FIFO.memory: $\SOC.Uart.TX_FIFO.memory$rdreg[0]
<suppressed ~1100 debug messages>

22.27. Executing TECHMAP pass (map to technology primitives).

22.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

22.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

22.27.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$8e5e72577b4c3b167a98ad5915719acd6a2ff3f4\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$58f24e643e5858c811559272a02c6d84f974d8a6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b7ec8ee89a7cd4851359941621e9dedf8c3b7d83\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$6d2a7df30888468e46c2233cf858b33a106d24cc\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$1a510b238205ce75968c294c5a2f9682007038e9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$d697ed060a7caa7345cbd011d88bf1d0e8cd46a0\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$882b16869816e01f56a454af0eb6e24b6778fa0c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b6fd6d9e43fa3d8e6bc64941b5b57ab422f7e603\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$983d377398e8a630797eecf765a80311ec60d100\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c8ec1437ade7762ec3882c3e3f576764a2f7bb09\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$1de9eb29388171a23037c69580dd741dfa07544f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$ccbfc2f8b7417ea49ec4f806e284aeee31f607b3\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
[25%] Optimizing Phase 2 completed
Running inference ...
Using template $paramod$b1d6656f42d8fe2eb2a963373a2667cf617d2bc5\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$80ae742e83efa97f5ae3dddd041ab9a1ef9ac7b6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$9a18a5918aa94986c2ace7118a70e41127dc33df\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c4c009ae968ecf5722a8a929fbdc163f47dedcc6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$7e65f9170886a0570d9059c94eef599a8e7c0c53\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$88ca364434c15edf84547ebc10bbf93659adea39\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$219b7093d2a2ec9427a92a1f7d983c7335efd508\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$0f1e956af4a0dd7da6349454a915a33336b22174\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$20534e299f87b4db290b2588b7ce04615b91104c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$73e415998dfd4e0d8b84ec3ac6390921a6a2c53b\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$7d81e3db939f1224434306a374696f893743b990\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$060a68a0493c8190183716105f9d8172975de01f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~1403 debug messages>

22.28. Executing OPT pass (performing simple optimizations).

22.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~146 debug messages>

22.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~21 debug messages>
Removed a total of 7 cells.

22.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $\SOC.Uart.RX_FIFO.memory$rdreg[0] ($dff) from module top (D = $auto$rtlil.cc:2582:Mux$2684, Q = $\SOC.Uart.RX_FIFO.memory$rdreg[0]$q, rval = 3'000).
Adding SRST signal on $auto$ff.cc:266:slice$2399 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$1879_Y, Q = \ResetBootSystem.counter, rval = 6'000000).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2387 ($sdff) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$2390 ($sdff) from module top.

22.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
Finding unused cells or wires in module \top..
Removed 21 unused cells and 7501 unused wires.
<suppressed ~22 debug messages>

22.28.5. Rerunning OPT passes. (Removed registers in this run.)

22.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

22.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$5133 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$2425 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).

22.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 3 unused cells and 3 unused wires.
<suppressed ~4 debug messages>

22.28.10. Rerunning OPT passes. (Removed registers in this run.)

22.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.28.13. Executing OPT_DFF pass (perform DFF optimizations).

22.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.28.15. Finished fast OPT passes.

22.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
Mapping memory $flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980 in module \top:
  created 16 $dff cells and 0 static cells of width 18.
  read interface: 0 $dff and 15 $mux cells.
  write interface: 0 write mux blocks.

22.30. Executing OPT pass (performing simple optimizations).

22.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$2706: $auto$rtlil.cc:2489:ReduceOr$2700 -> 1'1
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~59 debug messages>

22.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][6]$5178:
      Old ports: A=18'010000010000000000, B=18'010000011000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$5158
      New ports: A=1'0, B=1'1, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$5158 [9]
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$5158 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$5158 [8:0] } = 17'01000001000000000
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][5]$5175:
      Old ports: A=18'000000001010100100, B=18'101000010000000101, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$5156
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$5156 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$5156 [0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$5156 [17:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$5156 [4:1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$5156 [0] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$5156 [0] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$5156 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$5156 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$5156 [5] 5'00010 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][4]$5172:
      Old ports: A=18'010000001100000001, B=18'101000010000000100, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$5155
      New ports: A=2'01, B=2'10, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$5155 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$5155 [0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$5155 [17:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$5155 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$5155 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$5155 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$5155 [2] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$5155 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$5155 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$5155 [0] 6'000000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][3]$5169:
      Old ports: A=18'000000001100000000, B=18'000000000000001000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$5153
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$5153 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$5153 [3] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$5153 [17:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$5153 [7:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$5153 [2:0] } = { 8'00000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$5153 [8] 7'0000000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][2]$5166:
      Old ports: A=18'000000100000001000, B=18'000000000000010010, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$5152
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$5152 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$5152 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$5152 [17:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$5152 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$5152 [0] } = { 6'000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$5152 [3] 6'000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$5152 [1] 2'00 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][1]$5163:
      Old ports: A=18'010000001000000000, B=18'000010000000000010, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$5150
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$5150 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$5150 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$5150 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$5150 [8:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$5150 [0] } = { 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$5150 [9] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$5150 [1] 11'00000000000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][0]$5160:
      Old ports: A=18'101110000000000000, B=18'010000010000000000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$5149
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$5149 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$5149 [10] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$5149 [17:14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$5149 [12:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$5149 [9:0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$5149 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$5149 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$5149 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$5149 [13] 12'000000000000 }
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$2691:
      Old ports: A={ \SOC.Memory.buffer [31:16] \SOC.Memory.write_data [15:0] }, B=\SOC.Memory.write_data, Y=$auto$rtlil.cc:2582:Mux$2692
      New ports: A=\SOC.Memory.buffer [31:16], B=\SOC.Memory.write_data [31:16], Y=$auto$rtlil.cc:2582:Mux$2692 [31:16]
      New connections: $auto$rtlil.cc:2582:Mux$2692 [15:0] = \SOC.Memory.write_data [15:0]
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$1888: { $flatten\ResetBootSystem.$procmux$1883_CMP $flatten\ResetBootSystem.$procmux$1882_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1891:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$1891_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$1891_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$1891_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$1984:
      Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$2427 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$2427 [2]
      New connections: $auto$wreduce.cc:461:run$2427 [1:0] = 2'10
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$2005:
      Old ports: A=4'0110, B=12'101101111110, Y=$flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0]
      New ports: A=3'010, B=9'101011110, Y={ $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [3:2] $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [0] }
      New connections: $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [1] = 1'1
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1643: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1664_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1663_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1656_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1655_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1654_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1653_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1652_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1651_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1650_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1649_CMP $auto$opt_reduce.cc:134:opt_pmux$2191 $auto$opt_reduce.cc:134:opt_pmux$2189 $auto$opt_reduce.cc:134:opt_pmux$2187 $auto$opt_reduce.cc:134:opt_pmux$2185 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][3][7]$5181:
      Old ports: A=18'010000001000000000, B=18'000001000001001000, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$5159
      New ports: A=2'10, B=2'01, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$5159 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$5159 [3] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$5159 [17:10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$5159 [8:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$5159 [2:0] } = { 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$5159 [9] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$5159 [3] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$5159 [3] 5'00000 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1923:
      Old ports: A=3'101, B=3'011, Y=$auto$wreduce.cc:461:run$2431 [2:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$2431 [2:1]
      New connections: $auto$wreduce.cc:461:run$2431 [0] = 1'1
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1599:
      Old ports: A={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] }, B={ 27'000000000000000000000000000 \SOC.Core.instruction_register [24:20] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0]
      New ports: A=\SOC.Core.instruction_register [24], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [31:6] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] \SOC.Core.instruction_register [24:20] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1626:
      Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, B={ 19'0000000000000000000 \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0]
      New ports: A=\SOC.Core.instruction_register [31], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [31:14] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Memory.$procmux$1335:
      Old ports: A=\SOC.Memory.buffer, B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7:0] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:0] 24'000000000000000000000000 \SOC.Memory.buffer [7:0] 16'0000000000000000 \SOC.Memory.buffer [15:0] }, Y=\SOC.Bus.slave_0_read_data
      New ports: A=\SOC.Memory.buffer [31:8], B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:8] 40'0000000000000000000000000000000000000000 \SOC.Memory.buffer [15:8] }, Y=\SOC.Bus.slave_0_read_data [31:8]
      New connections: \SOC.Bus.slave_0_read_data [7:0] = \SOC.Memory.buffer [7:0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_rx.$procmux$1169:
      Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$2449 [0] 1'0 $auto$wreduce.cc:461:run$2450 [1:0] 2'01 \SOC.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$2452 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$2449 [0] $auto$wreduce.cc:461:run$2450 [1:0] 1'1 \SOC.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$2452 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$951:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2452 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2452 [0]
      New connections: $auto$wreduce.cc:461:run$2452 [1] = $auto$wreduce.cc:461:run$2452 [0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$1306:
      Old ports: A=3'000, B={ 2'00 \SOC.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$2454 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$2456 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \SOC.Uart.uart_tx_en $auto$wreduce.cc:461:run$2454 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$2456 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$894:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$2456 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$2456 [0]
      New connections: $auto$wreduce.cc:461:run$2456 [1] = $auto$wreduce.cc:461:run$2456 [0]
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$5157:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$5158, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$5159, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$5147
      New ports: A={ 2'11 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$a$5158 [9] 1'0 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$5159 [9] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$5159 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][3]$b$5159 [3] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$5147 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$5147 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$5147 [3] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$5147 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$5147 [15:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$5147 [8:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$5147 [2:0] } = { 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$5147 [3] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$5147 [3] 5'00000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$5154:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$5155, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$5156, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$5155 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$5155 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$5155 [0] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$5155 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$a$5155 [0] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$5156 [0] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$5156 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$5156 [5] 1'1 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][2]$b$5156 [0] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [17:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [7:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [4:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [10] 4'0000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [5] 4'0000 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$5151:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$5152, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$5153, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$5152 [3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$5152 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$a$5152 [1] }, B={ 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$5153 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][1]$b$5153 [3] 1'0 }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144 [11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144 [17:12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144 [7:4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144 [0] } = { 7'0000000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144 [8] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144 [1] 2'00 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$5148:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$5149, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$5150, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$5143
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$5149 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$5149 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$5149 [13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$a$5149 [10] 2'00 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$5150 [9] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$5150 [1] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$5150 [9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][2][0]$b$5150 [1] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$5143 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$5143 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$5143 [10:9] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$5143 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$5143 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$5143 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$5143 [12:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$5143 [8:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$5143 [0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$5143 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$5143 [14] 10'0000000000 }
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$2695:
      Old ports: A=$auto$rtlil.cc:2582:Mux$2692, B={ \SOC.Memory.buffer [31:8] \SOC.Memory.write_data [7:0] }, Y=$auto$rtlil.cc:2582:Mux$2696
      New ports: A={ $auto$rtlil.cc:2582:Mux$2692 [31:16] \SOC.Memory.write_data [15:8] }, B=\SOC.Memory.buffer [31:8], Y=$auto$rtlil.cc:2582:Mux$2696 [31:8]
      New connections: $auto$rtlil.cc:2582:Mux$2696 [7:0] = \SOC.Memory.write_data [7:0]
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1897:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$1891_Y, Y=$flatten\ResetBootSystem.$procmux$1897_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$1891_Y [1], Y=$flatten\ResetBootSystem.$procmux$1897_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$1897_Y [0] = 1'0
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1610:
      Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:20] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] 20'00000000000000000000 \SOC.Core.instruction_register [31:20] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0]
      New ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:25] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] 1'0 \SOC.Core.instruction_register [31:25] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12:5]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [31:13] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] \SOC.Core.instruction_register [24:20] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$5145:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$5147, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [10] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$a$5146 [0] }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$5147 [16] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$5147 [10:9] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][1]$b$5147 [3] 2'00 }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [16:15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [3:2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [0] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [14:11] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [7:6] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [4] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [1] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [15] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [3] 2'00 }
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$5142:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$5143, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144, Y=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$5143 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$5143 [14:13] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$5143 [10:9] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$a$5143 [1] }, B={ 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144 [11] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144 [8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144 [1] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][1][0]$b$5144 [1] }, Y={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [11:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [4:3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [1] }
      New connections: { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [17] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [15] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [12] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [7:5] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [2] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [0] } = { $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [14] 6'000000 }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$5139:
      Old ports: A=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140, B=$memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141, Y={ \SOC.Core.pc_write \SOC.Core.AluInputBMUX.option \SOC.Core.Control_Unit.ir_write \SOC.Bus.read \SOC.Core.MemoryDataMUX.option \SOC.Core.AluInputAMUX.option \SOC.Core.ALU_Control.aluop_in \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond \SOC.Bus.write \SOC.Core.Control_Unit.reg_write \SOC.Core.PCSourceMUX.option [0] \SOC.Core.MemoryAddressMUX.option [0] \SOC.Core.ALU_Control.is_immediate }
      New ports: A={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [16] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [14] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [14:13] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [11:8] 2'00 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [4:3] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$a$5140 [1] 1'0 }, B={ $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [16:15] 3'000 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [10:8] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [3] $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [5] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [3:2] 1'0 $memory$flatten\SOC.\Core.\Control_Unit.$auto$proc_rom.cc:155:do_switch$980$rdmux[0][0][0]$b$5141 [0] }, Y={ \SOC.Core.AluInputBMUX.option \SOC.Core.Control_Unit.ir_write \SOC.Bus.read \SOC.Core.MemoryDataMUX.option [0] \SOC.Core.AluInputAMUX.option \SOC.Core.ALU_Control.aluop_in [1] \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond \SOC.Bus.write \SOC.Core.Control_Unit.reg_write \SOC.Core.PCSourceMUX.option [0] \SOC.Core.MemoryAddressMUX.option [0] \SOC.Core.ALU_Control.is_immediate }
      New connections: { \SOC.Core.pc_write \SOC.Core.MemoryDataMUX.option [1] \SOC.Core.ALU_Control.aluop_in [0] } = { \SOC.Core.AluInputBMUX.option [0] \SOC.Core.CSR_Unit.csr_write_enable \SOC.Core.pc_write_cond }
  Optimizing cells in module \top.
Performed a total of 34 changes.

22.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~15 debug messages>
Removed a total of 5 cells.

22.30.6. Executing OPT_DFF pass (perform DFF optimizations).

22.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 22 unused wires.
<suppressed ~2 debug messages>

22.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~1 debug messages>

22.30.9. Rerunning OPT passes. (Maybe there is more to do..)

22.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~62 debug messages>

22.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.30.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$2275 ($sdff) from module top.

22.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

22.30.16. Rerunning OPT passes. (Maybe there is more to do..)

22.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~62 debug messages>

22.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.30.20. Executing OPT_DFF pass (perform DFF optimizations).

22.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.30.23. Finished OPT passes. (There is nothing left to do.)

22.31. Executing TECHMAP pass (map to technology primitives).

22.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

22.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

22.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $bmux.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $logic_not.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux.
Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $and.
Using template $paramod$21b43a343f2bc4ba62df8a2c90631d371d8e7ce8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $tribuf.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu.
Using template $paramod$91e5b74f11633b3386c40b03efcf15406a306835\_80_ecp5_alu for cells of type $alu.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$d16a138d50c5473e76a26446ec9bb0a651b19901\_80_ecp5_alu for cells of type $alu.
Using template $paramod$531b0e8664cf0177363f10a943e616839f246c95\_80_ecp5_alu for cells of type $alu.
Using template $paramod$19e9557905baa9d3741d0daa66e2ef076e9bab7d\_90_pmux for cells of type $pmux.
Using template $paramod$bf541dd3c0ba8228982b61e7bfbc350a2c253f4c\_90_demux for cells of type $demux.
Using template $paramod$f1fc4bc1d42e857fca43ce0fdd0da6ff25c612c4\_90_pmux for cells of type $pmux.
Using template $paramod$4d45682f6d5f8751d24fc75184ef72226da353f7\_90_pmux for cells of type $pmux.
Using template $paramod$a13703aa027da371a1931fc542d213d7de559b19\_90_pmux for cells of type $pmux.
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $dlatch.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$56955d0f36f77738c952d3505dc563df3ee11b94\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$a5f0941832cc861549e29ccafffe20bfdf2e5528\_90_pmux for cells of type $pmux.
Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod$e4e871699ef984d49b67460a907fd39b385c5c53\_90_demux for cells of type $demux.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~4581 debug messages>

22.32. Executing OPT pass (performing simple optimizations).

22.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~9819 debug messages>

22.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~4272 debug messages>
Removed a total of 1424 cells.

22.32.3. Executing OPT_DFF pass (perform DFF optimizations).

22.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 631 unused cells and 4263 unused wires.
<suppressed ~632 debug messages>

22.32.5. Finished fast OPT passes.

22.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

22.35. Executing TECHMAP pass (map to technology primitives).

22.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

22.35.2. Continuing TECHMAP pass.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_.
No more expansions possible.
<suppressed ~817 debug messages>

22.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~22 debug messages>

22.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

22.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in top.

22.39. Executing ATTRMVCP pass (move or copy attributes).

22.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3995 unused wires.
<suppressed ~1 debug messages>

22.41. Executing TECHMAP pass (map to technology primitives).

22.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

22.41.2. Continuing TECHMAP pass.

22.41.3. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping \$_DLATCH_N_.$ternary$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$31353 ($mux).
Mapping \$_DLATCH_N_.$logic_not$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$31352 ($logic_not).
<suppressed ~4 debug messages>

22.41.4. Executing OPT pass (performing simple optimizations).

22.41.4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.
<suppressed ~1 debug messages>

22.41.4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

22.41.4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.41.4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

22.41.4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

22.41.4.6. Executing OPT_DFF pass (perform DFF optimizations).

22.41.4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..
Removed 1 unused cells and 2 unused wires.
<suppressed ~2 debug messages>

22.41.4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

22.41.4.9. Rerunning OPT passes. (Maybe there is more to do..)

22.41.4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.41.4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

22.41.4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

22.41.4.13. Executing OPT_DFF pass (perform DFF optimizations).

22.41.4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..

22.41.4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

22.41.4.16. Finished OPT passes. (There is nothing left to do.)
Using template \$_DLATCH_N_ for cells of type $_DLATCH_N_.
No more expansions possible.
<suppressed ~4 debug messages>

22.42. Executing ABC9 pass.

22.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.3. Executing PROC pass (convert processes to netlists).

22.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31457'.
Cleaned up 1 empty switch.

22.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31458 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.3.4. Executing PROC_INIT pass (extract init attributes).

22.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31458'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31456_EN[3:0]$31464
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31456_DATA[3:0]$31463
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31456_ADDR[3:0]$31462
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31457'.

22.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31444_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31449_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31441_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31454_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31446_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31455_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31451_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31447_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31440_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31452_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31442_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31450_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31445_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31453_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31448_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31443_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31456_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31458'.
  created $dff cell `$procdff$31508' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31456_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31458'.
  created $dff cell `$procdff$31509' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31456_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31458'.
  created $dff cell `$procdff$31510' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31457'.
  created direct connection (no actual register cell created).

22.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31482'.
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31458'.
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31457'.
Cleaned up 1 empty switch.

22.42.3.12. Executing OPT_EXPR pass (perform const folding).

22.42.4. Executing PROC pass (convert processes to netlists).

22.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31528'.
Cleaned up 1 empty switch.

22.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31529 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.4.4. Executing PROC_INIT pass (extract init attributes).

22.42.4.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31529'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31527_EN[3:0]$31534
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31527_DATA[3:0]$31535
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31527_ADDR[3:0]$31533
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31528'.

22.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31511_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31518_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31522_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31519_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31524_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31525_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31523_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31515_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31513_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31517_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31520_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31514_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31512_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31526_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31521_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31516_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31527_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31529'.
  created $dff cell `$procdff$31579' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31527_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31529'.
  created $dff cell `$procdff$31580' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31527_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31529'.
  created $dff cell `$procdff$31581' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31528'.
  created direct connection (no actual register cell created).

22.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31553'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31529'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31528'.
Cleaned up 1 empty switch.

22.42.4.12. Executing OPT_EXPR pass (perform const folding).

22.42.5. Executing PROC pass (convert processes to netlists).

22.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31599'.
Cleaned up 1 empty switch.

22.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31600 in module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.5.4. Executing PROC_INIT pass (extract init attributes).

22.42.5.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
Creating decoders for process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31600'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31598_EN[3:0]$31605
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31598_DATA[3:0]$31606
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31598_ADDR[3:0]$31604
Creating decoders for process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31599'.

22.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.\i' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31585_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31590_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31591_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31587_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31596_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31595_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31588_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31597_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31592_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31583_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31586_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31593_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31594_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31589_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31584_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31582_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31598_ADDR' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31600'.
  created $dff cell `$procdff$31650' with positive edge clock.
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31598_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31600'.
  created $dff cell `$procdff$31651' with positive edge clock.
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31598_DATA' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31600'.
  created $dff cell `$procdff$31652' with positive edge clock.
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31599'.
  created direct connection (no actual register cell created).

22.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31624'.
Found and cleaned up 1 empty switch in `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31600'.
Removing empty process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31599'.
Cleaned up 1 empty switch.

22.42.5.12. Executing OPT_EXPR pass (perform const folding).

22.42.6. Executing PROC pass (convert processes to netlists).

22.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31670'.
Cleaned up 1 empty switch.

22.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31671 in module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.6.4. Executing PROC_INIT pass (extract init attributes).

22.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
Creating decoders for process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31671'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31669_EN[3:0]$31675
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31669_DATA[3:0]$31676
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31669_ADDR[3:0]$31677
Creating decoders for process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31670'.

22.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31662_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.\i' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31656_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31668_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31660_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31659_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31655_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31666_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31665_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31661_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31667_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31664_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31658_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31653_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31654_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31663_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31657_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31669_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31671'.
  created $dff cell `$procdff$31721' with positive edge clock.
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31669_DATA' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31671'.
  created $dff cell `$procdff$31722' with positive edge clock.
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31669_ADDR' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31671'.
  created $dff cell `$procdff$31723' with positive edge clock.
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.\muxwre' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31670'.
  created direct connection (no actual register cell created).

22.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31695'.
Found and cleaned up 1 empty switch in `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31671'.
Removing empty process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31670'.
Cleaned up 1 empty switch.

22.42.6.12. Executing OPT_EXPR pass (perform const folding).

22.42.7. Executing PROC pass (convert processes to netlists).

22.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31741'.
Cleaned up 1 empty switch.

22.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31742 in module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.7.4. Executing PROC_INIT pass (extract init attributes).

22.42.7.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
Creating decoders for process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31742'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31740_EN[3:0]$31747
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31740_DATA[3:0]$31748
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31740_ADDR[3:0]$31746
Creating decoders for process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31741'.

22.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.\i' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31728_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31735_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31724_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31729_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31734_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31730_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31726_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31736_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31725_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31731_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31732_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31737_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31738_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31739_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31733_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31727_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31740_ADDR' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31742'.
  created $dff cell `$procdff$31792' with positive edge clock.
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31740_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31742'.
  created $dff cell `$procdff$31793' with positive edge clock.
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31740_DATA' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31742'.
  created $dff cell `$procdff$31794' with positive edge clock.
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.\muxwre' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31741'.
  created direct connection (no actual register cell created).

22.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31766'.
Found and cleaned up 1 empty switch in `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31742'.
Removing empty process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31741'.
Cleaned up 1 empty switch.

22.42.7.12. Executing OPT_EXPR pass (perform const folding).

22.42.8. Executing PROC pass (convert processes to netlists).

22.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31812'.
Cleaned up 1 empty switch.

22.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31813 in module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.8.4. Executing PROC_INIT pass (extract init attributes).

22.42.8.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.8.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
Creating decoders for process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31813'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31811_EN[3:0]$31819
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31811_DATA[3:0]$31818
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31811_ADDR[3:0]$31817
Creating decoders for process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31812'.

22.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.\i' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31798_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31799_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31804_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31805_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31806_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31810_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31796_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31802_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31801_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31807_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31808_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31800_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31809_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31803_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31797_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31795_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31811_ADDR' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31813'.
  created $dff cell `$procdff$31863' with positive edge clock.
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31811_DATA' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31813'.
  created $dff cell `$procdff$31864' with positive edge clock.
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31811_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31813'.
  created $dff cell `$procdff$31865' with positive edge clock.
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.\muxwre' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31812'.
  created direct connection (no actual register cell created).

22.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31837'.
Found and cleaned up 1 empty switch in `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31813'.
Removing empty process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31812'.
Cleaned up 1 empty switch.

22.42.8.12. Executing OPT_EXPR pass (perform const folding).

22.42.9. Executing PROC pass (convert processes to netlists).

22.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31883'.
Cleaned up 1 empty switch.

22.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31884 in module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.9.4. Executing PROC_INIT pass (extract init attributes).

22.42.9.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.9.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
Creating decoders for process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31884'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31882_EN[3:0]$31890
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31882_DATA[3:0]$31889
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31882_ADDR[3:0]$31888
Creating decoders for process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31883'.

22.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.\i' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31866_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31868_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31869_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31870_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31876_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31880_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31881_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31871_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31872_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31877_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31878_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31875_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31874_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31879_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31873_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31867_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31882_ADDR' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31884'.
  created $dff cell `$procdff$31934' with positive edge clock.
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31882_DATA' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31884'.
  created $dff cell `$procdff$31935' with positive edge clock.
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31882_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31884'.
  created $dff cell `$procdff$31936' with positive edge clock.
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.\muxwre' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31883'.
  created direct connection (no actual register cell created).

22.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31908'.
Found and cleaned up 1 empty switch in `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31884'.
Removing empty process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31883'.
Cleaned up 1 empty switch.

22.42.9.12. Executing OPT_EXPR pass (perform const folding).

22.42.10. Executing PROC pass (convert processes to netlists).

22.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31954'.
Cleaned up 1 empty switch.

22.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31955 in module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.10.4. Executing PROC_INIT pass (extract init attributes).

22.42.10.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.10.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
Creating decoders for process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31955'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31953_EN[3:0]$31961
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31953_DATA[3:0]$31960
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31953_ADDR[3:0]$31959
Creating decoders for process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31954'.

22.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.\i' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31937_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31938_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31939_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31940_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31944_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31945_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31946_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31950_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31951_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31941_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31952_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31942_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31947_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31948_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31949_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31943_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31953_ADDR' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31955'.
  created $dff cell `$procdff$32005' with positive edge clock.
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31953_DATA' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31955'.
  created $dff cell `$procdff$32006' with positive edge clock.
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31953_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31955'.
  created $dff cell `$procdff$32007' with positive edge clock.
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.\muxwre' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31954'.
  created direct connection (no actual register cell created).

22.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31979'.
Found and cleaned up 1 empty switch in `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31955'.
Removing empty process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31954'.
Cleaned up 1 empty switch.

22.42.10.12. Executing OPT_EXPR pass (perform const folding).

22.42.11. Executing PROC pass (convert processes to netlists).

22.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32025'.
Cleaned up 1 empty switch.

22.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32026 in module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.11.4. Executing PROC_INIT pass (extract init attributes).

22.42.11.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.11.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
Creating decoders for process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32026'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32024_EN[3:0]$32030
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32024_DATA[3:0]$32032
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32024_ADDR[3:0]$32031
Creating decoders for process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32025'.

22.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.\i' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32008_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32009_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32010_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32014_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32015_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32021_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32016_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32020_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32022_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32018_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32023_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32011_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32012_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32017_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32019_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32013_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32024_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32026'.
  created $dff cell `$procdff$32076' with positive edge clock.
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32024_ADDR' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32026'.
  created $dff cell `$procdff$32077' with positive edge clock.
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32024_DATA' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32026'.
  created $dff cell `$procdff$32078' with positive edge clock.
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.\muxwre' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32025'.
  created direct connection (no actual register cell created).

22.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32050'.
Found and cleaned up 1 empty switch in `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32026'.
Removing empty process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32025'.
Cleaned up 1 empty switch.

22.42.11.12. Executing OPT_EXPR pass (perform const folding).

22.42.12. Executing PROC pass (convert processes to netlists).

22.42.12.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32096'.
Cleaned up 1 empty switch.

22.42.12.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32097 in module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.12.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.12.4. Executing PROC_INIT pass (extract init attributes).

22.42.12.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.12.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.12.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
Creating decoders for process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32097'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32095_EN[3:0]$32102
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32095_DATA[3:0]$32101
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32095_ADDR[3:0]$32103
Creating decoders for process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32096'.

22.42.12.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.12.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.\i' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32079_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32084_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32080_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32094_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32088_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32093_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32085_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32086_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32090_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32091_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32081_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32092_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32082_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32087_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32089_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32083_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32095_DATA' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32097'.
  created $dff cell `$procdff$32147' with positive edge clock.
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32095_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32097'.
  created $dff cell `$procdff$32148' with positive edge clock.
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32095_ADDR' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32097'.
  created $dff cell `$procdff$32149' with positive edge clock.
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32096'.
  created direct connection (no actual register cell created).

22.42.12.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.12.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32121'.
Found and cleaned up 1 empty switch in `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32097'.
Removing empty process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32096'.
Cleaned up 1 empty switch.

22.42.12.12. Executing OPT_EXPR pass (perform const folding).

22.42.13. Executing PROC pass (convert processes to netlists).

22.42.13.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32167'.
Cleaned up 1 empty switch.

22.42.13.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32168 in module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.13.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.13.4. Executing PROC_INIT pass (extract init attributes).

22.42.13.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.13.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.13.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
Creating decoders for process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32168'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32166_EN[3:0]$32174
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32166_DATA[3:0]$32173
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32166_ADDR[3:0]$32172
Creating decoders for process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32167'.

22.42.13.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.13.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.\i' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32150_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32154_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32155_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32156_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32160_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32161_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32151_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32162_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32152_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32157_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32158_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32163_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32164_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32165_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32159_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32153_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32166_ADDR' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32168'.
  created $dff cell `$procdff$32218' with positive edge clock.
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32166_DATA' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32168'.
  created $dff cell `$procdff$32219' with positive edge clock.
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32166_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32168'.
  created $dff cell `$procdff$32220' with positive edge clock.
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.\muxwre' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32167'.
  created direct connection (no actual register cell created).

22.42.13.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.13.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32192'.
Found and cleaned up 1 empty switch in `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32168'.
Removing empty process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32167'.
Cleaned up 1 empty switch.

22.42.13.12. Executing OPT_EXPR pass (perform const folding).

22.42.14. Executing PROC pass (convert processes to netlists).

22.42.14.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32238'.
Cleaned up 1 empty switch.

22.42.14.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32239 in module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.14.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.14.4. Executing PROC_INIT pass (extract init attributes).

22.42.14.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.14.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.14.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
Creating decoders for process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32239'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32237_EN[3:0]$32245
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32237_DATA[3:0]$32244
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32237_ADDR[3:0]$32243
Creating decoders for process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32238'.

22.42.14.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.14.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.\i' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32224_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32225_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32226_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32230_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32231_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32232_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32236_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32222_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32227_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32228_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32233_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32234_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32235_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32229_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32223_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32221_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32237_ADDR' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32239'.
  created $dff cell `$procdff$32289' with positive edge clock.
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32237_DATA' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32239'.
  created $dff cell `$procdff$32290' with positive edge clock.
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32237_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32239'.
  created $dff cell `$procdff$32291' with positive edge clock.
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32238'.
  created direct connection (no actual register cell created).

22.42.14.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.14.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32263'.
Found and cleaned up 1 empty switch in `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32239'.
Removing empty process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32238'.
Cleaned up 1 empty switch.

22.42.14.12. Executing OPT_EXPR pass (perform const folding).

****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

source run.tcl
# read_verilog "main.v"

22.42.15. Executing PROC pass (convert processes to netlists).

22.42.15.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32309'.
Cleaned up 1 empty switch.

22.42.15.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32310 in module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.15.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.15.4. Executing PROC_INIT pass (extract init attributes).

22.42.15.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.15.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.15.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
Creating decoders for process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32310'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32308_EN[3:0]$32316
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32308_DATA[3:0]$32315
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32308_ADDR[3:0]$32314
Creating decoders for process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32309'.

22.42.15.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.15.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.\i' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32292_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32294_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32295_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32296_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32300_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32301_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32302_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32306_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32307_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32297_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32298_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32303_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32304_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32305_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32299_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32293_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32308_ADDR' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32310'.
  created $dff cell `$procdff$32360' with positive edge clock.
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32308_DATA' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32310'.
  created $dff cell `$procdff$32361' with positive edge clock.
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32308_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32310'.
  created $dff cell `$procdff$32362' with positive edge clock.
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32309'.
  created direct connection (no actual register cell created).

22.42.15.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.15.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32334'.
Found and cleaned up 1 empty switch in `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32310'.
Removing empty process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32309'.
Cleaned up 1 empty switch.

22.42.15.12. Executing OPT_EXPR pass (perform const folding).

22.42.16. Executing PROC pass (convert processes to netlists).

22.42.16.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32380'.
Cleaned up 1 empty switch.

22.42.16.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32381 in module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.16.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.16.4. Executing PROC_INIT pass (extract init attributes).

22.42.16.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.16.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.16.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
Creating decoders for process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32381'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32379_EN[3:0]$32387
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32379_DATA[3:0]$32386
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32379_ADDR[3:0]$32385
Creating decoders for process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32380'.

22.42.16.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.16.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.\i' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32363_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32364_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32365_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32366_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32370_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32371_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32372_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32376_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32377_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32367_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32378_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32368_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32373_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32374_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32375_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32369_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32379_ADDR' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32381'.
  created $dff cell `$procdff$32431' with positive edge clock.
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32379_DATA' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32381'.
  created $dff cell `$procdff$32432' with positive edge clock.
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32379_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32381'.
  created $dff cell `$procdff$32433' with positive edge clock.
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32380'.
  created direct connection (no actual register cell created).

22.42.16.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.16.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32405'.
Found and cleaned up 1 empty switch in `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32381'.
Removing empty process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32380'.
Cleaned up 1 empty switch.

22.42.16.12. Executing OPT_EXPR pass (perform const folding).

22.42.17. Executing PROC pass (convert processes to netlists).

22.42.17.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32451'.
Cleaned up 1 empty switch.

22.42.17.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32452 in module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.17.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.17.4. Executing PROC_INIT pass (extract init attributes).

22.42.17.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.17.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.17.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
Creating decoders for process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32452'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32450_EN[3:0]$32456
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32450_DATA[3:0]$32458
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32450_ADDR[3:0]$32457
Creating decoders for process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32451'.

22.42.17.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.17.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.\i' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32434_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32435_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32436_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32440_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32441_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32442_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32446_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32447_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32437_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32448_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32438_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32443_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32444_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32449_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32445_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32439_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32450_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32452'.
  created $dff cell `$procdff$32502' with positive edge clock.
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32450_ADDR' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32452'.
  created $dff cell `$procdff$32503' with positive edge clock.
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32450_DATA' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32452'.
  created $dff cell `$procdff$32504' with positive edge clock.
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.\muxwre' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32451'.
  created direct connection (no actual register cell created).

22.42.17.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.17.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32476'.
Found and cleaned up 1 empty switch in `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32452'.
Removing empty process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32451'.
Cleaned up 1 empty switch.

22.42.17.12. Executing OPT_EXPR pass (perform const folding).

22.42.18. Executing PROC pass (convert processes to netlists).

22.42.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32522'.
Cleaned up 1 empty switch.

22.42.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32523 in module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.18.4. Executing PROC_INIT pass (extract init attributes).

22.42.18.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.18.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
Creating decoders for process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32523'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32521_EN[3:0]$32528
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32521_DATA[3:0]$32527
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32521_ADDR[3:0]$32529
Creating decoders for process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32522'.

22.42.18.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.18.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.\i' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32505_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32506_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32510_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32511_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32512_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32516_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32517_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32507_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32518_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32508_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32513_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32514_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32519_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32520_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32515_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32509_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32521_DATA' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32523'.
  created $dff cell `$procdff$32573' with positive edge clock.
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32521_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32523'.
  created $dff cell `$procdff$32574' with positive edge clock.
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32521_ADDR' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32523'.
  created $dff cell `$procdff$32575' with positive edge clock.
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32522'.
  created direct connection (no actual register cell created).

22.42.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32547'.
Found and cleaned up 1 empty switch in `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32523'.
Removing empty process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32522'.
Cleaned up 1 empty switch.

22.42.18.12. Executing OPT_EXPR pass (perform const folding).

22.42.19. Executing PROC pass (convert processes to netlists).

22.42.19.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32593'.
Cleaned up 1 empty switch.

22.42.19.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32594 in module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.19.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.19.4. Executing PROC_INIT pass (extract init attributes).

22.42.19.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.19.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.19.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
Creating decoders for process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32594'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32592_EN[3:0]$32600
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32592_DATA[3:0]$32599
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32592_ADDR[3:0]$32598
Creating decoders for process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32593'.

22.42.19.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.19.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.\i' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32576_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32580_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32581_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32582_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32586_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32587_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32577_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32588_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32578_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32583_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32584_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32589_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32590_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32591_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32585_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32579_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32592_ADDR' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32594'.
  created $dff cell `$procdff$32644' with positive edge clock.
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32592_DATA' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32594'.
  created $dff cell `$procdff$32645' with positive edge clock.
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32592_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32594'.
  created $dff cell `$procdff$32646' with positive edge clock.
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.\muxwre' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32593'.
  created direct connection (no actual register cell created).

22.42.19.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.19.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32618'.
Found and cleaned up 1 empty switch in `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32594'.
Removing empty process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32593'.
Cleaned up 1 empty switch.

22.42.19.12. Executing OPT_EXPR pass (perform const folding).

22.42.20. Executing PROC pass (convert processes to netlists).

22.42.20.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32664'.
Cleaned up 1 empty switch.

22.42.20.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32665 in module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.20.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.20.4. Executing PROC_INIT pass (extract init attributes).

22.42.20.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.20.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.20.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
Creating decoders for process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32665'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32663_EN[3:0]$32671
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32663_DATA[3:0]$32670
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32663_ADDR[3:0]$32669
Creating decoders for process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32664'.

22.42.20.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.20.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.\i' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32650_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32651_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32652_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32656_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32657_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32658_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32662_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32648_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32653_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32654_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32659_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32660_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32661_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32655_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32649_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32647_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32663_ADDR' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32665'.
  created $dff cell `$procdff$32715' with positive edge clock.
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32663_DATA' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32665'.
  created $dff cell `$procdff$32716' with positive edge clock.
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32663_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32665'.
  created $dff cell `$procdff$32717' with positive edge clock.
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.\muxwre' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32664'.
  created direct connection (no actual register cell created).

22.42.20.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.20.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32689'.
Found and cleaned up 1 empty switch in `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32665'.
Removing empty process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32664'.
Cleaned up 1 empty switch.

22.42.20.12. Executing OPT_EXPR pass (perform const folding).

22.42.21. Executing PROC pass (convert processes to netlists).

22.42.21.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32735'.
Cleaned up 1 empty switch.

22.42.21.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32736 in module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.21.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.21.4. Executing PROC_INIT pass (extract init attributes).

22.42.21.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.21.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.21.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
Creating decoders for process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32736'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32734_EN[3:0]$32742
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32734_DATA[3:0]$32741
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32734_ADDR[3:0]$32740
Creating decoders for process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32735'.

22.42.21.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.21.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.\i' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32718_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32720_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32721_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32722_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32726_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32727_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32728_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32732_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32733_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32723_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32724_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32729_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32730_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32731_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32725_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32719_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32734_ADDR' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32736'.
  created $dff cell `$procdff$32786' with positive edge clock.
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32734_DATA' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32736'.
  created $dff cell `$procdff$32787' with positive edge clock.
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32734_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32736'.
  created $dff cell `$procdff$32788' with positive edge clock.
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.\muxwre' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32735'.
  created direct connection (no actual register cell created).

22.42.21.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.21.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32760'.
Found and cleaned up 1 empty switch in `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32736'.
Removing empty process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32735'.
Cleaned up 1 empty switch.

22.42.21.12. Executing OPT_EXPR pass (perform const folding).

22.42.22. Executing PROC pass (convert processes to netlists).

22.42.22.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32806'.
Cleaned up 1 empty switch.

22.42.22.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32807 in module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.22.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.22.4. Executing PROC_INIT pass (extract init attributes).

22.42.22.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.22.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.22.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
Creating decoders for process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32807'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32805_EN[3:0]$32813
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32805_DATA[3:0]$32812
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32805_ADDR[3:0]$32811
Creating decoders for process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32806'.

22.42.22.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.22.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.\i' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32789_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32790_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32791_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32792_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32796_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32797_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32798_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32802_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32803_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32793_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32804_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32794_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32799_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32800_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32801_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32795_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32805_ADDR' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32807'.
  created $dff cell `$procdff$32857' with positive edge clock.
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32805_DATA' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32807'.
  created $dff cell `$procdff$32858' with positive edge clock.
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32805_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32807'.
  created $dff cell `$procdff$32859' with positive edge clock.
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.\muxwre' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32806'.
  created direct connection (no actual register cell created).

22.42.22.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.22.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32831'.
Found and cleaned up 1 empty switch in `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32807'.
Removing empty process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32806'.
Cleaned up 1 empty switch.

22.42.22.12. Executing OPT_EXPR pass (perform const folding).

22.42.23. Executing PROC pass (convert processes to netlists).

22.42.23.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32877'.
Cleaned up 1 empty switch.

22.42.23.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32878 in module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.23.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.23.4. Executing PROC_INIT pass (extract init attributes).

22.42.23.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.23.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.23.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
Creating decoders for process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32878'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32876_EN[3:0]$32882
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32876_DATA[3:0]$32884
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32876_ADDR[3:0]$32883
Creating decoders for process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32877'.

22.42.23.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.23.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.\i' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32864_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32869_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32870_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32875_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32860_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32861_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32862_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32866_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32867_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32868_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32872_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32873_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32863_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32874_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32871_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32865_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32876_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32878'.
  created $dff cell `$procdff$32928' with positive edge clock.
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32876_ADDR' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32878'.
  created $dff cell `$procdff$32929' with positive edge clock.
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32876_DATA' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32878'.
  created $dff cell `$procdff$32930' with positive edge clock.
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.\muxwre' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32877'.
  created direct connection (no actual register cell created).

22.42.23.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.23.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32902'.
Found and cleaned up 1 empty switch in `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32878'.
Removing empty process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32877'.
Cleaned up 1 empty switch.

22.42.23.12. Executing OPT_EXPR pass (perform const folding).

22.42.24. Executing PROC pass (convert processes to netlists).

22.42.24.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32948'.
Cleaned up 1 empty switch.

22.42.24.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32949 in module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.24.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.24.4. Executing PROC_INIT pass (extract init attributes).

22.42.24.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.24.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.24.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
Creating decoders for process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32949'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32947_EN[3:0]$32954
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32947_DATA[3:0]$32953
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32947_ADDR[3:0]$32955
Creating decoders for process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32948'.

22.42.24.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.24.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.\i' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32931_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32932_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32936_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32937_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32938_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32942_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32943_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32933_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32944_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32934_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32939_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32940_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32945_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32946_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32941_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32935_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32947_DATA' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32949'.
  created $dff cell `$procdff$32999' with positive edge clock.
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32947_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32949'.
  created $dff cell `$procdff$33000' with positive edge clock.
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32947_ADDR' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32949'.
  created $dff cell `$procdff$33001' with positive edge clock.
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.\muxwre' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32948'.
  created direct connection (no actual register cell created).

22.42.24.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.24.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32973'.
Found and cleaned up 1 empty switch in `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32949'.
Removing empty process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32948'.
Cleaned up 1 empty switch.

22.42.24.12. Executing OPT_EXPR pass (perform const folding).

22.42.25. Executing PROC pass (convert processes to netlists).

22.42.25.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$33019'.
Cleaned up 1 empty switch.

22.42.25.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33020 in module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.25.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.25.4. Executing PROC_INIT pass (extract init attributes).

22.42.25.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.25.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.25.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
Creating decoders for process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33020'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33018_EN[3:0]$33026
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33018_DATA[3:0]$33025
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33018_ADDR[3:0]$33024
Creating decoders for process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$33019'.

22.42.25.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.25.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.\i' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33013_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33008_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33003_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33002_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33004_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33005_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33009_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33010_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33014_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33006_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33015_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33011_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33007_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33016_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33012_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33017_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33018_ADDR' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33020'.
  created $dff cell `$procdff$33070' with positive edge clock.
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33018_DATA' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33020'.
  created $dff cell `$procdff$33071' with positive edge clock.
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33018_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33020'.
  created $dff cell `$procdff$33072' with positive edge clock.
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.\muxwre' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$33019'.
  created direct connection (no actual register cell created).

22.42.25.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.25.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33044'.
Found and cleaned up 1 empty switch in `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33020'.
Removing empty process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$33019'.
Cleaned up 1 empty switch.

22.42.25.12. Executing OPT_EXPR pass (perform const folding).

22.42.26. Executing PROC pass (convert processes to netlists).

22.42.26.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$33090'.
Cleaned up 1 empty switch.

22.42.26.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33091 in module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.26.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.26.4. Executing PROC_INIT pass (extract init attributes).

22.42.26.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.26.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.26.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
Creating decoders for process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33091'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33089_EN[3:0]$33095
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33089_DATA[3:0]$33097
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33089_ADDR[3:0]$33096
Creating decoders for process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$33090'.

22.42.26.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.26.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.\i' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33086_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33081_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33076_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33073_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33077_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33078_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33082_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33074_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33083_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33087_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33079_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33088_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33075_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33084_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33080_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33085_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33089_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33091'.
  created $dff cell `$procdff$33141' with positive edge clock.
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33089_ADDR' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33091'.
  created $dff cell `$procdff$33142' with positive edge clock.
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33089_DATA' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33091'.
  created $dff cell `$procdff$33143' with positive edge clock.
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$33090'.
  created direct connection (no actual register cell created).

22.42.26.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.26.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33115'.
Found and cleaned up 1 empty switch in `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33091'.
Removing empty process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$33090'.
Cleaned up 1 empty switch.

22.42.26.12. Executing OPT_EXPR pass (perform const folding).

22.42.27. Executing PROC pass (convert processes to netlists).

22.42.27.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$33161'.
Cleaned up 1 empty switch.

22.42.27.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33162 in module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.27.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.27.4. Executing PROC_INIT pass (extract init attributes).

22.42.27.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.27.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.27.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
Creating decoders for process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33162'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33160_EN[3:0]$33168
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33160_DATA[3:0]$33167
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33160_ADDR[3:0]$33166
Creating decoders for process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$33161'.

22.42.27.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.27.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.\i' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33152_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33159_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33154_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33149_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33144_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33145_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33146_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33150_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33151_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33155_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33156_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33147_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33148_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33157_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33153_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33158_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33160_ADDR' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33162'.
  created $dff cell `$procdff$33212' with positive edge clock.
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33160_DATA' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33162'.
  created $dff cell `$procdff$33213' with positive edge clock.
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33160_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33162'.
  created $dff cell `$procdff$33214' with positive edge clock.
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.\muxwre' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$33161'.
  created direct connection (no actual register cell created).

22.42.27.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.27.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33186'.
Found and cleaned up 1 empty switch in `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33162'.
Removing empty process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$33161'.
Cleaned up 1 empty switch.

22.42.27.12. Executing OPT_EXPR pass (perform const folding).

22.42.28. Executing PROC pass (convert processes to netlists).

22.42.28.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$33232'.
Cleaned up 1 empty switch.

22.42.28.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33233 in module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.28.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.28.4. Executing PROC_INIT pass (extract init attributes).

22.42.28.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.28.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.28.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
Creating decoders for process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33233'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33231_EN[3:0]$33238
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33231_DATA[3:0]$33237
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33231_ADDR[3:0]$33239
Creating decoders for process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$33232'.

22.42.28.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.28.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.\i' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33227_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33222_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33217_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33215_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33218_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33219_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33223_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33224_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33228_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33220_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33229_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33216_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33225_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33221_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33230_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$33226_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33231_DATA' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33233'.
  created $dff cell `$procdff$33283' with positive edge clock.
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33231_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33233'.
  created $dff cell `$procdff$33284' with positive edge clock.
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$33231_ADDR' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33233'.
  created $dff cell `$procdff$33285' with positive edge clock.
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.\muxwre' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$33232'.
  created direct connection (no actual register cell created).

22.42.28.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.28.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$33257'.
Found and cleaned up 1 empty switch in `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$33233'.
Removing empty process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$33232'.
Cleaned up 1 empty switch.

22.42.28.12. Executing OPT_EXPR pass (perform const folding).

22.42.29. Executing SCC pass (detecting logic loops).
Found an SCC: $techmap$auto$ff.cc:266:slice$13107.$auto$simplemap.cc:267:simplemap_mux$31355
Found an SCC: $techmap$auto$ff.cc:266:slice$13106.$auto$simplemap.cc:267:simplemap_mux$31355
Found an SCC: $techmap$auto$ff.cc:266:slice$13105.$auto$simplemap.cc:267:simplemap_mux$31355
Found an SCC: $techmap$auto$ff.cc:266:slice$13104.$auto$simplemap.cc:267:simplemap_mux$31355
Found an SCC: $auto$ff.cc:266:slice$10813 $auto$ff.cc:266:slice$10812 $auto$simplemap.cc:126:simplemap_reduce$10913 $auto$opt_expr.cc:613:replace_const_cells$30406 $auto$simplemap.cc:126:simplemap_reduce$10928 $auto$ff.cc:266:slice$10811 $auto$opt_expr.cc:613:replace_const_cells$30428 $auto$simplemap.cc:267:simplemap_mux$17760 $auto$simplemap.cc:126:simplemap_reduce$17745 $auto$simplemap.cc:126:simplemap_reduce$17742 $auto$simplemap.cc:75:simplemap_bitop$17757 $auto$simplemap.cc:267:simplemap_mux$10899 $auto$simplemap.cc:225:simplemap_logbin$10903 $auto$simplemap.cc:196:simplemap_lognot$10918 $auto$simplemap.cc:126:simplemap_reduce$10916 $auto$simplemap.cc:126:simplemap_reduce$10914 $auto$simplemap.cc:126:simplemap_reduce$17747 $auto$simplemap.cc:75:simplemap_bitop$17755 $auto$simplemap.cc:196:simplemap_lognot$10933 $auto$simplemap.cc:126:simplemap_reduce$10931 $auto$simplemap.cc:126:simplemap_reduce$10929 $auto$opt_expr.cc:613:replace_const_cells$30422 $auto$ff.cc:266:slice$10814 $auto$simplemap.cc:126:simplemap_reduce$9962 $auto$simplemap.cc:126:simplemap_reduce$9960 $auto$simplemap.cc:225:simplemap_logbin$10858 $auto$simplemap.cc:196:simplemap_lognot$10868 $auto$simplemap.cc:126:simplemap_reduce$10866 $auto$opt_expr.cc:613:replace_const_cells$30426 $auto$simplemap.cc:267:simplemap_mux$17759 $auto$simplemap.cc:126:simplemap_reduce$17750
Found an SCC: $auto$ff.cc:266:slice$10679 $auto$opt_expr.cc:613:replace_const_cells$30300 $auto$ff.cc:266:slice$10678 $auto$simplemap.cc:126:simplemap_reduce$10769 $auto$simplemap.cc:126:simplemap_reduce$10796 $auto$opt_expr.cc:613:replace_const_cells$30298 $auto$ff.cc:266:slice$10677 $auto$simplemap.cc:38:simplemap_not$17736 $auto$ff.cc:266:slice$10676 $auto$simplemap.cc:126:simplemap_reduce$10772 $auto$simplemap.cc:126:simplemap_reduce$10768 $auto$simplemap.cc:126:simplemap_reduce$10799 $auto$simplemap.cc:126:simplemap_reduce$10795 $auto$simplemap.cc:38:simplemap_not$17735 $auto$ff.cc:266:slice$10675 $auto$simplemap.cc:38:simplemap_not$17734 $auto$ff.cc:266:slice$10674 $auto$simplemap.cc:38:simplemap_not$17731 $auto$ff.cc:266:slice$10671 $auto$simplemap.cc:126:simplemap_reduce$10794 $auto$ff.cc:266:slice$10673 $auto$simplemap.cc:126:simplemap_reduce$10766 $auto$simplemap.cc:196:simplemap_lognot$10805 $auto$simplemap.cc:126:simplemap_reduce$10803 $auto$simplemap.cc:126:simplemap_reduce$10801 $auto$simplemap.cc:126:simplemap_reduce$10798 $auto$simplemap.cc:126:simplemap_reduce$10793 $auto$ff.cc:266:slice$10672 $auto$simplemap.cc:167:logic_reduce$9941 $auto$simplemap.cc:225:simplemap_logbin$10750 $auto$simplemap.cc:225:simplemap_logbin$10751 $auto$simplemap.cc:196:simplemap_lognot$10778 $auto$simplemap.cc:126:simplemap_reduce$10776 $auto$simplemap.cc:126:simplemap_reduce$10774 $auto$simplemap.cc:126:simplemap_reduce$10771 $auto$simplemap.cc:126:simplemap_reduce$10767 $auto$simplemap.cc:38:simplemap_not$17733
Found an SCC: $auto$ff.cc:266:slice$10823 $auto$opt_expr.cc:613:replace_const_cells$30418 $auto$ff.cc:266:slice$10822 $auto$ff.cc:266:slice$10816 $auto$simplemap.cc:126:simplemap_reduce$10948 $auto$simplemap.cc:38:simplemap_not$17806 $auto$ff.cc:266:slice$10815 $auto$simplemap.cc:126:simplemap_reduce$10951 $auto$opt_expr.cc:613:replace_const_cells$30416 $auto$ff.cc:266:slice$10821 $auto$ff.cc:266:slice$10820 $auto$simplemap.cc:126:simplemap_reduce$10954 $auto$simplemap.cc:126:simplemap_reduce$10950 $auto$simplemap.cc:38:simplemap_not$17810 $auto$ff.cc:266:slice$10819 $auto$ff.cc:266:slice$10818 $auto$ff.cc:266:slice$10817 $auto$simplemap.cc:126:simplemap_reduce$9989 $auto$simplemap.cc:196:simplemap_lognot$10960 $auto$simplemap.cc:126:simplemap_reduce$10958 $auto$simplemap.cc:126:simplemap_reduce$10956 $auto$simplemap.cc:126:simplemap_reduce$10953 $auto$simplemap.cc:126:simplemap_reduce$10949 $auto$simplemap.cc:38:simplemap_not$17809
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$10118 $auto$simplemap.cc:38:simplemap_not$28373 $auto$ff.cc:266:slice$9423 $auto$ff.cc:479:convert_ce_over_srst$30648 $auto$simplemap.cc:38:simplemap_not$16311 $auto$ff.cc:266:slice$9419 $auto$ff.cc:479:convert_ce_over_srst$30640 $auto$ff.cc:266:slice$9420 $auto$ff.cc:479:convert_ce_over_srst$30642 $auto$simplemap.cc:126:simplemap_reduce$9842 $auto$opt_expr.cc:613:replace_const_cells$30146 $auto$alumacc.cc:485:replace_alu$2555.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$2555.slice[0].ccu2c_i $auto$ff.cc:266:slice$9418 $auto$ff.cc:479:convert_ce_over_srst$30638 $auto$simplemap.cc:126:simplemap_reduce$9844 $auto$simplemap.cc:38:simplemap_not$9756 $auto$alumacc.cc:485:replace_alu$2555.slice[4].ccu2c_i $auto$ff.cc:266:slice$9422 $auto$ff.cc:479:convert_ce_over_srst$30646 $auto$simplemap.cc:126:simplemap_reduce$10097 $auto$simplemap.cc:126:simplemap_reduce$10071 $auto$simplemap.cc:126:simplemap_reduce$10121 $auto$simplemap.cc:126:simplemap_reduce$10119 $auto$simplemap.cc:38:simplemap_not$9849 $auto$simplemap.cc:75:simplemap_bitop$9840 $auto$simplemap.cc:126:simplemap_reduce$9848 $auto$simplemap.cc:126:simplemap_reduce$9846 $auto$simplemap.cc:126:simplemap_reduce$9843 $auto$simplemap.cc:38:simplemap_not$16313 $auto$ff.cc:266:slice$9421 $auto$ff.cc:479:convert_ce_over_srst$30644 $auto$simplemap.cc:126:simplemap_reduce$10073
Found 8 SCCs in module top.
Found 8 SCCs.

22.42.30. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.31. Executing PROC pass (convert processes to netlists).

22.42.31.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

22.42.31.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

22.42.31.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

22.42.31.4. Executing PROC_INIT pass (extract init attributes).

22.42.31.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.31.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

22.42.31.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

22.42.31.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.31.9. Executing PROC_DFF pass (convert process syncs to FFs).

22.42.31.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.31.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

22.42.31.12. Executing OPT_EXPR pass (perform const folding).

22.42.32. Executing TECHMAP pass (map to technology primitives).

22.42.32.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

22.42.32.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~212 debug messages>

22.42.33. Executing OPT pass (performing simple optimizations).

22.42.33.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
Optimizing module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
Optimizing module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
Optimizing module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
Optimizing module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
Optimizing module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
Optimizing module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
Optimizing module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.
Optimizing module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
Optimizing module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
Optimizing module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
Optimizing module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
Optimizing module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
Optimizing module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
Optimizing module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
Optimizing module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
Optimizing module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
Optimizing module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
Optimizing module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
Optimizing module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
Optimizing module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
Optimizing module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
Optimizing module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
Optimizing module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.

22.42.33.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

22.42.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.42.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.
Performed a total of 0 changes.

22.42.33.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

22.42.33.6. Executing OPT_DFF pass (perform DFF optimizations).

22.42.33.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4..

22.42.33.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
Optimizing module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
Optimizing module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
Optimizing module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
Optimizing module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
Optimizing module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
Optimizing module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
Optimizing module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.
Optimizing module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
Optimizing module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
Optimizing module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
Optimizing module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
Optimizing module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
Optimizing module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
Optimizing module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
Optimizing module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
Optimizing module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
Optimizing module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
Optimizing module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
Optimizing module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
Optimizing module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
Optimizing module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.

22.42.33.9. Finished OPT passes. (There is nothing left to do.)

22.42.34. Executing TECHMAP pass (map to technology primitives).

22.42.34.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

22.42.34.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4 for cells of type $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
Using template $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4 for cells of type $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
Using template $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4 for cells of type $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
Using template $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4 for cells of type $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
Using template $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4 for cells of type $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
Using template $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4 for cells of type $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
Using template $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4 for cells of type $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
Using template $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4 for cells of type $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
Using template $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4 for cells of type $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.
Using template $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4 for cells of type $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
Using template $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4 for cells of type $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
Using template $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4 for cells of type $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
Using template $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4 for cells of type $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
Using template $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4 for cells of type $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
Using template $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4 for cells of type $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.
Using template $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4 for cells of type $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
Using template $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4 for cells of type $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
Using template $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4 for cells of type $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
Using template $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4 for cells of type $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
Using template $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4 for cells of type $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
Using template $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4 for cells of type $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
Using template $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4 for cells of type $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
Using template $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4 for cells of type $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
Using template $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4 for cells of type $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~1088 debug messages>

22.42.35. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

22.42.36. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

22.42.37. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.38. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

22.42.39. Executing TECHMAP pass (map to technology primitives).

22.42.39.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

22.42.39.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using extmapper simplemap for cells of type $not.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~251 debug messages>

22.42.40. Executing OPT pass (performing simple optimizations).

22.42.40.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~18 debug messages>

22.42.40.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

22.42.40.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.42.40.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.42.40.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.42.40.6. Executing OPT_DFF pass (perform DFF optimizations).

22.42.40.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

22.42.40.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.42.40.9. Rerunning OPT passes. (Maybe there is more to do..)

22.42.40.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.42.40.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.42.40.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.42.40.13. Executing OPT_DFF pass (perform DFF optimizations).

22.42.40.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.42.40.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.42.40.16. Finished OPT passes. (There is nothing left to do.)

22.42.41. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

22.42.42. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 7181 cells with 46202 new cells, skipped 4979 cells.
  replaced 3 cell types:
    1355 $_OR_
      94 $_XOR_
    5732 $_MUX_
  not replaced 59 cell types:
      30 $scopeinfo
     365 $_NOT_
    1384 $_AND_
       6 $_TBUF_
       1 $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4_$abc9_byp
     702 TRELLIS_FF
       1 $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4_$abc9_byp
      16 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4_$abc9_byp
    1020 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4_$abc9_byp
       1 $__ABC9_SCC_BREAKER
       1 $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4_$abc9_byp
      16 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4
    1020 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
       1 $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4
       1 $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4
       1 $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4
       1 $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4
       1 $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4
       1 $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4
       1 $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4
       1 $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4_$abc9_byp
     371 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
       1 $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4
       1 $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4
       1 $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4
       1 $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4
       1 $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4
       1 $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4
       1 $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4
       1 $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4
       1 $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4
       1 $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4
       1 $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4
       1 $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4
       1 $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4
       1 $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4
       1 $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4
       1 $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4
       1 $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4
       1 $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4_$abc9_byp

22.42.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.42.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 20217 AND gates and 59017 wires from module `top' to a netlist network with 4959 inputs and 829 outputs.

22.42.42.4. Executing ABC9_EXE pass (technology mapping using ABC9).

22.42.42.5. Executing ABC9.
read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1274.730 ; gain = 24.836 ; free physical = 10053 ; free virtual = 29970
# read_verilog ../../debug/reset.v
# read_verilog ../../src/core/alu_control.v
# read_verilog ../../src/core/alu.v
# read_verilog ../../src/core/control_unit.v
# read_verilog ../../src/core/core.v
# read_verilog ../../src/core/immediate_generator.v
# read_verilog ../../src/core/mux.v
# read_verilog ../../src/core/pc.v
# read_verilog ../../src/core/registers.v
# read_verilog ../../src/core/csr_unit.v
# read_verilog ../../src/peripheral/bus.v
# read_verilog ../../src/peripheral/gpio.v
# read_verilog ../../src/peripheral/gpios.v
# read_verilog ../../src/peripheral/leds.v
# read_verilog ../../src/peripheral/memory.v
# read_verilog ../../src/peripheral/soc.v
# read_verilog ../../src/peripheral/uart_rx.v
# read_verilog ../../src/peripheral/uart_tx.v
# read_verilog ../../src/peripheral/uart.v
# read_verilog ../../src/peripheral/fifo.v
# read_xdc "digilent_nexys4_ddr.xdc"
# set_property PROCESSING_ORDER EARLY [get_files digilent_nexys4_ddr.xdc]
# synth_design -top "top" -part "xc7a100tcsg324-1"
Command: synth_design -top top -part xc7a100tcsg324-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   4959/    829  and =   18627  lev =   46 (6.43)  mem = 0.56 MB  box = 1431  bb = 1060
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   4959/    829  and =   23730  lev =   62 (3.55)  mem = 0.61 MB  ch = 2138  box = 1353  bb = 1060
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   60. Obj =  140. Set =  636. CutMin = no
ABC: Node =   23730.  Ch =  1481.  Total mem =    6.81 MB. Peak cut mem =    0.24 MB.
ABC: P:  Del = 6904.00.  Ar =   25261.0.  Edge =    29160.  Cut =   326051.  T =     0.09 sec
ABC: P:  Del = 6876.00.  Ar =   28687.0.  Edge =    30607.  Cut =   294720.  T =     0.08 sec
ABC: P:  Del = 6876.00.  Ar =    9900.0.  Edge =    22788.  Cut =   797690.  T =     0.20 sec
ABC: F:  Del = 6876.00.  Ar =    7096.0.  Edge =    20201.  Cut =   535380.  T =     0.14 sec
ABC: A:  Del = 6876.00.  Ar =    6545.0.  Edge =    18711.  Cut =   481315.  T =     0.21 sec
ABC: A:  Del = 6876.00.  Ar =    6471.0.  Edge =    18623.  Cut =   503614.  T =     0.22 sec
ABC: Total time =     0.94 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   4959/    829  and =   15101  lev =   41 (3.89)  mem = 0.51 MB  box = 1353  bb = 1060
ABC: Mapping (K=7)  :  lut =   4624  edge =   18553  lev =   14 (1.89)  levB =   42  mem = 0.25 MB
ABC: LUT = 4624 : 2=321 6.9 %  3=577 12.5 %  4=2743 59.3 %  5=796 17.2 %  6=81 1.8 %  7=106 2.3 %  Ave = 4.01
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 8.85 seconds, total: 8.85 seconds

22.42.42.6. Executing AIGER frontend.
<suppressed ~11666 debug messages>
Removed 20051 unused cells and 46685 unused wires.

22.42.42.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     4649
ABC RESULTS:   $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells:       16
ABC RESULTS:   $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:     1020
ABC RESULTS:   $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      293
ABC RESULTS:   $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:           input signals:     1105
ABC RESULTS:          output signals:      131
Removing temp directory.

22.42.43. Executing TECHMAP pass (map to technology primitives).

22.42.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

22.42.43.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001000 for cells of type $__ABC9_SCC_BREAKER.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4 for cells of type $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
Using template $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4 for cells of type $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
Using template $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4 for cells of type $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
Using template $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4 for cells of type $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
Using template $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4 for cells of type $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
Using template $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4 for cells of type $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
Using template $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4 for cells of type $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
Using template $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4 for cells of type $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
Using template $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4 for cells of type $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.
Using template $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4 for cells of type $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
Using template $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4 for cells of type $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
Using template $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4 for cells of type $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
Using template $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4 for cells of type $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
Using template $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4 for cells of type $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
Using template $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4 for cells of type $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.
Using template $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4 for cells of type $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
Using template $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4 for cells of type $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
Using template $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4 for cells of type $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
Using template $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4 for cells of type $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
Using template $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4 for cells of type $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
Using template $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4 for cells of type $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
Using template $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4 for cells of type $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
Using template $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4 for cells of type $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
Using template $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4 for cells of type $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
Using template $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4_$abc9_byp.
No more expansions possible.
<suppressed ~2483 debug messages>
Removed 326 unused cells and 74867 unused wires.

22.43. Executing TECHMAP pass (map to technology primitives).

22.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

22.43.2. Continuing TECHMAP pass.
Using template $paramod$f28a4401e00366386f5c9da01093cb438d2ef37a\$lut for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod$73168779d124d0e86f3f4da4f351086f6646bb40\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$88a106be73851c7a5d1740739afdb4dbd65330dc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$faba0cf60f1c89602d59ba2d491152c8f0d36384\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$bde6c96e44b0f8e6d9db97eafdf28d77ceaa9a96\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$1221ecddf806ed98cf6cee2f2b5a80f38aeb4bee\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod$ce44877a8aba311086973ef3ef648b154684306e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$9a8855b22366cbd3367af17a25fe0def507b1d15\$lut for cells of type $lut.
Using template $paramod$b2b8f14c1dc45737f0261c4484079d734f30d41f\$lut for cells of type $lut.
Using template $paramod$c19ac226b2328a9dc00b76bc0a6d1e025c6f4fca\$lut for cells of type $lut.
Using template $paramod$ccd3e15dc00d71b9284dff48e88ccef5be7362c8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut.
Using template $paramod$fb7bbfbe62f17d1abd6f8eaee546f5a966c46c29\$lut for cells of type $lut.
Using template $paramod$b97ff285770a798ba31d840db2ce52fdc36910ae\$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$a8f200f2806e23893fd75a1574871ecd897f762e\$lut for cells of type $lut.
Using template $paramod$08466811901d5e03ed77c75ae1ee4f324a7c22b7\$lut for cells of type $lut.
Using template $paramod$38e18d818042e7be412a935b1fcbd89ce659b02d\$lut for cells of type $lut.
Using template $paramod$05402c79be82cc63a2eaed19f98c2af9df54d241\$lut for cells of type $lut.
Using template $paramod$c045fbf07081c13ec34b91ab657284248665e203\$lut for cells of type $lut.
Using template $paramod$3cc80e2a63856e1f46075e358d1c072c35cc4ca8\$lut for cells of type $lut.
Using template $paramod$83c1b6108170249166239e09804c5f4542556524\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$1780b599fad82e57d6459b81ca42390759dd97e1\$lut for cells of type $lut.
Using template $paramod$c441dbd41fa7b52ce609b1fb3e8a706905598601\$lut for cells of type $lut.
Using template $paramod$4a9f20a18e16e687c50b1afb238d77d575a68f2d\$lut for cells of type $lut.
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 1578399
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$872def176acf0af46aee1a4df67a9291309e3c01\$lut for cells of type $lut.
Using template $paramod$c79aec6bf66334ca918f85c196e004c918c371ef\$lut for cells of type $lut.
Using template $paramod$173257c402a3003de28bff8c2a49d358e5f4004c\$lut for cells of type $lut.
Using template $paramod$71112c23185f325d93f810329cb9d4a033178614\$lut for cells of type $lut.
Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut.
Using template $paramod$b45308ffeb4031bc5d55ef31b149afd94d3d7565\$lut for cells of type $lut.
Using template $paramod$0fe8fbf45fc9407b7d9f6cdf3b662e78e91e9b55\$lut for cells of type $lut.
Using template $paramod$e6062a78edaf68ec0dbea59d4c8352dcb2ce0366\$lut for cells of type $lut.
Using template $paramod$db47c23db3b77188dd646c8fe3a0fef7aef96f3c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110010 for cells of type $lut.
Using template $paramod$2e6f7636c4430e71acfafacf89034290c19a68d2\$lut for cells of type $lut.
Using template $paramod$db8547c0ce3f404162c765a55df5db805b4e10bc\$lut for cells of type $lut.
Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$df5c8730c0a53792c3f54c2192a2221c27162fb5\$lut for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod$40bf400bfab4b5cf32dcfe01e14f0900ac7f6b1b\$lut for cells of type $lut.
Using template $paramod$90dc599eed99da511e64ad217d69e7ff2c1e56cc\$lut for cells of type $lut.
Using template $paramod$be95f3a2132281eadd1adcfe6229e43dbc3353c9\$lut for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod$9c6e6a10ea00e5b0682f6243b802d7839a398197\$lut for cells of type $lut.
Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$63114da772fb28945ba24699e32f1e30ca7142f4\$lut for cells of type $lut.
Using template $paramod$c20bb0ec9b7ffe048b440bc5b52865dca055e17d\$lut for cells of type $lut.
Using template $paramod$394086530b97e2ede4325cfef07483589916f736\$lut for cells of type $lut.
Using template $paramod$5400b6807adef39a9693b2fbff17f8c0ab116b66\$lut for cells of type $lut.
Using template $paramod$23ba03b3f106a8b0f20f18bfebd862b419996ddc\$lut for cells of type $lut.
Using template $paramod$7202672b7332febf25cdbe5424cf24593f5449be\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2\$lut for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$a56a39c0f6a5a7dc6beed165205ecc9aaf916f10\$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod$b44044b00f12778166d6621b324da4bb4c9dbcca\$lut for cells of type $lut.
Using template $paramod$f546bd96bcec6e3bf1b78bdea64b0f5bbbaff6df\$lut for cells of type $lut.
Using template $paramod$40f50322426372d948aaadc2f14dc77fbf5a9200\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod$b8113752b08bd47f69a1c8c2bca1cfb157e800c9\$lut for cells of type $lut.
Using template $paramod$7cd2eb6a7d66e3dc32689a836e66ef851f6abf28\$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod$f4924b9d1c382d0cb922de70d1eb4371b36c168b\$lut for cells of type $lut.
Using template $paramod$256f3f936b752cf569dca900ae92c3ac452c7e57\$lut for cells of type $lut.
Using template $paramod$440117a2733b1fd30b1ced35f0463059c21c5ab1\$lut for cells of type $lut.
Using template $paramod$3dc8df1b07971bda7726ddf94f6377e60804ab64\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$3b374b0454c507d1efadee363d480c52c3b3f58f\$lut for cells of type $lut.
Using template $paramod$26d876869d6ab003366d0470e095daef2ccfcbd7\$lut for cells of type $lut.
Using template $paramod$32218055f2504e562f91aae196e4a7b00a3db31a\$lut for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
Using template $paramod$94cc9dc7ba20eb6ef27973e1d776ca04cbc15deb\$lut for cells of type $lut.
Using template $paramod$f320887d5863d39721ed331710b3512af9a0a006\$lut for cells of type $lut.
Using template $paramod$41b777a122fa6162fe05e453fac63a5bd726825e\$lut for cells of type $lut.
Using template $paramod$5529c41ee416b5701a489bbfc97ea1f8107995ba\$lut for cells of type $lut.
Using template $paramod$b0672a65aa303b87176ce0d751841df5aee685da\$lut for cells of type $lut.
Using template $paramod$6fc23ce09f2013cb9de2228dbcdda21841008f92\$lut for cells of type $lut.
Using template $paramod$2d52a1d6cf603c98ba7b908cd4e344a0536dbeca\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$ee19d45db61acb4c70d938b97483a4ed4b792645\$lut for cells of type $lut.
Using template $paramod$b7c4f08b7346c19e2ae421f414a600eb78d5cf1c\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod$0331e023d83b8009e60defb446ce9fa640b122c7\$lut for cells of type $lut.
Using template $paramod$c35ad3063d5038410210ddc72c1fd5fed46413b4\$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut.
Using template $paramod$c39b4ae3eed03ff4e0ef2a41844cc5ea3df00d09\$lut for cells of type $lut.
Using template $paramod$c5d89add2125c31a1c240c4821f835a035144566\$lut for cells of type $lut.
Using template $paramod$ec77ef2f39e0c5347eaada9711f26fca6a276050\$lut for cells of type $lut.
Using template $paramod$d9c249f7cd5fb5f45e81da04b06adf97422cf801\$lut for cells of type $lut.
Using template $paramod$02750f8d568bd99efbda01449a05e084a3143ca8\$lut for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$f672f1e5ea7eaf40630014635549af40fc023a51\$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$95884ef07789cca69cca4bd11ba6c919d1a2b875\$lut for cells of type $lut.
Using template $paramod$a48d96b3084901aac1f541d9be59ab6aad37df36\$lut for cells of type $lut.
Using template $paramod$d08ae3e2fee668f1a68bd32fd012d46d229cb782\$lut for cells of type $lut.
Using template $paramod$9cf976b4f3a576aa2cd6b51304cf5de7fc836fbd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$425da8bbf32ad83dea76dd417944f9ef98f2525c\$lut for cells of type $lut.
Using template $paramod$f6b0369b7a6b62efe8db4bdbe0374a320e4dbf53\$lut for cells of type $lut.
Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut.
Using template $paramod$302ba22a83dfb50189674147c5c2626b9e9dab7e\$lut for cells of type $lut.
Using template $paramod$fd16523b66efc91890bfb23f6b1dcc83fa36d799\$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod$0a85ef24bbe0af4c0a398eda4c9c483e3a950ffc\$lut for cells of type $lut.
Using template $paramod$aab54572d5ffecd31253b36e73e9cb718d05be34\$lut for cells of type $lut.
Using template $paramod$c8e56946d7b33b4de9359965a8ef2b5e8c6d31ec\$lut for cells of type $lut.
Using template $paramod$e2520d8be466a84086b4da8143161ae3b479d330\$lut for cells of type $lut.
Using template $paramod$ea8c3614309befced1c4cfc4249e324e2d77ca4c\$lut for cells of type $lut.
Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut.
Using template $paramod$f7744fc299c4b6dc315f22eb6110994661b48d3f\$lut for cells of type $lut.
Using template $paramod$e484b1e0bd351ba5af34f5fd66a8e850cc5b8335\$lut for cells of type $lut.
Using template $paramod$4db3f0d067a6794efd5979ea33ffc0ce06e2e75c\$lut for cells of type $lut.
Using template $paramod$e0a16b39d62021fbd2d1c105eda1b9c3b86f8b30\$lut for cells of type $lut.
Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut.
Using template $paramod$20ba583962918fa0136fc97b1558cc45cc91cc29\$lut for cells of type $lut.
Using template $paramod$4d1533dad4814c51bde53f9a378e78c03dd47a9f\$lut for cells of type $lut.
Using template $paramod$2a20620c354bffb676ef0f9bc2892af8e67982c5\$lut for cells of type $lut.
Using template $paramod$bb896c9520758d48845887b7d5fac44a20655d69\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$238ce1c123ccd5620a61157a2c5350ee6fc4d4ff\$lut for cells of type $lut.
Using template $paramod$31387621d1610a0290872bbf4d90a41c51f62d2e\$lut for cells of type $lut.
Using template $paramod$f4f9de784ca3575929d156571325ea01b8f0a70a\$lut for cells of type $lut.
Using template $paramod$31f64b4b2cb5d8113d9a1455af902b3edbe63394\$lut for cells of type $lut.
Using template $paramod$83cb19296515f545f4c69bf6713ff705a6b55de0\$lut for cells of type $lut.
Using template $paramod$50f9a6467c37a4d0cfda22d5b986a065ac8b06be\$lut for cells of type $lut.
Using template $paramod$4c0221505c29b55a66f4801128a7e9ab143964dc\$lut for cells of type $lut.
Using template $paramod$2d4481c9d2ae7cd8d959f57c294a86ed1352e33b\$lut for cells of type $lut.
Using template $paramod$2ba51c7bf234f9ce3d769281ed286d6830810ff5\$lut for cells of type $lut.
Using template $paramod$7a0b348a7069d0c8f44afe945e212fcf3f3fd64c\$lut for cells of type $lut.
Using template $paramod$60b99ddfae8ffcebbb1fe7f9e676a60f7472edd5\$lut for cells of type $lut.
Using template $paramod$6e8412e945297528d3f6f3ce2a821de69911673c\$lut for cells of type $lut.
Using template $paramod$440c55e9b86a4d19d2d9af4513ac1f3c626292af\$lut for cells of type $lut.
Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut.
Using template $paramod$b29666689b5895d7f4c59f3f89ca40b0a44ebc7f\$lut for cells of type $lut.
Using template $paramod$920f0a1cc9938be111b5c04600835f53cc53f910\$lut for cells of type $lut.
Using template $paramod$a18efd9245448b0a198b87f7e710a6a1c17ab9de\$lut for cells of type $lut.
Using template $paramod$1e5056f17e701b074b5b9bb51f1fdafd68ae2520\$lut for cells of type $lut.
Using template $paramod$23e9bb0ff10d3a9c79f6d3d3cf26137e71ba410d\$lut for cells of type $lut.
Using template $paramod$f7a897257decedfb6cc642e53d65fef7fc0df390\$lut for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut.
Using template $paramod$52d1e412bd12f078644292b145d7825721eeb433\$lut for cells of type $lut.
Using template $paramod$cb63a6e25879a415b84a2418577cc471d6e8d208\$lut for cells of type $lut.
Using template $paramod$4ccee6169b0c58a36a5a004acb932f18d67fbfcc\$lut for cells of type $lut.
Using template $paramod$e8488368726b26e1784e8c2eac92a5addd7a1468\$lut for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod$c058c384c633392b4b79f5cf10f43b61852c2b95\$lut for cells of type $lut.
Using template $paramod$085cb83d0db09780ae5aa544a0f286ba9445143f\$lut for cells of type $lut.
Using template $paramod$a7f859672851132f3d2d2940ee1472fcd00650cb\$lut for cells of type $lut.
Using template $paramod$95993c7d70457a51738c6b0f8898a55038ff3107\$lut for cells of type $lut.
Using template $paramod$78f2830b3bdaa23d946a56e5d472d0f9d7865dd5\$lut for cells of type $lut.
Using template $paramod$ad8700612668374cd530c0eb26afbe5a191ed159\$lut for cells of type $lut.
Using template $paramod$b2b30911308a63f7227e01a0485aa84d04fb8425\$lut for cells of type $lut.
Using template $paramod$fbcdd716a4ea00acec277b2ee1add2b937d6418a\$lut for cells of type $lut.
Using template $paramod$f983ebb11dd4e9235400b2bcd430365f0e2c16f6\$lut for cells of type $lut.
Using template $paramod$3ec5e45cb3e54de9dbe908707155b5f9917c9370\$lut for cells of type $lut.
Using template $paramod$56c6fc98268f6966dd23dcb4af9b8f5298fa7ead\$lut for cells of type $lut.
Using template $paramod$1ea196eb83cd232655d79aada0723cbc2a668eb2\$lut for cells of type $lut.
Using template $paramod$90f80678b5c678e47c26cbc6bbe579cce2c79a45\$lut for cells of type $lut.
Using template $paramod$1f575543d734f2d93dfcc8f91b30fb001334bb95\$lut for cells of type $lut.
Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut.
Using template $paramod$0c82c8f391184e9c3e95dc3a62142a4793ea2390\$lut for cells of type $lut.
Using template $paramod$23496d84c5233265e839dc8a58e76c7e3b2a2d5b\$lut for cells of type $lut.
Using template $paramod$fb4ed309581bcd972f41afa8566ae8b9812c7f6c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$56e6d8a28a52006bb4e50e077743f0a2163235af\$lut for cells of type $lut.
Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut.
Using template $paramod$cf0e777009b9fa214d95cb0cba7e014624b88bc3\$lut for cells of type $lut.
Using template $paramod$1313a6b1a6c981c250f4c9824fa8244853b185a0\$lut for cells of type $lut.
Using template $paramod$61af1d481b7498f3c1c0d3ee184d91bad8d2389f\$lut for cells of type $lut.
Using template $paramod$98c377328f303d3ed9039ca0db26b18f36e929b2\$lut for cells of type $lut.
Using template $paramod$db0052e63506de7ad7fc8dcb58daadd8306f8d61\$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut.
Using template $paramod$c4af7f2c88559dab5f19c52110f1d82cb05f465f\$lut for cells of type $lut.
Using template $paramod$28a53bb6c6a9a5c0cb65efa353716299ec275d23\$lut for cells of type $lut.
Using template $paramod$83c275fd45b33e2ad6e78b030b1b76eb29b38ac8\$lut for cells of type $lut.
Using template $paramod$39a3022e55aa03d0b5478da3a6d9fcb662c62e56\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut.
Using template $paramod$c5e227af307b9c53329a9bcea914f98030ca9bc6\$lut for cells of type $lut.
Using template $paramod$51307cdec77060d17363ea3d60427c9afef1ddc2\$lut for cells of type $lut.
Using template $paramod$f24ba3ced4b870f8e829f5ac5a8af88573350e6f\$lut for cells of type $lut.
Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut.
Using template $paramod$19fe1ba23ba7fdb117bb75432cd43fbe2b988d53\$lut for cells of type $lut.
Using template $paramod$f0c28a28de377bb72130fdf38bf9d493df673759\$lut for cells of type $lut.
Using template $paramod$3d3b27a05038b537a70291f74c8054b2e7044bc8\$lut for cells of type $lut.
Using template $paramod$757c055b2d591f99a56beeb4bd1bdff266f67334\$lut for cells of type $lut.
Using template $paramod$7f7120086b74d2ad6501bbaa30925c183268a1c2\$lut for cells of type $lut.
Using template $paramod$0f1054d7a869eb1bffa14eab6537eeff64eb55da\$lut for cells of type $lut.
Using template $paramod$877f25a4a3e4fd1c08538bf588c1796b84c739a7\$lut for cells of type $lut.
Using template $paramod$050221686252202c3dcb014324b7b753c760a3f5\$lut for cells of type $lut.
Using template $paramod$3b7df84b40237f179c777fa44f7a12c9ed5dcf4b\$lut for cells of type $lut.
Using template $paramod$f12d10d287cac698abbc1fdcf0ed680dbb02f4ab\$lut for cells of type $lut.
Using template $paramod$74bb18f03ae7d4d63f0045b9903bb94ae7da759a\$lut for cells of type $lut.
Using template $paramod$c00a97a4180683080e53823eb85ac210b3105deb\$lut for cells of type $lut.
Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514\$lut for cells of type $lut.
Using template $paramod$81f38dbe34c0131668a5f4192c3c2c07e8338073\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$e94e31904cb3f366c19ab928f0be83b3c0113285\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod$cce6b847e730f5f1cfb4a8ef6c78f9f44e4f1145\$lut for cells of type $lut.
Using template $paramod$688d1b1930305f527f6ca277ea7672730fff14e3\$lut for cells of type $lut.
Using template $paramod$ff4c34c892697f83ba0d96e47f38056385f2a0fc\$lut for cells of type $lut.
Using template $paramod$7191402f23bc32c9e0c6169b9c6968c0d60d92d5\$lut for cells of type $lut.
Using template $paramod$e2d4399e1e149b2bd3c04b32fc0d847bb8cdd6d6\$lut for cells of type $lut.
Using template $paramod$590adea7e2b9aba53477cdd95a6adbd8ad85ac9c\$lut for cells of type $lut.
Using template $paramod$dc3f607d55e1ab4beacef20186049b1cd93fb9be\$lut for cells of type $lut.
Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut.
Using template $paramod$3b56205e0e57b3ea26d80fc7983017f83663129e\$lut for cells of type $lut.
Using template $paramod$8f7210088a40da1859d27e900c288fd298d68bed\$lut for cells of type $lut.
Using template $paramod$9e0d5e3cbbbadb2b139aaae0b912cff38011856c\$lut for cells of type $lut.
Using template $paramod$3f95c15e882729f63793f446e65b165e4b662f5c\$lut for cells of type $lut.
Using template $paramod$caad58040116ab75470aaad37ed97fe8e10a8158\$lut for cells of type $lut.
Using template $paramod$957e56f96aadf5ff00cb0b3fb6b32614376a90df\$lut for cells of type $lut.
Using template $paramod$e21ab7140f5d70efd4439745db2467fa93905bb6\$lut for cells of type $lut.
Using template $paramod$ffc05a226acfd31e6af5121b0fe98d90f7462941\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut.
Using template $paramod$f62bf7b9bf368c5a044dd284e6192cdfb023ea0f\$lut for cells of type $lut.
Using template $paramod$18455d4fd1270af2266bf4bb1c44971b2eb6b37a\$lut for cells of type $lut.
Using template $paramod$73123ef57cf5b679a999a57ecf6fb42fbb6533d3\$lut for cells of type $lut.
Using template $paramod$ac9e3968766d438b96ef7a04264cc79d386f7658\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod$3ee26675fdb86c62f9449255b242f36533c51cab\$lut for cells of type $lut.
Using template $paramod$a7c36edc05c8db41cbf46577da74e02a7f2a516f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$c362ad8dedc7d166ed978091aca319ab1e81a2d4\$lut for cells of type $lut.
Using template $paramod$cedf4e85fa7d99c3f6bd280e7df7624d55412661\$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod$7da7d7bde408365fd9edb48231a23e665dbb7ed8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e\$lut for cells of type $lut.
Using template $paramod$023d9d13c9ddd8e6cbda8fa49753038bbbacbfa4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$323dbb47a6d14615772fecb6fe7c4bec277e6c6b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee\$lut for cells of type $lut.
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$ac0fa5d7a90a8bbe2427a08d007dd31ff56eaf3f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut.
Using template $paramod$f3ee5765ea56176ac8c982f75ee3bef4839909ee\$lut for cells of type $lut.
Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut.
Using template $paramod$75e0e34d4dfcc6790c6d23b7c18487e4249acd2d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$e412821338883e25f2e0d1a1d7fada158db69807\$lut for cells of type $lut.
Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut.
Using template $paramod$70a934594406e8042bf2854c778fef542ef3ea5f\$lut for cells of type $lut.
Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$c5b694ec89d7629b942ccf6a9be1d39e24f8edec\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$75ae9627805e0c99d176bdce0ae8ff0c02687aab\$lut for cells of type $lut.
Using template $paramod$20235ca863361fbc253329cfc7eeea38c77404dc\$lut for cells of type $lut.
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut.
Using template $paramod$9bfe1886af55ab8065e0fb6a586fb9a29caf058d\$lut for cells of type $lut.
Using template $paramod$d0e42eec83ea592bf45e9ec906447f1ed04bd355\$lut for cells of type $lut.
Using template $paramod$244d83ba2e7e81b167beb2b38995cd1740a1a017\$lut for cells of type $lut.
Using template $paramod$ca2167e97c50792f5ced35a59198c1ac5e93e2b7\$lut for cells of type $lut.
Using template $paramod$14be92385bbee427caaa7aeb6d27336100a0e06a\$lut for cells of type $lut.
Using template $paramod$2f01b21e0accd52580ad84d7a99afe91d37fd639\$lut for cells of type $lut.
Using template $paramod$6de442abe246ff8c0692702d40d84ce1c07479d9\$lut for cells of type $lut.
Using template $paramod$72ded892102901a938d0204a3ef623a63cbafebd\$lut for cells of type $lut.
Using template $paramod$5159aa72a9be8cd7c1ab392b987d253f353eb36d\$lut for cells of type $lut.
Using template $paramod$84c5cfa8d7481774250caab0fcdd6d249a376a31\$lut for cells of type $lut.
Using template $paramod$723be7177967d6866729df0ff463a602326a012e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut.
Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut.
Using template $paramod$8833253c105c1f3ff9a03a20302d6d0a2f4d9c5b\$lut for cells of type $lut.
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$cf6936c7d99de0c7f4156f3db3bf26d8befb0936\$lut for cells of type $lut.
Using template $paramod$8e224a63a74b6daf8fc2e441cb0688a65e7a4073\$lut for cells of type $lut.
Using template $paramod$09c0cfb7ba7c1ccd6bbcc158637d85f80001f113\$lut for cells of type $lut.
Using template $paramod$9db1993881d03bd5308ad9239c3179b3b86cd7a2\$lut for cells of type $lut.
Using template $paramod$8b29aeb10cb2dfdf28aeb1de1044554f641e26c0\$lut for cells of type $lut.
Using template $paramod$dd24d8e525309e501adcd3146c939ec8f54e3772\$lut for cells of type $lut.
Using template $paramod$00da6ee835349555028231ae835c9b401a5c1dee\$lut for cells of type $lut.
Using template $paramod$7b6c4d052c7295b2792bd37891e125d30c68d644\$lut for cells of type $lut.
Using template $paramod$7ce7683c590e6b9a2ebd543a8f468551f1af24cf\$lut for cells of type $lut.
Using template $paramod$6f6a7fb6482d3745a696e7ec281190b5f0109710\$lut for cells of type $lut.
Using template $paramod$92c3899764cd8074859d6a5a5b733cffe8a391b3\$lut for cells of type $lut.
Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut.
Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut.
Using template $paramod$085ac7365a6944179805d8afe884e1cb78f0d512\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut.
Using template $paramod$12879138d1e376f344e47ea40be66b776233be75\$lut for cells of type $lut.
Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$362d3371b8ed20fb6ca7b8ef0d2618b79e1f4813\$lut for cells of type $lut.
Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71\$lut for cells of type $lut.
Using template $paramod$2a4b250d89be3556c74aa0e719a4f6242369d42f\$lut for cells of type $lut.
Using template $paramod$9e1755e3954600257bb9b9ab192e2c0243b0f35a\$lut for cells of type $lut.
Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut.
Using template $paramod$df29fe9e6d6d694a9cc5697e4251bf7d8cd4d8e4\$lut for cells of type $lut.
Using template $paramod$6d23198eb2b8f79a41c7626605a61009695893b1\$lut for cells of type $lut.
Using template $paramod$0833e4a4157f571b57062516e7aa9f735c7ed0a0\$lut for cells of type $lut.
Using template $paramod$303607065f6eb15d8928442960164bdd7e8c8c39\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut.
Using template $paramod$b66af2b8158579d12b02bd7ae4b5161b219e1924\$lut for cells of type $lut.
Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut.
Using template $paramod$5dc1dd2a2307e3866b2f9a674fd9134301e1466f\$lut for cells of type $lut.
Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut.
Using template $paramod$ae9cbe56af7d110f5343191e833a294ed77c21e0\$lut for cells of type $lut.
Using template $paramod$95994721d3c832b251cca338772f7ec207995711\$lut for cells of type $lut.
Using template $paramod$9fc14cb0ba5120a1da0c687a9fb19472f206fdfe\$lut for cells of type $lut.
Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut.
Using template $paramod$e01a027fedb28671a20c130493a89c7afd4e87d3\$lut for cells of type $lut.
Using template $paramod$1632c1c0242796acfc963a05742c4acd2f475c4e\$lut for cells of type $lut.
Using template $paramod$d7856980c8e3df62f97c26ab34037f33a9e831b5\$lut for cells of type $lut.
Using template $paramod$cd6c4b4da6d8737b72fd2dc8f5d83d8967445809\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$240e171f8bae87a2fe4bee672a3055fa35afe320\$lut for cells of type $lut.
Using template $paramod$62fb31b1a783eac472264027492b859f55ad08ed\$lut for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut.
Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f\$lut for cells of type $lut.
Using template $paramod$fc58c9af90158fac687a02e52e79f6b0904e5074\$lut for cells of type $lut.
Using template $paramod$2a3aee6f1b16b87fae5ad552f211bb1ef99dfafe\$lut for cells of type $lut.
Using template $paramod$c18316765b193c8fc68dacbcf73829d51ebe1631\$lut for cells of type $lut.
Using template $paramod$b7685cb0c8a6753256bc84bc31d36a443c15fab7\$lut for cells of type $lut.
Using template $paramod$77c2a0573790d304ab2299da6d598e8d2e184867\$lut for cells of type $lut.
Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$3e895991b845b8c620b8c9e0068c52e372d1fbc1\$lut for cells of type $lut.
Using template $paramod$32abbd1d449a67fb913b4733374e345d4c17175b\$lut for cells of type $lut.
Using template $paramod$3f8bddb26a8905ea147acf4247acf6d000ca20f7\$lut for cells of type $lut.
Using template $paramod$3db826965e677cc72a454d5e910d68e35d246aa3\$lut for cells of type $lut.
Using template $paramod$00621a3c55d483214eef3eec42a14cc6a616135c\$lut for cells of type $lut.
Using template $paramod$1e3f8a5d31c944af2c420a98182bc898ab495e11\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut.
Using template $paramod$0fcb06ed76df01e8d45bc2b9e6c8a9b43fa42cb4\$lut for cells of type $lut.
Using template $paramod$1078665aa144cf7ff525a892db61e5cee078ce7c\$lut for cells of type $lut.
Using template $paramod$09ff6bc38860bc684248b0f5479347794277f7f7\$lut for cells of type $lut.
Using template $paramod$74c0f3179b5cebe485563ea55e9b637e7ee5c0c3\$lut for cells of type $lut.
Using template $paramod$52acd744af558b1acd7f06b0e1d721506b042b9b\$lut for cells of type $lut.
Using template $paramod$3258fabf91107b4a007ae89b2246a16c31e8ae28\$lut for cells of type $lut.
Using template $paramod$424d6e5504f284c1c9fcb89924a2758a91d0d4e2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111011 for cells of type $lut.
Using template $paramod$e0e16f0e69ba9e6596b61d072bd230c598f46f32\$lut for cells of type $lut.
Using template $paramod$7b733f5b3466ec911060896fccc5c2626cbe3d64\$lut for cells of type $lut.
Using template $paramod$7e8d331d1e06632d29fbdf6c3afc2de1856d3c67\$lut for cells of type $lut.
Using template $paramod$f4c6fe0020190952fcd7d4a4d5f3ec5a8512a50b\$lut for cells of type $lut.
Using template $paramod$dc10581988ca640d0fb32ac47d12e56acfff793a\$lut for cells of type $lut.
Using template $paramod$29e6d4598488760861f6b73d2b7f65cb302fdcde\$lut for cells of type $lut.
Using template $paramod$ba4b1c9b57f942a38af35848615a2f06189d3bfe\$lut for cells of type $lut.
Using template $paramod$56816554deebe056ecb846d5d4a927b68b8ab003\$lut for cells of type $lut.
Using template $paramod$a56367d136d7dc4a23dd7d5692da8809b431b7f1\$lut for cells of type $lut.
Using template $paramod$e39243124eb3a8d6d78379d1970d7cbb795b1c50\$lut for cells of type $lut.
Using template $paramod$784f4711405f84982df518be1f8d295ab4d5b427\$lut for cells of type $lut.
Using template $paramod$7ccb46ee9b56c39e0a7d82a185b08cb026e04fbc\$lut for cells of type $lut.
Using template $paramod$21a1ca6f9f5c15b304c8c46ce6cda8b91e063cf1\$lut for cells of type $lut.
Using template $paramod$c6a0421f5b5114b68e9782f0585d571421cf8f01\$lut for cells of type $lut.
Using template $paramod$fe4e24b614c63965c11dc88a1deafdb9e255213c\$lut for cells of type $lut.
Using template $paramod$18b66a2dc66be2a0d172c3d50ba03932f5924e22\$lut for cells of type $lut.
Using template $paramod$8c0db9f181e8f62a22ce244eda3828e09c37557c\$lut for cells of type $lut.
Using template $paramod$8d8a6111e2a82db0bfbd78666fa69c753d8df004\$lut for cells of type $lut.
Using template $paramod$5afe21d6fdc7c33aeb338fdb508ea02813207bfd\$lut for cells of type $lut.
Using template $paramod$189e88d497adae6ca37717cdb181bb2c6415c908\$lut for cells of type $lut.
Using template $paramod$f03663c7f91be924d1e9df8220b895406b3f6489\$lut for cells of type $lut.
Using template $paramod$9c7a967a5dd69d8b7070c7493295b0c7b420660f\$lut for cells of type $lut.
Using template $paramod$82ed25b11a6a11eb861f4dd3d46f5fc9aa1eebaf\$lut for cells of type $lut.
Using template $paramod$8cac5452d526045503c5864c3a1dac0121c7053e\$lut for cells of type $lut.
Using template $paramod$bb2e3da3f50c642f1ba2a4b036322559c80c8088\$lut for cells of type $lut.
Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402\$lut for cells of type $lut.
Using template $paramod$6c51c1ba6c39f0c09b896d52432b366f116bd3c1\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$383937d21a28172b345409fac698db2f2097b514\$lut for cells of type $lut.
Using template $paramod$6e3a03c79073e44642e8ed2dab4ee82dfd40dfba\$lut for cells of type $lut.
Using template $paramod$76a3573bcdc463a06a69af63dc6e05bcdfd81fc9\$lut for cells of type $lut.
Using template $paramod$183ec76ed3429a430a8be24b57f3de734985f568\$lut for cells of type $lut.
Using template $paramod$5f99aa1a31b4f0c356281a67e16706e1e689d29f\$lut for cells of type $lut.
Using template $paramod$4385b611926e5c0509dba4de58311d325da0ff0d\$lut for cells of type $lut.
Using template $paramod$71b6d833a4170eede1dcc8409c3fc7460c2df8d9\$lut for cells of type $lut.
Using template $paramod$b22ba37c34e69c72fbc3647cad959d4a2b5366fe\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26\$lut for cells of type $lut.
Using template $paramod$658d8ae8f10d8bd0c2aa5487f4823315bd52b0e0\$lut for cells of type $lut.
Using template $paramod$f00c0376cdf8518a9288594305173c177a0a27e2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut.
Using template $paramod$263b613d26e59958a0d1e36903a2016b82f2f359\$lut for cells of type $lut.
Using template $paramod$4f6ef5838c139220e91b3d9534b74e9d61193cac\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$ab4188c7524eec831e9177bc675d62b21a3ccd8b\$lut for cells of type $lut.
Using template $paramod$811a39cc5365627b9ae26581054f3a4477281b93\$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$02b63907fb626de3e5f6572173cbabd407ece191\$lut for cells of type $lut.
Using template $paramod$3b9568ec5a46302f9cbc51f59214d0908f01aa31\$lut for cells of type $lut.
Using template $paramod$3c712553f2f5a448e8c696903ee0800251a0a2fe\$lut for cells of type $lut.
Using template $paramod$4d673f44384ebded9d542bceabb0e9271e6f9336\$lut for cells of type $lut.
Using template $paramod$95c95ad5ff5e8913d849041bd15c71cab184de35\$lut for cells of type $lut.
Using template $paramod$68fb804d669647184c50ec0cf4be7adc48bffd61\$lut for cells of type $lut.
Using template $paramod$e46b6ec985dc11aea9db28100b02ce8dd695948c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod$899a7d400185b4f778bea81a50f62c95a0b19d77\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod$8b24fb07373c4ee224b517e500c9710a464b35dc\$lut for cells of type $lut.
Using template $paramod$531ab17e2e1260426d6ef9925b4ed2d798463bdf\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut.
Using template $paramod$3c17557fcd213346f7b38856ecb30fe49bafcccd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$22c25d613899ade7d2e410f426ffff42f8da3567\$lut for cells of type $lut.
Using template $paramod$651e836885d95717c36e69441422c3fe04ee5f4d\$lut for cells of type $lut.
Using template $paramod$0e6f7067c2a44b2e3cbef1e1c87513a6042c22b4\$lut for cells of type $lut.
Using template $paramod$de5328836923c44c99600bcab852423201246f91\$lut for cells of type $lut.
Using template $paramod$d01b12b2e3fe73c32cc2ed54e644a6c6afdf052a\$lut for cells of type $lut.
Using template $paramod$56abb120b7f083882b1440587b6d9f3a229c9ef5\$lut for cells of type $lut.
Using template $paramod$d77ed6ee97ee637e059d4c865314c2fbcd7e2b1c\$lut for cells of type $lut.
Using template $paramod$e9d317c55f397705fc52599574a03ca7c6820239\$lut for cells of type $lut.
Using template $paramod$33844396c65e360198a3f6cab98eb67cf799695c\$lut for cells of type $lut.
Using template $paramod$fc4c231d1b8b034b24b5324d045443e2e9694ca3\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~10676 debug messages>

22.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127370.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127371.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$21185.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20187.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$19441.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$16481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$15823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$15812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$15774.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$15458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$15133.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$14690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$14690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$14690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$14690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$14684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$14637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$13952.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13952.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$13946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$13465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127516.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127515.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$13021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127522.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12417.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12417.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12417.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12417.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12417.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12248.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12248.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12191.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11911.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$11846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$11821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$11821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$11803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$11803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$11779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11699.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11699.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11699.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11699.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11699.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11699.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$11576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$11291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$11001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$10734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$10236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$10665.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10661.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10657.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$10534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$10502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$10476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$10476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127587.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127587.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127587.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$10449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$10130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$10143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10545.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$10210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$10236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$10254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$10438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10449.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$10476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127559.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$10502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10527.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$10534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10573.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10581.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10592.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10600.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10800.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$10990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11001.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11025.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$11342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11432.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11519.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11532.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$11591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$11599.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$11607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut\SOC.Core.Alu.ALU_out_S[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$11655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$11663.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$11682.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11699.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11699.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11779.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11786.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11794.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$11803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11803.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$11839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11846.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11850.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$11868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11883.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11893.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11974.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$11995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12160.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12272.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12283.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12331.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12355.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12417.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12417.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12736.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12897.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12923.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$12948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$12963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$12968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$12996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13015.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13040.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$13060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$13128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$13465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$13473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$13516.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13895.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$13916.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$13946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13952.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$13964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14045.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$14113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14249.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14294.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$14301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$14354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14421.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14469.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$14524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14620.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$14637.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14647.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14678.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14700.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$14809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14938.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$14945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$14997.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15013.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$15125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$15138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15257.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15353.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$15360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15376.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15421.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$15462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$15509.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15541.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15603.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15645.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15706.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$15713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$15812.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15827.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$15886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$15990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16016.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16318.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16375.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$16413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16474.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$16502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$16507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$16560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16619.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16652.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16710.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16723.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$16730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$16876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16937.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$16944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$16994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17097.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17232.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17679.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17705.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17763.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17796.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$17863.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$17874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$17943.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$17977.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$17984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18019.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18035.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18269.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18282.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$18289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18315.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18487.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$18542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$18572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18986.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$18993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$19208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$19243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$19380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19412.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19445.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$19452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$19499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$19531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19631.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$19671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19700.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$19775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19836.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$19864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$19887.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$19922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19955.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$19983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$19990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20016.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20084.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20191.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$20231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20274.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$20555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20605.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20628.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20679.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20777.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$20784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20865.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$20919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20929.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$20936.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$20987.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$21236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$21304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21357.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$21507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21558.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$21605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$21673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21705.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21752.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$21895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21921.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$21980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$21996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$22117.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$22190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$22264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$22281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22395.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22428.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$22486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22627.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$22748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$22765.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22842.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$22849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$22958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$22975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$22991.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23089.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23213.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23376.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23496.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23548.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$23658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23772.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23779.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23975.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23982.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$23992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$23999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24113.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24181.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$24435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24467.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24488.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24511.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$24556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$aiger127289$24614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$127290$lut$auto$fsm_map.cc:170:map_fsm$2217[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$13143.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$auto$fsm_map.cc:170:map_fsm$2217[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$21189.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut$aiger127289$13201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$127290$lut$auto$rtlil.cc:2582:Mux$2704[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$24220.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$127290$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127396.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127375.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127401.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127408.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127413.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127423.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127433.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127428.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127446.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127460.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127495.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127513.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127523.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127543.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127554.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$127290$lut$aiger127289$10650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$127290$lut$aiger127289$10193.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$127599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Removed 0 unused cells and 14307 unused wires.

22.45. Executing AUTONAME pass.
Renamed 256509 objects in module top (269 iterations).
<suppressed ~16904 debug messages>

22.46. Executing HIERARCHY pass (managing design hierarchy).

22.46.1. Analyzing design hierarchy..
Top module:  \top

22.46.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

22.47. Printing statistics.

=== top ===

   Number of wires:               7912
   Number of wire bits:          22357
   Number of public wires:        7912
   Number of public wire bits:   22357
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              10303
     $_TBUF_                         6
     $scopeinfo                     30
     CCU2C                         293
     L6MUX21                       399
     LUT4                         6431
     PFUMX                        1382
     TRELLIS_DPR16X4              1060
     TRELLIS_FF                    702

22.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

22.49. Executing JSON backend.

Warnings: 213 unique messages, 214 total
End of script. Logfile hash: 87f12fe231, CPU: user 12.44s system 0.10s, MEM: 253.09 MB peak
Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)
Time spent: 41% 1x abc9_exe (8 sec), 10% 11x techmap (2 sec), ...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (NextPNR)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2030.328 ; gain = 405.684 ; free physical = 9125 ; free virtual = 29053
---------------------------------------------------------------------------------
Info: constraining clock net 'clk' to 25.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:     13377/43848    30%
Info:         logic LUTs:   6431/43848    14%
Info:         carry LUTs:    586/43848     1%
Info:           RAM LUTs:   4240/ 5481    77%
Info:          RAMW LUTs:   2120/10962    19%

Info:      Total DFFs:       702/43848     1%

Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     317 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xb0a0d393

Info: Device utilisation:
Info: 	          TRELLIS_IO:    18/  245     7%
Info: 	                DCCA:     1/   56     1%
Info: 	              DP16KD:     0/  108     0%
Info: 	          MULT18X18D:     0/   72     0%
Info: 	              ALU54B:     0/   36     0%
Info: 	             EHXPLLL:     0/    4     0%
Info: 	             EXTREFB:     0/    2     0%
Info: 	                DCUA:     0/    2     0%
Info: 	           PCSCLKDIV:     0/    2     0%
Info: 	             IOLOGIC:     0/  160     0%
Info: 	            SIOLOGIC:     0/   85     0%
Info: 	                 GSR:     0/    1     0%
Info: 	               JTAGG:     0/    1     0%
Info: 	                OSCG:     0/    1     0%
Info: 	               SEDGA:     0/    1     0%
Info: 	                 DTR:     0/    1     0%
Info: 	             USRMCLK:     0/    1     0%
Info: 	             CLKDIVF:     0/    4     0%
Info: 	           ECLKSYNCB:     0/   10     0%
Info: 	             DLLDELD:     0/    8     0%
Info: 	              DDRDLL:     0/    4     0%
Info: 	             DQSBUFM:     0/   10     0%
Info: 	     TRELLIS_ECLKBUF:     0/    8     0%
Info: 	        ECLKBRIDGECS:     0/    2     0%
Info: 	                DCSC:     0/    2     0%
Info: 	          TRELLIS_FF:   702/43848     1%
Info: 	        TRELLIS_COMB: 13461/43848    30%
Info: 	        TRELLIS_RAMW:  1060/ 5481    19%

Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 6122 cells, random placement wirelen = 571852.
INFO: [Synth 8-11241] undeclared symbol 'pc_source', assumed default net type 'wire' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:112]
WARNING: [Synth 8-11065] parameter 'SET_DIRECTION' becomes localparam in 'GPIOS' with formal parameter declaration list [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:17]
WARNING: [Synth 8-11065] parameter 'READ' becomes localparam in 'GPIOS' with formal parameter declaration list [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:18]
WARNING: [Synth 8-9400] empty statement in sequential block [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:40]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:17]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:16]
INFO: [Synth 8-6157] synthesizing module 'top' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1]
	Parameter CYCLES bound to: 20 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1]
WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:17]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 3 connections declared, but only 2 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:17]
INFO: [Synth 8-6157] synthesizing module 'Risco_5_SOC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
	Parameter CLOCK_FREQ bound to: 100000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter MEMORY_SIZE bound to: 2048 - type: integer 
	Parameter MEMORY_FILE bound to: ../../software/memory/fpga_test_3.hex - type: string 
	Parameter GPIO_WIDHT bound to: 8 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:1]
	Parameter BOOT_ADDRESS bound to: 0 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'PC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'PC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6157] synthesizing module 'MUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:11]
INFO: [Synth 8-6155] done synthesizing module 'MUX' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1]
WARNING: [Synth 8-7071] port 'C' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:79]
WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'MemoryAddressMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:79]
WARNING: [Synth 8-7023] instance 'MemoryAddressMUX' of module 'MUX' has 6 connections declared, but only 4 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:79]
WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'MemoryDataMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:86]
WARNING: [Synth 8-7023] instance 'MemoryDataMUX' of module 'MUX' has 6 connections declared, but only 5 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:86]
WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'AluInputBMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:103]
WARNING: [Synth 8-7023] instance 'AluInputBMUX' of module 'MUX' has 6 connections declared, but only 5 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:103]
WARNING: [Synth 8-7071] port 'C' of module 'MUX' is unconnected for instance 'PCSourceMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:111]
WARNING: [Synth 8-7071] port 'D' of module 'MUX' is unconnected for instance 'PCSourceMUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:111]
WARNING: [Synth 8-7023] instance 'PCSourceMUX' of module 'MUX' has 6 connections declared, but only 4 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:111]
INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1]
INFO: [Synth 8-6157] synthesizing module 'Control_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:1]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:82]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:86]
INFO: [Synth 8-6155] done synthesizing module 'Control_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:1]
INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:33]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:10]
INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6157] synthesizing module 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:132]
INFO: [Synth 8-6155] done synthesizing module 'CSR_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
WARNING: [Synth 8-7071] port 'save_pc' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:174]
WARNING: [Synth 8-7071] port 'interrupt_on_hold' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:174]
WARNING: [Synth 8-7023] instance 'CSR_Unit' of module 'CSR_Unit' has 15 connections declared, but only 13 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:174]
INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:1]
WARNING: [Synth 8-7071] port 'instruction_request_external' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:29]
WARNING: [Synth 8-7071] port 'instruction_request_timer' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:29]
WARNING: [Synth 8-7071] port 'instruction_request_software' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:29]
WARNING: [Synth 8-7071] port 'instruction_request_fast' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:29]
WARNING: [Synth 8-7023] instance 'Core' of module 'Core' has 12 connections declared, but only 8 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:29]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
	Parameter MEMORY_FILE bound to: ../../software/memory/fpga_test_3.hex - type: string 
	Parameter MEMORY_SIZE bound to: 2048 - type: integer 
INFO: [Synth 8-3876] $readmem data file '../../software/memory/fpga_test_3.hex' is read successfully [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:29]
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
INFO: [Synth 8-6157] synthesizing module 'BUS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6155] done synthesizing module 'BUS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6157] synthesizing module 'LEDs' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6155] done synthesizing module 'LEDs' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
	Parameter CLOCK_FREQ bound to: 100000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
	Parameter DEPTH bound to: 8 - type: integer 
	Parameter WIDTH bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_rx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 100000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_rx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_tx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 100000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_tx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'GPIOS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
	Parameter WIDHT bound to: 8 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'GPIO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIOS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Risco_5_SOC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
WARNING: [Synth 8-3848] Net interrupt_on_hold in module/entity CSR_Unit does not have driver. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:20]
WARNING: [Synth 8-6014] Unused sequential element buffer_full_reg was removed.  [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:49]
WARNING: [Synth 8-6014] Unused sequential element tx_fifo_read_reg was removed.  [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:43]
Info:     at initial placer iter 0, wirelen = 2265
WARNING: [Synth 8-7129] Port address[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[4] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[3] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[2] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[16] in module UART is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2113.297 ; gain = 488.652 ; free physical = 8686 ; free virtual = 28615
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2131.109 ; gain = 506.465 ; free physical = 8686 ; free virtual = 28615
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2131.109 ; gain = 506.465 ; free physical = 8686 ; free virtual = 28615
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2131.109 ; gain = 0.000 ; free physical = 8686 ; free virtual = 28615
Info:     at initial placer iter 1, wirelen = 2052
Info:     at initial placer iter 2, wirelen = 1949
Info:     at initial placer iter 3, wirelen = 1795
Info: Running main analytical placer, max placement attempts per cell = 29039820.
Info:     at iteration #1, type ALL: wirelen solved = 1877, spread = 98278, legal = 99282; time = 0.39s
Info:     at iteration #2, type ALL: wirelen solved = 6486, spread = 73430, legal = 74448; time = 0.44s
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2280.859 ; gain = 0.000 ; free physical = 8678 ; free virtual = 28607
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2280.895 ; gain = 0.000 ; free physical = 8678 ; free virtual = 28607
Info:     at iteration #3, type ALL: wirelen solved = 12689, spread = 68748, legal = 70343; time = 0.45s
Info:     at iteration #4, type ALL: wirelen solved = 16322, spread = 67334, legal = 68758; time = 0.58s
Info:     at iteration #5, type ALL: wirelen solved = 18634, spread = 60306, legal = 61722; time = 0.41s
Info:     at iteration #6, type ALL: wirelen solved = 19583, spread = 58065, legal = 59410; time = 0.40s
Info:     at iteration #7, type ALL: wirelen solved = 23674, spread = 55518, legal = 56840; time = 0.40s
Info:     at iteration #8, type ALL: wirelen solved = 24581, spread = 53545, legal = 55185; time = 0.54s
Info:     at iteration #9, type ALL: wirelen solved = 26191, spread = 53713, legal = 55224; time = 0.39s
Info:     at iteration #10, type ALL: wirelen solved = 27078, spread = 53491, legal = 54947; time = 0.38s
Info:     at iteration #11, type ALL: wirelen solved = 28965, spread = 51331, legal = 52895; time = 0.37s
Info:     at iteration #12, type ALL: wirelen solved = 28846, spread = 51275, legal = 52927; time = 0.37s
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.895 ; gain = 656.250 ; free physical = 8659 ; free virtual = 28588
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.895 ; gain = 656.250 ; free physical = 8659 ; free virtual = 28588
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.895 ; gain = 656.250 ; free physical = 8659 ; free virtual = 28588
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
           RESET_COUNTER |                               00 |                               01
                    IDLE |                               01 |                               10
                    INIT |                               10 |                               00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                   FETCH |                 0000000000000001 |                             0000
                  DECODE |                 0000000000000010 |                             0001
                  MEMADR |                 0000000000000100 |                             0010
                 MEMREAD |                 0000000000001000 |                             0011
                   MEMWB |                 0000000000010000 |                             0100
                MEMWRITE |                 0000000000100000 |                             0101
                EXECUTER |                 0000000001000000 |                             0110
                EXECUTEI |                 0000000010000000 |                             1000
                     JAL |                 0000000100000000 |                             1001
                     BEQ |                 0000001000000000 |                             1010
                   AUIPC |                 0000010000000000 |                             1100
                     LUI |                 0000100000000000 |                             1101
                 JALR_PC |                 0001000000000000 |                             1110
                    JALR |                 0010000000000000 |                             1011
                   ALUWB |                 0100000000000000 |                             0111
              EXECUTECSR |                 1000000000000000 |                             1111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
WARNING: [Synth 8-327] inferring latch for variable 'aluop_out_reg' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:12]
Info:     at iteration #13, type ALL: wirelen solved = 29699, spread = 50722, legal = 52374; time = 0.61s
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_RECV |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_SEND |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2280.895 ; gain = 656.250 ; free physical = 8662 ; free virtual = 28592
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input   32 Bit       Adders := 1     
	   3 Input   32 Bit       Adders := 1     
	   2 Input   11 Bit       Adders := 2     
	   2 Input    6 Bit       Adders := 4     
	   2 Input    5 Bit       Adders := 1     
	   2 Input    4 Bit       Adders := 2     
+---XORs : 
	   2 Input     32 Bit         XORs := 1     
+---Registers : 
	               33 Bit    Registers := 1     
	               32 Bit    Registers := 44    
	               16 Bit    Registers := 2     
	               11 Bit    Registers := 2     
	                8 Bit    Registers := 8     
	                6 Bit    Registers := 1     
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 17    
+---RAMs : 
	              16K Bit	(512 X 32 bit)          RAMs := 1     
	               64 Bit	(8 X 8 bit)          RAMs := 2     
+---Muxes : 
	   3 Input   33 Bit        Muxes := 1     
	   4 Input   32 Bit        Muxes := 18    
	   2 Input   32 Bit        Muxes := 34    
	   8 Input   32 Bit        Muxes := 1     
	  16 Input   32 Bit        Muxes := 1     
	   6 Input   32 Bit        Muxes := 1     
	  16 Input   16 Bit        Muxes := 1     
	  11 Input   16 Bit        Muxes := 1     
	   2 Input   16 Bit        Muxes := 1     
	   2 Input    8 Bit        Muxes := 3     
	   5 Input    8 Bit        Muxes := 1     
	   3 Input    6 Bit        Muxes := 1     
	   2 Input    6 Bit        Muxes := 4     
	   2 Input    5 Bit        Muxes := 1     
	  10 Input    4 Bit        Muxes := 1     
	   8 Input    4 Bit        Muxes := 1     
	  23 Input    4 Bit        Muxes := 1     
	  10 Input    3 Bit        Muxes := 1     
	   2 Input    3 Bit        Muxes := 1     
	   3 Input    2 Bit        Muxes := 1     
	   2 Input    2 Bit        Muxes := 14    
	  16 Input    2 Bit        Muxes := 3     
	   4 Input    2 Bit        Muxes := 4     
	   3 Input    1 Bit        Muxes := 6     
	   2 Input    1 Bit        Muxes := 49    
	  16 Input    1 Bit        Muxes := 6     
	   4 Input    1 Bit        Muxes := 2     
	  13 Input    1 Bit        Muxes := 2     
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
Info:     at iteration #14, type ALL: wirelen solved = 29970, spread = 50410, legal = 51862; time = 0.41s
Info:     at iteration #15, type ALL: wirelen solved = 30799, spread = 51346, legal = 52785; time = 0.36s
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN  (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":172)
WARN  (NL0002) : The module "MUX" instantiated to "MemoryAddressMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
[95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
Info:     at iteration #16, type ALL: wirelen solved = 31799, spread = 50993, legal = 52403; time = 0.38s
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template. 
Info:     at iteration #17, type ALL: wirelen solved = 31739, spread = 50716, legal = 52290; time = 0.46s
Info:     at iteration #18, type ALL: wirelen solved = 32550, spread = 49245, legal = 51011; time = 0.53s
Info:     at iteration #19, type ALL: wirelen solved = 33153, spread = 48674, legal = 50236; time = 0.38s
[100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg"
Info:     at iteration #20, type ALL: wirelen solved = 33159, spread = 48618, legal = 50122; time = 0.37s
Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Processing netlist completed
Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst"
Physical Constraint parsed completed
Running placement......
Info:     at iteration #21, type ALL: wirelen solved = 33470, spread = 48253, legal = 49921; time = 0.38s
Info:     at iteration #22, type ALL: wirelen solved = 34019, spread = 48505, legal = 50285; time = 0.60s
Info:     at iteration #23, type ALL: wirelen solved = 34237, spread = 48471, legal = 50139; time = 0.55s
Info:     at iteration #24, type ALL: wirelen solved = 33974, spread = 48741, legal = 50487; time = 0.48s
Info:     at iteration #25, type ALL: wirelen solved = 34622, spread = 48140, legal = 49774; time = 0.37s
Info:     at iteration #26, type ALL: wirelen solved = 34923, spread = 48041, legal = 49839; time = 0.40s
Info:     at iteration #27, type ALL: wirelen solved = 34851, spread = 48621, legal = 50409; time = 0.53s
[10%] Placement Phase 0 completed
Info:     at iteration #28, type ALL: wirelen solved = 35543, spread = 48106, legal = 49837; time = 0.38s
Info:     at iteration #29, type ALL: wirelen solved = 35451, spread = 47554, legal = 49470; time = 0.38s
Info:     at iteration #30, type ALL: wirelen solved = 35806, spread = 47705, legal = 49576; time = 0.36s
[20%] Placement Phase 1 completed
Info:     at iteration #31, type ALL: wirelen solved = 36043, spread = 48110, legal = 50096; time = 0.53s
Info:     at iteration #32, type ALL: wirelen solved = 36127, spread = 48277, legal = 50072; time = 0.41s
Info:     at iteration #33, type ALL: wirelen solved = 36829, spread = 48261, legal = 49822; time = 0.37s
Info:     at iteration #34, type ALL: wirelen solved = 36856, spread = 48170, legal = 49729; time = 0.39s
Info: HeAP Placer Time: 22.84s
Info:   of which solving equations: 13.38s
Info:   of which spreading cells: 1.70s
Info:   of which strict legalisation: 0.54s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 18921, wirelen = 49470
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 2280.895 ; gain = 656.250 ; free physical = 8334 ; free virtual = 28273
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object                  | Inference | Size (Depth x Width) | Primitives      | 
+------------+-----------------------------+-----------+----------------------+-----------------+
|top         | SOC/Memory/memory_reg       | Implied   | 512 x 32             | RAM256X1S x 64  | 
|top         | SOC/Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
|top         | SOC/Uart/TX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
+------------+-----------------------------+-----------+----------------------+-----------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2280.895 ; gain = 656.250 ; free physical = 8333 ; free virtual = 28272
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
Info:   at iteration #5: temp = 0.000000, timing cost = 18828, wirelen = 43612
[30%] Placement Phase 2 completed
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2280.895 ; gain = 656.250 ; free physical = 8307 ; free virtual = 28246
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object                  | Inference | Size (Depth x Width) | Primitives      | 
+------------+-----------------------------+-----------+----------------------+-----------------+
|top         | SOC/Memory/memory_reg       | Implied   | 512 x 32             | RAM256X1S x 64  | 
|top         | SOC/Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
|top         | SOC/Uart/TX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
+------------+-----------------------------+-----------+----------------------+-----------------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2280.895 ; gain = 656.250 ; free physical = 8274 ; free virtual = 28213
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2280.895 ; gain = 656.250 ; free physical = 8268 ; free virtual = 28207
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2280.895 ; gain = 656.250 ; free physical = 8267 ; free virtual = 28206
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2280.895 ; gain = 656.250 ; free physical = 8271 ; free virtual = 28210
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2280.895 ; gain = 656.250 ; free physical = 8269 ; free virtual = 28208
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:47 ; elapsed = 00:00:47 . Memory (MB): peak = 2280.895 ; gain = 656.250 ; free physical = 8272 ; free virtual = 28211
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:47 ; elapsed = 00:00:47 . Memory (MB): peak = 2280.895 ; gain = 656.250 ; free physical = 8272 ; free virtual = 28211
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+----------+------+
|      |Cell      |Count |
+------+----------+------+
|1     |BUFG      |     1|
|2     |CARRY4    |    55|
|3     |LUT1      |    19|
|4     |LUT2      |   139|
|5     |LUT3      |    70|
|6     |LUT4      |   153|
|7     |LUT5      |   391|
|8     |LUT6      |  1334|
|9     |MUXF7     |   256|
|10    |RAM256X1S |    64|
|11    |RAM32M    |     2|
|12    |RAM32X1D  |     4|
|13    |FDRE      |  1721|
|14    |FDSE      |     5|
|15    |LD        |     4|
|16    |IBUF      |     2|
|17    |OBUF      |     9|
|18    |OBUFT     |     8|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:47 ; elapsed = 00:00:47 . Memory (MB): peak = 2280.895 ; gain = 656.250 ; free physical = 8272 ; free virtual = 28211
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 43 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2280.895 ; gain = 506.465 ; free physical = 8272 ; free virtual = 28211
Synthesis Optimization Complete : Time (s): cpu = 00:00:47 ; elapsed = 00:00:47 . Memory (MB): peak = 2280.895 ; gain = 656.250 ; free physical = 8272 ; free virtual = 28211
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2280.895 ; gain = 0.000 ; free physical = 8548 ; free virtual = 28487
INFO: [Netlist 29-17] Analyzing 385 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Info:   at iteration #10: temp = 0.000000, timing cost = 20551, wirelen = 42012
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2352.891 ; gain = 0.000 ; free physical = 8546 ; free virtual = 28485
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 74 instances were transformed.
  LD => LDCE: 4 instances
  RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances

Synth Design complete | Checksum: 2749c0b
INFO: [Common 17-83] Releasing license: Synthesis
75 Infos, 130 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:00:53 . Memory (MB): peak = 2352.926 ; gain = 1078.195 ; free physical = 8546 ; free virtual = 28485
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2034.902; main = 1783.999; forked = 422.878
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3218.504; main = 2352.895; forked = 969.656
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors, 8 Warnings
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.84 . Memory (MB): peak = 2416.922 ; gain = 63.996 ; free physical = 8535 ; free virtual = 28474

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 15925b380

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2517.742 ; gain = 100.820 ; free physical = 8501 ; free virtual = 28440

Starting Logic Optimization Task

Phase 1 Initialization

Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 15925b380

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2767.648 ; gain = 0.000 ; free physical = 8235 ; free virtual = 28174

Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 15925b380

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2767.648 ; gain = 0.000 ; free physical = 8235 ; free virtual = 28174
Phase 1 Initialization | Checksum: 15925b380

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2767.648 ; gain = 0.000 ; free physical = 8235 ; free virtual = 28174

Phase 2 Timer Update And Timing Data Collection

Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 15925b380

Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2767.648 ; gain = 0.000 ; free physical = 8227 ; free virtual = 28167

Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 15925b380

Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2767.648 ; gain = 0.000 ; free physical = 8226 ; free virtual = 28166
Phase 2 Timer Update And Timing Data Collection | Checksum: 15925b380

Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2767.648 ; gain = 0.000 ; free physical = 8226 ; free virtual = 28166

Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 3 inverters resulting in an inversion of 9 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 2621db72c

Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2767.648 ; gain = 0.000 ; free physical = 8217 ; free virtual = 28156
Retarget | Checksum: 2621db72c
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 11 cells

Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 2621db72c

Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2767.648 ; gain = 0.000 ; free physical = 8218 ; free virtual = 28157
Constant propagation | Checksum: 2621db72c
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 5 Sweep
Phase 5 Sweep | Checksum: 236eec1f4

Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2767.648 ; gain = 0.000 ; free physical = 8213 ; free virtual = 28153
Sweep | Checksum: 236eec1f4
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 0 cells

Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 236eec1f4

Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2799.664 ; gain = 32.016 ; free physical = 8213 ; free virtual = 28152
BUFG optimization | Checksum: 236eec1f4
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 236eec1f4

Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2799.664 ; gain = 32.016 ; free physical = 8213 ; free virtual = 28152
Shift Register Optimization | Checksum: 236eec1f4
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 232eeb757

Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2799.664 ; gain = 32.016 ; free physical = 8213 ; free virtual = 28152
Post Processing Netlist | Checksum: 232eeb757
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells

Phase 9 Finalization

Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 14806a170

Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.4 . Memory (MB): peak = 2799.664 ; gain = 32.016 ; free physical = 8215 ; free virtual = 28154

Phase 9.2 Verifying Netlist Connectivity

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.664 ; gain = 0.000 ; free physical = 8215 ; free virtual = 28154
Phase 9.2 Verifying Netlist Connectivity | Checksum: 14806a170

Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2799.664 ; gain = 32.016 ; free physical = 8215 ; free virtual = 28154
Phase 9 Finalization | Checksum: 14806a170

Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2799.664 ; gain = 32.016 ; free physical = 8215 ; free virtual = 28154
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |              11  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               8  |               0  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------


Ending Logic Optimization Task | Checksum: 14806a170

Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2799.664 ; gain = 32.016 ; free physical = 8215 ; free virtual = 28154
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.664 ; gain = 0.000 ; free physical = 8215 ; free virtual = 28154

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 14806a170

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.664 ; gain = 0.000 ; free physical = 8215 ; free virtual = 28154

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 14806a170

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.664 ; gain = 0.000 ; free physical = 8215 ; free virtual = 28154

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.664 ; gain = 0.000 ; free physical = 8215 ; free virtual = 28154
Ending Netlist Obfuscation Task | Checksum: 14806a170

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.664 ; gain = 0.000 ; free physical = 8215 ; free virtual = 28154
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2799.664 ; gain = 446.738 ; free physical = 8215 ; free virtual = 28154
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 8 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2831.680 ; gain = 0.000 ; free physical = 8215 ; free virtual = 28155
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1105c4d3c

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2831.680 ; gain = 0.000 ; free physical = 8215 ; free virtual = 28155
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2831.680 ; gain = 0.000 ; free physical = 8215 ; free virtual = 28155

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: c2b9d6f2

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2831.680 ; gain = 0.000 ; free physical = 8215 ; free virtual = 28155

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1035d4b79

Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8215 ; free virtual = 28154

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1035d4b79

Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8215 ; free virtual = 28154
Phase 1 Placer Initialization | Checksum: 1035d4b79

Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8215 ; free virtual = 28154

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1b8b689da

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8208 ; free virtual = 28148

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1103ade3f

Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8220 ; free virtual = 28160

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1103ade3f

Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8217 ; free virtual = 28157

Phase 2.4 Global Placement Core
Info:   at iteration #15: temp = 0.000000, timing cost = 19199, wirelen = 41292
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed

Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: ceea6ed7

Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8168 ; free virtual = 28107

Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 48 LUTNM shape to break, 41 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 15, two critical 33, total 48, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 61 nets or LUTs. Breaked 48 LUTs, combined 13 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8167 ; free virtual = 28106

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |           48  |             13  |                    61  |           0  |           1  |  00:00:00  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |           48  |             13  |                    61  |           0  |           9  |  00:00:00  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.2 Physical Synthesis In Placer | Checksum: 18af9d291

Time (s): cpu = 00:00:27 ; elapsed = 00:00:09 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8165 ; free virtual = 28104
Phase 2.4 Global Placement Core | Checksum: 1b078c7e4

Time (s): cpu = 00:00:31 ; elapsed = 00:00:09 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8164 ; free virtual = 28104
Phase 2 Global Placement | Checksum: 1b078c7e4

Time (s): cpu = 00:00:31 ; elapsed = 00:00:09 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8164 ; free virtual = 28104

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1fb62ed45

Time (s): cpu = 00:00:32 ; elapsed = 00:00:10 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8164 ; free virtual = 28104

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c0f49b53

Time (s): cpu = 00:00:34 ; elapsed = 00:00:10 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8164 ; free virtual = 28104

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1bbb47b6b

Time (s): cpu = 00:00:34 ; elapsed = 00:00:10 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8164 ; free virtual = 28104

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1e1ede7bc

Time (s): cpu = 00:00:34 ; elapsed = 00:00:10 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8164 ; free virtual = 28104

Phase 3.5 Fast Optimization
Info:   at iteration #20: temp = 0.000000, timing cost = 18518, wirelen = 41115
Phase 3.5 Fast Optimization | Checksum: 1db4cf242

Time (s): cpu = 00:00:39 ; elapsed = 00:00:14 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8159 ; free virtual = 28098

Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 144a82b42

Time (s): cpu = 00:00:41 ; elapsed = 00:00:16 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8153 ; free virtual = 28092

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 1467ad040

Time (s): cpu = 00:00:41 ; elapsed = 00:00:16 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8153 ; free virtual = 28092

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 131d70474

Time (s): cpu = 00:00:41 ; elapsed = 00:00:16 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8153 ; free virtual = 28092

Phase 3.9 Fast Optimization
[70%] Routing Phase 1 completed
Phase 3.9 Fast Optimization | Checksum: 1760021b3

Time (s): cpu = 00:00:48 ; elapsed = 00:00:20 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8139 ; free virtual = 28078
Phase 3 Detail Placement | Checksum: 1760021b3

Time (s): cpu = 00:00:48 ; elapsed = 00:00:20 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8139 ; free virtual = 28078

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 37f1a22c

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.071 | TNS=-52.440 |
Phase 1 Physical Synthesis Initialization | Checksum: 5d771248

Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8139 ; free virtual = 28079
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 5d771248

Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8139 ; free virtual = 28079
Phase 4.1.1.1 BUFG Insertion | Checksum: 37f1a22c

Time (s): cpu = 00:00:52 ; elapsed = 00:00:22 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8139 ; free virtual = 28079

Phase 4.1.1.2 Post Placement Timing Optimization
Info:   at iteration #25: temp = 0.000000, timing cost = 19070, wirelen = 41042
[80%] Routing Phase 2 completed
Info:   at iteration #30: temp = 0.000000, timing cost = 18272, wirelen = 41008
Info:   at iteration #30: temp = 0.000000, timing cost = 18257, wirelen = 41008 
Info: SA placement time 58.84s

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 29.23 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.24 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 8.28 ns

Info: Slack histogram:
Info:  legend: * represents 144 endpoint(s)
Info:          + represents [1,144) endpoint(s)
Info: [  5786,   7459) |+
Info: [  7459,   9132) |*+
Info: [  9132,  10805) |********+
Info: [ 10805,  12478) |****+
Info: [ 12478,  14151) |+
Info: [ 14151,  15824) |******+
Info: [ 15824,  17497) |*************+
Info: [ 17497,  19170) |*************+
Info: [ 19170,  20843) |************************************************************ 
Info: [ 20843,  22516) |***********************************************************+
Info: [ 22516,  24189) |******+
Info: [ 24189,  25862) |**+
Info: [ 25862,  27535) |**+
Info: [ 27535,  29208) |+
Info: [ 29208,  30881) |+
Info: [ 30881,  32554) |+
Info: [ 32554,  34227) |**+
Info: [ 34227,  35900) |**+
Info: [ 35900,  37573) |+
Info: [ 37573,  39246) |*+
Info: Checksum: 0x67560895
Info: Routing globals...
Info:     routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0

Info: Routing..
Info: Setting up routing queue.
Info: Routing 66293 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |      107        892 |  107   892 |     65690|       1.26       1.26|
Info:       2000 |      238       1761 |  131   869 |     65018|       0.30       1.56|
Info:       3000 |      417       2582 |  179   821 |     64399|       0.36       1.92|
Info:       4000 |      568       3431 |  151   849 |     63866|       0.36       2.28|
Info:       5000 |      725       4274 |  157   843 |     63356|       0.34       2.62|
Info:       6000 |      826       5173 |  101   899 |     63127|       0.35       2.97|
Info:       7000 |      979       6020 |  153   847 |     62787|       0.38       3.35|
Info:       8000 |     1098       6901 |  119   881 |     62146|       0.34       3.69|
Info:       9000 |     1226       7773 |  128   872 |     62004|       0.39       4.07|
Info:      10000 |     1332       8667 |  106   894 |     61359|       0.36       4.43|
WARN  (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
[90%] Routing Phase 3 completed
Info:      11000 |     1458       9541 |  126   874 |     60763|       0.37       4.81|
Running timing analysis......
Info:      12000 |     1619      10380 |  161   839 |     60430|       0.48       5.28|
Info:      13000 |     1769      11230 |  150   850 |     60250|       0.45       5.74|
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.017. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: bfbf9288

Time (s): cpu = 00:01:14 ; elapsed = 00:00:40 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8132 ; free virtual = 28072

Time (s): cpu = 00:01:14 ; elapsed = 00:00:40 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8132 ; free virtual = 28072
Phase 4.1 Post Commit Optimization | Checksum: bfbf9288

Time (s): cpu = 00:01:14 ; elapsed = 00:00:40 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8132 ; free virtual = 28072

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: bfbf9288

Time (s): cpu = 00:01:14 ; elapsed = 00:00:40 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8132 ; free virtual = 28072

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                4x4|
|___________|___________________|___________________|
|      South|                1x1|                1x1|
|___________|___________________|___________________|
|       East|                1x1|                1x1|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: bfbf9288

Time (s): cpu = 00:01:14 ; elapsed = 00:00:40 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8132 ; free virtual = 28072
Phase 4.3 Placer Reporting | Checksum: bfbf9288

Time (s): cpu = 00:01:14 ; elapsed = 00:00:40 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8132 ; free virtual = 28072

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8132 ; free virtual = 28072

Time (s): cpu = 00:01:14 ; elapsed = 00:00:40 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8132 ; free virtual = 28072
Phase 4 Post Placement Optimization and Clean-Up | Checksum: f21d45c8

Time (s): cpu = 00:01:14 ; elapsed = 00:00:40 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8132 ; free virtual = 28072
Ending Placer Task | Checksum: ef006d9e

Time (s): cpu = 00:01:14 ; elapsed = 00:00:40 . Memory (MB): peak = 2838.707 ; gain = 7.027 ; free physical = 8132 ; free virtual = 28072
37 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:01:16 ; elapsed = 00:00:40 . Memory (MB): peak = 2838.707 ; gain = 39.043 ; free physical = 8132 ; free virtual = 28072
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
Info:      14000 |     1899      12100 |  130   870 |     59702|       0.34       6.08|
report_io: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8132 ; free virtual = 28071
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8134 ; free virtual = 28074
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
Info:      15000 |     2058      12941 |  159   841 |     59256|       0.40       6.48|
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
Info:      16000 |     2197      13802 |  139   861 |     58687|       0.43       6.90|
INFO: [DRC 23-27] Running DRC with 8 threads
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Info:      17000 |     2347      14652 |  150   850 |     57985|       0.48       7.38|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs

Phase 1 Build RT Design
Checksum: PlaceDB: 970cab0f ConstDB: 0 ShapeSum: 57f3c28f RouteDB: 0
Info:      18000 |     2498      15501 |  151   849 |     57523|       0.54       7.92|
Info:      19000 |     2643      16356 |  145   855 |     57031|       0.43       8.35|
Info:      20000 |     2822      17177 |  179   821 |     56920|       0.40       8.75|
Info:      21000 |     2954      18045 |  132   868 |     56544|       0.43       9.18|
Info:      22000 |     3085      18914 |  131   869 |     56091|       0.40       9.58|
Info:      23000 |     3215      19784 |  130   870 |     55589|       0.38       9.96|
Info:      24000 |     3345      20654 |  130   870 |     55534|       0.32      10.28|
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
Info:      25000 |     3483      21516 |  138   862 |     55266|       0.41      10.69|
Info:      26000 |     3596      22403 |  113   887 |     54675|       0.41      11.10|
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Sun Apr 14 16:41:48 2024

[Pipeline] }
Info:      27000 |     3748      23251 |  152   848 |     54235|       0.44      11.55|
[Pipeline] // stage
Info:      28000 |     3904      24095 |  156   844 |     54284|       0.34      11.89|
[Pipeline] }
Info:      29000 |     4028      24971 |  124   876 |     53841|       0.39      12.28|
Info:      30000 |     4102      25897 |   74   926 |     53610|       0.35      12.63|
Info:      31000 |     4189      26810 |   87   913 |     53503|       0.37      12.99|
Info:      32000 |     4296      27703 |  107   893 |     52783|       0.41      13.40|
Info:      33000 |     4426      28573 |  130   870 |     52389|       0.50      13.90|
Info:      34000 |     4554      29445 |  128   872 |     52809|       0.42      14.33|
Info:      35000 |     4686      30313 |  132   868 |     52195|       0.41      14.74|
Info:      36000 |     4806      31193 |  120   880 |     51628|       0.43      15.16|
Info:      37000 |     4930      32069 |  124   876 |     51181|       0.41      15.57|
Info:      38000 |     4995      33004 |   65   935 |     51448|       0.37      15.94|
Info:      39000 |     5097      33902 |  102   898 |     51345|       0.40      16.34|
Info:      40000 |     5192      34807 |   95   905 |     50897|       0.37      16.71|
Info:      41000 |     5318      35681 |  126   874 |     50757|       0.39      17.10|
Info:      42000 |     5402      36597 |   84   916 |     50880|       0.32      17.42|
Info:      43000 |     5493      37506 |   91   909 |     50235|       0.32      17.74|
Info:      44000 |     5572      38427 |   79   921 |     49770|       0.35      18.09|
Info:      45000 |     5733      39266 |  161   839 |     49274|       0.37      18.46|
Info:      46000 |     5872      40127 |  139   861 |     48685|       0.47      18.93|
Info:      47000 |     6075      40924 |  203   797 |     48644|       0.47      19.40|
Info:      48000 |     6267      41732 |  192   808 |     48928|       0.46      19.87|
Info:      49000 |     6367      42632 |  100   900 |     48732|       0.49      20.36|
Info:      50000 |     6486      43513 |  119   881 |     48044|       0.41      20.77|
Info:      51000 |     6654      44345 |  168   832 |     47447|       0.42      21.18|
Info:      52000 |     6789      45210 |  135   865 |     47067|       0.41      21.59|
Info:      53000 |     6891      46108 |  102   898 |     46959|       0.42      22.02|
Info:      54000 |     6919      47080 |   28   972 |     46678|       0.34      22.36|
Info:      55000 |     7100      47899 |  181   819 |     46136|       0.44      22.80|
Info:      56000 |     7190      48809 |   90   910 |     46244|       0.38      23.18|
Info:      57000 |     7248      49751 |   58   942 |     45486|       0.45      23.63|
Info:      58000 |     7407      50592 |  159   841 |     44899|       0.47      24.10|
Info:      59000 |     7539      51460 |  132   868 |     44252|       0.44      24.54|
Info:      60000 |     7709      52290 |  170   830 |     44484|       0.42      24.96|
Info:      61000 |     7786      53213 |   77   923 |     43725|       0.53      25.49|
Info:      62000 |     7942      54057 |  156   844 |     44145|       0.39      25.88|
Info:      63000 |     7950      55049 |    8   992 |     43177|       0.28      26.16|
Info:      64000 |     8127      55872 |  177   823 |     42564|       0.38      26.54|
Info:      65000 |     8341      56658 |  214   786 |     42917|       0.49      27.03|
Info:      66000 |     8518      57481 |  177   823 |     42716|       0.52      27.55|
Info:      67000 |     8702      58297 |  184   816 |     42358|       0.48      28.03|
Info:      68000 |     8839      59160 |  137   863 |     42613|       0.46      28.49|
Info:      69000 |     8865      60134 |   26   974 |     42632|       0.48      28.96|
Info:      70000 |     8908      61091 |   43   957 |     41721|       0.48      29.44|
Info:      71000 |     9110      61889 |  202   798 |     41204|       0.46      29.91|
Info:      72000 |     9187      62812 |   77   923 |     41129|       0.39      30.30|
Info:      73000 |     9274      63725 |   87   913 |     41234|       0.52      30.82|
Info:      74000 |     9433      64566 |  159   841 |     40898|       0.53      31.35|
Info:      75000 |     9616      65383 |  183   817 |     40541|       0.42      31.76|
Info:      76000 |     9775      66224 |  159   841 |     39926|       0.40      32.17|
Info:      77000 |     9952      67047 |  177   823 |     39705|       0.57      32.74|
Info:      78000 |    10069      67930 |  117   883 |     39210|       0.40      33.14|
Info:      79000 |    10218      68781 |  149   851 |     38671|       0.45      33.59|
Info:      80000 |    10440      69559 |  222   778 |     38568|       0.41      34.00|
Info:      81000 |    10583      70416 |  143   857 |     38464|       0.59      34.60|
Info:      82000 |    10779      71220 |  196   804 |     37998|       0.56      35.16|
Info:      83000 |    10927      72072 |  148   852 |     37558|       0.56      35.71|
Info:      84000 |    11096      72903 |  169   831 |     36889|       0.50      36.21|
Info:      85000 |    11264      73735 |  168   832 |     36614|       0.60      36.81|
Info:      86000 |    11392      74607 |  128   872 |     36927|       0.67      37.49|
Info:      87000 |    11490      75509 |   98   902 |     36332|       0.63      38.12|
Info:      88000 |    11665      76334 |  175   825 |     36197|       0.55      38.67|
Info:      89000 |    11742      77257 |   77   923 |     37068|       0.51      39.18|
Post Restoration Checksum: NetGraph: 9d600986 | NumContArr: 5d0968c3 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 27fbb6783

Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8421 ; free virtual = 28367

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 27fbb6783

Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8421 ; free virtual = 28367

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 27fbb6783

Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8421 ; free virtual = 28367
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 200092481

Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8402 ; free virtual = 28349
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.253  | TNS=0.000  | WHS=-0.153 | THS=-12.672|


Router Utilization Summary
  Global Vertical Routing Utilization    = 0.00073987 %
  Global Horizontal Routing Utilization  = 0.0004973 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 3354
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 3351
  Number of Partially Routed Nets     = 3
  Number of Node Overlaps             = 1

Phase 2 Router Initialization | Checksum: 271a90c68

Time (s): cpu = 00:00:40 ; elapsed = 00:00:29 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8402 ; free virtual = 28349

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 271a90c68

Time (s): cpu = 00:00:40 ; elapsed = 00:00:29 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8402 ; free virtual = 28349

Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 155d4214f

Time (s): cpu = 00:00:43 ; elapsed = 00:00:30 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8402 ; free virtual = 28349
Phase 3 Initial Routing | Checksum: 155d4214f

Time (s): cpu = 00:00:43 ; elapsed = 00:00:30 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8402 ; free virtual = 28349

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 1680
Info:      90000 |    11846      78153 |  104   896 |     36564|       0.52      39.70|
Info:      91000 |    11953      79046 |  107   893 |     35899|       0.57      40.27|
Info:      92000 |    12162      79837 |  209   791 |     35574|       0.62      40.89|
 Number of Nodes with overlaps = 615
Info:      93000 |    12345      80654 |  183   817 |     35176|       0.67      41.56|
 Number of Nodes with overlaps = 362
Info:      94000 |    12525      81474 |  180   820 |     35066|       0.67      42.22|
Info:      95000 |    12615      82384 |   90   910 |     35015|       0.62      42.84|
Info:      96000 |    12755      83244 |  140   860 |     34622|       0.57      43.41|
 Number of Nodes with overlaps = 240
Info:      97000 |    12906      84093 |  151   849 |     34463|       0.65      44.06|
Info:      98000 |    13147      84852 |  241   759 |     33848|       0.60      44.66|
Info:      99000 |    13283      85716 |  136   864 |     34360|       0.55      45.21|
 Number of Nodes with overlaps = 145
Info:     100000 |    13435      86564 |  152   848 |     34035|       0.58      45.80|
Info:     101000 |    13600      87399 |  165   835 |     33375|       0.59      46.38|
Info:     102000 |    13801      88198 |  201   799 |     32728|       0.52      46.90|
 Number of Nodes with overlaps = 76
Info:     103000 |    14094      88905 |  293   707 |     32271|       0.64      47.54|
 Number of Nodes with overlaps = 50
Info:     104000 |    14319      89680 |  225   775 |     31739|       0.67      48.21|
Info:     105000 |    14585      90414 |  266   734 |     31238|       0.58      48.78|
 Number of Nodes with overlaps = 29
 Number of Nodes with overlaps = 19
Info:     106000 |    14869      91130 |  284   716 |     30837|       0.54      49.32|
 Number of Nodes with overlaps = 12
 Number of Nodes with overlaps = 5
Info:     107000 |    15284      91715 |  415   585 |     30461|       0.50      49.81|
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 0
Info:     108000 |    15530      92469 |  246   754 |     30191|       0.51      50.32|
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.028 | TNS=-83.943| WHS=N/A    | THS=N/A    |

Info:     109000 |    15888      93111 |  358   642 |     29811|       0.52      50.85|
Phase 4.1 Global Iteration 0 | Checksum: 232d7c8b4

Time (s): cpu = 00:01:20 ; elapsed = 00:00:43 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8377 ; free virtual = 28323

Phase 4.2 Global Iteration 1
Info:     110000 |    16217      93782 |  329   671 |     29483|       0.56      51.41|
 Number of Nodes with overlaps = 766
Info:     111000 |    16563      94436 |  346   654 |     29000|       0.60      52.01|
Info:     112000 |    16954      95045 |  391   609 |     28516|       0.67      52.68|
Info:     113000 |    17302      95697 |  348   652 |     28329|       0.67      53.35|
 Number of Nodes with overlaps = 412
Info:     114000 |    17702      96297 |  400   600 |     28004|       0.64      54.00|
 Number of Nodes with overlaps = 240
Info:     115000 |    17861      97138 |  159   841 |     28182|       0.62      54.62|
Info:     116000 |    18177      97822 |  316   684 |     27817|       0.61      55.23|
Info:     117000 |    18637      98362 |  460   540 |     27506|       0.65      55.88|
 Number of Nodes with overlaps = 166
Info:     118000 |    18930      99069 |  293   707 |     29154|       0.70      56.57|
 Number of Nodes with overlaps = 97
Info:     119000 |    18965     100034 |   35   965 |     28215|       0.66      57.24|
 Number of Nodes with overlaps = 76
Info:     120000 |    19024     100975 |   59   941 |     29041|       0.70      57.93|
Info:     121000 |    19112     101887 |   88   912 |     28464|       0.70      58.64|
Info:     122000 |    19168     102831 |   56   944 |     27762|       0.53      59.16|
 Number of Nodes with overlaps = 29
 Number of Nodes with overlaps = 17
Info:     123000 |    19377     103622 |  209   791 |     27144|       0.62      59.79|
Info:     124000 |    19802     104197 |  425   575 |     26768|       0.53      60.32|
 Number of Nodes with overlaps = 12
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 4
Info:     125000 |    20200     104799 |  398   602 |     26505|       0.55      60.87|
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.071 | TNS=-73.151| WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 26bbe5f40

Time (s): cpu = 00:01:44 ; elapsed = 00:00:54 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8377 ; free virtual = 28324
Phase 4 Rip-up And Reroute | Checksum: 26bbe5f40

Time (s): cpu = 00:01:44 ; elapsed = 00:00:54 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8377 ; free virtual = 28324

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 26a5b9294

Time (s): cpu = 00:01:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8381 ; free virtual = 28328
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.948 | TNS=-73.824| WHS=N/A    | THS=N/A    |

Info:     126000 |    20596     105403 |  396   604 |     26165|       0.69      61.56|
 Number of Nodes with overlaps = 0
Phase 5.1 Delay CleanUp | Checksum: 2bd066f60

Time (s): cpu = 00:01:46 ; elapsed = 00:00:54 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8381 ; free virtual = 28328

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 2bd066f60

Time (s): cpu = 00:01:46 ; elapsed = 00:00:54 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8381 ; free virtual = 28328
Phase 5 Delay and Skew Optimization | Checksum: 2bd066f60

Time (s): cpu = 00:01:46 ; elapsed = 00:00:54 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8381 ; free virtual = 28328

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Info:     127000 |    21043     105956 |  447   553 |     25887|       0.62      62.17|
Phase 6.1.1 Update Timing | Checksum: 2d7fffb2b

Time (s): cpu = 00:01:47 ; elapsed = 00:00:55 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8381 ; free virtual = 28328
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.886 | TNS=-74.673| WHS=0.081  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 2d7fffb2b

Time (s): cpu = 00:01:47 ; elapsed = 00:00:55 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8381 ; free virtual = 28328
Phase 6 Post Hold Fix | Checksum: 2d7fffb2b

Time (s): cpu = 00:01:47 ; elapsed = 00:00:55 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8381 ; free virtual = 28328

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 1.07046 %
  Global Horizontal Routing Utilization  = 1.36367 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0


--GLOBAL Congestion:
Utilization threshold used for congestion level computation: 0.85
Congestion Report
North Dir 1x1 Area, Max Cong = 64.8649%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 66.6667%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 72.0588%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 75%, No Congested Regions.

------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0

Phase 7 Route finalize | Checksum: 2d7fffb2b

Time (s): cpu = 00:01:47 ; elapsed = 00:00:55 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8381 ; free virtual = 28328

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 2d7fffb2b

Time (s): cpu = 00:01:47 ; elapsed = 00:00:55 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8381 ; free virtual = 28328

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 2b42b6adb

Time (s): cpu = 00:01:48 ; elapsed = 00:00:55 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8381 ; free virtual = 28328

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.886 | TNS=-74.673| WHS=0.081  | THS=0.000  |

WARNING: [Route 35-328] Router estimated timing not met.
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
Info:     128000 |    21496     106503 |  453   547 |     25568|       0.51      62.69|
Phase 10 Post Router Timing | Checksum: 2b42b6adb

Time (s): cpu = 00:01:49 ; elapsed = 00:00:55 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8381 ; free virtual = 28328
INFO: [Route 35-16] Router Completed Successfully

Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: d1cd68ab

Time (s): cpu = 00:01:49 ; elapsed = 00:00:55 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8381 ; free virtual = 28328
Ending Routing Task | Checksum: d1cd68ab

Time (s): cpu = 00:01:49 ; elapsed = 00:00:55 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8381 ; free virtual = 28328

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
13 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:51 ; elapsed = 00:00:56 . Memory (MB): peak = 2838.707 ; gain = 0.000 ; free physical = 8381 ; free virtual = 28328
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Info:     129000 |    22002     106997 |  506   494 |     25220|       0.51      63.20|
Info:     130000 |    22492     107507 |  490   510 |     24980|       0.55      63.75|
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (12)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (4)
5. checking no_input_delay (1)
6. checking no_output_delay (9)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (12)
-------------------------
 There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[6]/Q (HIGH)

 There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[7]/Q (HIGH)

 There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[9]/Q (HIGH)


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (4)
------------------------------------------------
 There are 4 pins that are not constrained for maximum delay. (HIGH)

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (1)
------------------------------
 There is 1 input port with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (9)
-------------------------------
 There are 9 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
     -0.887      -74.687                    198                 6655        0.081        0.000                      0                 6655        3.750        0.000                       0                  2015  


Timing constraints are not met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock        Waveform(ns)       Period(ns)      Frequency(MHz)
-----        ------------       ----------      --------------
sys_clk_pin  {0.000 5.000}      10.000          100.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
sys_clk_pin        -0.887      -74.687                    198                 6655        0.081        0.000                      0                 6655        3.750        0.000                       0                  2015  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
Info:     131000 |    23026     107973 |  534   466 |     24731|       0.59      64.34|
INFO: [DRC 23-27] Running DRC with 8 threads
Info:     132000 |    23584     108415 |  558   442 |     24433|       0.50      64.83|
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Info:     133000 |    23779     109220 |  195   805 |     24704|       0.89      65.73|
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...
Info:     134000 |    24096     109903 |  317   683 |     24391|       0.66      66.38|

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Info:     135000 |    24576     110423 |  480   520 |     24105|       0.54      66.92|
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
Info:     136000 |    25084     110915 |  508   492 |     23850|       0.49      67.41|
Info:     137000 |    25541     111458 |  457   543 |     23734|       0.47      67.88|
Info:     138000 |    25979     112020 |  438   562 |     23623|       0.51      68.38|
Info:     139000 |    26340     112659 |  361   639 |     23309|       0.49      68.87|
Info:     140000 |    26852     113147 |  512   488 |     23016|       0.47      69.34|
Info:     141000 |    27206     113793 |  354   646 |     22850|       0.57      69.90|
Info:     142000 |    27531     114468 |  325   675 |     22731|       0.52      70.43|
Info:     143000 |    28053     114946 |  522   478 |     22406|       0.47      70.90|
Info:     144000 |    28488     115499 |  435   553 |     21961|       0.42      71.32|
Info:     145000 |    28814     116168 |  326   669 |     21983|       0.47      71.79|
Info:     146000 |    29043     116934 |  229   766 |     21629|       0.51      72.30|
Info:     147000 |    29452     117510 |  409   576 |     21270|       0.45      72.75|
Info:     148000 |    29812     118113 |  360   603 |     20705|       0.31      73.06|
Info:     149000 |    30174     118703 |  362   590 |     20207|       0.35      73.41|
Info:     150000 |    30519     119336 |  345   633 |     19847|       0.39      73.80|
Info:     151000 |    30858     119965 |  339   629 |     19457|       0.36      74.16|
Info:     152000 |    31224     120558 |  366   593 |     18993|       0.37      74.53|
Info:     153000 |    31671     121069 |  447   511 |     18563|       0.40      74.93|
Info:     154000 |    32179     121519 |  508   450 |     18167|       0.41      75.34|
Info:     155000 |    32731     121928 |  552   409 |     17805|       0.41      75.75|
Info:     156000 |    33254     122358 |  523   430 |     17466|       0.44      76.19|
Info:     157000 |    33814     122762 |  560   404 |     17154|       0.43      76.62|
Info:     158000 |    34350     123177 |  536   415 |     16785|       0.44      77.06|
Info:     159000 |    34826     123629 |  476   452 |     16341|       0.49      77.54|
Info:     160000 |    35217     124137 |  391   508 |     15807|       0.41      77.96|
Info:     161000 |    35396     124934 |  179   797 |     15698|       0.47      78.43|
Info:     162000 |    35618     125529 |  222   595 |     14993|       0.32      78.74|
Info:     163000 |    35753     126205 |  135   676 |     14136|       0.25      78.99|
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
WARNING: [DRC PDRC-153] Gated clock check: Net SOC/Core/Control_Unit/FSM_onehot_state_reg[9]_0[0] is a gated clock net sourced by a combinational pin SOC/Core/Control_Unit/aluop_out_reg[3]_i_2/O, cell SOC/Core/Control_Unit/aluop_out_reg[3]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Info:     164000 |    35777     127119 |   24   914 |     13161|       0.15      79.14|
Info:     165000 |    35795     128070 |   18   951 |     12179|       0.15      79.29|
Info:     166000 |    35818     129029 |   23   959 |     11204|       0.15      79.44|
Info:     167000 |    35827     130007 |    9   978 |     10214|       0.14      79.58|
Info:     168000 |    35852     130974 |   25   967 |      9242|       0.15      79.72|
Info:     169000 |    35855     131965 |    3   991 |      8245|       0.14      79.86|
Info:     170000 |    35863     132949 |    8   984 |      7253|       0.14      80.00|
Info:     171000 |    35875     133931 |   12   982 |      6266|       0.15      80.15|
Info:     172000 |    35884     134919 |    9   988 |      5278|       0.15      80.30|
Info:     173000 |    35907     135888 |   23   969 |      4303|       0.16      80.46|
Info:     174000 |    35928     136861 |   21   973 |      3325|       0.16      80.63|
Info:     175000 |    36036     137733 |  108   872 |      2454|       0.29      80.91|
Info:     176000 |    36272     138471 |  236   738 |      1822|       0.40      81.31|
Loading site data...
Info:     177000 |    36410     139225 |  138   754 |      1188|       0.45      81.76|
Info:     178000 |    36447     139956 |   37   731 |       234|       0.36      82.12|
Info:     178233 |    36447     140073 |    0   117 |         0|       0.18      82.30|
Info: Routing complete.
Info: Router1 time 82.30s
Info: Checksum: 0xa376a95d
Loading route data...
Processing options...
Creating bitmap...

Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_3.Q
Info:  1.8  2.3    Net SOC.Core.Alu.ALU_out_S_LUT4_Z_2_B_LUT4_A_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_LUT4_Z_D[1] (34,31) -> (40,21)
Info:                Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.D
Info:                Defined in:
Info:                  Risco-5/src/core/control_unit.v:51.11-51.16
Info:  0.2  2.6  Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F
Info:  1.7  4.2    Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D[2] (40,21) -> (35,8)
Info:                Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  4.5  Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_LUT4_Z.F
Info:  1.9  6.4    Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1 (35,8) -> (37,18)
Info:                Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_COMB0.B
Info:  0.4  6.9  Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  6.9    Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_FCI_INT (37,18) -> (37,18)
Info:                Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  6.9  Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  6.9    Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT (37,18) -> (37,18)
Info:                Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  6.9  Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_COMB0.FCO
Info:  0.0  6.9    Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_FCI_INT (37,18) -> (37,18)
Info:                Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_COMB1.FCI
Info:  0.0  6.9  Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_COMB1.FCO
Info:  0.0  6.9    Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN_COUT (37,18) -> (37,18)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.0  Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  7.0    Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (37,18) -> (37,18)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  7.0  Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  7.0    Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (37,18) -> (38,18)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.1  Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  7.1    Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (38,18) -> (38,18)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  7.1  Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  7.1    Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (38,18) -> (38,18)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.2  Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  7.2    Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (38,18) -> (38,18)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  7.2  Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  7.2    Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (38,18) -> (38,18)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.2  Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  7.2    Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (38,18) -> (38,18)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  7.2  Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  7.2    Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (38,18) -> (38,18)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.3  Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  7.3    Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (38,18) -> (38,18)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  7.3  Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  7.3    Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (38,18) -> (39,18)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.4  Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  7.4    Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (39,18) -> (39,18)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  7.4  Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  7.4    Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B0_CCU2C_B1_CIN (39,18) -> (39,18)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  7.4  Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  7.4    Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (39,18) -> (39,18)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  7.4  Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  7.4    Net $nextpnr_CCU2C_1$CIN (39,18) -> (39,18)
Info:                Sink $nextpnr_CCU2C_1$CCU2_COMB0.FCI
Info:  0.4  7.9  Source $nextpnr_CCU2C_1$CCU2_COMB0.F
Info:  1.0  8.9    Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B0_CCU2C_B1_COUT (39,18) -> (38,21)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B1_LUT4_C.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  9.1  Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B1_LUT4_C.F
Info:  2.7 11.8    Net SOC.Bus.slave_1_write_LUT4_Z_C[1] (38,21) -> (17,39)
Info:                Sink SOC.Memory.address_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 12.0  Source SOC.Memory.address_LUT4_Z.F
Info:  3.6 15.6    Net SOC.slave_address[5] (17,39) -> (14,4)
Info:                Sink SOC.Memory.memory.0.771$DPRAM_COMB3.A
Info:                Defined in:
Info:                  Risco-5/src/peripheral/soc.v:22.5-22.18
Info:  0.2 15.8  Source SOC.Memory.memory.0.771$DPRAM_COMB3.F
Info:  0.9 16.7    Net SOC.Memory.memory.0.771_DO[3] (14,4) -> (13,4)
Info:                Sink SOC.Memory.memory.0.771_DO_LUT4_C.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 17.0  Source SOC.Memory.memory.0.771_DO_LUT4_C.F
Info:  0.9 17.8    Net SOC.Memory.memory.0.771_DO_LUT4_C_Z[3] (13,4) -> (13,6)
Info:                Sink SOC.Memory.memory.0.771_DO_LUT4_C_Z_LUT4_A.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 18.1  Source SOC.Memory.memory.0.771_DO_LUT4_C_Z_LUT4_A.F
Info:  1.6 19.6    Net SOC.Memory.memory.0.459_DO_LUT4_C_Z_LUT4_A_Z[2] (13,6) -> (21,14)
Info:                Sink SOC.Memory.memory.0.987_DO_LUT4_C_Z_LUT4_A_Z_LUT4_Z_1.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 19.9  Source SOC.Memory.memory.0.987_DO_LUT4_C_Z_LUT4_A_Z_LUT4_Z_1.F
Info:  0.9 20.7    Net SOC.Memory.memory.0.987_DO_LUT4_C_Z_LUT4_A_Z[4] (21,14) -> (22,16)
Info:                Sink SOC.Memory.memory.0.403_DO_LUT4_C_Z_LUT4_B_Z_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 21.0  Source SOC.Memory.memory.0.403_DO_LUT4_C_Z_LUT4_B_Z_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.4 21.4    Net SOC.Memory.memory.0.403_DO_LUT4_C_Z_LUT4_B_Z_LUT4_C_Z[4] (22,16) -> (22,16)
Info:                Sink SOC.Memory.memory.0.727_DO_LUT4_C_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 21.6  Source SOC.Memory.memory.0.727_DO_LUT4_C_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  3.1 24.7    Net SOC.Core.read_data_LUT4_Z_13_D[0] (22,16) -> (40,43)
Info:                Sink SOC.Core.read_data_PFUMX_Z_10_BLUT_LUT4_Z.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.4 25.1  Source SOC.Core.read_data_PFUMX_Z_10_BLUT_LUT4_Z.OFX
Info:  0.9 26.1    Net SOC.read_data[23] (40,43) -> (40,39)
Info:                Sink SOC.Core.memory_register_TRELLIS_FF_Q_8.M
Info:                Defined in:
Info:                  Risco-5/src/peripheral/soc.v:21.34-21.43
Info:  0.0 26.1  Setup SOC.Core.memory_register_TRELLIS_FF_Q_8.M
Info: 4.8 ns logic, 21.3 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source rx$tr_io.O
Info:  2.5  2.5    Net rx$TRELLIS_IO_IN (90,20) -> (68,5)
Info:                Sink SOC.Uart.i_uart_rx.rxd_reg_0_TRELLIS_FF_Q.M
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:4.16-4.18
Info:  0.0  2.5  Setup SOC.Uart.i_uart_rx.rxd_reg_0_TRELLIS_FF_Q.M
Info: 0.0 ns logic, 2.5 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source SOC.Leds.data_TRELLIS_FF_Q_29.Q
Info:  1.9  2.5    Net SOC.Core.read_data_LUT4_Z_2_C[0] (41,31) -> (60,36)
Info:                Sink led_LUT4_Z_6.D
Info:                Defined in:
Info:                  Risco-5/src/peripheral/leds.v:15.12-15.16
Info:  0.2  2.7  Source led_LUT4_Z_6.F
Info:  2.7  5.4    Net led[2]$TRELLIS_IO_OUT (60,36) -> (90,44)
Info:                Sink led[2]$tr_io.I
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 4.6 ns routing

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 38.33 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 2.51 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 5.39 ns

Info: Slack histogram:
Info:  legend: * represents 211 endpoint(s)
Info:          + represents [1,211) endpoint(s)
Info: [ 13911,  15169) |+
Info: [ 15169,  16427) |***+
Info: [ 16427,  17685) |*****+
Info: [ 17685,  18943) |+
Info: [ 18943,  20201) |+
Info: [ 20201,  21459) |***+
Info: [ 21459,  22717) |*********+
Info: [ 22717,  23975) |******+
Info: [ 23975,  25233) |********************+
Info: [ 25233,  26491) |************************************************************ 
Info: [ 26491,  27749) |*********+
Info: [ 27749,  29007) |*+
Info: [ 29007,  30265) |*+
Info: [ 30265,  31523) |*+
Info: [ 31523,  32781) |+
Info: [ 32781,  34039) |+
Info: [ 34039,  35297) |+
Info: [ 35297,  36555) |*+
Info: [ 36555,  37813) |*+
Info: [ 37813,  39071) |+
Creating bitstream...
Writing bitstream ./build/out.bit...

Info: Program finished normally.
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
[Pipeline] }
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 3153.832 ; gain = 236.270 ; free physical = 8471 ; free virtual = 28462
INFO: [Common 17-206] Exiting Vivado at Sun Apr 14 16:43:03 2024...
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
	0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] sh
[Pipeline] }
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz   -> real 6.00MHz  
Open file DONE
Parse file DONE
load program
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] }

Loading: [====                                              ] 7.94%[Pipeline] // script

Load SRAM: [=========                                         ] 18.00%[Pipeline] }
[Pipeline] // stage
[Pipeline] }

Loading: [========                                          ] 15.87%
Load SRAM: [===================                               ] 38.00%
Loading: [============                                      ] 23.81%
Load SRAM: [=============================                     ] 58.00%
Loading: [================                                  ] 31.74%
Load SRAM: [=======================================           ] 78.00%
Loading: [====================                              ] 39.68%
Load SRAM: [================================================= ] 98.00%
Load SRAM: [===================================================] 100.00%
Done
[Pipeline] }
Lock released on resource [nexys4]

Loading: [========================                          ] 47.61%[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }

Loading: [============================                      ] 55.55%[Pipeline] // stage
[Pipeline] }

Loading: [================================                  ] 63.48%
Loading: [====================================              ] 71.42%
Loading: [========================================          ] 79.35%
Loading: [============================================      ] 87.29%
Loading: [================================================  ] 95.22%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
Rodando teste na Nexys 4
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ echo testando na ecp5
testando na ecp5
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo testando na tang nano
testando na tang nano
[Pipeline] sh
+ echo testando na tang nano
testando na tang nano
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // script
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS