Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Risco_5
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -Rf Risco-5/ build/
[Pipeline] sh
+ git clone https://github.com/JN513/Risco-5
Cloning into 'Risco-5'...
[Pipeline] sh
+ cd Risco-5
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (IVerilog)
[Pipeline] sh
+ mkdir -p build
[Pipeline] sh
+ cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/csr_unit.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/fifo.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v
[Pipeline] sh
+ /eda/oss-cad-suite/bin/vvp build/soc_test.o
ERROR: Risco-5/src/peripheral/memory.v:29: $readmemh: Unable to open software/memory/generic.hex for reading.
VCD info: dumpfile build/soc.vcd opened for output.
Risco-5/tests/soc_test.v:34: $finish called at 3606 (1s)
[Pipeline] sh
+ rm -f Risco-5/software/memory/generic.hex
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Síntese)
[Pipeline] parallel
[Pipeline] { (Branch: OSS-Cad-Suite)
[Pipeline] { (Branch: Gowin)
[Pipeline] { (Branch: Vivado)
[Pipeline] stage
[Pipeline] { (OSS-Cad-Suite)
[Pipeline] stage
[Pipeline] { (Gowin)
[Pipeline] stage
[Pipeline] { (Vivado)
[Pipeline] stage
[Pipeline] { (Yosys)
[Pipeline] sh
[Pipeline] sh
+ rm -rf Risco-5/impl/pnr
[Pipeline] sh
+ cd Risco-5/fpga/nexys4_ddr
+ mkdir build
+ /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source run.tcl
+ /eda/oss-cad-suite/bin/yosys -p                                          read_verilog Risco-5/fpga/ecp5/*.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)

-- Running command `                                         read_verilog Risco-5/fpga/ecp5/*.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     ' --

1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v
Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: Risco-5/debug/reset.v
Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v
Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation.
Generating RTLIL representation for module `\Alu'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v
Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation.
Generating RTLIL representation for module `\ALU_Control'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v
Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: Risco-5/src/core/core.v
Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation.
Generating RTLIL representation for module `\Core'.
Risco-5/src/core/core.v:142: Warning: Identifier `\pc_source' is implicitly declared.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: Risco-5/src/core/csr_unit.v
Parsing Verilog input from `Risco-5/src/core/csr_unit.v' to AST representation.
Generating RTLIL representation for module `\CSR_Unit'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v
Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation.
Generating RTLIL representation for module `\Immediate_Generator'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v
Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation.
Generating RTLIL representation for module `\MUX'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v
Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation.
Generating RTLIL representation for module `\PC'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v
Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation.
Generating RTLIL representation for module `\Registers'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v
Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation.
Generating RTLIL representation for module `\BUS'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/fifo.v
Parsing Verilog input from `Risco-5/src/peripheral/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v
Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9)
Generating RTLIL representation for module `\GPIO'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v
Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation.
Generating RTLIL representation for module `\GPIOS'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v
Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation.
Generating RTLIL representation for module `\LEDs'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v
Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v
Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation.
Generating RTLIL representation for module `\Risco_5_SOC'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v
Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_rx'.
Successfully finished Verilog frontend.

21. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_tx'.
Successfully finished Verilog frontend.

22. Executing SYNTH_ECP5 pass.

22.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

22.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

22.3. Executing HIERARCHY pass (managing design hierarchy).

22.3.1. Finding top of design hierarchy..
root of   0 design levels: uart_tool_tx        
root of   0 design levels: uart_tool_rx        
root of   1 design levels: UART                
root of   2 design levels: Risco_5_SOC         
root of   0 design levels: Memory              
root of   0 design levels: LEDs                
root of   1 design levels: GPIOS               
root of   0 design levels: GPIO                
root of   0 design levels: FIFO                
root of   0 design levels: BUS                 
root of   0 design levels: Registers           
root of   0 design levels: PC                  
root of   0 design levels: MUX                 
root of   0 design levels: Immediate_Generator 
root of   0 design levels: CSR_Unit            
root of   1 design levels: Core                
root of   0 design levels: Control_Unit        
root of   0 design levels: ALU_Control         
root of   0 design levels: Alu                 
root of   0 design levels: ResetBootSystem     
root of   3 design levels: top                 
Automatically selected top as design top module.

22.3.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     \ResetBootSystem
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \MEMORY_SIZE = 8192
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6

22.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \MEMORY_SIZE = 8192
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6
Generating RTLIL representation for module `$paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC'.
Parameter \CYCLES = 20

22.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \WIDHT = 5

22.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 5
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600

22.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Generating RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

22.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \BOOT_ADDRESS = 0

22.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'.
Parameter \BOOT_ADDRESS = 0
Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.
Risco-5/src/core/core.v:142: Warning: Identifier `\pc_source' is implicitly declared.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

22.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

22.3.12. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \WIDHT = 6

22.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 6
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200

22.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Generating RTLIL representation for module `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART'.
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 8192

22.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 8192
Generating RTLIL representation for module `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory'.
Parameter \BOOT_ADDRESS = 0
Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.

22.3.16. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

22.3.19. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100

22.3.20. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Removing unused module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Removing unused module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Removing unused module `\uart_tool_tx'.
Removing unused module `\uart_tool_rx'.
Removing unused module `\UART'.
Removing unused module `\Risco_5_SOC'.
Removing unused module `\Memory'.
Removing unused module `\GPIOS'.
Removing unused module `\FIFO'.
Removing unused module `\Core'.
Removing unused module `\ResetBootSystem'.
Removed 14 unused modules.

22.4. Executing PROC pass (convert processes to netlists).

22.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$567'.
Found and cleaned up 1 empty switch in `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:0$979'.
Removing empty process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:0$979'.
Cleaned up 2 empty switches.

22.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$674 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$626 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$568 in module TRELLIS_DPR16X4.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/fifo.v:24$890 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:197$1072 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:186$1070 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:171$1062 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:160$1059 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:148$1053 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:133$1048 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:116$1043 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:97$1034 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:173$1021 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:162$1019 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:147$1011 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:130$997 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:115$991 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:98$986 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:244$777 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:45$977 in module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:33$940 in module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$286 in module LEDs.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:76$930 in module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:41$916 in module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:29$914 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:24$144 in module Registers.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:15$133 in module PC.
Removed 1 dead cases from process $proc$Risco-5/src/core/mux.v:14$132 in module MUX.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/mux.v:14$132 in module MUX.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:18$130 in module Immediate_Generator.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:187$128 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:178$124 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:164$122 in module CSR_Unit.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:118$115 in module CSR_Unit.
Marked 5 switch rules as full_case in process $proc$Risco-5/debug/reset.v:24$678 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:632$80 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:622$79 in module Control_Unit.
Marked 19 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:141$34 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:133$33 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:9$26 in module ALU_Control.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:9$26 in module ALU_Control.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:23$11 in module Alu.
Removed a total of 2 dead cases.

22.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 14 redundant assignments.
Promoted 149 assignments to connections.

22.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$675'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$1074'.
  Set init value: \i = 0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$1027'.
  Set init value: \i = 0
Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$783'.
  Set init value: \instruction_register = 0
  Set init value: \memory_register = 0
  Set init value: \alu_out_register = 0
  Set init value: \register_data_1 = 0
  Set init value: \register_data_2 = 0
  Set init value: \pc_old = 0
  Set init value: \temp_address = 0
  Set init value: \temp_reg2 = 0
  Set init value: \temp_write_value = 0
Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$289'.
  Set init value: \data = 33'000000000000000000000000000000000
Found init rule in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$933'.
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \buffer_full = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$136'.
  Set init value: \Output = 0
Found init rule in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$129'.
  Set init value: \csr_mcause = 0
  Set init value: \csr_mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \csr_mepc = 0
  Set init value: \csr_mie_mfie = 16'0000000000000000
  Set init value: \csr_mie_meie = 1'0
  Set init value: \csr_mie_msie = 1'0
  Set init value: \csr_mie_mtie = 1'0
  Set init value: \csr_mip_mfip = 16'0000000000000000
  Set init value: \csr_mip_meip = 1'0
  Set init value: \csr_mip_mtip = 1'0
  Set init value: \csr_mip_msip = 1'0
  Set init value: \csr_minstret = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \csr_mscratch = 0
  Set init value: \csr_mstatus_mie = 1'0
  Set init value: \csr_mstatus_mpie = 1'0
  Set init value: \csr_mtvec = 0
  Set init value: \csr_mtval = 0
  Set init value: \csr_write_data = 0
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$684'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000
Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$81'.
  Set init value: \state = 6'000000
  Set init value: \is_immediate = 1'0
  Set init value: \pc_write = 1'0
  Set init value: \ir_write = 1'0
  Set init value: \pc_source = 1'0
  Set init value: \reg_write = 1'0
  Set init value: \memory_read = 1'0
  Set init value: \memory_write = 1'0
  Set init value: \pc_write_cond = 1'0
  Set init value: \csr_write_enable = 1'0
  Set init value: \alu_input_selector = 1'0
  Set init value: \save_address = 1'0
  Set init value: \save_value = 1'0
  Set init value: \save_value_2 = 1'0
  Set init value: \save_write_value = 1'0
  Set init value: \control_memory_op = 1'0
  Set init value: \write_data_in = 1'0
  Set init value: \lorD = 2'00
  Set init value: \aluop = 2'00
  Set init value: \alu_src_a = 3'000
  Set init value: \alu_src_b = 3'000
  Set init value: \memory_to_reg = 3'000
  Set init value: \control_unit_memory_op = 3'010
  Set init value: \control_unit_aluop = 4'0000
  Set init value: \clear_hal_byte_one_block_option = 3'000
  Set init value: \clear_hal_byte_one_block_option_2 = 3'000
  Set init value: \nextstate = 6'000000

22.4.5. Executing PROC_ARST pass (detect async resets in processes).

22.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~111 debug messages>

22.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$675'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$674'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$626'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$625_EN[3:0]$632
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$625_DATA[3:0]$631
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$625_ADDR[3:0]$630
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$568'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$566_EN[3:0]$574
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$566_DATA[3:0]$573
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$566_ADDR[3:0]$572
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$567'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$890'.
     1/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$902
     2/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_DATA[7:0]$901
     3/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_ADDR[5:0]$900
     4/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$897
     5/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_DATA[7:0]$896
     6/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_ADDR[5:0]$895
     7/8: $0\write_ptr[5:0]
     8/8: $0\read_ptr[5:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$1074'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$1072'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$1070'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$1062'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$1059'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$1053'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$1048'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$1043'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$1034'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$1027'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$1021'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$1019'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$1011'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$997'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$991'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$986'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$783'.
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$777'.
     1/10: $0\alu_out_register[31:0]
     2/10: $0\register_data_2[31:0]
     3/10: $0\register_data_1[31:0]
     4/10: $0\memory_register[31:0]
     5/10: $0\temp_write_value[31:0]
     6/10: $0\temp_reg3[31:0]
     7/10: $0\temp_reg2[31:0]
     8/10: $0\temp_address[31:0]
     9/10: $0\pc_old[31:0]
    10/10: $0\instruction_register[31:0]
Creating decoders for process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:45$977'.
     1/1: $1\read_data[31:0]
Creating decoders for process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$940'.
     1/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$973
     2/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_DATA[31:0]$972
     3/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_ADDR[31:0]$971
     4/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$976
     5/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_DATA[31:0]$975
     6/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_ADDR[31:0]$974
     7/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$963
     8/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_DATA[31:0]$962
     9/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_ADDR[31:0]$961
    10/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$969
    11/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_DATA[31:0]$968
    12/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_ADDR[31:0]$967
    13/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$966
    14/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_DATA[31:0]$965
    15/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_ADDR[31:0]$964
    16/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$959
    17/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_DATA[31:0]$958
    18/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_ADDR[31:0]$957
    19/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$956
    20/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_DATA[31:0]$955
    21/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_ADDR[31:0]$954
    22/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$953
    23/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_DATA[31:0]$952
    24/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_ADDR[31:0]$951
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$289'.
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$286'.
     1/1: $0\data[32:0]
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$933'.
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$930'.
     1/1: $1\read_data[31:0]
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$916'.
     1/9: $0\rx_fifo_write[0:0]
     2/9: $0\rx_fifo_read[0:0]
     3/9: $0\tx_fifo_write[0:0]
     4/9: $0\tx_fifo_read[0:0]
     5/9: $0\uart_tx_en[0:0]
     6/9: $0\rx_fifo_write_data[7:0]
     7/9: $0\tx_fifo_write_data[7:0]
     8/9: $0\uart_tx_data[7:0]
     9/9: $0\buffer_full[0:0]
Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$914'.
     1/2: $0\gpio_value[5:0]
     2/2: $0\gpio_direction[5:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$162'.
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:24$144'.
     1/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$159
     2/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$139_DATA[31:0]$158
     3/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$139_ADDR[4:0]$157
     4/9: $2$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$160
     5/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$151
     6/9: $1$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$155
     7/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$154
     8/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$139_DATA[31:0]$153
     9/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$139_ADDR[4:0]$152
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$136'.
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:15$133'.
     1/1: $0\Output[31:0]
Creating decoders for process `\MUX.$proc$Risco-5/src/core/mux.v:14$132'.
     1/1: $1\S[31:0]
Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$130'.
     1/4: $4\immediate[31:0]
     2/4: $3\immediate[31:0]
     3/4: $2\immediate[31:0]
     4/4: $1\immediate[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$129'.
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$128'.
     1/1: $1\csr_data_out[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124'.
     1/1: $1\csr_write_data[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$122'.
     1/4: $0\csr_mip_msip[0:0]
     2/4: $0\csr_mip_mtip[0:0]
     3/4: $0\csr_mip_meip[0:0]
     4/4: $0\csr_mip_mfip[15:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
     1/13: $0\csr_mtval[31:0]
     2/13: $0\csr_mtvec[31:0]
     3/13: $0\csr_mstatus_mpie[0:0]
     4/13: $0\csr_mstatus_mie[0:0]
     5/13: $0\csr_mscratch[31:0]
     6/13: $0\csr_minstret[63:0]
     7/13: $0\csr_mie_mtie[0:0]
     8/13: $0\csr_mie_msie[0:0]
     9/13: $0\csr_mie_meie[0:0]
    10/13: $0\csr_mie_mfie[15:0]
    11/13: $0\csr_mepc[31:0]
    12/13: $0\csr_mcycle[63:0]
    13/13: $0\csr_mcause[31:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$684'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$678'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$81'.
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:632$80'.
     1/2: $0\clear_hal_byte_one_block_option_2[2:0]
     2/2: $0\clear_hal_byte_one_block_option[2:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:622$79'.
     1/1: $0\wb_filter[2:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
     1/21: $0\save_write_value[0:0]
     2/21: $0\write_data_in[0:0]
     3/21: $0\save_value_2[0:0]
     4/21: $0\save_value[0:0]
     5/21: $0\control_memory_op[0:0]
     6/21: $0\save_address[0:0]
     7/21: $0\control_unit_aluop[3:0]
     8/21: $0\alu_input_selector[0:0]
     9/21: $0\csr_write_enable[0:0]
    10/21: $0\is_immediate[0:0]
    11/21: $0\reg_write[0:0]
    12/21: $0\alu_src_a[2:0]
    13/21: $0\alu_src_b[2:0]
    14/21: $0\aluop[1:0]
    15/21: $0\pc_source[0:0]
    16/21: $0\memory_to_reg[2:0]
    17/21: $0\memory_write[0:0]
    18/21: $0\memory_read[0:0]
    19/21: $0\lorD[1:0]
    20/21: $0\pc_write_cond[0:0]
    21/21: $3\pc_write[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34'.
     1/23: $19\nextstate[5:0]
     2/23: $18\nextstate[5:0]
     3/23: $17\nextstate[5:0]
     4/23: $16\nextstate[5:0]
     5/23: $15\nextstate[5:0]
     6/23: $14\nextstate[5:0]
     7/23: $13\nextstate[5:0]
     8/23: $12\nextstate[5:0]
     9/23: $11\nextstate[5:0]
    10/23: $10\nextstate[5:0]
    11/23: $9\nextstate[5:0]
    12/23: $8\nextstate[5:0]
    13/23: $7\nextstate[5:0]
    14/23: $6\nextstate[5:0]
    15/23: $5\nextstate[5:0]
    16/23: $4\nextstate[5:0]
    17/23: $3\nextstate[5:0]
    18/23: $2\nextstate[5:0]
    19/23: $2\ir_write[0:0]
    20/23: $2\pc_write[0:0]
    21/23: $1\nextstate[5:0]
    22/23: $1\ir_write[0:0]
    23/23: $1\pc_write[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:133$33'.
     1/1: $0\state[5:0]
Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'.
     1/4: $4\aluop_out[3:0]
     2/4: $3\aluop_out[3:0]
     3/4: $2\aluop_out[3:0]
     4/4: $1\aluop_out[3:0]
Creating decoders for process `\Alu.$proc$Risco-5/src/core/alu.v:23$11'.
     1/1: $1\ALU_out_S[31:0]

22.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$1043'.
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$986'.
No latch inferred for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.\read_data' from process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:45$977'.
No latch inferred for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\read_data' from process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$930'.
No latch inferred for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:17$137_EN' from process `\Registers.$proc$Risco-5/src/core/registers.v:0$162'.
No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$Risco-5/src/core/mux.v:14$132'.
No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$130'.
No latch inferred for signal `\CSR_Unit.\csr_mcause_code' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$129'.
No latch inferred for signal `\CSR_Unit.\csr_mcause_interrupt_flag' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$129'.
No latch inferred for signal `\CSR_Unit.\csr_utime' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$129'.
No latch inferred for signal `\CSR_Unit.\csr_data_out' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$128'.
No latch inferred for signal `\CSR_Unit.\csr_write_data' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124'.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [0]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [1]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [2]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [3]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [4]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [5]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [6]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [7]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [8]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [9]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [10]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [11]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [12]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [13]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [14]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [15]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [16]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [17]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [18]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [19]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [20]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [21]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [22]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [23]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [24]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [25]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [26]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [27]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [28]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [29]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [30]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [31]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124`.
No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:632$80'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:632$80`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:632$80`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:632$80`.
No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option_2' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:632$80'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:632$80`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:632$80`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:632$80`.
No latch inferred for signal `\Control_Unit.\wb_filter' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:622$79'.
No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\csr_write_enable` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\alu_input_selector' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_input_selector` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\save_address' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_address` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\save_value' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\save_value_2' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value_2` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\save_write_value' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_write_value` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\control_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_memory_op` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\write_data_in' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\write_data_in` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\control_unit_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
Removing init bit 1'1 for non-memory siginal `\Control_Unit.\control_unit_memory_op [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
No latch inferred for signal `\Control_Unit.\control_unit_aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66`.
Latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66': $auto$proc_dlatch.cc:433:proc_dlatch$3301
No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34`.
No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34`.
No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [4]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [5]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34`.
Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26': $auto$proc_dlatch.cc:433:proc_dlatch$3318
No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$Risco-5/src/core/alu.v:23$11'.

22.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$674'.
  created $dff cell `$procdff$3341' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$610_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$611_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$612_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$613_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$614_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$615_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$616_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$617_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$618_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$619_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$620_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$621_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$622_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$623_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$624_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$625_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$626'.
  created $dff cell `$procdff$3342' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$625_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$626'.
  created $dff cell `$procdff$3343' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$625_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$626'.
  created $dff cell `$procdff$3344' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$550_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$551_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$552_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$553_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$554_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$555_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$556_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$557_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$558_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$559_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$560_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$561_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$562_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$563_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$564_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$565_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$566_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$568'.
  created $dff cell `$procdff$3345' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$566_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$568'.
  created $dff cell `$procdff$3346' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$566_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$568'.
  created $dff cell `$procdff$3347' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$567'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$890'.
  created $dff cell `$procdff$3348' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$890'.
  created $dff cell `$procdff$3349' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$890'.
  created $dff cell `$procdff$3350' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$890'.
  created $dff cell `$procdff$3351' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$890'.
  created $dff cell `$procdff$3352' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$1072'.
  created $dff cell `$procdff$3353' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$1072'.
  created $dff cell `$procdff$3354' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$1070'.
  created $dff cell `$procdff$3355' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$1062'.
  created $dff cell `$procdff$3356' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$1059'.
  created $dff cell `$procdff$3357' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$1053'.
  created $dff cell `$procdff$3358' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$1048'.
  created $dff cell `$procdff$3359' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$1048'.
  created $dff cell `$procdff$3360' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$1034'.
  created $dff cell `$procdff$3361' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$1021'.
  created $dff cell `$procdff$3362' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$1019'.
  created $dff cell `$procdff$3363' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$1011'.
  created $dff cell `$procdff$3364' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$997'.
  created $dff cell `$procdff$3365' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$991'.
  created $dff cell `$procdff$3366' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$991'.
  created $dff cell `$procdff$3367' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$777'.
  created $dff cell `$procdff$3368' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$777'.
  created $dff cell `$procdff$3369' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$777'.
  created $dff cell `$procdff$3370' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$777'.
  created $dff cell `$procdff$3371' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$777'.
  created $dff cell `$procdff$3372' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$777'.
  created $dff cell `$procdff$3373' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_address' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$777'.
  created $dff cell `$procdff$3374' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_reg2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$777'.
  created $dff cell `$procdff$3375' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_reg3' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$777'.
  created $dff cell `$procdff$3376' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_write_value' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$777'.
  created $dff cell `$procdff$3377' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_ADDR' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$940'.
  created $dff cell `$procdff$3378' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_DATA' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$940'.
  created $dff cell `$procdff$3379' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$940'.
  created $dff cell `$procdff$3380' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_ADDR' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$940'.
  created $dff cell `$procdff$3381' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_DATA' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$940'.
  created $dff cell `$procdff$3382' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$940'.
  created $dff cell `$procdff$3383' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_ADDR' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$940'.
  created $dff cell `$procdff$3384' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_DATA' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$940'.
  created $dff cell `$procdff$3385' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$940'.
  created $dff cell `$procdff$3386' with positive edge clock.
Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$286'.
  created $dff cell `$procdff$3387' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\uart_tx_en' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$916'.
  created $dff cell `$procdff$3388' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_read' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$916'.
  created $dff cell `$procdff$3389' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_write' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$916'.
  created $dff cell `$procdff$3390' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_read' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$916'.
  created $dff cell `$procdff$3391' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_write' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$916'.
  created $dff cell `$procdff$3392' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\buffer_full' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$916'.
  created $dff cell `$procdff$3393' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\uart_tx_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$916'.
  created $dff cell `$procdff$3394' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_write_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$916'.
  created $dff cell `$procdff$3395' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_write_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$916'.
  created $dff cell `$procdff$3396' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$914'.
  created $dff cell `$procdff$3397' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$914'.
  created $dff cell `$procdff$3398' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$144'.
  created $dff cell `$procdff$3399' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$139_ADDR' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$144'.
  created $dff cell `$procdff$3400' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$139_DATA' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$144'.
  created $dff cell `$procdff$3401' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$144'.
  created $dff cell `$procdff$3402' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$144'.
  created $dff cell `$procdff$3403' with positive edge clock.
Creating register for signal `\PC.\Output' using process `\PC.$proc$Risco-5/src/core/pc.v:15$133'.
  created $dff cell `$procdff$3404' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_mfip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$122'.
  created $dff cell `$procdff$3405' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_meip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$122'.
  created $dff cell `$procdff$3406' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_mtip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$122'.
  created $dff cell `$procdff$3407' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_msip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$122'.
  created $dff cell `$procdff$3408' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mcause' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$3409' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mcycle' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$3410' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mepc' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$3411' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_mfie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$3412' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_meie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$3413' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_msie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$3414' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_mtie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$3415' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_minstret' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$3416' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mscratch' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$3417' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mstatus_mie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$3418' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mstatus_mpie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$3419' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mtvec' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$3420' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mtval' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
  created $dff cell `$procdff$3421' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$678'.
  created $dff cell `$procdff$3422' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$678'.
  created $dff cell `$procdff$3423' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$678'.
  created $dff cell `$procdff$3424' with positive edge clock.
Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:133$33'.
  created $dff cell `$procdff$3425' with positive edge clock.

22.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$675'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$674'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$674'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$649'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$626'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$592'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$568'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$567'.
Found and cleaned up 3 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$890'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$890'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$1074'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$1072'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$1072'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$1070'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$1070'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$1062'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$1062'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$1059'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$1059'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$1053'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$1053'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$1048'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$1048'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$1043'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$1043'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$1034'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$1034'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$1027'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$1021'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$1021'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$1019'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$1019'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$1011'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$1011'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$997'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$997'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$991'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$991'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$986'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$986'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$783'.
Found and cleaned up 6 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$777'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$777'.
Found and cleaned up 1 empty switch in `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:45$977'.
Removing empty process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:45$977'.
Found and cleaned up 3 empty switches in `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$940'.
Removing empty process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:33$940'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$289'.
Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$286'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$286'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$933'.
Found and cleaned up 1 empty switch in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$930'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$930'.
Found and cleaned up 5 empty switches in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$916'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$916'.
Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$914'.
Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$914'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$162'.
Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:24$144'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:24$144'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$136'.
Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:15$133'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:15$133'.
Found and cleaned up 1 empty switch in `\MUX.$proc$Risco-5/src/core/mux.v:14$132'.
Removing empty process `MUX.$proc$Risco-5/src/core/mux.v:14$132'.
Found and cleaned up 4 empty switches in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$130'.
Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$130'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$129'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$128'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$128'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$124'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$122'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$122'.
Found and cleaned up 3 empty switches in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$115'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$684'.
Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$678'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$678'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$81'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:632$80'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:632$80'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:622$79'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:622$79'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$66'.
Found and cleaned up 19 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:133$33'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:133$33'.
Found and cleaned up 4 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'.
Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'.
Found and cleaned up 1 empty switch in `\Alu.$proc$Risco-5/src/core/alu.v:23$11'.
Removing empty process `Alu.$proc$Risco-5/src/core/alu.v:23$11'.
Cleaned up 111 empty switches.

22.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
<suppressed ~4 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
<suppressed ~9 debug messages>
Optimizing module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.
<suppressed ~5 debug messages>
Optimizing module LEDs.
<suppressed ~3 debug messages>
Optimizing module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
<suppressed ~9 debug messages>
Optimizing module GPIO.
<suppressed ~3 debug messages>
Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
<suppressed ~4 debug messages>
Optimizing module BUS.
Optimizing module Registers.
<suppressed ~2 debug messages>
Optimizing module PC.
<suppressed ~2 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module Immediate_Generator.
<suppressed ~1 debug messages>
Optimizing module CSR_Unit.
<suppressed ~2 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~7 debug messages>
Optimizing module Control_Unit.
<suppressed ~33 debug messages>
Optimizing module ALU_Control.
<suppressed ~15 debug messages>
Optimizing module Alu.
<suppressed ~1 debug messages>
Optimizing module $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC.
Optimizing module top.

22.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Deleting now unused module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.
Deleting now unused module LEDs.
Deleting now unused module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Deleting now unused module GPIO.
Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Deleting now unused module BUS.
Deleting now unused module Registers.
Deleting now unused module PC.
Deleting now unused module MUX.
Deleting now unused module Immediate_Generator.
Deleting now unused module CSR_Unit.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module Control_Unit.
Deleting now unused module ALU_Control.
Deleting now unused module Alu.
Deleting now unused module $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC.
<suppressed ~30 debug messages>

22.6. Executing TRIBUF pass.

22.7. Executing DEMINOUT pass (demote inout ports to input or output).
[Pipeline] sh

22.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~47 debug messages>

22.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 64 unused cells and 867 unused wires.
<suppressed ~85 debug messages>

22.10. Executing CHECK pass (checking for obvious problems).
Checking module top...
Warning: multiple conflicting drivers for top.\SOC.Core.Control_Unit.pc_write:
    port Q[0] of cell $flatten\SOC.\Core.\Control_Unit.$auto$proc_dlatch.cc:433:proc_dlatch$3301 ($dlatch)
    port Y[0] of cell $flatten\SOC.\Core.\Control_Unit.$procmux$3240 ($mux)
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [15] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [14] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [13] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [12] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [11] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [10] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [9] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [8] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [7] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [6] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [5] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [4] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [3] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [2] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [1] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [0] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_external is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_timer is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_software is used but has no driver.
Found and reported 20 problems.

22.11. Executing OPT pass (performing simple optimizations).

22.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~11 debug messages>

22.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~867 debug messages>
Removed a total of 289 cells.

22.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2396.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2409.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2425.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2427.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2442.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2460.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2481.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2506.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2533.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2563.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2596.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2641.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2688.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2736.
    dead port 1/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2786.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2788.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2838.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2840.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2889.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2948.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2999.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3050.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3101.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1717.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1719.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1730.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1745.
    dead port 1/9 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1700.
    dead port 2/9 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1700.
    dead port 3/9 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1700.
    dead port 4/9 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1700.
    dead port 1/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1700.
    dead port 2/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1700.
    dead port 3/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1700.
    dead port 4/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1700.
    dead port 5/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1700.
    dead port 6/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1700.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1660.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1666.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1672.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1678.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1457.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1459.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1466.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1468.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1475.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1477.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1484.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1486.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1493.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1495.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1502.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1504.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1510.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1516.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1522.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1528.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1534.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1540.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1546.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1552.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1558.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1102.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1108.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1114.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1102.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1108.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1114.
Removed 68 multiplexer ports.
<suppressed ~148 debug messages>

22.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2052: $auto$opt_reduce.cc:134:opt_pmux$3476
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2066: $auto$opt_reduce.cc:134:opt_pmux$3478
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2084: $auto$opt_reduce.cc:134:opt_pmux$3480
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2133: $auto$opt_reduce.cc:134:opt_pmux$3482
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2159: $auto$opt_reduce.cc:134:opt_pmux$3484
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2176: { $auto$opt_reduce.cc:134:opt_pmux$3488 $auto$opt_reduce.cc:134:opt_pmux$3486 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2204: $auto$opt_reduce.cc:134:opt_pmux$3490
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2224: $auto$opt_reduce.cc:134:opt_pmux$3492
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2227: $auto$opt_reduce.cc:134:opt_pmux$3494
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2234: { $flatten\SOC.\Core.\Control_Unit.$procmux$2087_CMP $auto$opt_reduce.cc:134:opt_pmux$3506 $auto$opt_reduce.cc:134:opt_pmux$3504 $auto$opt_reduce.cc:134:opt_pmux$3502 $auto$opt_reduce.cc:134:opt_pmux$3500 $auto$opt_reduce.cc:134:opt_pmux$3498 $auto$opt_reduce.cc:134:opt_pmux$3496 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2268: { $flatten\SOC.\Core.\Control_Unit.$procmux$2261_CMP $auto$opt_reduce.cc:134:opt_pmux$3520 $auto$opt_reduce.cc:134:opt_pmux$3518 $auto$opt_reduce.cc:134:opt_pmux$3516 $flatten\SOC.\Core.\Control_Unit.$procmux$2183_CMP $auto$opt_reduce.cc:134:opt_pmux$3514 $flatten\SOC.\Core.\Control_Unit.$procmux$2180_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2179_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2178_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2177_CMP $auto$opt_reduce.cc:134:opt_pmux$3512 $auto$opt_reduce.cc:134:opt_pmux$3510 $auto$opt_reduce.cc:134:opt_pmux$3508 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3261: { $flatten\SOC.\Core.\ALU_Control.$procmux$3268_CMP $auto$opt_reduce.cc:134:opt_pmux$3522 $flatten\SOC.\Core.\ALU_Control.$procmux$3265_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3264_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3263_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3262_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3275: { $auto$opt_reduce.cc:134:opt_pmux$3526 $auto$opt_reduce.cc:134:opt_pmux$3524 $flatten\SOC.\Core.\ALU_Control.$procmux$3268_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2303: { $auto$opt_reduce.cc:134:opt_pmux$3528 $flatten\SOC.\Core.\Control_Unit.$procmux$2239_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3284: { $flatten\SOC.\Core.\ALU_Control.$procmux$3286_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3285_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2310: $auto$opt_reduce.cc:134:opt_pmux$3530
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2314: { $flatten\SOC.\Core.\Control_Unit.$procmux$2232_CMP $auto$opt_reduce.cc:134:opt_pmux$3532 $flatten\SOC.\Core.\Control_Unit.$procmux$2220_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2330: $auto$opt_reduce.cc:134:opt_pmux$3534
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2352: $auto$opt_reduce.cc:134:opt_pmux$3536
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2370: $auto$opt_reduce.cc:134:opt_pmux$3538
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2937: { $auto$opt_reduce.cc:134:opt_pmux$3540 $flatten\SOC.\Core.\Control_Unit.$procmux$2945_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2944_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2943_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2942_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2941_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2940_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2939_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2938_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3104: { $flatten\SOC.\Core.\Control_Unit.$procmux$2297_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2266_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2162_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2357_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2139_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2333_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2238_CMP $auto$opt_reduce.cc:134:opt_pmux$3544 $flatten\SOC.\Core.\Control_Unit.$procmux$2190_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2231_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2161_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2138_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2189_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2261_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2137_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2121_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2088_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2087_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2185_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2256_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2086_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2183_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2182_CMP $auto$opt_reduce.cc:134:opt_pmux$3542 $flatten\SOC.\Core.\Control_Unit.$procmux$2054_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2068_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2160_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2135_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2180_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2179_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2085_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2178_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2177_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2053_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2067_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1759: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1780_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1779_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1772_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1771_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1770_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1769_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1768_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1767_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1766_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1765_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1764_CMP $auto$opt_reduce.cc:134:opt_pmux$3552 $auto$opt_reduce.cc:134:opt_pmux$3550 $auto$opt_reduce.cc:134:opt_pmux$3548 $auto$opt_reduce.cc:134:opt_pmux$3546 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1742: $auto$opt_reduce.cc:134:opt_pmux$3554
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1748: { $flatten\SOC.\Core.\Control_Unit.$procmux$2942_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2943_CMP $auto$opt_reduce.cc:134:opt_pmux$3558 $flatten\SOC.\Core.\Control_Unit.$procmux$2944_CMP $auto$opt_reduce.cc:134:opt_pmux$3556 $flatten\SOC.\Core.\Control_Unit.$procmux$2938_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2946_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1657:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1675:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1681:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$138_EN[31:0]$145 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1454:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1454_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1454_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1454_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] $flatten\SOC.\Memory.$procmux$1454_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1481:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Memory.$procmux$1481_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Memory.$procmux$1481_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1481_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] $flatten\SOC.\Memory.$procmux$1481_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1508:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1508_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1508_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1508_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] $flatten\SOC.\Memory.$procmux$1508_Y [0] }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2030: { $flatten\SOC.\Core.\Control_Unit.$procmux$2027_CMP $auto$opt_reduce.cc:134:opt_pmux$3560 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0]
      New connections: $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1684:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$160, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1675_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$140_EN[31:0]$149 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1687:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$159, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1657_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$139_EN[31:0]$148 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1526:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$976, B=0, Y=$flatten\SOC.\Memory.$procmux$1526_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1481_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1526_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1526_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] $flatten\SOC.\Memory.$procmux$1526_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1544:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$973, B=0, Y=$flatten\SOC.\Memory.$procmux$1544_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1454_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1544_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1544_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] $flatten\SOC.\Memory.$procmux$1544_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1579:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$963, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1508_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_EN[31:0]$943 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1117:
      Old ports: A=$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$902, B=8'00000000, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893
      New ports: A=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1099_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1117:
      Old ports: A=$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$902, B=8'00000000, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893
      New ports: A=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1099_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0]
      New connections: $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_EN[7:0]$893 [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1561:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$969, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1526_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_EN[31:0]$949 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1570:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$966, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1544_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_EN[31:0]$946 [0] }
  Optimizing cells in module \top.
Performed a total of 44 changes.

22.11.5. Executing OPT_MERGE pass (detect identical cells).
+ mkdir -p Risco-5/impl/pnr
Finding identical cells in module `\top'.
<suppressed ~21 debug messages>
Removed a total of 7 cells.

22.11.6. Executing OPT_DFF pass (perform DFF optimizations).

22.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 366 unused wires.
<suppressed ~3 debug messages>

22.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.11.9. Rerunning OPT passes. (Maybe there is more to do..)

22.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~145 debug messages>

22.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2268: { $flatten\SOC.\Core.\Control_Unit.$procmux$2261_CMP $auto$opt_reduce.cc:134:opt_pmux$3520 $auto$opt_reduce.cc:134:opt_pmux$3518 $auto$opt_reduce.cc:134:opt_pmux$3516 $flatten\SOC.\Core.\Control_Unit.$procmux$2183_CMP $auto$opt_reduce.cc:134:opt_pmux$3514 $auto$opt_reduce.cc:134:opt_pmux$3564 $auto$opt_reduce.cc:134:opt_pmux$3562 $auto$opt_reduce.cc:134:opt_pmux$3512 $auto$opt_reduce.cc:134:opt_pmux$3510 $auto$opt_reduce.cc:134:opt_pmux$3508 }
  Optimizing cells in module \top.
Performed a total of 1 changes.

22.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.11.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 1-bit at position 0 on $flatten\SOC.\Core.\Control_Unit.$auto$proc_dlatch.cc:433:proc_dlatch$3301 ($dlatch) from module top.

22.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Warning: Driver-driver conflict for \SOC.Core.Control_Unit.pc_write between cell $flatten\SOC.\Core.\Control_Unit.$procmux$3192.Y and constant 1'1 in top: Resolved using constant.
Removed 5 unused cells and 4 unused wires.
<suppressed ~6 debug messages>

22.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~4 debug messages>

22.11.16. Rerunning OPT passes. (Maybe there is more to do..)

22.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~144 debug messages>

22.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.11.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

22.11.20. Executing OPT_DFF pass (perform DFF optimizations).

22.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 4 unused cells and 10 unused wires.
<suppressed ~10 debug messages>

22.11.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.11.23. Rerunning OPT passes. (Maybe there is more to do..)

22.11.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~141 debug messages>

22.11.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.11.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.11.27. Executing OPT_DFF pass (perform DFF optimizations).
[Pipeline] sh

22.11.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.11.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.11.30. Finished OPT passes. (There is nothing left to do.)

22.12. Executing FSM pass (extract and optimize FSM).

22.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.
Not marking top.SOC.Core.CSR_Unit.csr_mip_mfip as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Not marking top.SOC.Core.Control_Unit.state as FSM state register:
    Register has an initialization value.
Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state.
Not marking top.SOC.Uart.i_uart_tx.fsm_state as FSM state register:
    Users of register don't seem to benefit from recoding.

22.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'.
  found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$3355
  root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$1036_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$1051_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$1064_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$1050_Y
  found state code: 3'000
  found ctrl input: \SOC.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \SOC.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$1064_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$1055_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$1051_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$1050_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$1036_Y
  ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o }
  ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$1036_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$1050_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$1051_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$1055_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$1064_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'0--0 ->      3'001 8'01010001
  transition:      3'000 4'1--0 ->      3'000 8'01010000
  transition:      3'000 4'---1 ->      3'000 8'01010000
  transition:      3'010 4'--00 ->      3'010 8'00100010
  transition:      3'010 4'--10 ->      3'011 8'00100011
  transition:      3'010 4'---1 ->      3'000 8'00100000
  transition:      3'001 4'-0-0 ->      3'001 8'00011001
  transition:      3'001 4'-1-0 ->      3'010 8'00011010
  transition:      3'001 4'---1 ->      3'000 8'00011000
  transition:      3'011 4'-0-0 ->      3'011 8'10010011
  transition:      3'011 4'-1-0 ->      3'000 8'10010000
  transition:      3'011 4'---1 ->      3'000 8'10010000

22.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3565' from module `\top'.

22.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 7 unused cells and 7 unused wires.
<suppressed ~8 debug messages>

22.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3565' from module `\top'.
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].

22.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3565' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---

22.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3565' from module `top':
-------------------------------------

  Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$3565 (\SOC.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \ResetBootSystem.reset_o
    1: \SOC.Uart.i_uart_rx.payload_done
    2: \SOC.Uart.i_uart_rx.next_bit
    3: \SOC.Uart.i_uart_rx.rxd_reg

  Output signals:
    0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$1064_Y
    1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$1055_Y
    2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$1051_Y
    3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$1050_Y
    4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$1036_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'1--0   ->     0 5'01010
      1:     0 4'---1   ->     0 5'01010
      2:     0 4'0--0   ->     2 5'01010
      3:     1 4'---1   ->     0 5'00100
      4:     1 4'--00   ->     1 5'00100
      5:     1 4'--10   ->     3 5'00100
      6:     2 4'---1   ->     0 5'00011
      7:     2 4'-1-0   ->     1 5'00011
      8:     2 4'-0-0   ->     2 5'00011
      9:     3 4'-1-0   ->     0 5'10010
     10:     3 4'---1   ->     0 5'10010
     11:     3 4'-0-0   ->     3 5'10010

-------------------------------------

22.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3565' from module `\top'.

22.13. Executing OPT pass (performing simple optimizations).

22.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

22.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

22.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~140 debug messages>

22.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3367 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1383_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1377_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1368_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1359_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1350_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1341_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1323_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1332_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3615 ($sdff) from module top (D = \SOC.Uart.uart_tx_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$3615 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1377_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1368_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1359_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1350_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1341_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1323_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1332_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3365 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1299_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3620 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1299_Y, Q = \SOC.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3364 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1288_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$3626 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$1018_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3363 ($dff) from module top (D = \SOC.Uart.i_uart_tx.n_fsm_state, Q = \SOC.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3362 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1277_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$3631 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1277_Y, Q = \SOC.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3361 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1266_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3637 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3360 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$1243_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1234_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1225_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1216_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1207_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1198_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1180_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1189_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3639 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3358 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1162_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3643 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$1058_Y, Q = \SOC.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3357 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1157_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3647 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3356 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1149_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$3649 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$1069_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3354 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3353 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$3349 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1126_Y, Q = \SOC.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3655 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$905_Y, Q = \SOC.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$3348 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1131_Y, Q = \SOC.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3657 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$910_Y [5:0], Q = \SOC.Uart.TX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$3349 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1126_Y, Q = \SOC.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3659 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$905_Y, Q = \SOC.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$3348 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1131_Y, Q = \SOC.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3661 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$910_Y [5:0], Q = \SOC.Uart.RX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3396 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1622_Y, Q = \SOC.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3663 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.uart_rx_data, Q = \SOC.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3395 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1627_Y, Q = \SOC.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3665 ($sdff) from module top (D = \SOC.Uart.write_data [7:0], Q = \SOC.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3394 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1632_Y, Q = \SOC.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3667 ($sdff) from module top (D = \SOC.Uart.tx_fifo_read_data, Q = \SOC.Uart.uart_tx_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3392 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1597_Y, Q = \SOC.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3391 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1602_Y, Q = \SOC.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3390 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1607_Y, Q = \SOC.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3388 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1612_Y, Q = \SOC.Uart.uart_tx_en, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Leds.$procdff$3387 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$1587_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3673 ($sdff) from module top (D = { 1'0 \SOC.Leds.write_data }, Q = \SOC.Leds.data).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$3398 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1643_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3675 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_value).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$3397 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1651_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3679 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_direction).
Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$3404 ($dff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.Output, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$3425 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 6'000000).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3421 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1803_Y, Q = \SOC.Core.CSR_Unit.csr_mtval, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3687 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mtval).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3420 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 1'0 \SOC.Core.CSR_Unit.csr_write_data [0] }, Q = \SOC.Core.CSR_Unit.csr_mtvec).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3419 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1829_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$3696 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3418 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1846_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3700 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mstatus_mie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3417 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1862_Y, Q = \SOC.Core.CSR_Unit.csr_mscratch, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3704 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mscratch).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3416 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1875_Y, Q = \SOC.Core.CSR_Unit.csr_minstret, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3708 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1875_Y, Q = \SOC.Core.CSR_Unit.csr_minstret).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3415 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1893_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mtie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3712 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mie_mtie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3414 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1911_Y, Q = \SOC.Core.CSR_Unit.csr_mie_msie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3716 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mie_msie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3413 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1929_Y, Q = \SOC.Core.CSR_Unit.csr_mie_meie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3720 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [11], Q = \SOC.Core.CSR_Unit.csr_mie_meie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3412 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1947_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mfie, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3724 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [31:16], Q = \SOC.Core.CSR_Unit.csr_mie_mfie).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3411 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 2'00 }, Q = \SOC.Core.CSR_Unit.csr_mepc).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3410 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1970_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3733 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1970_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3409 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1981_Y, Q = \SOC.Core.CSR_Unit.csr_mcause, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3737 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mcause).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3408 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_software, Q = \SOC.Core.CSR_Unit.csr_mip_msip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3407 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_timer, Q = \SOC.Core.CSR_Unit.csr_mip_mtip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3406 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_external, Q = \SOC.Core.CSR_Unit.csr_mip_meip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3405 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_fast, Q = \SOC.Core.CSR_Unit.csr_mip_mfip, rval = 16'0000000000000000).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3377 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1415_Y, Q = \SOC.Core.temp_write_value, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3745 ($sdff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.temp_write_value).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3376 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1420_Y, Q = \SOC.Core.temp_reg3, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3747 ($sdff) from module top (D = \SOC.Core.alu_out_register, Q = \SOC.Core.temp_reg3).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3375 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1425_Y, Q = \SOC.Core.temp_reg2, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3749 ($sdff) from module top (D = \SOC.Core.instruction_register, Q = \SOC.Core.temp_reg2).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3374 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1430_Y, Q = \SOC.Core.temp_address, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3751 ($sdff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.temp_address).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3373 ($dff) from module top (D = \SOC.Core.Pc.Output, Q = \SOC.Core.pc_old, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3372 ($dff) from module top (D = \SOC.Core.register_data_2_out, Q = \SOC.Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3371 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3370 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3368 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register, rval = 0).
Adding EN signal on $flatten\ResetBootSystem.$procdff$3424 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$3423 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding EN signal on $flatten\ResetBootSystem.$procdff$3422 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3728 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3728 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3691 ($dffe) from module top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$3674 ($sdffe) from module top.

22.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 134 unused cells and 130 unused wires.
<suppressed ~135 debug messages>

22.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

22.13.9. Rerunning OPT passes. (Maybe there is more to do..)

22.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~96 debug messages>

22.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$3645: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o }
  Optimizing cells in module \top.
Performed a total of 1 changes.

22.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~15 debug messages>
Removed a total of 5 cells.

22.13.13. Executing OPT_DFF pass (perform DFF optimizations).

22.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
+ cd Risco-5/fpga/tangnano20k/
+ /eda/gowin/IDE/bin/gw_sh run.tcl
*** GOWIN Tcl Command Line Console  *** 
current device: GW2AR-18C  GW2AR-LV18QN88C8/I7
add new file: "pinout.cst"
add new file: "top.sdc"
add new file: "main.v"
add new file: "../../debug/reset.v"
add new file: "../../src/core/alu_control.v"
add new file: "../../src/core/alu.v"
add new file: "../../src/core/control_unit.v"
add new file: "../../src/core/core.v"
add new file: "../../src/core/immediate_generator.v"
add new file: "../../src/core/mux.v"
add new file: "../../src/core/pc.v"
add new file: "../../src/core/registers.v"
add new file: "../../src/core/csr_unit.v"
add new file: "../../src/peripheral/bus.v"
add new file: "../../src/peripheral/gpio.v"
add new file: "../../src/peripheral/gpios.v"
add new file: "../../src/peripheral/leds.v"
add new file: "../../src/peripheral/memory.v"
add new file: "../../src/peripheral/soc.v"
add new file: "../../src/peripheral/uart_rx.v"
add new file: "../../src/peripheral/uart_tx.v"
add new file: "../../src/peripheral/uart.v"
add new file: "../../src/peripheral/fifo.v"
GowinSynthesis start
Running parser ...
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v'
Undeclared symbol 'pc_source', assumed default net type 'wire'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":142)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v'
WARN  (EX3801) : Parameter 'SET_DIRECTION' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":17)
WARN  (EX3801) : Parameter 'READ' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":18)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v'
WARN  (EX3012) : Empty statement in sequential block("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":40)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v'
WARN  (EX3073) : Port 'resetn_o' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":18)
Compiling module 'top'("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":1)
Compiling module 'ResetBootSystem'("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":1)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":37)
Compiling module 'Risco_5_SOC(CLOCK_FREQ=27000000,MEMORY_SIZE=2048,MEMORY_FILE="../../software/memory/fpga_test_3.hex")'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":1)
WARN  (EX3073) : Port 'interrupt_on_hold' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":242)
Compiling module 'Core(BOOT_ADDRESS=32'b00000000000000000000000000000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":1)
Compiling module 'PC'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v":1)
Compiling module 'MUX'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v":1)
Compiling module 'Registers'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v":1)
Compiling module 'Control_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":1)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":511)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":518)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":531)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":538)
WARN  (EX2420) : Latch inferred for net 'pc_write'; We do not recommend the use of latches in FPGA designs, as they may lead to timing problems("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":620)
ERROR (EX2000) : Net 'pc_write' is constantly driven from multiple places("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":620)
ERROR (EX1999) : Found another driver here("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":304)
Module 'Control_Unit' remains a black box due to errors in its contents("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":1)
Compiling module 'ALU_Control'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":1)
WARN  (EX2420) : Latch inferred for net 'aluop_out[3]'; We do not recommend the use of latches in FPGA designs, as they may lead to timing problems("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":57)
Compiling module 'Alu'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v":1)
Compiling module 'Immediate_Generator'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v":1)
Compiling module 'CSR_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":1)
WARN  (EX3780) : Using initial value of 'csr_utime' since it is never assigned("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":114)
WARN  (EX2565) : Input 'save_pc' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":242)
Compiling module 'Memory(MEMORY_FILE="../../software/memory/fpga_test_3.hex",MEMORY_SIZE=2048)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":1)
Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":15)
Compiling module 'BUS'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v":1)
Finding unused cells or wires in module \top..
Removed 1 unused cells and 6 unused wires.
<suppressed ~2 debug messages>

22.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.13.16. Rerunning OPT passes. (Maybe there is more to do..)

22.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~96 debug messages>

22.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.20. Executing OPT_DFF pass (perform DFF optimizations).

22.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.13.23. Finished OPT passes. (There is nothing left to do.)

22.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$3430 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$3432 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$meminit$\registers$Risco-5/src/core/registers.v:17$161 (SOC.Core.RegisterBank.registers).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3427 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3428 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3429 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$978 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$938 (SOC.Memory.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$3426 (SOC.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$889 (SOC.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$3426 (SOC.Uart.TX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\TX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$889 (SOC.Uart.TX_FIFO.memory).
Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$1998_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$682 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$681 ($add).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$681 ($add).
Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$680 ($lt).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$3769 ($ne).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$3764 ($ne).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:20$913 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$1594_CMP0 ($eq).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Uart.$procmux$1593 ($pmux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1123 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1111 ($mux).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$910 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$903 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$885 ($eq).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1123 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1111 ($mux).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$910 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$903 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$885 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$1047 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$1046 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$1045 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$1044 ($mux).
Removed top 2 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:111$1039 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:109$1037 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$1013 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$1005 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:135$1003 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$1000 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$999 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$995 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$990 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$989 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$988 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$987 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:94$983 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:92$981 ($eq).
Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$285 ($mux).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$165 ($le).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$168 ($ge).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$169 ($le).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$172 ($ge).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$173 ($le).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$176 ($ge).
Removed top 22 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$177 ($le).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:75$207 ($mux).
Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:84$223 ($mux).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$237 ($mux).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Memory.$procmux$1450_CMP0 ($eq).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1567 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1576 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1585 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1707_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1707_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1706_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1705_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1707_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1706_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1705_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1707_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1706_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1705_CMP0 ($eq).
Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2997 ($mux).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2946_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2945_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2944_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2941_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2940_CMP0 ($eq).
Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2937 ($pmux).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2836 ($mux).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2783 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2734 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2686 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2639 ($mux).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2594 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2561 ($mux).
Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2531 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2504 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2458 ($mux).
Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2407 ($mux).
Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2357_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2333_CMP0 ($eq).
Removed top 5 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2266_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2261_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2256_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2242_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2240_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2239_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2238_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2236_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2235_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2232_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2231_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2230_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2229_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2226_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2225_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2220_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2190_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2189_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2185_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2184_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2162_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2161_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2139_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2138_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2137_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2121_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2088_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2087_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2086_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2030 ($pmux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2028_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2027_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:531$75 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:511$69 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:242$48 ($eq).
Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:170$35 ($eq).
Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:101$32 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3286_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3268_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3267_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3266_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3254 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3299_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3298_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3297_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3296_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$25 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$17 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1785_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1772_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1771_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1770_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1769_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1768_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1767_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1766_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1765_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1764_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$121 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$119 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$118 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$164 ($ge).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1520 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1538 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1556 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1472 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1499 ($mux).
Removed top 19 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:80$215 ($mux).
Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$681_Y.
Removed top 24 bits (of 32) from wire top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$237_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$17_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$25_Y.
Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$10\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$11\nextstate[5:0].
Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$12\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$13\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$15\nextstate[5:0].
Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$18\nextstate[5:0].
Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0].
Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0].
Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$5\nextstate[5:0].
Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$6\nextstate[5:0].
Removed top 4 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$7\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$8\nextstate[5:0].
Removed top 4 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$9\nextstate[5:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:511$69_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:531$75_Y.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_ADDR[31:0]$941.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_ADDR[31:0]$944.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_ADDR[31:0]$947.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:36$934_ADDR[31:0]$961.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_ADDR[31:0]$964.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_ADDR[31:0]$967.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:38$935_ADDR[31:0]$971.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:40$936_ADDR[31:0]$974.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_ADDR[5:0]$891.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_ADDR[5:0]$900.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$910_Y.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_ADDR[5:0]$891.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$879_ADDR[5:0]$900.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$910_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$1044_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$1045_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$1046_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$1047_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$987_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$988_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$989_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$990_Y.

22.15. Executing PEEPOPT pass (run peephole optimizers).

22.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 46 unused wires.
<suppressed ~1 debug messages>

22.17. Executing SHARE pass (SAT-based resource sharing).
Found 5 cells in module top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$889 ($memrd):
    Found 1 activation_patterns using ctrl signal { $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:57$174_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:55$170_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$166_Y $flatten\SOC.\Uart.$procmux$1596_CMP $flatten\SOC.\Uart.$procmux$1595_CMP $flatten\SOC.\Uart.$procmux$1594_CMP }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:19$938 ($memrd):
    Found 7 activation_patterns using ctrl signal { $flatten\SOC.\Memory.$procmux$1451_CMP $flatten\SOC.\Memory.$procmux$1450_CMP $flatten\SOC.\Memory.$procmux$1449_CMP $flatten\SOC.\Memory.$procmux$1448_CMP \SOC.Memory.option [1:0] $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$166_Y \SOC.Bus.slave_0_write \SOC.Bus.slave_0_read }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\RegisterBank.$memrd$\registers$Risco-5/src/core/registers.v:22$143 ($memrd):
    Found 11 activation_patterns using ctrl signal { $flatten\SOC.\Core.\Alu.$procmux$3290_CMP $flatten\SOC.\Core.\Alu.$procmux$3291_CMP $flatten\SOC.\Core.\Alu.$procmux$3292_CMP $flatten\SOC.\Core.\Alu.$procmux$3293_CMP $flatten\SOC.\Core.\Alu.$procmux$3294_CMP $flatten\SOC.\Core.\Alu.$procmux$3295_CMP $flatten\SOC.\Core.\Alu.$procmux$3296_CMP $flatten\SOC.\Core.\Alu.$procmux$3297_CMP $flatten\SOC.\Core.\Alu.$procmux$3298_CMP $flatten\SOC.\Core.\Alu.$procmux$3299_CMP $flatten\SOC.\Core.\Alu.$procmux$3300_CMP $flatten\SOC.\Core.\AluInputBMUX.$procmux$1705_CMP }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:44$23 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3291_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:42$22 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3292_CMP.
    No candidates found.

22.18. Executing TECHMAP pass (map to technology primitives).

22.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

22.18.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~296 debug messages>

22.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.21. Executing TECHMAP pass (map to technology primitives).

22.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

22.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

22.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

22.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$681 ($add).
  creating $macc model for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$766 ($add).
  creating $macc model for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$765 ($sub).
  creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15 ($sub).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$116 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$117 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$118 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$119 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$120 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$121 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$882 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$904 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$882 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$904 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$1058 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$1069 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$1007 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$1018 ($add).
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$1018.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$1007.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$1069.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$1058.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$904.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$882.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$904.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$882.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$121.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$120.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$119.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$118.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$117.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$116.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14.
  creating $alu model for $macc $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$765.
  creating $alu model for $macc $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$766.
  creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$681.
  creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$680 ($lt): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$164 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$168 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$172 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$176 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$165 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$169 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$173 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$177 ($le): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24 ($ge): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
  creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$16 ($lt): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
  creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$682 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$680.
  creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21 ($eq): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$177: $auto$alumacc.cc:485:replace_alu$3839
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$173: $auto$alumacc.cc:485:replace_alu$3852
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$169: $auto$alumacc.cc:485:replace_alu$3865
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$165: $auto$alumacc.cc:485:replace_alu$3878
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$176: $auto$alumacc.cc:485:replace_alu$3891
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$172: $auto$alumacc.cc:485:replace_alu$3900
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$168: $auto$alumacc.cc:485:replace_alu$3909
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$164: $auto$alumacc.cc:485:replace_alu$3918
  creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$680, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$682: $auto$alumacc.cc:485:replace_alu$3927
  creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$681: $auto$alumacc.cc:485:replace_alu$3938
  creating $alu cell for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$766: $auto$alumacc.cc:485:replace_alu$3941
  creating $alu cell for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$765: $auto$alumacc.cc:485:replace_alu$3944
  creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14: $auto$alumacc.cc:485:replace_alu$3947
  creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15, $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$16, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21: $auto$alumacc.cc:485:replace_alu$3950
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$116: $auto$alumacc.cc:485:replace_alu$3963
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$117: $auto$alumacc.cc:485:replace_alu$3966
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$118: $auto$alumacc.cc:485:replace_alu$3969
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$119: $auto$alumacc.cc:485:replace_alu$3972
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$120: $auto$alumacc.cc:485:replace_alu$3975
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$121: $auto$alumacc.cc:485:replace_alu$3978
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$904: $auto$alumacc.cc:485:replace_alu$3981
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$882: $auto$alumacc.cc:485:replace_alu$3984
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909: $auto$alumacc.cc:485:replace_alu$3987
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$904: $auto$alumacc.cc:485:replace_alu$3990
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$882: $auto$alumacc.cc:485:replace_alu$3993
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$909: $auto$alumacc.cc:485:replace_alu$3996
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$1058: $auto$alumacc.cc:485:replace_alu$3999
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$1069: $auto$alumacc.cc:485:replace_alu$4002
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$1007: $auto$alumacc.cc:485:replace_alu$4005
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$1018: $auto$alumacc.cc:485:replace_alu$4008
  created 30 $alu and 0 $macc cells.

22.23. Executing OPT pass (performing simple optimizations).

22.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

22.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~10 debug messages>
Removed a total of 2 cells.

22.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~96 debug messages>

22.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.23.5. Executing OPT_MERGE pass (detect identical cells).
Compiling module 'LEDs'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":1)
WARN  (EX3791) : Expression size 33 truncated to fit in target size 32("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":21)
Compiling module 'UART(CLOCK_FREQ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v":1)
Compiling module 'FIFO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":1)
Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":15)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":35)
Compiling module 'uart_tool_rx(CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v":10)
Compiling module 'uart_tool_tx(CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v":10)
Compiling module 'GPIOS(WIDHT=5)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":1)
Compiling module 'GPIO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v":1)
WARN  (EX2565) : Input 'halt' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_external' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_timer' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_software' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_fast[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_fast[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_fast[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_fast[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_fast[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_fast[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_fast[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_fast[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_fast[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_fast[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_fast[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_fast[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_fast[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_fast[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_fast[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
WARN  (EX2565) : Input 'instruction_request_fast[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":56)
GowinSynthesis finish

    while executing
"run all"
    (file "run.tcl" line 30)
Finding identical cells in module `\top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

22.23.6. Executing OPT_DFF pass (perform DFF optimizations).

22.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 22 unused wires.
<suppressed ~1 debug messages>

22.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.23.9. Rerunning OPT passes. (Maybe there is more to do..)

22.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~96 debug messages>

22.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.23.13. Executing OPT_DFF pass (perform DFF optimizations).

22.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.23.16. Finished OPT passes. (There is nothing left to do.)

22.24. Executing MEMORY pass.

22.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

22.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

22.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing top.SOC.Core.RegisterBank.registers write port 0.
  Analyzing top.SOC.Core.RegisterBank.registers write port 1.
  Analyzing top.SOC.Core.RegisterBank.registers write port 2.
  Analyzing top.SOC.Memory.memory write port 0.
  Analyzing top.SOC.Memory.memory write port 1.
  Analyzing top.SOC.Memory.memory write port 2.
  Analyzing top.SOC.Uart.RX_FIFO.memory write port 0.
  Analyzing top.SOC.Uart.TX_FIFO.memory write port 0.

22.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

22.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\SOC.Core.RegisterBank.registers'[0] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[1] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[2] in module `\top': merging output FF to cell.
    Write port 0: don't care on collision.
    Write port 1: non-transparent.
    Write port 2: non-transparent.
Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found.
Checking read port `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': FF found, but with a mux select that doesn't seem to correspond to transparency logic.
Checking read port `\SOC.Uart.TX_FIFO.memory'[0] in module `\top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port address `\SOC.Core.RegisterBank.registers'[0] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Core.RegisterBank.registers'[1] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found.
Checking read port address `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': merged address FF to cell.

22.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 44 unused wires.
<suppressed ~7 debug messages>

22.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
  Merging ports 0, 2 (address 5'00000).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Memory.memory by address:
  Merging ports 0, 1 (address \SOC.Memory.address [12:2]).
  Merging ports 0, 2 (address \SOC.Memory.address [12:2]).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers using sat-based resource sharing:
  Checking group clocked with posedge \clk, width 32: ports 0, 1.
  Common input cone for all EN signals: 13 cells.
  Size of unconstrained SAT problem: 103 variables, 281 clauses
  Merging port 1 into port 0.

22.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

22.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 8 unused cells and 8 unused wires.
<suppressed ~9 debug messages>

22.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

22.25. Executing OPT_CLEAN pass (remove unused cells and wires).
[Pipeline] }
Finding unused cells or wires in module \top..

22.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory top.SOC.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_
Extracted data FF from read port 2 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[2]
mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory top.SOC.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted addr FF from read port 0 of top.SOC.Uart.RX_FIFO.memory: $\SOC.Uart.RX_FIFO.memory$rdreg[0]
mapping memory top.SOC.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of top.SOC.Uart.TX_FIFO.memory: $\SOC.Uart.TX_FIFO.memory$rdreg[0]
<suppressed ~1084 debug messages>

22.27. Executing TECHMAP pass (map to technology primitives).

22.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

22.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

22.27.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
[Pipeline] // stage
Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$8e5e72577b4c3b167a98ad5915719acd6a2ff3f4\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$58f24e643e5858c811559272a02c6d84f974d8a6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b7ec8ee89a7cd4851359941621e9dedf8c3b7d83\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$6d2a7df30888468e46c2233cf858b33a106d24cc\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$1a510b238205ce75968c294c5a2f9682007038e9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$d697ed060a7caa7345cbd011d88bf1d0e8cd46a0\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$882b16869816e01f56a454af0eb6e24b6778fa0c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b6fd6d9e43fa3d8e6bc64941b5b57ab422f7e603\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$983d377398e8a630797eecf765a80311ec60d100\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c8ec1437ade7762ec3882c3e3f576764a2f7bb09\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$1de9eb29388171a23037c69580dd741dfa07544f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$ccbfc2f8b7417ea49ec4f806e284aeee31f607b3\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b1d6656f42d8fe2eb2a963373a2667cf617d2bc5\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$80ae742e83efa97f5ae3dddd041ab9a1ef9ac7b6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$9a18a5918aa94986c2ace7118a70e41127dc33df\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c4c009ae968ecf5722a8a929fbdc163f47dedcc6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$7e65f9170886a0570d9059c94eef599a8e7c0c53\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$88ca364434c15edf84547ebc10bbf93659adea39\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$219b7093d2a2ec9427a92a1f7d983c7335efd508\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$0f1e956af4a0dd7da6349454a915a33336b22174\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$20534e299f87b4db290b2588b7ce04615b91104c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$73e415998dfd4e0d8b84ec3ac6390921a6a2c53b\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$7d81e3db939f1224434306a374696f893743b990\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$060a68a0493c8190183716105f9d8172975de01f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~1419 debug messages>

22.28. Executing OPT pass (performing simple optimizations).

22.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~103 debug messages>

22.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~30 debug messages>
Removed a total of 10 cells.

22.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $\SOC.Uart.RX_FIFO.memory$rdreg[0] ($dff) from module top (D = $auto$rtlil.cc:2582:Mux$4062, Q = $\SOC.Uart.RX_FIFO.memory$rdreg[0]$q, rval = 3'000).
Adding SRST signal on $auto$ff.cc:266:slice$3758 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$1995_Y, Q = \ResetBootSystem.counter, rval = 6'000000).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3741 ($sdff) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$3744 ($sdff) from module top.

22.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
[Pipeline] }
Failed in branch Gowin
Finding unused cells or wires in module \top..
Removed 19 unused cells and 7629 unused wires.
<suppressed ~20 debug messages>

22.28.5. Rerunning OPT passes. (Removed registers in this run.)

22.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$6550 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$3784 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).

22.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 1 unused wires.
<suppressed ~2 debug messages>

22.28.10. Rerunning OPT passes. (Removed registers in this run.)

22.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.28.13. Executing OPT_DFF pass (perform DFF optimizations).

22.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Sending interrupt signal to process
Sending interrupt signal to process
Terminated
script returned exit code 143

22.28.15. Finished fast OPT passes.

22.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

22.30. Executing OPT pass (performing simple optimizations).

22.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$4084: $auto$rtlil.cc:2489:ReduceOr$4078 -> 1'1
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~65 debug messages>

22.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$4069:
      Old ports: A={ \SOC.Memory.buffer [31:16] \SOC.Memory.write_data [15:0] }, B=\SOC.Memory.write_data, Y=$auto$rtlil.cc:2582:Mux$4070
      New ports: A=\SOC.Memory.buffer [31:16], B=\SOC.Memory.write_data [31:16], Y=$auto$rtlil.cc:2582:Mux$4070 [31:16]
      New connections: $auto$rtlil.cc:2582:Mux$4070 [15:0] = \SOC.Memory.write_data [15:0]
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2004: { $flatten\ResetBootSystem.$procmux$1999_CMP $flatten\ResetBootSystem.$procmux$1998_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2007:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2007_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2007_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2007_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3254:
      Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$3786 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3786 [2]
      New connections: $auto$wreduce.cc:461:run$3786 [1:0] = 2'10
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3275:
      Old ports: A=4'0110, B=12'101101111110, Y=$flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0]
      New ports: A=3'010, B=9'101011110, Y={ $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [3:2] $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [0] }
      New connections: $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [1] = 1'1
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1759: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1780_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1779_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1772_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1771_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1770_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1769_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1768_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1767_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1766_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1765_CMP $auto$opt_reduce.cc:134:opt_pmux$3552 $auto$opt_reduce.cc:134:opt_pmux$3550 $auto$opt_reduce.cc:134:opt_pmux$3548 $auto$opt_reduce.cc:134:opt_pmux$3546 }
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2176:
      Old ports: A=4'0000, B=8'10001001, Y=\SOC.Core.control_unit_aluop
      New ports: A=2'00, B=4'1011, Y={ \SOC.Core.control_unit_aluop [3] \SOC.Core.control_unit_aluop [0] }
      New connections: \SOC.Core.control_unit_aluop [2:1] = 2'00
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2370:
      Old ports: A=2'00, B=2'10, Y=\SOC.Core.lorD
      New ports: A=1'0, B=1'1, Y=\SOC.Core.lorD [1]
      New connections: \SOC.Core.lorD [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2394:
      Old ports: A=6'101101, B=6'000000, Y=$flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0]
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0]
      New connections: $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [5:1] = { $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] 1'0 $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2423:
      Old ports: A=6'000000, B=6'100101, Y=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0]
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0]
      New connections: $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [5:1] = { $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] 2'00 $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2458:
      Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$3794 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3794 [2]
      New connections: $auto$wreduce.cc:461:run$3794 [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2479:
      Old ports: A=6'011111, B=6'100010, Y=$flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0]
      New ports: A=2'01, B=2'10, Y={ $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [5] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] }
      New connections: $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [4:1] = { $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] 1'1 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2504:
      Old ports: A=3'110, B=3'011, Y=$auto$wreduce.cc:461:run$3793 [2:0]
      New ports: A=2'10, B=2'01, Y={ $auto$wreduce.cc:461:run$3793 [2] $auto$wreduce.cc:461:run$3793 [0] }
      New connections: $auto$wreduce.cc:461:run$3793 [1] = 1'1
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2561:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$3791 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3791 [2] $auto$wreduce.cc:461:run$3791 [0] }
      New connections: $auto$wreduce.cc:461:run$3791 [1] = $auto$wreduce.cc:461:run$3791 [0]
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2594:
      Old ports: A=5'00000, B=5'10010, Y=$auto$wreduce.cc:461:run$3790 [4:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3790 [1]
      New connections: { $auto$wreduce.cc:461:run$3790 [4:2] $auto$wreduce.cc:461:run$3790 [0] } = { $auto$wreduce.cc:461:run$3790 [1] 3'000 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2639:
      Old ports: A=3'101, B=3'000, Y=$auto$wreduce.cc:461:run$3802 [2:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3802 [0]
      New connections: $auto$wreduce.cc:461:run$3802 [2:1] = { $auto$wreduce.cc:461:run$3802 [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2686:
      Old ports: A=3'110, B=3'000, Y=$auto$wreduce.cc:461:run$3801 [2:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3801 [1]
      New connections: { $auto$wreduce.cc:461:run$3801 [2] $auto$wreduce.cc:461:run$3801 [0] } = { $auto$wreduce.cc:461:run$3801 [1] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2783:
      Old ports: A=5'00101, B=5'11000, Y=$auto$wreduce.cc:461:run$3799 [4:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3799 [3] $auto$wreduce.cc:461:run$3799 [0] }
      New connections: { $auto$wreduce.cc:461:run$3799 [4] $auto$wreduce.cc:461:run$3799 [2:1] } = { $auto$wreduce.cc:461:run$3799 [3] $auto$wreduce.cc:461:run$3799 [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2836:
      Old ports: A=5'00011, B=5'10110, Y=$auto$wreduce.cc:461:run$3798 [4:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3798 [2] $auto$wreduce.cc:461:run$3798 [0] }
      New connections: { $auto$wreduce.cc:461:run$3798 [4:3] $auto$wreduce.cc:461:run$3798 [1] } = { $auto$wreduce.cc:461:run$3798 [2] 2'01 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2887:
      Old ports: A={ 1'0 $auto$wreduce.cc:461:run$3799 [4:0] }, B={ 1'0 $auto$wreduce.cc:461:run$3798 [4:0] }, Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0]
      New ports: A=$auto$wreduce.cc:461:run$3799 [4:0], B=$auto$wreduce.cc:461:run$3798 [4:0], Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [4:0]
      New connections: $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [5] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:101$32:
      Old ports: A=2'11, B=2'01, Y=\SOC.Core.Control_Unit.second_block_write_src_b [1:0]
      New ports: A=1'1, B=1'0, Y=\SOC.Core.Control_Unit.second_block_write_src_b [1]
      New connections: \SOC.Core.Control_Unit.second_block_write_src_b [0] = 1'1
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1715:
      Old ports: A={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] }, B={ 27'000000000000000000000000000 \SOC.Core.instruction_register [24:20] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0]
      New ports: A=\SOC.Core.instruction_register [24], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [31:6] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] \SOC.Core.instruction_register [24:20] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1742:
      Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, B={ 19'0000000000000000000 \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0]
      New ports: A=\SOC.Core.instruction_register [31], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [31:14] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Memory.$procmux$1447:
      Old ports: A=\SOC.Memory.buffer, B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7:0] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:0] 24'000000000000000000000000 \SOC.Memory.buffer [7:0] 16'0000000000000000 \SOC.Memory.buffer [15:0] }, Y=\SOC.Bus.slave_0_read_data
      New ports: A=\SOC.Memory.buffer [31:8], B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:8] 40'0000000000000000000000000000000000000000 \SOC.Memory.buffer [15:8] }, Y=\SOC.Bus.slave_0_read_data [31:8]
      New connections: \SOC.Bus.slave_0_read_data [7:0] = \SOC.Memory.buffer [7:0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_rx.$procmux$1261:
      Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$3821 [0] 1'0 $auto$wreduce.cc:461:run$3822 [1:0] 2'01 \SOC.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$3824 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$3821 [0] $auto$wreduce.cc:461:run$3822 [1:0] 1'1 \SOC.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$3824 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$1047:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3824 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3824 [0]
      New connections: $auto$wreduce.cc:461:run$3824 [1] = $auto$wreduce.cc:461:run$3824 [0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$1398:
      Old ports: A=3'000, B={ 2'00 \SOC.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$3826 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$3828 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \SOC.Uart.uart_tx_en $auto$wreduce.cc:461:run$3826 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$3828 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$990:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3828 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3828 [0]
      New connections: $auto$wreduce.cc:461:run$3828 [1] = $auto$wreduce.cc:461:run$3828 [0]
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$4073:
      Old ports: A=$auto$rtlil.cc:2582:Mux$4070, B={ \SOC.Memory.buffer [31:8] \SOC.Memory.write_data [7:0] }, Y=$auto$rtlil.cc:2582:Mux$4074
      New ports: A={ $auto$rtlil.cc:2582:Mux$4070 [31:16] \SOC.Memory.write_data [15:8] }, B=\SOC.Memory.buffer [31:8], Y=$auto$rtlil.cc:2582:Mux$4074 [31:8]
      New connections: $auto$rtlil.cc:2582:Mux$4074 [7:0] = \SOC.Memory.write_data [7:0]
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2013:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2007_Y, Y=$flatten\ResetBootSystem.$procmux$2013_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2007_Y [1], Y=$flatten\ResetBootSystem.$procmux$2013_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2013_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2440:
      Old ports: A=6'100001, B=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0], Y=$flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0]
      New ports: A=2'01, B={ $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] }, Y={ $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [2] $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [0] }
      New connections: { $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [5:3] $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [1] } = { $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [0] 3'000 }
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1726:
      Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:20] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] 20'00000000000000000000 \SOC.Core.instruction_register [31:20] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0]
      New ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:25] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] 1'0 \SOC.Core.instruction_register [31:25] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12:5]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [31:13] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] \SOC.Core.instruction_register [24:20] }
  Optimizing cells in module \top.
Performed a total of 35 changes.

22.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

22.30.6. Executing OPT_DFF pass (perform DFF optimizations).

22.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Terminated
script returned exit code 143
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch Vivado
[Pipeline] stage
[Pipeline] { (NextPNR)
Stage "NextPNR" skipped due to earlier failure(s)
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
Stage "ECPPACK" skipped due to earlier failure(s)
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch OSS-Cad-Suite
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
Stage "FPGA Flash" skipped due to earlier failure(s)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
Stage "openFPGAloader ECP5" skipped due to earlier failure(s)
[Pipeline] }
Stage "openFPGAloader Tangnano 20k" skipped due to earlier failure(s)
[Pipeline] }
Stage "openFPGAloader Nexys 4 DDR" skipped due to earlier failure(s)
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch openFPGAloader ECP5
[Pipeline] }
Failed in branch openFPGAloader Tangnano 20k
[Pipeline] }
Failed in branch openFPGAloader Nexys 4 DDR
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
Stage "Testes" skipped due to earlier failure(s)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
Stage "ECP5 - Testes" skipped due to earlier failure(s)
[Pipeline] }
Stage "TangNano - Testes" skipped due to earlier failure(s)
[Pipeline] }
Stage "Nexys 4 - Testes" skipped due to earlier failure(s)
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch ECP5 - Testes
[Pipeline] }
Failed in branch TangNano - Testes
[Pipeline] }
Failed in branch Nexys 4 - Testes
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE