Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Risco_5
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -Rf Risco-5/ build/
[Pipeline] sh
+ git clone https://github.com/JN513/Risco-5
Cloning into 'Risco-5'...
[Pipeline] sh
+ cd Risco-5
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (IVerilog)
[Pipeline] sh
+ mkdir -p build
[Pipeline] sh
+ cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/csr_unit.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/fifo.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v
[Pipeline] sh
+ /eda/oss-cad-suite/bin/vvp build/soc_test.o
ERROR: Risco-5/src/peripheral/memory.v:35: $readmemh: Unable to open software/memory/generic.hex for reading.
VCD info: dumpfile build/soc.vcd opened for output.
Risco-5/tests/soc_test.v:34: $finish called at 3606 (1s)
[Pipeline] sh
+ rm -f Risco-5/software/memory/generic.hex
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Síntese)
[Pipeline] parallel
[Pipeline] { (Branch: OSS-Cad-Suite)
[Pipeline] { (Branch: Gowin)
[Pipeline] { (Branch: Vivado)
[Pipeline] stage
[Pipeline] { (OSS-Cad-Suite)
[Pipeline] stage
[Pipeline] { (Gowin)
[Pipeline] stage
[Pipeline] { (Vivado)
[Pipeline] stage
[Pipeline] { (Yosys)
[Pipeline] sh
[Pipeline] sh
+ rm -rf Risco-5/impl/pnr
[Pipeline] sh
+ cd Risco-5/fpga/nexys4_ddr
+ mkdir build
+ /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source run.tcl
+ /eda/oss-cad-suite/bin/yosys -p                                          read_verilog Risco-5/fpga/ecp5/*.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)

-- Running command `                                         read_verilog Risco-5/fpga/ecp5/*.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     ' --

1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v
Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: Risco-5/debug/reset.v
Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v
Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation.
Generating RTLIL representation for module `\Alu'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v
Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation.
Generating RTLIL representation for module `\ALU_Control'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v
Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: Risco-5/src/core/core.v
Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation.
Generating RTLIL representation for module `\Core'.
Risco-5/src/core/core.v:142: Warning: Identifier `\pc_source' is implicitly declared.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: Risco-5/src/core/csr_unit.v
Parsing Verilog input from `Risco-5/src/core/csr_unit.v' to AST representation.
Generating RTLIL representation for module `\CSR_Unit'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v
Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation.
Generating RTLIL representation for module `\Immediate_Generator'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v
Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation.
Generating RTLIL representation for module `\MUX'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v
Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation.
Generating RTLIL representation for module `\PC'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v
Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation.
Generating RTLIL representation for module `\Registers'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v
Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation.
Generating RTLIL representation for module `\BUS'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/fifo.v
Parsing Verilog input from `Risco-5/src/peripheral/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v
Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9)
Generating RTLIL representation for module `\GPIO'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v
Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation.
Generating RTLIL representation for module `\GPIOS'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v
Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation.
Generating RTLIL representation for module `\LEDs'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v
Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v
Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation.
Generating RTLIL representation for module `\Risco_5_SOC'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v
Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_rx'.
Successfully finished Verilog frontend.

21. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_tx'.
Successfully finished Verilog frontend.

22. Executing SYNTH_ECP5 pass.

22.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

22.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

22.3. Executing HIERARCHY pass (managing design hierarchy).

22.3.1. Finding top of design hierarchy..
root of   0 design levels: uart_tool_tx        
root of   0 design levels: uart_tool_rx        
root of   1 design levels: UART                
root of   2 design levels: Risco_5_SOC         
root of   0 design levels: Memory              
root of   0 design levels: LEDs                
root of   1 design levels: GPIOS               
root of   0 design levels: GPIO                
root of   0 design levels: FIFO                
root of   0 design levels: BUS                 
root of   0 design levels: Registers           
root of   0 design levels: PC                  
root of   0 design levels: MUX                 
root of   0 design levels: Immediate_Generator 
root of   0 design levels: CSR_Unit            
root of   1 design levels: Core                
root of   0 design levels: Control_Unit        
root of   0 design levels: ALU_Control         
root of   0 design levels: Alu                 
root of   0 design levels: ResetBootSystem     
root of   3 design levels: top                 
Automatically selected top as design top module.

22.3.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     \ResetBootSystem
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \MEMORY_SIZE = 8192
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6

22.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \MEMORY_SIZE = 8192
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6
Generating RTLIL representation for module `$paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC'.
Parameter \CYCLES = 20

22.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \WIDHT = 5

22.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 5
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600

22.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Generating RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

22.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \BOOT_ADDRESS = 0

22.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'.
Parameter \BOOT_ADDRESS = 0
Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.
Risco-5/src/core/core.v:142: Warning: Identifier `\pc_source' is implicitly declared.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

22.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

22.3.12. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \WIDHT = 6

22.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 6
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200

22.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Generating RTLIL representation for module `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART'.
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 8192

22.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000
Parameter \MEMORY_SIZE = 8192
Generating RTLIL representation for module `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory'.
Parameter \BOOT_ADDRESS = 0
Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.

22.3.16. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

22.3.19. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100

22.3.20. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Removing unused module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'.
Removing unused module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Removing unused module `\uart_tool_tx'.
Removing unused module `\uart_tool_rx'.
Removing unused module `\UART'.
Removing unused module `\Risco_5_SOC'.
Removing unused module `\Memory'.
Removing unused module `\GPIOS'.
Removing unused module `\FIFO'.
Removing unused module `\Core'.
Removing unused module `\ResetBootSystem'.
Removed 14 unused modules.

22.4. Executing PROC pass (convert processes to netlists).

22.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$571'.
Found and cleaned up 1 empty switch in `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:0$989'.
Cleaned up 2 empty switches.

22.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$678 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$630 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$572 in module TRELLIS_DPR16X4.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/fifo.v:24$898 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:197$1082 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:186$1080 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:171$1072 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:160$1069 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:148$1063 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:133$1058 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:116$1053 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:97$1044 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:173$1031 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:162$1029 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:147$1021 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:130$1007 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:115$1001 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:98$996 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:244$783 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:59$987 in module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:47$950 in module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$289 in module LEDs.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:76$938 in module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:41$924 in module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:29$922 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:24$147 in module Registers.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:15$136 in module PC.
Removed 1 dead cases from process $proc$Risco-5/src/core/mux.v:14$135 in module MUX.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/mux.v:14$135 in module MUX.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:18$133 in module Immediate_Generator.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:187$131 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:178$127 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:164$125 in module CSR_Unit.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:118$118 in module CSR_Unit.
Marked 5 switch rules as full_case in process $proc$Risco-5/debug/reset.v:24$681 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:628$80 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:618$79 in module Control_Unit.
Marked 19 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:141$34 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:133$33 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:9$26 in module ALU_Control.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:9$26 in module ALU_Control.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:23$11 in module Alu.
Removed a total of 2 dead cases.

22.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 14 redundant assignments.
Promoted 148 assignments to connections.

22.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$679'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$1084'.
  Set init value: \i = 0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$1037'.
  Set init value: \i = 0
Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$791'.
  Set init value: \instruction_register = 0
  Set init value: \memory_register = 0
  Set init value: \alu_out_register = 0
  Set init value: \register_data_1 = 0
  Set init value: \register_data_2 = 0
  Set init value: \pc_old = 0
  Set init value: \temp_address = 0
  Set init value: \temp_reg2 = 0
  Set init value: \temp_write_value = 0
Found init rule in `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:0$989'.
  Set init value: \memory_response = 1'0
Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$292'.
  Set init value: \data = 33'000000000000000000000000000000000
Found init rule in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$941'.
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \buffer_full = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$139'.
  Set init value: \Output = 0
Found init rule in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$132'.
  Set init value: \csr_mcause = 0
  Set init value: \csr_mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \csr_mepc = 0
  Set init value: \csr_mie_mfie = 16'0000000000000000
  Set init value: \csr_mie_meie = 1'0
  Set init value: \csr_mie_msie = 1'0
  Set init value: \csr_mie_mtie = 1'0
  Set init value: \csr_mip_mfip = 16'0000000000000000
  Set init value: \csr_mip_meip = 1'0
  Set init value: \csr_mip_mtip = 1'0
  Set init value: \csr_mip_msip = 1'0
  Set init value: \csr_minstret = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \csr_mscratch = 0
  Set init value: \csr_mstatus_mie = 1'0
  Set init value: \csr_mstatus_mpie = 1'0
  Set init value: \csr_mtvec = 0
  Set init value: \csr_mtval = 0
  Set init value: \csr_write_data = 0
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$687'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000
Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$81'.
  Set init value: \state = 6'000000
  Set init value: \is_immediate = 1'0
  Set init value: \pc_write = 1'0
  Set init value: \ir_write = 1'0
  Set init value: \pc_source = 1'0
  Set init value: \reg_write = 1'0
  Set init value: \memory_read = 1'0
  Set init value: \memory_write = 1'0
  Set init value: \pc_write_cond = 1'0
  Set init value: \csr_write_enable = 1'0
  Set init value: \alu_input_selector = 1'0
  Set init value: \save_address = 1'0
  Set init value: \save_value = 1'0
  Set init value: \save_value_2 = 1'0
  Set init value: \save_write_value = 1'0
  Set init value: \control_memory_op = 1'0
  Set init value: \write_data_in = 1'0
  Set init value: \lorD = 2'00
  Set init value: \aluop = 2'00
  Set init value: \alu_src_a = 3'000
  Set init value: \alu_src_b = 3'000
  Set init value: \memory_to_reg = 3'000
  Set init value: \control_unit_memory_op = 3'010
  Set init value: \control_unit_aluop = 4'0000
  Set init value: \clear_hal_byte_one_block_option = 3'000
  Set init value: \clear_hal_byte_one_block_option_2 = 3'000
  Set init value: \nextstate = 6'000000

22.4.5. Executing PROC_ARST pass (detect async resets in processes).

22.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~112 debug messages>

22.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$679'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$678'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$630'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$629_EN[3:0]$636
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$629_DATA[3:0]$635
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$629_ADDR[3:0]$634
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$572'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$570_EN[3:0]$578
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$570_DATA[3:0]$577
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$570_ADDR[3:0]$576
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$571'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$898'.
     1/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$910
     2/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_DATA[7:0]$909
     3/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_ADDR[5:0]$908
     4/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$905
     5/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_DATA[7:0]$904
     6/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_ADDR[5:0]$903
     7/8: $0\write_ptr[5:0]
     8/8: $0\read_ptr[5:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$1084'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$1082'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$1080'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$1072'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$1069'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$1063'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$1058'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$1053'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$1044'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$1037'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$1031'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$1029'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$1021'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$1007'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$1001'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$996'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$791'.
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$783'.
     1/10: $0\alu_out_register[31:0]
     2/10: $0\register_data_2[31:0]
     3/10: $0\register_data_1[31:0]
     4/10: $0\memory_register[31:0]
     5/10: $0\temp_write_value[31:0]
     6/10: $0\temp_reg3[31:0]
     7/10: $0\temp_reg2[31:0]
     8/10: $0\temp_address[31:0]
     9/10: $0\pc_old[31:0]
    10/10: $0\instruction_register[31:0]
Creating decoders for process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:0$989'.
Creating decoders for process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:59$987'.
     1/1: $1\read_data[31:0]
Creating decoders for process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$950'.
     1/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$983
     2/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_DATA[31:0]$982
     3/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_ADDR[31:0]$981
     4/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$986
     5/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_DATA[31:0]$985
     6/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_ADDR[31:0]$984
     7/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$973
     8/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_DATA[31:0]$972
     9/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_ADDR[31:0]$971
    10/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$979
    11/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_DATA[31:0]$978
    12/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_ADDR[31:0]$977
    13/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$976
    14/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_DATA[31:0]$975
    15/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_ADDR[31:0]$974
    16/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$969
    17/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_DATA[31:0]$968
    18/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_ADDR[31:0]$967
    19/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$966
    20/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_DATA[31:0]$965
    21/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_ADDR[31:0]$964
    22/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$963
    23/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_DATA[31:0]$962
    24/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_ADDR[31:0]$961
Creating decoders for process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:39$948'.
     1/1: $0\memory_response[0:0]
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$292'.
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$289'.
     1/1: $0\data[32:0]
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$941'.
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$938'.
     1/1: $1\read_data[31:0]
Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$924'.
     1/9: $0\rx_fifo_write[0:0]
     2/9: $0\rx_fifo_read[0:0]
     3/9: $0\tx_fifo_write[0:0]
     4/9: $0\tx_fifo_read[0:0]
     5/9: $0\uart_tx_en[0:0]
     6/9: $0\rx_fifo_write_data[7:0]
     7/9: $0\tx_fifo_write_data[7:0]
     8/9: $0\uart_tx_data[7:0]
     9/9: $0\buffer_full[0:0]
Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$922'.
     1/2: $0\gpio_value[5:0]
     2/2: $0\gpio_direction[5:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$165'.
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:24$147'.
     1/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$162
     2/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$142_DATA[31:0]$161
     3/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$142_ADDR[4:0]$160
     4/9: $2$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$163
     5/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$154
     6/9: $1$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$158
     7/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$157
     8/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$142_DATA[31:0]$156
     9/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$142_ADDR[4:0]$155
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$139'.
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:15$136'.
     1/1: $0\Output[31:0]
Creating decoders for process `\MUX.$proc$Risco-5/src/core/mux.v:14$135'.
     1/1: $1\S[31:0]
Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$133'.
     1/4: $4\immediate[31:0]
     2/4: $3\immediate[31:0]
     3/4: $2\immediate[31:0]
     4/4: $1\immediate[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$132'.
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$131'.
     1/1: $1\csr_data_out[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127'.
     1/1: $1\csr_write_data[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$125'.
     1/4: $0\csr_mip_msip[0:0]
     2/4: $0\csr_mip_mtip[0:0]
     3/4: $0\csr_mip_meip[0:0]
     4/4: $0\csr_mip_mfip[15:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$118'.
     1/13: $0\csr_mtval[31:0]
     2/13: $0\csr_mtvec[31:0]
     3/13: $0\csr_mstatus_mpie[0:0]
     4/13: $0\csr_mstatus_mie[0:0]
     5/13: $0\csr_mscratch[31:0]
     6/13: $0\csr_minstret[63:0]
     7/13: $0\csr_mie_mtie[0:0]
     8/13: $0\csr_mie_msie[0:0]
     9/13: $0\csr_mie_meie[0:0]
    10/13: $0\csr_mie_mfie[15:0]
    11/13: $0\csr_mepc[31:0]
    12/13: $0\csr_mcycle[63:0]
    13/13: $0\csr_mcause[31:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$687'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$681'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$81'.
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$80'.
     1/2: $0\clear_hal_byte_one_block_option_2[2:0]
     2/2: $0\clear_hal_byte_one_block_option[2:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:618$79'.
     1/1: $0\wb_filter[2:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
     1/22: $0\save_write_value[0:0]
     2/22: $0\write_data_in[0:0]
     3/22: $0\save_value_2[0:0]
     4/22: $0\save_value[0:0]
     5/22: $0\control_memory_op[0:0]
     6/22: $0\save_address[0:0]
     7/22: $0\control_unit_aluop[3:0]
     8/22: $0\alu_input_selector[0:0]
     9/22: $0\csr_write_enable[0:0]
    10/22: $0\is_immediate[0:0]
    11/22: $0\reg_write[0:0]
    12/22: $0\alu_src_a[2:0]
    13/22: $0\alu_src_b[2:0]
    14/22: $0\aluop[1:0]
    15/22: $0\pc_source[0:0]
    16/22: $0\memory_to_reg[2:0]
    17/22: $0\memory_write[0:0]
    18/22: $0\memory_read[0:0]
    19/22: $0\lorD[1:0]
    20/22: $0\ir_write[0:0]
    21/22: $0\pc_write[0:0]
    22/22: $0\pc_write_cond[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34'.
     1/19: $19\nextstate[5:0]
     2/19: $18\nextstate[5:0]
     3/19: $17\nextstate[5:0]
     4/19: $16\nextstate[5:0]
     5/19: $15\nextstate[5:0]
     6/19: $14\nextstate[5:0]
     7/19: $13\nextstate[5:0]
     8/19: $12\nextstate[5:0]
     9/19: $11\nextstate[5:0]
    10/19: $10\nextstate[5:0]
    11/19: $9\nextstate[5:0]
    12/19: $8\nextstate[5:0]
    13/19: $7\nextstate[5:0]
    14/19: $6\nextstate[5:0]
    15/19: $5\nextstate[5:0]
    16/19: $4\nextstate[5:0]
    17/19: $3\nextstate[5:0]
    18/19: $2\nextstate[5:0]
    19/19: $1\nextstate[5:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:133$33'.
     1/1: $0\state[5:0]
Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'.
     1/4: $4\aluop_out[3:0]
     2/4: $3\aluop_out[3:0]
     3/4: $2\aluop_out[3:0]
     4/4: $1\aluop_out[3:0]
Creating decoders for process `\Alu.$proc$Risco-5/src/core/alu.v:23$11'.
     1/1: $1\ALU_out_S[31:0]

22.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$1053'.
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$996'.
No latch inferred for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.\read_data' from process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:59$987'.
No latch inferred for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\read_data' from process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$938'.
No latch inferred for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:17$140_EN' from process `\Registers.$proc$Risco-5/src/core/registers.v:0$165'.
No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$Risco-5/src/core/mux.v:14$135'.
No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$133'.
No latch inferred for signal `\CSR_Unit.\csr_mcause_code' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$132'.
No latch inferred for signal `\CSR_Unit.\csr_mcause_interrupt_flag' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$132'.
No latch inferred for signal `\CSR_Unit.\csr_utime' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$132'.
No latch inferred for signal `\CSR_Unit.\csr_data_out' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$131'.
No latch inferred for signal `\CSR_Unit.\csr_write_data' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127'.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [0]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [1]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [2]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [3]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [4]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [5]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [6]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [7]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [8]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [9]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [10]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [11]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [12]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [13]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [14]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [15]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [16]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [17]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [18]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [19]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [20]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [21]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [22]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [23]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [24]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [25]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [26]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [27]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [28]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [29]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [30]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [31]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127`.
No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$80'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$80`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$80`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$80`.
No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option_2' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$80'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$80`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$80`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$80`.
No latch inferred for signal `\Control_Unit.\wb_filter' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:618$79'.
No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\csr_write_enable` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\alu_input_selector' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_input_selector` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\save_address' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_address` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\save_value' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\save_value_2' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value_2` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\save_write_value' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_write_value` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\control_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_memory_op` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\write_data_in' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\write_data_in` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\control_unit_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
Removing init bit 1'1 for non-memory siginal `\Control_Unit.\control_unit_memory_op [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\control_unit_aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66`.
No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [4]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [5]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34`.
Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26': $auto$proc_dlatch.cc:433:proc_dlatch$3163
No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$Risco-5/src/core/alu.v:23$11'.

22.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$678'.
  created $dff cell `$procdff$3186' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$614_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$615_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$616_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$617_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$618_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$619_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$620_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$621_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$622_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$623_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$624_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$625_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$626_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$627_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$628_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$629_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$630'.
  created $dff cell `$procdff$3187' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$629_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$630'.
  created $dff cell `$procdff$3188' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$629_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$630'.
  created $dff cell `$procdff$3189' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$554_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$555_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$556_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$557_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$558_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$559_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$560_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$561_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$562_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$563_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$564_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$565_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$566_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$567_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$568_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$569_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$570_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$572'.
  created $dff cell `$procdff$3190' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$570_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$572'.
  created $dff cell `$procdff$3191' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$570_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$572'.
  created $dff cell `$procdff$3192' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$571'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$898'.
  created $dff cell `$procdff$3193' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$898'.
  created $dff cell `$procdff$3194' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$898'.
  created $dff cell `$procdff$3195' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$898'.
  created $dff cell `$procdff$3196' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$898'.
  created $dff cell `$procdff$3197' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$1082'.
  created $dff cell `$procdff$3198' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$1082'.
  created $dff cell `$procdff$3199' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$1080'.
  created $dff cell `$procdff$3200' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$1072'.
  created $dff cell `$procdff$3201' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$1069'.
  created $dff cell `$procdff$3202' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$1063'.
  created $dff cell `$procdff$3203' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$1058'.
  created $dff cell `$procdff$3204' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$1058'.
  created $dff cell `$procdff$3205' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$1044'.
  created $dff cell `$procdff$3206' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$1031'.
  created $dff cell `$procdff$3207' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$1029'.
  created $dff cell `$procdff$3208' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$1021'.
  created $dff cell `$procdff$3209' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$1007'.
  created $dff cell `$procdff$3210' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$1001'.
  created $dff cell `$procdff$3211' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$1001'.
  created $dff cell `$procdff$3212' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$783'.
  created $dff cell `$procdff$3213' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$783'.
  created $dff cell `$procdff$3214' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$783'.
  created $dff cell `$procdff$3215' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$783'.
  created $dff cell `$procdff$3216' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$783'.
  created $dff cell `$procdff$3217' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$783'.
  created $dff cell `$procdff$3218' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_address' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$783'.
  created $dff cell `$procdff$3219' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_reg2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$783'.
  created $dff cell `$procdff$3220' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_reg3' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$783'.
  created $dff cell `$procdff$3221' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_write_value' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$783'.
  created $dff cell `$procdff$3222' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_ADDR' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$950'.
  created $dff cell `$procdff$3223' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_DATA' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$950'.
  created $dff cell `$procdff$3224' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$950'.
  created $dff cell `$procdff$3225' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_ADDR' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$950'.
  created $dff cell `$procdff$3226' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_DATA' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$950'.
  created $dff cell `$procdff$3227' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$950'.
  created $dff cell `$procdff$3228' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_ADDR' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$950'.
  created $dff cell `$procdff$3229' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_DATA' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$950'.
  created $dff cell `$procdff$3230' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$950'.
  created $dff cell `$procdff$3231' with positive edge clock.
Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.\memory_response' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:39$948'.
  created $dff cell `$procdff$3232' with positive edge clock.
Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$289'.
  created $dff cell `$procdff$3233' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\uart_tx_en' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$924'.
  created $dff cell `$procdff$3234' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_read' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$924'.
  created $dff cell `$procdff$3235' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_write' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$924'.
  created $dff cell `$procdff$3236' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_read' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$924'.
  created $dff cell `$procdff$3237' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_write' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$924'.
  created $dff cell `$procdff$3238' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\buffer_full' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$924'.
  created $dff cell `$procdff$3239' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\uart_tx_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$924'.
  created $dff cell `$procdff$3240' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_write_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$924'.
  created $dff cell `$procdff$3241' with positive edge clock.
Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_write_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$924'.
  created $dff cell `$procdff$3242' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$922'.
  created $dff cell `$procdff$3243' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$922'.
  created $dff cell `$procdff$3244' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$147'.
  created $dff cell `$procdff$3245' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$142_ADDR' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$147'.
  created $dff cell `$procdff$3246' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$142_DATA' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$147'.
  created $dff cell `$procdff$3247' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$147'.
  created $dff cell `$procdff$3248' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$147'.
  created $dff cell `$procdff$3249' with positive edge clock.
Creating register for signal `\PC.\Output' using process `\PC.$proc$Risco-5/src/core/pc.v:15$136'.
  created $dff cell `$procdff$3250' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_mfip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$125'.
  created $dff cell `$procdff$3251' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_meip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$125'.
  created $dff cell `$procdff$3252' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_mtip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$125'.
  created $dff cell `$procdff$3253' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_msip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$125'.
  created $dff cell `$procdff$3254' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mcause' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$118'.
  created $dff cell `$procdff$3255' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mcycle' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$118'.
  created $dff cell `$procdff$3256' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mepc' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$118'.
  created $dff cell `$procdff$3257' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_mfie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$118'.
  created $dff cell `$procdff$3258' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_meie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$118'.
  created $dff cell `$procdff$3259' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_msie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$118'.
  created $dff cell `$procdff$3260' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_mtie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$118'.
  created $dff cell `$procdff$3261' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_minstret' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$118'.
  created $dff cell `$procdff$3262' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mscratch' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$118'.
  created $dff cell `$procdff$3263' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mstatus_mie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$118'.
  created $dff cell `$procdff$3264' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mstatus_mpie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$118'.
  created $dff cell `$procdff$3265' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mtvec' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$118'.
  created $dff cell `$procdff$3266' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mtval' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$118'.
  created $dff cell `$procdff$3267' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$681'.
  created $dff cell `$procdff$3268' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$681'.
  created $dff cell `$procdff$3269' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$681'.
  created $dff cell `$procdff$3270' with positive edge clock.
Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:133$33'.
  created $dff cell `$procdff$3271' with positive edge clock.

22.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$679'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$678'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$678'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$630'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$596'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$572'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$571'.
Found and cleaned up 3 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$898'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$898'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:132$1084'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$1082'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:197$1082'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$1080'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:186$1080'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$1072'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:171$1072'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$1069'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:160$1069'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$1063'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:148$1063'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$1058'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:133$1058'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$1053'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:116$1053'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$1044'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:97$1044'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:114$1037'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$1031'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:173$1031'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$1029'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:162$1029'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$1021'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:147$1021'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$1007'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:130$1007'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$1001'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:115$1001'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$996'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:98$996'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$791'.
Found and cleaned up 6 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$783'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$783'.
Removing empty process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:0$989'.
Found and cleaned up 1 empty switch in `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:59$987'.
Removing empty process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:59$987'.
Found and cleaned up 3 empty switches in `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$950'.
Removing empty process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$950'.
Found and cleaned up 1 empty switch in `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:39$948'.
Removing empty process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:39$948'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$292'.
Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$289'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$289'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$941'.
Found and cleaned up 1 empty switch in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$938'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:76$938'.
Found and cleaned up 5 empty switches in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$924'.
Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:41$924'.
Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$922'.
Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:29$922'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$165'.
Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:24$147'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:24$147'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$139'.
Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:15$136'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:15$136'.
Found and cleaned up 1 empty switch in `\MUX.$proc$Risco-5/src/core/mux.v:14$135'.
Removing empty process `MUX.$proc$Risco-5/src/core/mux.v:14$135'.
Found and cleaned up 4 empty switches in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$133'.
Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$133'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$132'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$131'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:187$131'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:178$127'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$125'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:164$125'.
Found and cleaned up 3 empty switches in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$118'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:118$118'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$687'.
Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$681'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$681'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$81'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$80'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$80'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:618$79'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:618$79'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$66'.
Found and cleaned up 19 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$34'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:133$33'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:133$33'.
Found and cleaned up 4 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'.
Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$26'.
Found and cleaned up 1 empty switch in `\Alu.$proc$Risco-5/src/core/alu.v:23$11'.
Removing empty process `Alu.$proc$Risco-5/src/core/alu.v:23$11'.
Cleaned up 112 empty switches.

22.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
<suppressed ~4 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
<suppressed ~10 debug messages>
Optimizing module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.
<suppressed ~5 debug messages>
Optimizing module LEDs.
<suppressed ~3 debug messages>
Optimizing module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
<suppressed ~9 debug messages>
Optimizing module GPIO.
<suppressed ~3 debug messages>
Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
<suppressed ~4 debug messages>
Optimizing module BUS.
Optimizing module Registers.
<suppressed ~2 debug messages>
Optimizing module PC.
<suppressed ~2 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module Immediate_Generator.
<suppressed ~1 debug messages>
Optimizing module CSR_Unit.
<suppressed ~2 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~7 debug messages>
Optimizing module Control_Unit.
<suppressed ~26 debug messages>
Optimizing module ALU_Control.
<suppressed ~15 debug messages>
Optimizing module Alu.
<suppressed ~1 debug messages>
Optimizing module $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC.
Optimizing module top.

22.5. Executing FLATTEN pass (flatten design).
[Pipeline] sh
Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Deleting now unused module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.
Deleting now unused module LEDs.
Deleting now unused module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.
Deleting now unused module GPIO.
Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Deleting now unused module BUS.
Deleting now unused module Registers.
Deleting now unused module PC.
Deleting now unused module MUX.
Deleting now unused module Immediate_Generator.
Deleting now unused module CSR_Unit.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module Control_Unit.
Deleting now unused module ALU_Control.
Deleting now unused module Alu.
Deleting now unused module $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC.
<suppressed ~30 debug messages>

22.6. Executing TRIBUF pass.

22.7. Executing DEMINOUT pass (demote inout ports to input or output).

22.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~47 debug messages>

22.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 63 unused cells and 858 unused wires.
<suppressed ~83 debug messages>

22.10. Executing CHECK pass (checking for obvious problems).
Checking module top...
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [15] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [14] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [13] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [12] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [11] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [10] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [9] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [8] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [7] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [6] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [5] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [4] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [3] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [2] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [1] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_fast [0] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_external is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_timer is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.instruction_request_software is used but has no driver.
Found and reported 19 problems.

22.11. Executing OPT pass (performing simple optimizations).

22.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~11 debug messages>

22.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~861 debug messages>
Removed a total of 287 cells.

22.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+ mkdir -p Risco-5/impl/pnr
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2456.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2469.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2485.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2487.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2502.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2520.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2541.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2566.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2593.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2623.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2656.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2701.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2748.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2796.
    dead port 1/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2846.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2848.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2898.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2900.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2949.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3008.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3059.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1729.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1731.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1742.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1757.
    dead port 1/9 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1712.
    dead port 2/9 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1712.
    dead port 3/9 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1712.
    dead port 4/9 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1712.
    dead port 1/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1712.
    dead port 2/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1712.
    dead port 3/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1712.
    dead port 4/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1712.
    dead port 5/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1712.
    dead port 6/9 on $pmux $flatten\SOC.\Core.\PCSourceMUX.$procmux$1712.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1672.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1678.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1684.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1690.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1467.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1469.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1476.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1478.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1485.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1487.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1494.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1496.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1503.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1505.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1512.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1514.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1520.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1526.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1532.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1538.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1544.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1550.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1556.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1562.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1568.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1112.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1118.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1124.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1112.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1118.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1124.
Removed 66 multiplexer ports.
<suppressed ~148 debug messages>

22.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2064: $auto$opt_reduce.cc:134:opt_pmux$3322
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2078: $auto$opt_reduce.cc:134:opt_pmux$3324
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2096: $auto$opt_reduce.cc:134:opt_pmux$3326
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2145: $auto$opt_reduce.cc:134:opt_pmux$3328
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2171: $auto$opt_reduce.cc:134:opt_pmux$3330
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2188: { $auto$opt_reduce.cc:134:opt_pmux$3334 $auto$opt_reduce.cc:134:opt_pmux$3332 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2216: $auto$opt_reduce.cc:134:opt_pmux$3336
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2236: $auto$opt_reduce.cc:134:opt_pmux$3338
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2239: $auto$opt_reduce.cc:134:opt_pmux$3340
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2246: { $flatten\SOC.\Core.\Control_Unit.$procmux$2099_CMP $auto$opt_reduce.cc:134:opt_pmux$3352 $auto$opt_reduce.cc:134:opt_pmux$3350 $auto$opt_reduce.cc:134:opt_pmux$3348 $auto$opt_reduce.cc:134:opt_pmux$3346 $auto$opt_reduce.cc:134:opt_pmux$3344 $auto$opt_reduce.cc:134:opt_pmux$3342 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2280: { $flatten\SOC.\Core.\Control_Unit.$procmux$2273_CMP $auto$opt_reduce.cc:134:opt_pmux$3366 $auto$opt_reduce.cc:134:opt_pmux$3364 $auto$opt_reduce.cc:134:opt_pmux$3362 $flatten\SOC.\Core.\Control_Unit.$procmux$2195_CMP $auto$opt_reduce.cc:134:opt_pmux$3360 $flatten\SOC.\Core.\Control_Unit.$procmux$2192_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2191_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2190_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2189_CMP $auto$opt_reduce.cc:134:opt_pmux$3358 $auto$opt_reduce.cc:134:opt_pmux$3356 $auto$opt_reduce.cc:134:opt_pmux$3354 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3123: { $flatten\SOC.\Core.\ALU_Control.$procmux$3130_CMP $auto$opt_reduce.cc:134:opt_pmux$3368 $flatten\SOC.\Core.\ALU_Control.$procmux$3127_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3126_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3125_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3124_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3137: { $auto$opt_reduce.cc:134:opt_pmux$3372 $auto$opt_reduce.cc:134:opt_pmux$3370 $flatten\SOC.\Core.\ALU_Control.$procmux$3130_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2315: { $auto$opt_reduce.cc:134:opt_pmux$3374 $flatten\SOC.\Core.\Control_Unit.$procmux$2251_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3146: { $flatten\SOC.\Core.\ALU_Control.$procmux$3148_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3147_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2322: $auto$opt_reduce.cc:134:opt_pmux$3376
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2326: { $flatten\SOC.\Core.\Control_Unit.$procmux$2244_CMP $auto$opt_reduce.cc:134:opt_pmux$3378 $flatten\SOC.\Core.\Control_Unit.$procmux$2232_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2342: $auto$opt_reduce.cc:134:opt_pmux$3380
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2364: $auto$opt_reduce.cc:134:opt_pmux$3382
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2382: $auto$opt_reduce.cc:134:opt_pmux$3384
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2441: $auto$opt_reduce.cc:134:opt_pmux$3386
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2997: { $auto$opt_reduce.cc:134:opt_pmux$3388 $flatten\SOC.\Core.\Control_Unit.$procmux$3005_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3004_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3003_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3002_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3001_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3000_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2999_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2998_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3062: { $flatten\SOC.\Core.\Control_Unit.$procmux$2309_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2278_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2174_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2369_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2151_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2345_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2250_CMP $auto$opt_reduce.cc:134:opt_pmux$3392 $flatten\SOC.\Core.\Control_Unit.$procmux$2202_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2243_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2173_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2150_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2201_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2273_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2149_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2133_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2100_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2099_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2197_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2268_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2098_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2195_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2194_CMP $auto$opt_reduce.cc:134:opt_pmux$3390 $flatten\SOC.\Core.\Control_Unit.$procmux$2066_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2080_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2172_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2147_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2192_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2191_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2097_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2190_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2189_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2065_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2079_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1771: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1792_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1791_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1784_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1783_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1782_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1781_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1780_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1779_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1778_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1777_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1776_CMP $auto$opt_reduce.cc:134:opt_pmux$3400 $auto$opt_reduce.cc:134:opt_pmux$3398 $auto$opt_reduce.cc:134:opt_pmux$3396 $auto$opt_reduce.cc:134:opt_pmux$3394 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1754: $auto$opt_reduce.cc:134:opt_pmux$3402
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1760: { $flatten\SOC.\Core.\Control_Unit.$procmux$3002_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3003_CMP $auto$opt_reduce.cc:134:opt_pmux$3406 $flatten\SOC.\Core.\Control_Unit.$procmux$3004_CMP $auto$opt_reduce.cc:134:opt_pmux$3404 $flatten\SOC.\Core.\Control_Unit.$procmux$2998_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3006_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1669:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1687:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1693:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$141_EN[31:0]$148 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1464:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1464_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1464_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1464_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] $flatten\SOC.\Memory.$procmux$1464_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1491:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Memory.$procmux$1491_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Memory.$procmux$1491_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1491_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] $flatten\SOC.\Memory.$procmux$1491_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1518:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1518_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1518_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1518_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] $flatten\SOC.\Memory.$procmux$1518_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1109:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1109_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1109_Y [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$procmux$1109_Y [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$procmux$1109_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1109_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1109_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1109_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1109_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1109_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1109_Y [0] }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2042: { $flatten\SOC.\Core.\Control_Unit.$procmux$2039_CMP $auto$opt_reduce.cc:134:opt_pmux$3408 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1109:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1109_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1109_Y [0]
      New connections: $flatten\SOC.\Uart.\TX_FIFO.$procmux$1109_Y [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$procmux$1109_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1109_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1109_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1109_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1109_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1109_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1109_Y [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1696:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$163, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1687_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$143_EN[31:0]$152 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1699:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$162, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1669_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$142_EN[31:0]$151 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1536:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$986, B=0, Y=$flatten\SOC.\Memory.$procmux$1536_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1491_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1536_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1536_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] $flatten\SOC.\Memory.$procmux$1536_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1554:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$983, B=0, Y=$flatten\SOC.\Memory.$procmux$1554_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1464_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1554_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1554_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] $flatten\SOC.\Memory.$procmux$1554_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1589:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$973, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1518_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_EN[31:0]$953 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1127:
      Old ports: A=$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$910, B=8'00000000, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901
      New ports: A=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1109_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1127:
      Old ports: A=$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$910, B=8'00000000, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901
      New ports: A=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1109_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [0]
      New connections: $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_EN[7:0]$901 [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1571:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$979, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1536_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_EN[31:0]$959 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1580:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$976, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1554_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_EN[31:0]$956 [0] }
  Optimizing cells in module \top.
Performed a total of 44 changes.

22.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~15 debug messages>
Removed a total of 5 cells.

22.11.6. Executing OPT_DFF pass (perform DFF optimizations).

22.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 360 unused wires.
<suppressed ~3 debug messages>

22.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.11.9. Rerunning OPT passes. (Maybe there is more to do..)

22.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~147 debug messages>

22.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2280: { $flatten\SOC.\Core.\Control_Unit.$procmux$2273_CMP $auto$opt_reduce.cc:134:opt_pmux$3366 $auto$opt_reduce.cc:134:opt_pmux$3364 $auto$opt_reduce.cc:134:opt_pmux$3362 $flatten\SOC.\Core.\Control_Unit.$procmux$2195_CMP $auto$opt_reduce.cc:134:opt_pmux$3360 $auto$opt_reduce.cc:134:opt_pmux$3412 $auto$opt_reduce.cc:134:opt_pmux$3410 $auto$opt_reduce.cc:134:opt_pmux$3358 $auto$opt_reduce.cc:134:opt_pmux$3356 $auto$opt_reduce.cc:134:opt_pmux$3354 }
  Optimizing cells in module \top.
Performed a total of 1 changes.

22.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.11.13. Executing OPT_DFF pass (perform DFF optimizations).

22.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.11.16. Rerunning OPT passes. (Maybe there is more to do..)

22.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~147 debug messages>

22.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.11.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.11.20. Executing OPT_DFF pass (perform DFF optimizations).

22.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.11.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.11.23. Finished OPT passes. (There is nothing left to do.)

22.12. Executing FSM pass (extract and optimize FSM).

22.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.
Not marking top.SOC.Core.CSR_Unit.csr_mip_mfip as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Not marking top.SOC.Core.Control_Unit.state as FSM state register:
    Register has an initialization value.
Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state.
Not marking top.SOC.Uart.i_uart_tx.fsm_state as FSM state register:
    Users of register don't seem to benefit from recoding.

22.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
[Pipeline] sh
Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'.
  found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$3200
  root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$1046_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$1061_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$1074_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$1060_Y
  found state code: 3'000
  found ctrl input: \SOC.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \SOC.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$1074_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$1065_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$1061_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$1060_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$1046_Y
  ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o }
  ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$1046_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$1060_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$1061_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$1065_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$1074_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'0--0 ->      3'001 8'01010001
  transition:      3'000 4'1--0 ->      3'000 8'01010000
  transition:      3'000 4'---1 ->      3'000 8'01010000
  transition:      3'010 4'--00 ->      3'010 8'00100010
  transition:      3'010 4'--10 ->      3'011 8'00100011
  transition:      3'010 4'---1 ->      3'000 8'00100000
  transition:      3'001 4'-0-0 ->      3'001 8'00011001
  transition:      3'001 4'-1-0 ->      3'010 8'00011010
  transition:      3'001 4'---1 ->      3'000 8'00011000
  transition:      3'011 4'-0-0 ->      3'011 8'10010011
  transition:      3'011 4'-1-0 ->      3'000 8'10010000
  transition:      3'011 4'---1 ->      3'000 8'10010000

22.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3413' from module `\top'.

22.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 7 unused cells and 7 unused wires.
<suppressed ~8 debug messages>

22.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3413' from module `\top'.
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].

22.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3413' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---

22.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3413' from module `top':
-------------------------------------

  Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$3413 (\SOC.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \ResetBootSystem.reset_o
    1: \SOC.Uart.i_uart_rx.payload_done
    2: \SOC.Uart.i_uart_rx.next_bit
    3: \SOC.Uart.i_uart_rx.rxd_reg

  Output signals:
    0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:176$1074_Y
    1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:151$1065_Y
    2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:138$1061_Y
    3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:136$1060_Y
    4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:100$1046_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'1--0   ->     0 5'01010
      1:     0 4'---1   ->     0 5'01010
      2:     0 4'0--0   ->     2 5'01010
      3:     1 4'---1   ->     0 5'00100
      4:     1 4'--00   ->     1 5'00100
      5:     1 4'--10   ->     3 5'00100
      6:     2 4'---1   ->     0 5'00011
      7:     2 4'-1-0   ->     1 5'00011
      8:     2 4'-0-0   ->     2 5'00011
      9:     3 4'-1-0   ->     0 5'10010
     10:     3 4'---1   ->     0 5'10010
     11:     3 4'-0-0   ->     3 5'10010

-------------------------------------

22.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3413' from module `\top'.

22.13. Executing OPT pass (performing simple optimizations).

22.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

22.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

22.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~146 debug messages>

22.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3212 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1393_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1387_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1378_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1369_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1360_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1351_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1333_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1342_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3463 ($sdff) from module top (D = \SOC.Uart.uart_tx_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$3463 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1387_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1378_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1369_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1360_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1351_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1333_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1342_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3210 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1309_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3468 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1309_Y, Q = \SOC.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3209 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1298_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$3474 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$1028_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3208 ($dff) from module top (D = \SOC.Uart.i_uart_tx.n_fsm_state, Q = \SOC.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3207 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1287_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$3479 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1287_Y, Q = \SOC.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3206 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1276_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3485 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3204 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$1253_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1244_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1235_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1226_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1217_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1208_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1190_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1199_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3487 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3203 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1172_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3491 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$1068_Y, Q = \SOC.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3202 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1167_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3495 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3201 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1159_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$3497 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$1079_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3199 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3198 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$3194 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1136_Y, Q = \SOC.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3503 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$913_Y, Q = \SOC.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$3193 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1141_Y, Q = \SOC.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3505 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$918_Y [5:0], Q = \SOC.Uart.TX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$3194 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1136_Y, Q = \SOC.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3507 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$913_Y, Q = \SOC.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$3193 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1141_Y, Q = \SOC.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3509 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$918_Y [5:0], Q = \SOC.Uart.RX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3242 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1634_Y, Q = \SOC.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3511 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.uart_rx_data, Q = \SOC.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3241 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1639_Y, Q = \SOC.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3513 ($sdff) from module top (D = \SOC.Uart.write_data [7:0], Q = \SOC.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3240 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1644_Y, Q = \SOC.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3515 ($sdff) from module top (D = \SOC.Uart.tx_fifo_read_data, Q = \SOC.Uart.uart_tx_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3238 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1609_Y, Q = \SOC.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3237 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1614_Y, Q = \SOC.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3236 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1619_Y, Q = \SOC.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3234 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1624_Y, Q = \SOC.Uart.uart_tx_en, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Leds.$procdff$3233 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$1599_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3521 ($sdff) from module top (D = { 1'0 \SOC.Leds.write_data }, Q = \SOC.Leds.data).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$3244 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1655_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3523 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_value).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$3243 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1663_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3527 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_direction).
Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$3250 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$1707_Y, Q = \SOC.Core.Pc.Output, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3533 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.Output).
Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$3271 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 6'000000).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3267 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1815_Y, Q = \SOC.Core.CSR_Unit.csr_mtval, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3536 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mtval).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3266 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 1'0 \SOC.Core.CSR_Unit.csr_write_data [0] }, Q = \SOC.Core.CSR_Unit.csr_mtvec).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3265 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1841_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$3545 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3264 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1858_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3549 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mstatus_mie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3263 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1874_Y, Q = \SOC.Core.CSR_Unit.csr_mscratch, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3553 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mscratch).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3262 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1887_Y, Q = \SOC.Core.CSR_Unit.csr_minstret, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3557 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1887_Y, Q = \SOC.Core.CSR_Unit.csr_minstret).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3261 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1905_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mtie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3561 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mie_mtie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3260 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1923_Y, Q = \SOC.Core.CSR_Unit.csr_mie_msie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3565 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mie_msie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3259 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1941_Y, Q = \SOC.Core.CSR_Unit.csr_mie_meie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3569 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [11], Q = \SOC.Core.CSR_Unit.csr_mie_meie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3258 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1959_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mfie, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3573 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [31:16], Q = \SOC.Core.CSR_Unit.csr_mie_mfie).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3257 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 2'00 }, Q = \SOC.Core.CSR_Unit.csr_mepc).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3256 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1982_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3582 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1982_Y, Q = \SOC.Core.CSR_Unit.csr_mcycle).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3255 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1993_Y, Q = \SOC.Core.CSR_Unit.csr_mcause, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3586 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mcause).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3254 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_software, Q = \SOC.Core.CSR_Unit.csr_mip_msip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3253 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_timer, Q = \SOC.Core.CSR_Unit.csr_mip_mtip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3252 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_external, Q = \SOC.Core.CSR_Unit.csr_mip_meip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3251 ($dff) from module top (D = \SOC.Core.CSR_Unit.instruction_request_fast, Q = \SOC.Core.CSR_Unit.csr_mip_mfip, rval = 16'0000000000000000).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3222 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1425_Y, Q = \SOC.Core.temp_write_value, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3594 ($sdff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.temp_write_value).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3221 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1430_Y, Q = \SOC.Core.temp_reg3, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3596 ($sdff) from module top (D = \SOC.Core.alu_out_register, Q = \SOC.Core.temp_reg3).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3220 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1435_Y, Q = \SOC.Core.temp_reg2, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3598 ($sdff) from module top (D = \SOC.Core.memory_register, Q = \SOC.Core.temp_reg2).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3219 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1440_Y, Q = \SOC.Core.temp_address, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3600 ($sdff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.temp_address).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3218 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1445_Y, Q = \SOC.Core.pc_old, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3602 ($sdff) from module top (D = \SOC.Core.Pc.Output, Q = \SOC.Core.pc_old).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3217 ($dff) from module top (D = \SOC.Core.register_data_2_out, Q = \SOC.Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3216 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3215 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3214 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3213 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1450_Y, Q = \SOC.Core.instruction_register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3608 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register).
Adding EN signal on $flatten\ResetBootSystem.$procdff$3270 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$3269 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding EN signal on $flatten\ResetBootSystem.$procdff$3268 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3577 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3577 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3540 ($dffe) from module top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$3522 ($sdffe) from module top.

22.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 138 unused cells and 134 unused wires.
<suppressed ~139 debug messages>

22.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

22.13.9. Rerunning OPT passes. (Maybe there is more to do..)

22.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~100 debug messages>

22.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$3493: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o }
  Optimizing cells in module \top.
Performed a total of 1 changes.

22.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~15 debug messages>
Removed a total of 5 cells.

22.13.13. Executing OPT_DFF pass (perform DFF optimizations).

22.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 6 unused wires.
<suppressed ~2 debug messages>

22.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.13.16. Rerunning OPT passes. (Maybe there is more to do..)

22.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~100 debug messages>

22.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.20. Executing OPT_DFF pass (perform DFF optimizations).

22.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
+ cd Risco-5/fpga/tangnano20k/
+ /eda/gowin/IDE/bin/gw_sh run.tcl
*** GOWIN Tcl Command Line Console  *** 
current device: GW2AR-18C  GW2AR-LV18QN88C8/I7
add new file: "pinout.cst"
add new file: "top.sdc"
add new file: "main.v"
add new file: "../../debug/reset.v"
add new file: "../../src/core/alu_control.v"
add new file: "../../src/core/alu.v"
add new file: "../../src/core/control_unit.v"
add new file: "../../src/core/core.v"
add new file: "../../src/core/immediate_generator.v"
add new file: "../../src/core/mux.v"
add new file: "../../src/core/pc.v"
add new file: "../../src/core/registers.v"
add new file: "../../src/core/csr_unit.v"
add new file: "../../src/peripheral/bus.v"
add new file: "../../src/peripheral/gpio.v"
add new file: "../../src/peripheral/gpios.v"
add new file: "../../src/peripheral/leds.v"
add new file: "../../src/peripheral/memory.v"
add new file: "../../src/peripheral/soc.v"
add new file: "../../src/peripheral/uart_rx.v"
add new file: "../../src/peripheral/uart_tx.v"
add new file: "../../src/peripheral/uart.v"
add new file: "../../src/peripheral/fifo.v"
GowinSynthesis start
Running parser ...
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v'
Undeclared symbol 'pc_source', assumed default net type 'wire'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":142)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v'
WARN  (EX3801) : Parameter 'SET_DIRECTION' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":17)
WARN  (EX3801) : Parameter 'READ' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":18)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v'
WARN  (EX3012) : Empty statement in sequential block("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":54)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v'
WARN  (EX3073) : Port 'resetn_o' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":18)
Compiling module 'top'("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":1)
Compiling module 'ResetBootSystem'("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":1)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":37)
Compiling module 'Risco_5_SOC(CLOCK_FREQ=27000000,MEMORY_SIZE=2048,MEMORY_FILE="../../software/memory/fpga_test_3.hex")'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":1)
WARN  (EX3073) : Port 'interrupt_on_hold' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":242)
Compiling module 'Core(BOOT_ADDRESS=32'b00000000000000000000000000000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":1)
Compiling module 'PC'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v":1)
Compiling module 'MUX'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v":1)
Compiling module 'Registers'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v":1)
Compiling module 'Control_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":1)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":507)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":514)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":527)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":534)
Compiling module 'ALU_Control'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":1)
WARN  (EX2420) : Latch inferred for net 'aluop_out[3]'; We do not recommend the use of latches in FPGA designs, as they may lead to timing problems("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":57)
Compiling module 'Alu'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v":1)
Compiling module 'Immediate_Generator'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v":1)
Compiling module 'CSR_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":1)
WARN  (EX3780) : Using initial value of 'csr_utime' since it is never assigned("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":114)
WARN  (EX2565) : Input 'save_pc' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":242)
Compiling module 'Memory(MEMORY_FILE="../../software/memory/fpga_test_3.hex",MEMORY_SIZE=2048)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":1)
Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":16)
Compiling module 'BUS'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v":1)
Compiling module 'LEDs'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":1)
WARN  (EX3791) : Expression size 33 truncated to fit in target size 32("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":21)
Compiling module 'UART(CLOCK_FREQ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v":1)
Compiling module 'FIFO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":1)
Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":15)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":35)
Finding unused cells or wires in module \top..

22.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.13.23. Finished OPT passes. (There is nothing left to do.)

22.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$3276 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$3278 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$meminit$\registers$Risco-5/src/core/registers.v:17$164 (SOC.Core.RegisterBank.registers).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3273 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3274 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3275 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$988 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:24$946 (SOC.Memory.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$3272 (SOC.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$897 (SOC.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$3272 (SOC.Uart.TX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\TX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$897 (SOC.Uart.TX_FIFO.memory).
Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$2010_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$685 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$684 ($add).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$684 ($add).
Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$683 ($lt).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$3621 ($ne).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$3616 ($ne).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:20$921 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$1606_CMP0 ($eq).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Uart.$procmux$1605 ($pmux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1133 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1121 ($mux).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$918 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$917 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$911 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$893 ($eq).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1133 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1121 ($mux).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$918 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$917 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$911 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$893 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$1057 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$1056 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$1055 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$1054 ($mux).
Removed top 2 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:111$1049 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:109$1047 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:152$1023 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:137$1015 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:135$1013 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$1010 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:133$1009 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:120$1005 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$1000 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$999 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$998 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$997 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:94$993 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:92$991 ($eq).
Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$288 ($mux).
Removed top 19 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$168 ($le).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$171 ($ge).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$172 ($le).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$175 ($ge).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$176 ($le).
Removed top 18 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$179 ($ge).
Removed top 22 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$180 ($le).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:75$210 ($mux).
Removed top 27 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:84$226 ($mux).
Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$240 ($mux).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Memory.$procmux$1460_CMP0 ($eq).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1577 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1586 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1595 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1719_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1719_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1718_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$procmux$1717_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1719_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1718_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$procmux$1717_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1719_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1718_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$procmux$1717_CMP0 ($eq).
Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3057 ($mux).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3006_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3005_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3004_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3001_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3000_CMP0 ($eq).
Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2997 ($pmux).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2896 ($mux).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2843 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2794 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2746 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2699 ($mux).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2654 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2621 ($mux).
Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2591 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2564 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2518 ($mux).
Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2467 ($mux).
Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2369_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2345_CMP0 ($eq).
Removed top 5 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2278_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2273_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2268_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2254_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2252_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2251_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2250_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2248_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2247_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2244_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2243_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2242_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2241_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2238_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2237_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2232_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2202_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2201_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2197_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2196_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2174_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2173_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2151_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2150_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2149_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2133_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2100_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2099_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2098_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2042 ($pmux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2040_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2039_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:527$75 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:507$69 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:238$48 ($eq).
Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:166$35 ($eq).
Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:101$32 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3148_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3130_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3129_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3128_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3116 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3161_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3160_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3159_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3158_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$25 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$17 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1797_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1784_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1783_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1782_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1781_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1780_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1779_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1778_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1777_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1776_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$124 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$122 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$121 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$167 ($ge).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1530 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1548 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1566 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1482 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1509 ($mux).
Removed top 19 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:80$218 ($mux).
Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$684_Y.
Removed top 24 bits (of 32) from wire top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:91$240_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:34$17_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:46$25_Y.
Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$10\nextstate[5:0].
Removed top 4 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$11\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$13\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$15\nextstate[5:0].
Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$18\nextstate[5:0].
Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0].
Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0].
Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$5\nextstate[5:0].
Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$6\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$7\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$8\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$9\nextstate[5:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:507$69_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:527$75_Y.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_ADDR[31:0]$951.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_ADDR[31:0]$954.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_ADDR[31:0]$957.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$942_ADDR[31:0]$971.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_ADDR[31:0]$974.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_ADDR[31:0]$977.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$943_ADDR[31:0]$981.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$944_ADDR[31:0]$984.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_ADDR[5:0]$899.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_ADDR[5:0]$908.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$917_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$918_Y.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_ADDR[5:0]$899.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$887_ADDR[5:0]$908.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$917_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$918_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:118$1054_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:119$1055_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:120$1056_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$1057_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:100$997_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:101$998_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:102$999_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$1000_Y.

22.15. Executing PEEPOPT pass (run peephole optimizers).

22.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 45 unused wires.
<suppressed ~1 debug messages>

22.17. Executing SHARE pass (SAT-based resource sharing).
Found 5 cells in module top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$897 ($memrd):
    Found 1 activation_patterns using ctrl signal { $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:57$177_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:55$173_Y $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$169_Y $flatten\SOC.\Uart.$procmux$1608_CMP $flatten\SOC.\Uart.$procmux$1607_CMP $flatten\SOC.\Uart.$procmux$1606_CMP }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:24$946 ($memrd):
    Found 7 activation_patterns using ctrl signal { $flatten\SOC.\Memory.$procmux$1461_CMP $flatten\SOC.\Memory.$procmux$1460_CMP $flatten\SOC.\Memory.$procmux$1459_CMP $flatten\SOC.\Memory.$procmux$1458_CMP \SOC.Memory.option [1:0] \SOC.Memory.memory_write \SOC.Memory.memory_read $flatten\SOC.\Bus.$logic_and$Risco-5/src/peripheral/bus.v:53$169_Y }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\RegisterBank.$memrd$\registers$Risco-5/src/core/registers.v:22$146 ($memrd):
    Found 11 activation_patterns using ctrl signal { $flatten\SOC.\Core.\Alu.$procmux$3152_CMP $flatten\SOC.\Core.\Alu.$procmux$3153_CMP $flatten\SOC.\Core.\Alu.$procmux$3154_CMP $flatten\SOC.\Core.\Alu.$procmux$3155_CMP $flatten\SOC.\Core.\Alu.$procmux$3156_CMP $flatten\SOC.\Core.\Alu.$procmux$3157_CMP $flatten\SOC.\Core.\Alu.$procmux$3158_CMP $flatten\SOC.\Core.\Alu.$procmux$3159_CMP $flatten\SOC.\Core.\Alu.$procmux$3160_CMP $flatten\SOC.\Core.\Alu.$procmux$3161_CMP $flatten\SOC.\Core.\Alu.$procmux$3162_CMP $flatten\SOC.\Core.\AluInputBMUX.$procmux$1717_CMP }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:44$23 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3153_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:42$22 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3154_CMP.
    No candidates found.

22.18. Executing TECHMAP pass (map to technology primitives).

22.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

22.18.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~296 debug messages>

22.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.21. Executing TECHMAP pass (map to technology primitives).

22.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

22.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

22.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

22.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$684 ($add).
  creating $macc model for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$772 ($add).
  creating $macc model for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$771 ($sub).
  creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15 ($sub).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$119 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$120 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$121 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$122 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$123 ($add).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$124 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$890 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$912 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$917 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$890 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$912 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$917 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$1068 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$1079 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$1017 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$1028 ($add).
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$1028.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$1017.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$1079.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$1068.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$917.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$912.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$890.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$917.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$912.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$890.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$124.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$123.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$122.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$121.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$120.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$119.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14.
  creating $alu model for $macc $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$771.
  creating $alu model for $macc $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$772.
  creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$684.
  creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$683 ($lt): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$167 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$171 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$175 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$179 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$168 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$172 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$176 ($le): new $alu
  creating $alu model for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$180 ($le): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24 ($ge): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
  creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$16 ($lt): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
  creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$685 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$683.
  creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21 ($eq): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15.
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:60$180: $auto$alumacc.cc:485:replace_alu$3690
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:58$176: $auto$alumacc.cc:485:replace_alu$3703
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:56$172: $auto$alumacc.cc:485:replace_alu$3716
  creating $alu cell for $flatten\SOC.\Bus.$le$Risco-5/src/peripheral/bus.v:54$168: $auto$alumacc.cc:485:replace_alu$3729
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:59$179: $auto$alumacc.cc:485:replace_alu$3742
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:57$175: $auto$alumacc.cc:485:replace_alu$3751
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:55$171: $auto$alumacc.cc:485:replace_alu$3760
  creating $alu cell for $flatten\SOC.\Bus.$ge$Risco-5/src/peripheral/bus.v:53$167: $auto$alumacc.cc:485:replace_alu$3769
  creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$683, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$685: $auto$alumacc.cc:485:replace_alu$3778
  creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$684: $auto$alumacc.cc:485:replace_alu$3789
  creating $alu cell for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$772: $auto$alumacc.cc:485:replace_alu$3792
  creating $alu cell for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$771: $auto$alumacc.cc:485:replace_alu$3795
  creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:30$14: $auto$alumacc.cc:485:replace_alu$3798
  creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:32$15, $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:46$24, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:34$16, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:40$21: $auto$alumacc.cc:485:replace_alu$3801
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:146$119: $auto$alumacc.cc:485:replace_alu$3814
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:147$120: $auto$alumacc.cc:485:replace_alu$3817
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:148$121: $auto$alumacc.cc:485:replace_alu$3820
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:149$122: $auto$alumacc.cc:485:replace_alu$3823
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:156$123: $auto$alumacc.cc:485:replace_alu$3826
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:157$124: $auto$alumacc.cc:485:replace_alu$3829
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$912: $auto$alumacc.cc:485:replace_alu$3832
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$890: $auto$alumacc.cc:485:replace_alu$3835
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$917: $auto$alumacc.cc:485:replace_alu$3838
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$912: $auto$alumacc.cc:485:replace_alu$3841
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$890: $auto$alumacc.cc:485:replace_alu$3844
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$917: $auto$alumacc.cc:485:replace_alu$3847
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:154$1068: $auto$alumacc.cc:485:replace_alu$3850
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:179$1079: $auto$alumacc.cc:485:replace_alu$3853
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:138$1017: $auto$alumacc.cc:485:replace_alu$3856
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:155$1028: $auto$alumacc.cc:485:replace_alu$3859
  created 30 $alu and 0 $macc cells.

22.23. Executing OPT pass (performing simple optimizations).

22.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

22.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~10 debug messages>
Removed a total of 2 cells.

22.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~100 debug messages>

22.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

22.23.6. Executing OPT_DFF pass (perform DFF optimizations).

22.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 22 unused wires.
<suppressed ~1 debug messages>

22.23.8. Executing OPT_EXPR pass (perform const folding).
Compiling module 'uart_tool_rx(CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v":10)
Compiling module 'uart_tool_tx(CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v":10)
Compiling module 'GPIOS(WIDHT=5)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":1)
Compiling module 'GPIO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v":1)
WARN  (EX2565) : Input 'halt' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_external' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_timer' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_software' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_fast[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_fast[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_fast[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_fast[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_fast[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_fast[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_fast[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_fast[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_fast[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_fast[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_fast[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_fast[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_fast[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_fast[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_fast[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
WARN  (EX2565) : Input 'instruction_request_fast[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":54)
NOTE  (EX0101) : Current top module is "top"
WARN  (EX0211) : The output port "interrupt_on_hold" of module "CSR_Unit" has no driver, assigning undriven bits to Z, simulation mismatch possible("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":20)
[5%] Running netlist conversion ...
WARN  (CV0016) : Input reset is unused("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":3)
Running device independent optimization ...
Optimizing module top.

22.23.9. Rerunning OPT passes. (Maybe there is more to do..)

22.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~100 debug messages>

22.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.23.13. Executing OPT_DFF pass (perform DFF optimizations).

22.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.23.16. Finished OPT passes. (There is nothing left to do.)

22.24. Executing MEMORY pass.

22.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

22.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

22.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing top.SOC.Core.RegisterBank.registers write port 0.
  Analyzing top.SOC.Core.RegisterBank.registers write port 1.
  Analyzing top.SOC.Core.RegisterBank.registers write port 2.
  Analyzing top.SOC.Memory.memory write port 0.
  Analyzing top.SOC.Memory.memory write port 1.
  Analyzing top.SOC.Memory.memory write port 2.
  Analyzing top.SOC.Uart.RX_FIFO.memory write port 0.
  Analyzing top.SOC.Uart.TX_FIFO.memory write port 0.

22.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

22.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\SOC.Core.RegisterBank.registers'[0] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[1] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[2] in module `\top': merging output FF to cell.
    Write port 0: don't care on collision.
    Write port 1: non-transparent.
    Write port 2: non-transparent.
Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found.
Checking read port `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': no output FF found.
Checking read port `\SOC.Uart.TX_FIFO.memory'[0] in module `\top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port address `\SOC.Core.RegisterBank.registers'[0] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Core.RegisterBank.registers'[1] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found.
Checking read port address `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': merged address FF to cell.

22.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 44 unused wires.
<suppressed ~7 debug messages>

22.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
  Merging ports 0, 2 (address 5'00000).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Memory.memory by address:
  Merging ports 0, 1 (address \SOC.Memory.address [12:2]).
  Merging ports 0, 2 (address \SOC.Memory.address [12:2]).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers using sat-based resource sharing:
  Checking group clocked with posedge \clk, width 32: ports 0, 1.
  Common input cone for all EN signals: 13 cells.
  Size of unconstrained SAT problem: 103 variables, 281 clauses
  Merging port 1 into port 0.

22.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

22.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 8 unused cells and 8 unused wires.
<suppressed ~9 debug messages>

22.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

22.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory top.SOC.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_
Extracted data FF from read port 2 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[2]
mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory top.SOC.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted addr FF from read port 0 of top.SOC.Uart.RX_FIFO.memory: $\SOC.Uart.RX_FIFO.memory$rdreg[0]
mapping memory top.SOC.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of top.SOC.Uart.TX_FIFO.memory: $\SOC.Uart.TX_FIFO.memory$rdreg[0]
<suppressed ~1084 debug messages>

22.27. Executing TECHMAP pass (map to technology primitives).

22.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

22.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

22.27.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$8e5e72577b4c3b167a98ad5915719acd6a2ff3f4\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$58f24e643e5858c811559272a02c6d84f974d8a6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b7ec8ee89a7cd4851359941621e9dedf8c3b7d83\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$6d2a7df30888468e46c2233cf858b33a106d24cc\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$1a510b238205ce75968c294c5a2f9682007038e9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$d697ed060a7caa7345cbd011d88bf1d0e8cd46a0\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$882b16869816e01f56a454af0eb6e24b6778fa0c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b6fd6d9e43fa3d8e6bc64941b5b57ab422f7e603\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$983d377398e8a630797eecf765a80311ec60d100\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c8ec1437ade7762ec3882c3e3f576764a2f7bb09\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$1de9eb29388171a23037c69580dd741dfa07544f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$ccbfc2f8b7417ea49ec4f806e284aeee31f607b3\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b1d6656f42d8fe2eb2a963373a2667cf617d2bc5\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$80ae742e83efa97f5ae3dddd041ab9a1ef9ac7b6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$9a18a5918aa94986c2ace7118a70e41127dc33df\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c4c009ae968ecf5722a8a929fbdc163f47dedcc6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$7e65f9170886a0570d9059c94eef599a8e7c0c53\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$88ca364434c15edf84547ebc10bbf93659adea39\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$219b7093d2a2ec9427a92a1f7d983c7335efd508\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$0f1e956af4a0dd7da6349454a915a33336b22174\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$20534e299f87b4db290b2588b7ce04615b91104c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$73e415998dfd4e0d8b84ec3ac6390921a6a2c53b\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$7d81e3db939f1224434306a374696f893743b990\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$060a68a0493c8190183716105f9d8172975de01f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~1419 debug messages>

22.28. Executing OPT pass (performing simple optimizations).

22.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~107 debug messages>

22.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~30 debug messages>
Removed a total of 10 cells.

22.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $\SOC.Uart.RX_FIFO.memory$rdreg[0] ($dff) from module top (D = $auto$rtlil.cc:2582:Mux$3913, Q = $\SOC.Uart.RX_FIFO.memory$rdreg[0]$q, rval = 3'000).
Adding SRST signal on $auto$ff.cc:266:slice$3610 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$2007_Y, Q = \ResetBootSystem.counter, rval = 6'000000).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3590 ($sdff) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3593 ($sdff) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3593 ($sdff) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3593 ($sdff) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$3593 ($sdff) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$3593 ($sdff) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$3593 ($sdff) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$3593 ($sdff) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$3593 ($sdff) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$3593 ($sdff) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$3593 ($sdff) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$3593 ($sdff) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$3593 ($sdff) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$3593 ($sdff) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$3593 ($sdff) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$3593 ($sdff) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$3593 ($sdff) from module top.

22.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
Finding unused cells or wires in module \top..
Removed 19 unused cells and 7633 unused wires.
<suppressed ~20 debug messages>

22.28.5. Rerunning OPT passes. (Removed registers in this run.)

22.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$6401 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$3636 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).

22.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 1 unused wires.
<suppressed ~2 debug messages>

22.28.10. Rerunning OPT passes. (Removed registers in this run.)

22.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.28.13. Executing OPT_DFF pass (perform DFF optimizations).

22.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
[55%] Inferring Phase 3 completed
Running technical mapping ...
Finding unused cells or wires in module \top..

22.28.15. Finished fast OPT passes.

22.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

22.30. Executing OPT pass (performing simple optimizations).

22.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$3935: $auto$rtlil.cc:2489:ReduceOr$3929 -> 1'1
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~65 debug messages>

22.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$3920:
      Old ports: A={ \SOC.Memory.buffer [31:16] \SOC.Memory.write_data [15:0] }, B=\SOC.Memory.write_data, Y=$auto$rtlil.cc:2582:Mux$3921
      New ports: A=\SOC.Memory.buffer [31:16], B=\SOC.Memory.write_data [31:16], Y=$auto$rtlil.cc:2582:Mux$3921 [31:16]
      New connections: $auto$rtlil.cc:2582:Mux$3921 [15:0] = \SOC.Memory.write_data [15:0]
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2016: { $flatten\ResetBootSystem.$procmux$2011_CMP $flatten\ResetBootSystem.$procmux$2010_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2019:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2019_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2019_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2019_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3116:
      Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$3638 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3638 [2]
      New connections: $auto$wreduce.cc:461:run$3638 [1:0] = 2'10
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3137:
      Old ports: A=4'0110, B=12'101101111110, Y=$flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0]
      New ports: A=3'010, B=9'101011110, Y={ $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [3:2] $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [0] }
      New connections: $flatten\SOC.\Core.\ALU_Control.$2\aluop_out[3:0] [1] = 1'1
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1771: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1792_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1791_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1784_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1783_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1782_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1781_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1780_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1779_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1778_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1777_CMP $auto$opt_reduce.cc:134:opt_pmux$3400 $auto$opt_reduce.cc:134:opt_pmux$3398 $auto$opt_reduce.cc:134:opt_pmux$3396 $auto$opt_reduce.cc:134:opt_pmux$3394 }
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2188:
      Old ports: A=4'0000, B=8'10001001, Y=\SOC.Core.control_unit_aluop
      New ports: A=2'00, B=4'1011, Y={ \SOC.Core.control_unit_aluop [3] \SOC.Core.control_unit_aluop [0] }
      New connections: \SOC.Core.control_unit_aluop [2:1] = 2'00
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2382:
      Old ports: A=2'00, B=2'10, Y=\SOC.Core.lorD
      New ports: A=1'0, B=1'1, Y=\SOC.Core.lorD [1]
      New connections: \SOC.Core.lorD [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2454:
      Old ports: A=6'101101, B=6'000000, Y=$flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0]
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0]
      New connections: $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [5:1] = { $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] 1'0 $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2483:
      Old ports: A=6'000000, B=6'100101, Y=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0]
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0]
      New connections: $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [5:1] = { $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] 2'00 $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2518:
      Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$3645 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3645 [2]
      New connections: $auto$wreduce.cc:461:run$3645 [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2539:
      Old ports: A=6'011111, B=6'100010, Y=$flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0]
      New ports: A=2'01, B=2'10, Y={ $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [5] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] }
      New connections: $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [4:1] = { $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] 1'1 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2564:
      Old ports: A=3'110, B=3'011, Y=$auto$wreduce.cc:461:run$3644 [2:0]
      New ports: A=2'10, B=2'01, Y={ $auto$wreduce.cc:461:run$3644 [2] $auto$wreduce.cc:461:run$3644 [0] }
      New connections: $auto$wreduce.cc:461:run$3644 [1] = 1'1
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2621:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$3643 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3643 [2] $auto$wreduce.cc:461:run$3643 [0] }
      New connections: $auto$wreduce.cc:461:run$3643 [1] = $auto$wreduce.cc:461:run$3643 [0]
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2654:
      Old ports: A=5'00000, B=5'10010, Y=$auto$wreduce.cc:461:run$3642 [4:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3642 [1]
      New connections: { $auto$wreduce.cc:461:run$3642 [4:2] $auto$wreduce.cc:461:run$3642 [0] } = { $auto$wreduce.cc:461:run$3642 [1] 3'000 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2699:
      Old ports: A=3'101, B=3'000, Y=$auto$wreduce.cc:461:run$3653 [2:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3653 [0]
      New connections: $auto$wreduce.cc:461:run$3653 [2:1] = { $auto$wreduce.cc:461:run$3653 [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2746:
      Old ports: A=3'110, B=3'000, Y=$auto$wreduce.cc:461:run$3652 [2:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3652 [1]
      New connections: { $auto$wreduce.cc:461:run$3652 [2] $auto$wreduce.cc:461:run$3652 [0] } = { $auto$wreduce.cc:461:run$3652 [1] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2843:
      Old ports: A=5'00101, B=5'11000, Y=$auto$wreduce.cc:461:run$3650 [4:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3650 [3] $auto$wreduce.cc:461:run$3650 [0] }
      New connections: { $auto$wreduce.cc:461:run$3650 [4] $auto$wreduce.cc:461:run$3650 [2:1] } = { $auto$wreduce.cc:461:run$3650 [3] $auto$wreduce.cc:461:run$3650 [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2896:
      Old ports: A=5'00011, B=5'10110, Y=$auto$wreduce.cc:461:run$3649 [4:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3649 [2] $auto$wreduce.cc:461:run$3649 [0] }
      New connections: { $auto$wreduce.cc:461:run$3649 [4:3] $auto$wreduce.cc:461:run$3649 [1] } = { $auto$wreduce.cc:461:run$3649 [2] 2'01 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2947:
      Old ports: A={ 1'0 $auto$wreduce.cc:461:run$3650 [4:0] }, B={ 1'0 $auto$wreduce.cc:461:run$3649 [4:0] }, Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0]
      New ports: A=$auto$wreduce.cc:461:run$3650 [4:0], B=$auto$wreduce.cc:461:run$3649 [4:0], Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [4:0]
      New connections: $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [5] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:101$32:
      Old ports: A=2'11, B=2'01, Y=\SOC.Core.Control_Unit.second_block_write_src_b [1:0]
      New ports: A=1'1, B=1'0, Y=\SOC.Core.Control_Unit.second_block_write_src_b [1]
      New connections: \SOC.Core.Control_Unit.second_block_write_src_b [0] = 1'1
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1727:
      Old ports: A={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] }, B={ 27'000000000000000000000000000 \SOC.Core.instruction_register [24:20] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0]
      New ports: A=\SOC.Core.instruction_register [24], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [31:6] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] \SOC.Core.instruction_register [24:20] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1754:
      Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, B={ 19'0000000000000000000 \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0]
      New ports: A=\SOC.Core.instruction_register [31], B=1'0, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [31:14] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [13] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [7] \SOC.Core.instruction_register [30:25] \SOC.Core.instruction_register [11:8] 1'0 }
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Memory.$procmux$1457:
      Old ports: A=\SOC.Memory.buffer, B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7:0] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:0] 24'000000000000000000000000 \SOC.Memory.buffer [7:0] 16'0000000000000000 \SOC.Memory.buffer [15:0] }, Y=\SOC.Bus.slave_0_read_data
      New ports: A=\SOC.Memory.buffer [31:8], B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:8] 40'0000000000000000000000000000000000000000 \SOC.Memory.buffer [15:8] }, Y=\SOC.Bus.slave_0_read_data [31:8]
      New connections: \SOC.Bus.slave_0_read_data [7:0] = \SOC.Memory.buffer [7:0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_rx.$procmux$1271:
      Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$3672 [0] 1'0 $auto$wreduce.cc:461:run$3673 [1:0] 2'01 \SOC.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$3675 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$3672 [0] $auto$wreduce.cc:461:run$3673 [1:0] 1'1 \SOC.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$3675 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:121$1057:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3675 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3675 [0]
      New connections: $auto$wreduce.cc:461:run$3675 [1] = $auto$wreduce.cc:461:run$3675 [0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$1408:
      Old ports: A=3'000, B={ 2'00 \SOC.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$3677 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$3679 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \SOC.Uart.uart_tx_en $auto$wreduce.cc:461:run$3677 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$3679 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:103$1000:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3679 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3679 [0]
      New connections: $auto$wreduce.cc:461:run$3679 [1] = $auto$wreduce.cc:461:run$3679 [0]
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$3924:
      Old ports: A=$auto$rtlil.cc:2582:Mux$3921, B={ \SOC.Memory.buffer [31:8] \SOC.Memory.write_data [7:0] }, Y=$auto$rtlil.cc:2582:Mux$3925
      New ports: A={ $auto$rtlil.cc:2582:Mux$3921 [31:16] \SOC.Memory.write_data [15:8] }, B=\SOC.Memory.buffer [31:8], Y=$auto$rtlil.cc:2582:Mux$3925 [31:8]
      New connections: $auto$rtlil.cc:2582:Mux$3925 [7:0] = \SOC.Memory.write_data [7:0]
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2025:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2019_Y, Y=$flatten\ResetBootSystem.$procmux$2025_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2019_Y [1], Y=$flatten\ResetBootSystem.$procmux$2025_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2025_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2500:
      Old ports: A=6'100001, B=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0], Y=$flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0]
      New ports: A=2'01, B={ $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] }, Y={ $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [2] $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [0] }
      New connections: { $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [5:3] $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [1] } = { $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [0] 3'000 }
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1738:
      Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:20] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] 20'00000000000000000000 \SOC.Core.instruction_register [31:20] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0]
      New ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:25] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] 1'0 \SOC.Core.instruction_register [31:25] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] $flatten\SOC.\Core.\Immediate_Generator.$4\immediate[31:0] [5] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12:5]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [31:13] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$3\immediate[31:0] [12] \SOC.Core.instruction_register [24:20] }
  Optimizing cells in module \top.
Performed a total of 35 changes.

22.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

22.30.6. Executing OPT_DFF pass (perform DFF optimizations).

22.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 4 unused wires.
<suppressed ~2 debug messages>

22.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

22.30.9. Rerunning OPT passes. (Maybe there is more to do..)

22.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 1/4 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1712.
    dead port 3/4 on $pmux $flatten\SOC.\Core.\MemoryAddressMUX.$procmux$1712.
Removed 2 multiplexer ports.
<suppressed ~67 debug messages>

22.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2947:
      Old ports: A={ $auto$wreduce.cc:461:run$3649 [4] $auto$wreduce.cc:461:run$3649 [4] $auto$wreduce.cc:461:run$3649 [0] 1'0 $auto$wreduce.cc:461:run$3649 [0] }, B={ $auto$wreduce.cc:461:run$3649 [4] 1'0 $auto$wreduce.cc:461:run$3649 [4] 1'1 $auto$wreduce.cc:461:run$3649 [0] }, Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [4:0]
      New ports: A={ $auto$wreduce.cc:461:run$3649 [4] $auto$wreduce.cc:461:run$3649 [0] 1'0 }, B={ 1'0 $auto$wreduce.cc:461:run$3649 [4] 1'1 }, Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [3:1]
      New connections: { $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [4] $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [0] } = { $auto$wreduce.cc:461:run$3649 [4] $auto$wreduce.cc:461:run$3649 [0] }
  Optimizing cells in module \top.
Performed a total of 1 changes.

22.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.30.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3478 ($sdff) from module top.

22.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.
<suppressed ~1 debug messages>

22.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

22.30.16. Rerunning OPT passes. (Maybe there is more to do..)

22.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~68 debug messages>

22.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.30.20. Executing OPT_DFF pass (perform DFF optimizations).

22.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.30.23. Finished OPT passes. (There is nothing left to do.)

22.31. Executing TECHMAP pass (map to technology primitives).

22.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

22.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

22.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $sdffce.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $mux.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $reduce_bool.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $bmux.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $dff.
Using template $paramod$bf541dd3c0ba8228982b61e7bfbc350a2c253f4c\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $ne.
Using template $paramod$21b43a343f2bc4ba62df8a2c90631d371d8e7ce8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $tribuf.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $sdff.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu.
Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux.
Using template $paramod$91e5b74f11633b3386c40b03efcf15406a306835\_80_ecp5_alu for cells of type $alu.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$d16a138d50c5473e76a26446ec9bb0a651b19901\_80_ecp5_alu for cells of type $alu.
Using template $paramod$531b0e8664cf0177363f10a943e616839f246c95\_80_ecp5_alu for cells of type $alu.
Using template $paramod$3945f32547a814e98e0af098256e32675d1d77b0\_80_ecp5_alu for cells of type $alu.
Using template $paramod$19e9557905baa9d3741d0daa66e2ef076e9bab7d\_90_pmux for cells of type $pmux.
Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux.
Using template $paramod$2116a631f856d4d4902c2618dca73dafa3b8c9c0\_90_alu for cells of type $alu.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using template $paramod$f1fc4bc1d42e857fca43ce0fdd0da6ff25c612c4\_90_pmux for cells of type $pmux.
Using template $paramod$4d45682f6d5f8751d24fc75184ef72226da353f7\_90_pmux for cells of type $pmux.
Using template $paramod$382ee18765329ac2a4237df67c8ed074f3b7e946\_90_pmux for cells of type $pmux.
Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux.
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
Using template $paramod$e25898cce02b4d043ab08e065e45db8cf66c901c\_90_pmux for cells of type $pmux.
Using template $paramod$a285b5a57fe61eabc57c91b8c412748ee1151a85\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $reduce_xor.
Using template $paramod$a13703aa027da371a1931fc542d213d7de559b19\_90_pmux for cells of type $pmux.
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $dlatch.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$56955d0f36f77738c952d3505dc563df3ee11b94\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$a5f0941832cc861549e29ccafffe20bfdf2e5528\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod$e4e871699ef984d49b67460a907fd39b385c5c53\_90_demux for cells of type $demux.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~5194 debug messages>

22.32. Executing OPT pass (performing simple optimizations).

22.32.1. Executing OPT_EXPR pass (perform const folding).
[75%] Tech-Mapping Phase 2 completed
Optimizing module top.
<suppressed ~10975 debug messages>

22.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~5436 debug messages>
Removed a total of 1812 cells.

22.32.3. Executing OPT_DFF pass (perform DFF optimizations).

22.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 631 unused cells and 4952 unused wires.
<suppressed ~632 debug messages>

22.32.5. Finished fast OPT passes.

22.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

22.35. Executing TECHMAP pass (map to technology primitives).

22.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

22.35.2. Continuing TECHMAP pass.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_.
No more expansions possible.

****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

source run.tcl
# read_verilog "main.v"
<suppressed ~948 debug messages>

22.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~28 debug messages>

22.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

22.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in top.

22.39. Executing ATTRMVCP pass (move or copy attributes).

22.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 4777 unused wires.
<suppressed ~1 debug messages>

22.41. Executing TECHMAP pass (map to technology primitives).

22.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

22.41.2. Continuing TECHMAP pass.

22.41.3. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping \$_DLATCH_N_.$ternary$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$36237 ($mux).
Mapping \$_DLATCH_N_.$logic_not$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$36236 ($logic_not).
<suppressed ~4 debug messages>

22.41.4. Executing OPT pass (performing simple optimizations).

22.41.4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.
<suppressed ~1 debug messages>

22.41.4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

22.41.4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.41.4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

22.41.4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

22.41.4.6. Executing OPT_DFF pass (perform DFF optimizations).

22.41.4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..
Removed 1 unused cells and 2 unused wires.
<suppressed ~2 debug messages>

22.41.4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

22.41.4.9. Rerunning OPT passes. (Maybe there is more to do..)

22.41.4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.41.4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

22.41.4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

22.41.4.13. Executing OPT_DFF pass (perform DFF optimizations).

22.41.4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..

22.41.4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

22.41.4.16. Finished OPT passes. (There is nothing left to do.)
Using template \$_DLATCH_N_ for cells of type $_DLATCH_N_.
No more expansions possible.
<suppressed ~4 debug messages>

22.42. Executing ABC9 pass.

22.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.3. Executing PROC pass (convert processes to netlists).

22.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36341'.
Cleaned up 1 empty switch.

22.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36342 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.3.4. Executing PROC_INIT pass (extract init attributes).

22.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36342'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36340_EN[3:0]$36348
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36340_DATA[3:0]$36347
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36340_ADDR[3:0]$36346
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36341'.

22.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36331_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36339_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36327_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36336_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36337_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36335_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36324_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36329_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36325_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36330_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36326_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36334_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36332_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36338_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36333_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36328_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36340_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36342'.
  created $dff cell `$procdff$36392' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36340_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36342'.
  created $dff cell `$procdff$36393' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36340_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36342'.
  created $dff cell `$procdff$36394' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36341'.
  created direct connection (no actual register cell created).

22.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36366'.
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36342'.
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36341'.
Cleaned up 1 empty switch.

22.42.3.12. Executing OPT_EXPR pass (perform const folding).

22.42.4. Executing PROC pass (convert processes to netlists).

22.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36412'.
Cleaned up 1 empty switch.

22.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36413 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.4.4. Executing PROC_INIT pass (extract init attributes).

22.42.4.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36413'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36411_EN[3:0]$36418
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36411_DATA[3:0]$36417
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36411_ADDR[3:0]$36419
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36412'.

22.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36395_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36407_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36410_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36404_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36400_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36409_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36405_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36397_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36398_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36402_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36403_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36399_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36408_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36406_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36401_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36396_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36411_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36413'.
  created $dff cell `$procdff$36463' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36411_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36413'.
  created $dff cell `$procdff$36464' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36411_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36413'.
  created $dff cell `$procdff$36465' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36412'.
  created direct connection (no actual register cell created).

22.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36437'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36413'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36412'.
Cleaned up 1 empty switch.

22.42.4.12. Executing OPT_EXPR pass (perform const folding).

22.42.5. Executing PROC pass (convert processes to netlists).

22.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36483'.
Cleaned up 1 empty switch.

22.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36484 in module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.5.4. Executing PROC_INIT pass (extract init attributes).

22.42.5.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
Creating decoders for process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36484'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36482_EN[3:0]$36490
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36482_DATA[3:0]$36489
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36482_ADDR[3:0]$36488
Creating decoders for process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36483'.

22.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.\i' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36466_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36471_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36467_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36475_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36476_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36480_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36472_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36468_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36470_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36473_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36478_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36481_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36477_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36479_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36474_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36469_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36482_ADDR' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36484'.
  created $dff cell `$procdff$36534' with positive edge clock.
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36482_DATA' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36484'.
  created $dff cell `$procdff$36535' with positive edge clock.
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36482_EN' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36484'.
  created $dff cell `$procdff$36536' with positive edge clock.
Creating register for signal `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36483'.
  created direct connection (no actual register cell created).

22.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36508'.
Found and cleaned up 1 empty switch in `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36484'.
Removing empty process `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36483'.
Cleaned up 1 empty switch.

22.42.5.12. Executing OPT_EXPR pass (perform const folding).

22.42.6. Executing PROC pass (convert processes to netlists).

22.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36554'.
Cleaned up 1 empty switch.

22.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36555 in module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.6.4. Executing PROC_INIT pass (extract init attributes).

22.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
Creating decoders for process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36555'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36553_EN[3:0]$36561
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36553_DATA[3:0]$36559
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36553_ADDR[3:0]$36560
Creating decoders for process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36554'.

22.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.\i' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36537_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36542_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36547_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36549_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36538_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36539_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36544_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36541_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36545_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36543_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36550_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36548_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36551_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36552_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36546_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36540_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36553_DATA' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36555'.
  created $dff cell `$procdff$36605' with positive edge clock.
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36553_ADDR' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36555'.
  created $dff cell `$procdff$36606' with positive edge clock.
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36553_EN' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36555'.
  created $dff cell `$procdff$36607' with positive edge clock.
Creating register for signal `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.\muxwre' using process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36554'.
  created direct connection (no actual register cell created).

22.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36579'.
Found and cleaned up 1 empty switch in `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36555'.
Removing empty process `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36554'.
Cleaned up 1 empty switch.

22.42.6.12. Executing OPT_EXPR pass (perform const folding).

22.42.7. Executing PROC pass (convert processes to netlists).

22.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36625'.
Cleaned up 1 empty switch.

22.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36626 in module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.7.4. Executing PROC_INIT pass (extract init attributes).

22.42.7.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
Creating decoders for process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36626'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36624_EN[3:0]$36631
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36624_DATA[3:0]$36632
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36624_ADDR[3:0]$36630
Creating decoders for process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36625'.

22.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.\i' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36612_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36617_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36619_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36609_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36614_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36611_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36615_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36613_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36620_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36618_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36621_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36623_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36622_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36616_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36610_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36608_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36624_ADDR' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36626'.
  created $dff cell `$procdff$36676' with positive edge clock.
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36624_EN' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36626'.
  created $dff cell `$procdff$36677' with positive edge clock.
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36624_DATA' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36626'.
  created $dff cell `$procdff$36678' with positive edge clock.
Creating register for signal `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.\muxwre' using process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36625'.
  created direct connection (no actual register cell created).

22.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36650'.
Found and cleaned up 1 empty switch in `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36626'.
Removing empty process `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36625'.
Cleaned up 1 empty switch.

22.42.7.12. Executing OPT_EXPR pass (perform const folding).

22.42.8. Executing PROC pass (convert processes to netlists).

22.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36696'.
Cleaned up 1 empty switch.

22.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36697 in module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.8.4. Executing PROC_INIT pass (extract init attributes).

22.42.8.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.8.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
Creating decoders for process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36697'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36695_EN[3:0]$36703
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36695_DATA[3:0]$36702
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36695_ADDR[3:0]$36701
Creating decoders for process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36696'.

22.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.\i' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36679_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36681_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36682_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36685_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36690_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36691_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36689_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36683_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36687_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36688_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36693_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36694_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36684_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36692_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36686_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36680_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36695_ADDR' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36697'.
  created $dff cell `$procdff$36747' with positive edge clock.
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36695_DATA' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36697'.
  created $dff cell `$procdff$36748' with positive edge clock.
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36695_EN' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36697'.
  created $dff cell `$procdff$36749' with positive edge clock.
Creating register for signal `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.\muxwre' using process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36696'.
  created direct connection (no actual register cell created).

22.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36721'.
Found and cleaned up 1 empty switch in `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36697'.
Removing empty process `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36696'.
Cleaned up 1 empty switch.

22.42.8.12. Executing OPT_EXPR pass (perform const folding).

22.42.9. Executing PROC pass (convert processes to netlists).

22.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36767'.
Cleaned up 1 empty switch.

22.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36768 in module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.9.4. Executing PROC_INIT pass (extract init attributes).

22.42.9.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.9.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
Creating decoders for process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36768'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36766_EN[3:0]$36774
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36766_DATA[3:0]$36773
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36766_ADDR[3:0]$36772
Creating decoders for process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36767'.

22.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.\i' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36750_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36751_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36752_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36753_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36757_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36758_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36759_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36763_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36764_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36754_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36765_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36755_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36760_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36761_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36762_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36756_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36766_ADDR' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36768'.
  created $dff cell `$procdff$36818' with positive edge clock.
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36766_DATA' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36768'.
  created $dff cell `$procdff$36819' with positive edge clock.
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36766_EN' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36768'.
  created $dff cell `$procdff$36820' with positive edge clock.
Creating register for signal `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.\muxwre' using process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36767'.
  created direct connection (no actual register cell created).

22.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36792'.
Found and cleaned up 1 empty switch in `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36768'.
Removing empty process `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36767'.
Cleaned up 1 empty switch.

22.42.9.12. Executing OPT_EXPR pass (perform const folding).

22.42.10. Executing PROC pass (convert processes to netlists).

22.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36838'.
Cleaned up 1 empty switch.

22.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36839 in module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.10.4. Executing PROC_INIT pass (extract init attributes).

22.42.10.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.10.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
Creating decoders for process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36839'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36837_EN[3:0]$36844
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36837_DATA[3:0]$36845
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36837_ADDR[3:0]$36843
Creating decoders for process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36838'.

22.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.\i' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36821_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36823_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36827_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36828_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36829_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36833_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36834_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36824_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36835_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36830_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36831_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36836_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36822_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36825_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36832_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36826_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36837_ADDR' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36839'.
  created $dff cell `$procdff$36889' with positive edge clock.
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36837_EN' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36839'.
  created $dff cell `$procdff$36890' with positive edge clock.
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36837_DATA' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36839'.
  created $dff cell `$procdff$36891' with positive edge clock.
Creating register for signal `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.\muxwre' using process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36838'.
  created direct connection (no actual register cell created).

22.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36863'.
Found and cleaned up 1 empty switch in `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36839'.
Removing empty process `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36838'.
Cleaned up 1 empty switch.

22.42.10.12. Executing OPT_EXPR pass (perform const folding).

22.42.11. Executing PROC pass (convert processes to netlists).

22.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36909'.
Cleaned up 1 empty switch.

22.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36910 in module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.11.4. Executing PROC_INIT pass (extract init attributes).

22.42.11.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.11.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
Creating decoders for process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36910'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36908_EN[3:0]$36915
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36908_DATA[3:0]$36914
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36908_ADDR[3:0]$36916
Creating decoders for process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36909'.

22.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.\i' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36899_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36903_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36904_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36894_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36905_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36895_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36900_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36901_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36906_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36907_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36898_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36892_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36893_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36897_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36902_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36896_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36908_DATA' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36910'.
  created $dff cell `$procdff$36960' with positive edge clock.
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36908_EN' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36910'.
  created $dff cell `$procdff$36961' with positive edge clock.
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36908_ADDR' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36910'.
  created $dff cell `$procdff$36962' with positive edge clock.
Creating register for signal `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.\muxwre' using process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36909'.
  created direct connection (no actual register cell created).

22.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$36934'.
Found and cleaned up 1 empty switch in `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36910'.
Removing empty process `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36909'.
Cleaned up 1 empty switch.

22.42.11.12. Executing OPT_EXPR pass (perform const folding).

22.42.12. Executing PROC pass (convert processes to netlists).

22.42.12.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36980'.
Cleaned up 1 empty switch.

22.42.12.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36981 in module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.12.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.12.4. Executing PROC_INIT pass (extract init attributes).

22.42.12.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.12.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.12.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
Creating decoders for process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36981'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36979_EN[3:0]$36987
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36979_DATA[3:0]$36986
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36979_ADDR[3:0]$36985
Creating decoders for process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36980'.

22.42.12.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.12.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.\i' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36963_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36967_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36968_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36969_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36973_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36974_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36964_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36975_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36965_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36970_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36971_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36976_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36977_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36978_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36972_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$36966_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36979_ADDR' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36981'.
  created $dff cell `$procdff$37031' with positive edge clock.
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36979_DATA' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36981'.
  created $dff cell `$procdff$37032' with positive edge clock.
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$36979_EN' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36981'.
  created $dff cell `$procdff$37033' with positive edge clock.
Creating register for signal `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36980'.
  created direct connection (no actual register cell created).

22.42.12.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.12.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37005'.
Found and cleaned up 1 empty switch in `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$36981'.
Removing empty process `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$36980'.
Cleaned up 1 empty switch.

22.42.12.12. Executing OPT_EXPR pass (perform const folding).

22.42.13. Executing PROC pass (convert processes to netlists).

22.42.13.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37051'.
Cleaned up 1 empty switch.

22.42.13.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37052 in module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.13.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.13.4. Executing PROC_INIT pass (extract init attributes).

22.42.13.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.13.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.13.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
Creating decoders for process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37052'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37050_EN[3:0]$37056
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37050_DATA[3:0]$37057
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37050_ADDR[3:0]$37058
Creating decoders for process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37051'.

22.42.13.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.13.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.\i' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37046_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37047_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37041_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37040_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37043_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37044_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37045_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37049_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37035_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37037_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37038_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37039_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37048_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37042_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37036_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37034_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37050_EN' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37052'.
  created $dff cell `$procdff$37102' with positive edge clock.
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37050_DATA' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37052'.
  created $dff cell `$procdff$37103' with positive edge clock.
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37050_ADDR' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37052'.
  created $dff cell `$procdff$37104' with positive edge clock.
Creating register for signal `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.\muxwre' using process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37051'.
  created direct connection (no actual register cell created).

22.42.13.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.13.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37076'.
Found and cleaned up 1 empty switch in `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37052'.
Removing empty process `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37051'.
Cleaned up 1 empty switch.

22.42.13.12. Executing OPT_EXPR pass (perform const folding).

22.42.14. Executing PROC pass (convert processes to netlists).

22.42.14.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37122'.
Cleaned up 1 empty switch.

22.42.14.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37123 in module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.14.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.14.4. Executing PROC_INIT pass (extract init attributes).

22.42.14.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.14.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.14.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
Creating decoders for process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37123'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37121_EN[3:0]$37127
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37121_DATA[3:0]$37128
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37121_ADDR[3:0]$37129
Creating decoders for process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37122'.

22.42.14.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.14.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.\i' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37117_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37116_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37111_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37110_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37120_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37119_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37115_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37114_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37113_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37109_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37108_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37107_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37105_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37118_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37112_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37106_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37121_EN' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37123'.
  created $dff cell `$procdff$37173' with positive edge clock.
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37121_DATA' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37123'.
  created $dff cell `$procdff$37174' with positive edge clock.
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37121_ADDR' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37123'.
  created $dff cell `$procdff$37175' with positive edge clock.
Creating register for signal `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37122'.
  created direct connection (no actual register cell created).

22.42.14.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.14.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37147'.
Found and cleaned up 1 empty switch in `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37123'.
Removing empty process `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37122'.
Cleaned up 1 empty switch.

22.42.14.12. Executing OPT_EXPR pass (perform const folding).

22.42.15. Executing PROC pass (convert processes to netlists).

22.42.15.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37193'.
Cleaned up 1 empty switch.

22.42.15.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37194 in module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.15.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.15.4. Executing PROC_INIT pass (extract init attributes).

22.42.15.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.15.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.15.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
Creating decoders for process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37194'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37192_EN[3:0]$37200
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37192_DATA[3:0]$37198
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37192_ADDR[3:0]$37199
Creating decoders for process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37193'.

22.42.15.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.15.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37186_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.\i' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37187_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37181_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37191_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37180_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37190_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37189_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37185_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37184_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37183_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37179_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37178_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37177_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37176_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37188_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37182_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37192_DATA' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37194'.
  created $dff cell `$procdff$37244' with positive edge clock.
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37192_ADDR' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37194'.
  created $dff cell `$procdff$37245' with positive edge clock.
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37192_EN' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37194'.
  created $dff cell `$procdff$37246' with positive edge clock.
Creating register for signal `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37193'.
  created direct connection (no actual register cell created).

22.42.15.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.15.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37218'.
Found and cleaned up 1 empty switch in `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37194'.
Removing empty process `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37193'.
Cleaned up 1 empty switch.

22.42.15.12. Executing OPT_EXPR pass (perform const folding).

22.42.16. Executing PROC pass (convert processes to netlists).

22.42.16.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37264'.
Cleaned up 1 empty switch.

22.42.16.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37265 in module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.16.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.16.4. Executing PROC_INIT pass (extract init attributes).

22.42.16.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.16.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.16.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
Creating decoders for process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37265'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37263_EN[3:0]$37269
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37263_DATA[3:0]$37271
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37263_ADDR[3:0]$37270
Creating decoders for process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37264'.

22.42.16.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.16.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37251_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37261_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37250_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37260_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.\i' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37253_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37256_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37247_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37259_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37255_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37254_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37249_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37248_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37262_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37257_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37258_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37252_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37263_EN' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37265'.
  created $dff cell `$procdff$37315' with positive edge clock.
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37263_ADDR' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37265'.
  created $dff cell `$procdff$37316' with positive edge clock.
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37263_DATA' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37265'.
  created $dff cell `$procdff$37317' with positive edge clock.
Creating register for signal `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37264'.
  created direct connection (no actual register cell created).

22.42.16.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.16.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37289'.
Found and cleaned up 1 empty switch in `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37265'.
Removing empty process `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37264'.
Cleaned up 1 empty switch.

22.42.16.12. Executing OPT_EXPR pass (perform const folding).

22.42.17. Executing PROC pass (convert processes to netlists).

22.42.17.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37335'.
Cleaned up 1 empty switch.

22.42.17.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37336 in module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.17.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.17.4. Executing PROC_INIT pass (extract init attributes).

22.42.17.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.17.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.17.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
Creating decoders for process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37336'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37334_EN[3:0]$37341
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37334_DATA[3:0]$37340
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37334_ADDR[3:0]$37342
Creating decoders for process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37335'.

22.42.17.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.17.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37330_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37320_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37331_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37329_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37321_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37325_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37326_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37327_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37332_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37333_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.\i' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37318_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37324_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37323_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37319_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37328_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37322_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37334_DATA' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37336'.
  created $dff cell `$procdff$37386' with positive edge clock.
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37334_EN' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37336'.
  created $dff cell `$procdff$37387' with positive edge clock.
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37334_ADDR' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37336'.
  created $dff cell `$procdff$37388' with positive edge clock.
Creating register for signal `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.\muxwre' using process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37335'.
  created direct connection (no actual register cell created).

22.42.17.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.17.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37360'.
Found and cleaned up 1 empty switch in `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37336'.
Removing empty process `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37335'.
Cleaned up 1 empty switch.

22.42.17.12. Executing OPT_EXPR pass (perform const folding).

22.42.18. Executing PROC pass (convert processes to netlists).

22.42.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37406'.
Cleaned up 1 empty switch.

22.42.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37407 in module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.18.4. Executing PROC_INIT pass (extract init attributes).

22.42.18.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.18.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
Creating decoders for process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37407'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37405_EN[3:0]$37413
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37405_DATA[3:0]$37412
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37405_ADDR[3:0]$37411
Creating decoders for process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37406'.

22.42.18.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.18.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37401_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37395_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37391_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37396_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37399_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37400_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37390_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.\i' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37389_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37403_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37402_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37397_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37394_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37393_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37404_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37398_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37392_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37405_ADDR' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37407'.
  created $dff cell `$procdff$37457' with positive edge clock.
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37405_DATA' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37407'.
  created $dff cell `$procdff$37458' with positive edge clock.
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37405_EN' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37407'.
  created $dff cell `$procdff$37459' with positive edge clock.
Creating register for signal `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37406'.
  created direct connection (no actual register cell created).

22.42.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37431'.
Found and cleaned up 1 empty switch in `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37407'.
Removing empty process `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37406'.
Cleaned up 1 empty switch.

22.42.18.12. Executing OPT_EXPR pass (perform const folding).

22.42.19. Executing PROC pass (convert processes to netlists).

22.42.19.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37477'.
Cleaned up 1 empty switch.

22.42.19.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37478 in module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.19.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.19.4. Executing PROC_INIT pass (extract init attributes).

22.42.19.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.19.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.19.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
Creating decoders for process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37478'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37476_EN[3:0]$37484
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37476_DATA[3:0]$37483
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37476_ADDR[3:0]$37482
Creating decoders for process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37477'.

22.42.19.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.19.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.\i' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37463_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37464_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37465_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37469_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37470_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37471_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37475_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37461_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37466_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37467_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37472_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37473_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37474_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37468_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37462_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37460_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37476_ADDR' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37478'.
  created $dff cell `$procdff$37528' with positive edge clock.
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37476_DATA' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37478'.
  created $dff cell `$procdff$37529' with positive edge clock.
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37476_EN' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37478'.
  created $dff cell `$procdff$37530' with positive edge clock.
Creating register for signal `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.\muxwre' using process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37477'.
  created direct connection (no actual register cell created).

22.42.19.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.19.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37502'.
Found and cleaned up 1 empty switch in `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37478'.
Removing empty process `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37477'.
Cleaned up 1 empty switch.

22.42.19.12. Executing OPT_EXPR pass (perform const folding).

22.42.20. Executing PROC pass (convert processes to netlists).

22.42.20.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37548'.
Cleaned up 1 empty switch.

22.42.20.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37549 in module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.20.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.20.4. Executing PROC_INIT pass (extract init attributes).

22.42.20.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.20.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.20.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
Creating decoders for process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37549'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37547_EN[3:0]$37555
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37547_DATA[3:0]$37554
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37547_ADDR[3:0]$37553
Creating decoders for process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37548'.

22.42.20.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.20.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.\i' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37531_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37533_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37534_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37535_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37539_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37540_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37541_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37545_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37546_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37536_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37537_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37542_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37543_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37544_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37538_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37532_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37547_ADDR' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37549'.
  created $dff cell `$procdff$37599' with positive edge clock.
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37547_DATA' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37549'.
  created $dff cell `$procdff$37600' with positive edge clock.
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37547_EN' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37549'.
  created $dff cell `$procdff$37601' with positive edge clock.
Creating register for signal `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.\muxwre' using process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37548'.
  created direct connection (no actual register cell created).

22.42.20.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.20.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37573'.
Found and cleaned up 1 empty switch in `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37549'.
Removing empty process `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37548'.
Cleaned up 1 empty switch.

22.42.20.12. Executing OPT_EXPR pass (perform const folding).

22.42.21. Executing PROC pass (convert processes to netlists).

22.42.21.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37619'.
Cleaned up 1 empty switch.

22.42.21.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37620 in module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.21.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.21.4. Executing PROC_INIT pass (extract init attributes).

22.42.21.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.21.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.21.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
Creating decoders for process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37620'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37618_EN[3:0]$37626
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37618_DATA[3:0]$37625
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37618_ADDR[3:0]$37624
Creating decoders for process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37619'.

22.42.21.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.21.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.\i' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37602_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37603_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37604_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37605_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37609_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37610_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37611_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37615_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37616_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37606_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37617_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37607_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37612_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37613_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37614_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37608_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37618_ADDR' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37620'.
  created $dff cell `$procdff$37670' with positive edge clock.
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37618_DATA' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37620'.
  created $dff cell `$procdff$37671' with positive edge clock.
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37618_EN' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37620'.
  created $dff cell `$procdff$37672' with positive edge clock.
Creating register for signal `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.\muxwre' using process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37619'.
  created direct connection (no actual register cell created).

22.42.21.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.21.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37644'.
Found and cleaned up 1 empty switch in `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37620'.
Removing empty process `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37619'.
Cleaned up 1 empty switch.

22.42.21.12. Executing OPT_EXPR pass (perform const folding).

22.42.22. Executing PROC pass (convert processes to netlists).

22.42.22.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37690'.
Cleaned up 1 empty switch.

22.42.22.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37691 in module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.22.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.22.4. Executing PROC_INIT pass (extract init attributes).

22.42.22.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.22.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.22.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
Creating decoders for process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37691'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37689_EN[3:0]$37695
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37689_DATA[3:0]$37697
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37689_ADDR[3:0]$37696
Creating decoders for process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37690'.

22.42.22.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.22.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.\i' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37674_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37675_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37673_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37679_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37680_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37681_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37685_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37686_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37676_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37687_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37677_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37682_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37683_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37688_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37684_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37678_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37689_EN' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37691'.
  created $dff cell `$procdff$37741' with positive edge clock.
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37689_ADDR' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37691'.
  created $dff cell `$procdff$37742' with positive edge clock.
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37689_DATA' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37691'.
  created $dff cell `$procdff$37743' with positive edge clock.
Creating register for signal `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.\muxwre' using process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37690'.
  created direct connection (no actual register cell created).

22.42.22.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.22.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37715'.
Found and cleaned up 1 empty switch in `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37691'.
Removing empty process `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37690'.
Cleaned up 1 empty switch.

22.42.22.12. Executing OPT_EXPR pass (perform const folding).

22.42.23. Executing PROC pass (convert processes to netlists).

22.42.23.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37761'.
Cleaned up 1 empty switch.

22.42.23.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37762 in module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.23.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.23.4. Executing PROC_INIT pass (extract init attributes).

22.42.23.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.23.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.23.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
Creating decoders for process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37762'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37760_EN[3:0]$37767
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37760_DATA[3:0]$37766
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37760_ADDR[3:0]$37768
Creating decoders for process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37761'.

22.42.23.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.23.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.\i' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37759_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37744_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37745_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37749_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37750_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37751_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37755_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37756_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37746_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37757_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37747_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37758_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37752_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37753_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37754_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37748_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37760_DATA' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37762'.
  created $dff cell `$procdff$37812' with positive edge clock.
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37760_EN' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37762'.
  created $dff cell `$procdff$37813' with positive edge clock.
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37760_ADDR' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37762'.
  created $dff cell `$procdff$37814' with positive edge clock.
Creating register for signal `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.\muxwre' using process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37761'.
  created direct connection (no actual register cell created).

22.42.23.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.23.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37786'.
Found and cleaned up 1 empty switch in `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37762'.
Removing empty process `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37761'.
Cleaned up 1 empty switch.

22.42.23.12. Executing OPT_EXPR pass (perform const folding).

22.42.24. Executing PROC pass (convert processes to netlists).

22.42.24.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37832'.
Cleaned up 1 empty switch.

22.42.24.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37833 in module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.24.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.24.4. Executing PROC_INIT pass (extract init attributes).

22.42.24.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.24.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.24.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
Creating decoders for process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37833'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37831_EN[3:0]$37839
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37831_DATA[3:0]$37838
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37831_ADDR[3:0]$37837
Creating decoders for process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37832'.

22.42.24.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.24.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.\i' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37815_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37819_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37820_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37821_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37825_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37826_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37816_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37827_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37817_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37822_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37823_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37828_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37829_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37830_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37824_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37818_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37831_ADDR' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37833'.
  created $dff cell `$procdff$37883' with positive edge clock.
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37831_DATA' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37833'.
  created $dff cell `$procdff$37884' with positive edge clock.
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37831_EN' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37833'.
  created $dff cell `$procdff$37885' with positive edge clock.
Creating register for signal `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.\muxwre' using process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37832'.
  created direct connection (no actual register cell created).

22.42.24.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.24.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37857'.
Found and cleaned up 1 empty switch in `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37833'.
Removing empty process `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37832'.
Cleaned up 1 empty switch.

22.42.24.12. Executing OPT_EXPR pass (perform const folding).

22.42.25. Executing PROC pass (convert processes to netlists).

22.42.25.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37903'.
Cleaned up 1 empty switch.

22.42.25.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37904 in module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.25.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.25.4. Executing PROC_INIT pass (extract init attributes).

22.42.25.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.25.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.25.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
Creating decoders for process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37904'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37902_EN[3:0]$37910
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37902_DATA[3:0]$37909
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37902_ADDR[3:0]$37908
Creating decoders for process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37903'.

22.42.25.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.25.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.\i' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37889_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37890_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37894_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37895_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37896_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37900_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37901_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37891_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37892_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37897_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37898_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37899_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37893_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37888_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37886_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37887_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37902_ADDR' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37904'.
  created $dff cell `$procdff$37954' with positive edge clock.
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37902_DATA' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37904'.
  created $dff cell `$procdff$37955' with positive edge clock.
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37902_EN' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37904'.
  created $dff cell `$procdff$37956' with positive edge clock.
Creating register for signal `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.\muxwre' using process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37903'.
  created direct connection (no actual register cell created).

22.42.25.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.25.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37928'.
Found and cleaned up 1 empty switch in `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37904'.
Removing empty process `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37903'.
Cleaned up 1 empty switch.

22.42.25.12. Executing OPT_EXPR pass (perform const folding).

22.42.26. Executing PROC pass (convert processes to netlists).

22.42.26.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37974'.
Cleaned up 1 empty switch.

22.42.26.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37975 in module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.26.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.26.4. Executing PROC_INIT pass (extract init attributes).

22.42.26.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.26.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.26.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
Creating decoders for process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37975'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37973_EN[3:0]$37981
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37973_DATA[3:0]$37980
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37973_ADDR[3:0]$37979
Creating decoders for process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37974'.

22.42.26.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.26.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.\i' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37957_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37958_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37959_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37960_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37964_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37965_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37966_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37970_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37971_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37961_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37972_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37962_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37967_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37968_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37969_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$37963_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37973_ADDR' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37975'.
  created $dff cell `$procdff$38025' with positive edge clock.
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37973_DATA' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37975'.
  created $dff cell `$procdff$38026' with positive edge clock.
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$37973_EN' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37975'.
  created $dff cell `$procdff$38027' with positive edge clock.
Creating register for signal `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37974'.
  created direct connection (no actual register cell created).

22.42.26.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.26.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$37999'.
Found and cleaned up 1 empty switch in `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$37975'.
Removing empty process `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$37974'.
Cleaned up 1 empty switch.

22.42.26.12. Executing OPT_EXPR pass (perform const folding).

22.42.27. Executing PROC pass (convert processes to netlists).

22.42.27.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$38045'.
Cleaned up 1 empty switch.

22.42.27.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38046 in module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.27.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.27.4. Executing PROC_INIT pass (extract init attributes).

22.42.27.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.27.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.27.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
Creating decoders for process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38046'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38044_EN[3:0]$38051
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38044_DATA[3:0]$38050
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38044_ADDR[3:0]$38052
Creating decoders for process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$38045'.

22.42.27.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.27.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.\i' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38028_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38039_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38033_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38029_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38030_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38034_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38035_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38036_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38040_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38041_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38031_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38042_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38032_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38037_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38038_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38043_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38044_DATA' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38046'.
  created $dff cell `$procdff$38096' with positive edge clock.
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38044_EN' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38046'.
  created $dff cell `$procdff$38097' with positive edge clock.
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38044_ADDR' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38046'.
  created $dff cell `$procdff$38098' with positive edge clock.
Creating register for signal `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.\muxwre' using process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$38045'.
  created direct connection (no actual register cell created).

22.42.27.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.27.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38070'.
Found and cleaned up 1 empty switch in `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38046'.
Removing empty process `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$38045'.
Cleaned up 1 empty switch.

22.42.27.12. Executing OPT_EXPR pass (perform const folding).

22.42.28. Executing PROC pass (convert processes to netlists).

22.42.28.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$38116'.
Cleaned up 1 empty switch.

22.42.28.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38117 in module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.28.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.28.4. Executing PROC_INIT pass (extract init attributes).

22.42.28.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.28.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.28.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
Creating decoders for process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38117'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38115_EN[3:0]$38123
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38115_DATA[3:0]$38122
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38115_ADDR[3:0]$38121
Creating decoders for process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$38116'.

22.42.28.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.28.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.\i' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38109_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38103_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38099_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38106_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38100_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38105_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38104_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38110_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38111_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38101_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38112_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38102_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38107_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38108_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38113_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$38114_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38115_ADDR' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38117'.
  created $dff cell `$procdff$38167' with positive edge clock.
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38115_DATA' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38117'.
  created $dff cell `$procdff$38168' with positive edge clock.
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$38115_EN' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38117'.
  created $dff cell `$procdff$38169' with positive edge clock.
Creating register for signal `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.\muxwre' using process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$38116'.
  created direct connection (no actual register cell created).

22.42.28.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.28.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$38141'.
Found and cleaned up 1 empty switch in `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$38117'.
Removing empty process `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$38116'.
Cleaned up 1 empty switch.

22.42.28.12. Executing OPT_EXPR pass (perform const folding).

22.42.29. Executing SCC pass (detecting logic loops).
Found an SCC: $techmap$auto$ff.cc:266:slice$15745.$auto$simplemap.cc:267:simplemap_mux$36239
Found an SCC: $techmap$auto$ff.cc:266:slice$15744.$auto$simplemap.cc:267:simplemap_mux$36239
Found an SCC: $techmap$auto$ff.cc:266:slice$15743.$auto$simplemap.cc:267:simplemap_mux$36239
Found an SCC: $techmap$auto$ff.cc:266:slice$15742.$auto$simplemap.cc:267:simplemap_mux$36239
Found an SCC: $auto$simplemap.cc:38:simplemap_not$22240 $auto$ff.cc:266:slice$12242 $auto$simplemap.cc:126:simplemap_reduce$12435 $auto$simplemap.cc:126:simplemap_reduce$12420 $auto$ff.cc:266:slice$12243 $auto$ff.cc:266:slice$12244 $auto$simplemap.cc:75:simplemap_bitop$24384 $auto$simplemap.cc:196:simplemap_lognot$12440 $auto$simplemap.cc:126:simplemap_reduce$12438 $auto$simplemap.cc:126:simplemap_reduce$12436 $auto$opt_expr.cc:613:replace_const_cells$34617 $auto$simplemap.cc:126:simplemap_reduce$24358 $auto$opt_expr.cc:613:replace_const_cells$34615 $auto$simplemap.cc:267:simplemap_mux$24381 $auto$simplemap.cc:126:simplemap_reduce$24402 $auto$simplemap.cc:126:simplemap_reduce$24399 $auto$simplemap.cc:75:simplemap_bitop$24383 $auto$simplemap.cc:267:simplemap_mux$12406 $auto$simplemap.cc:225:simplemap_logbin$12410 $auto$simplemap.cc:196:simplemap_lognot$12425 $auto$simplemap.cc:126:simplemap_reduce$12423 $auto$simplemap.cc:126:simplemap_reduce$12421 $auto$ff.cc:266:slice$12245 $auto$simplemap.cc:126:simplemap_reduce$10930 $auto$simplemap.cc:126:simplemap_reduce$10928 $auto$simplemap.cc:225:simplemap_logbin$12365 $auto$simplemap.cc:196:simplemap_lognot$12375 $auto$simplemap.cc:126:simplemap_reduce$12373 $auto$opt_expr.cc:613:replace_const_cells$34619 $auto$simplemap.cc:267:simplemap_mux$24380 $auto$simplemap.cc:126:simplemap_reduce$24361
Found an SCC: $auto$ff.cc:266:slice$12250 $auto$ff.cc:266:slice$12251 $auto$simplemap.cc:38:simplemap_not$19086 $auto$ff.cc:266:slice$12252 $auto$simplemap.cc:126:simplemap_reduce$12458 $auto$simplemap.cc:38:simplemap_not$19087 $auto$ff.cc:266:slice$12253 $auto$ff.cc:266:slice$12254 $auto$opt_expr.cc:613:replace_const_cells$34629 $auto$ff.cc:266:slice$12246 $auto$simplemap.cc:126:simplemap_reduce$12455 $auto$ff.cc:266:slice$12247 $auto$ff.cc:266:slice$12248 $auto$simplemap.cc:126:simplemap_reduce$12460 $auto$simplemap.cc:126:simplemap_reduce$12456 $auto$simplemap.cc:38:simplemap_not$19083 $auto$ff.cc:266:slice$12249 $auto$simplemap.cc:126:simplemap_reduce$11553 $auto$simplemap.cc:196:simplemap_lognot$12467 $auto$simplemap.cc:126:simplemap_reduce$12465 $auto$simplemap.cc:126:simplemap_reduce$12463 $auto$simplemap.cc:126:simplemap_reduce$12461 $auto$simplemap.cc:126:simplemap_reduce$12457 $auto$simplemap.cc:38:simplemap_not$19084
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$11404 $auto$simplemap.cc:126:simplemap_reduce$11388 $auto$simplemap.cc:126:simplemap_reduce$11386 $auto$simplemap.cc:126:simplemap_reduce$11407 $auto$simplemap.cc:126:simplemap_reduce$11405 $auto$simplemap.cc:38:simplemap_not$6702 $auto$simplemap.cc:38:simplemap_not$32866 $auto$ff.cc:266:slice$6500 $auto$ff.cc:479:convert_ce_over_srst$35401 $auto$simplemap.cc:126:simplemap_reduce$6710 $auto$ff.cc:266:slice$6499 $auto$ff.cc:479:convert_ce_over_srst$35399 $auto$simplemap.cc:38:simplemap_not$32862 $auto$ff.cc:266:slice$6496 $auto$ff.cc:479:convert_ce_over_srst$35393 $auto$ff.cc:266:slice$6497 $auto$ff.cc:479:convert_ce_over_srst$35395 $auto$alumacc.cc:485:replace_alu$3778.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$6708 $auto$simplemap.cc:38:simplemap_not$32861 $auto$ff.cc:266:slice$6495 $auto$ff.cc:479:convert_ce_over_srst$35391 $auto$simplemap.cc:38:simplemap_not$6700 $auto$alumacc.cc:485:replace_alu$3778.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$3778.slice[2].ccu2c_i $auto$ff.cc:266:slice$6498 $auto$ff.cc:479:convert_ce_over_srst$35397 $auto$simplemap.cc:126:simplemap_reduce$11375 $auto$simplemap.cc:75:simplemap_bitop$6703 $auto$simplemap.cc:126:simplemap_reduce$6714 $auto$simplemap.cc:126:simplemap_reduce$6712 $auto$simplemap.cc:126:simplemap_reduce$6709 $auto$simplemap.cc:38:simplemap_not$19381
Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$35089 $auto$ff.cc:266:slice$12092 $auto$ff.cc:266:slice$12100 $auto$simplemap.cc:38:simplemap_not$24343 $auto$ff.cc:266:slice$12099 $auto$simplemap.cc:126:simplemap_reduce$12225 $auto$simplemap.cc:126:simplemap_reduce$12198 $auto$opt_expr.cc:613:replace_const_cells$35083 $auto$ff.cc:266:slice$12098 $auto$opt_expr.cc:613:replace_const_cells$35093 $auto$ff.cc:266:slice$12097 $auto$simplemap.cc:126:simplemap_reduce$12228 $auto$simplemap.cc:126:simplemap_reduce$12224 $auto$opt_expr.cc:613:replace_const_cells$35085 $auto$simplemap.cc:126:simplemap_reduce$12201 $auto$simplemap.cc:126:simplemap_reduce$12197 $auto$ff.cc:266:slice$12096 $auto$simplemap.cc:38:simplemap_not$24339 $auto$ff.cc:266:slice$12095 $auto$simplemap.cc:126:simplemap_reduce$12196 $auto$opt_expr.cc:613:replace_const_cells$35095 $auto$simplemap.cc:126:simplemap_reduce$12223 $auto$ff.cc:266:slice$12094 $auto$simplemap.cc:126:simplemap_reduce$12222 $auto$simplemap.cc:225:simplemap_logbin$12180 $auto$simplemap.cc:196:simplemap_lognot$12207 $auto$simplemap.cc:126:simplemap_reduce$12205 $auto$simplemap.cc:126:simplemap_reduce$12203 $auto$simplemap.cc:126:simplemap_reduce$12200 $auto$simplemap.cc:126:simplemap_reduce$12195 $auto$ff.cc:266:slice$12093 $auto$simplemap.cc:167:logic_reduce$10909 $auto$simplemap.cc:225:simplemap_logbin$12179 $auto$simplemap.cc:196:simplemap_lognot$12234 $auto$simplemap.cc:126:simplemap_reduce$12232 $auto$simplemap.cc:126:simplemap_reduce$12230 $auto$simplemap.cc:126:simplemap_reduce$12227
Found 8 SCCs in module top.
Found 8 SCCs.

22.42.30. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.31. Executing PROC pass (convert processes to netlists).

22.42.31.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

22.42.31.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

22.42.31.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

22.42.31.4. Executing PROC_INIT pass (extract init attributes).

22.42.31.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.31.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

22.42.31.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

22.42.31.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.31.9. Executing PROC_DFF pass (convert process syncs to FFs).

22.42.31.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.31.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

22.42.31.12. Executing OPT_EXPR pass (perform const folding).

22.42.32. Executing TECHMAP pass (map to technology primitives).

22.42.32.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

22.42.32.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~212 debug messages>

22.42.33. Executing OPT pass (performing simple optimizations).

22.42.33.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
Optimizing module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
Optimizing module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
Optimizing module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
Optimizing module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
Optimizing module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
Optimizing module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
Optimizing module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.
Optimizing module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
Optimizing module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
Optimizing module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
Optimizing module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
Optimizing module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
Optimizing module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
Optimizing module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
Optimizing module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
Optimizing module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
Optimizing module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
Optimizing module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
Optimizing module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
Optimizing module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
Optimizing module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
Optimizing module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
Optimizing module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.

22.42.33.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

22.42.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.42.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.
Performed a total of 0 changes.

22.42.33.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

22.42.33.6. Executing OPT_DFF pass (perform DFF optimizations).

22.42.33.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4..

22.42.33.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
Optimizing module $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
Optimizing module $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
Optimizing module $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
Optimizing module $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
Optimizing module $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
Optimizing module $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
Optimizing module $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.
Optimizing module $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
Optimizing module $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
Optimizing module $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
Optimizing module $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
Optimizing module $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
Optimizing module $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
Optimizing module $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
Optimizing module $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
Optimizing module $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
Optimizing module $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
Optimizing module $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
Optimizing module $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
Optimizing module $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
Optimizing module $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.

22.42.33.9. Finished OPT passes. (There is nothing left to do.)

22.42.34. Executing TECHMAP pass (map to technology primitives).

22.42.34.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

22.42.34.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4 for cells of type $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
Using template $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4 for cells of type $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
Using template $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4 for cells of type $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
Using template $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4 for cells of type $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
Using template $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4 for cells of type $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
Using template $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4 for cells of type $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
Using template $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4 for cells of type $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
Using template $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4 for cells of type $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
Using template $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4 for cells of type $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
Using template $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4 for cells of type $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.
Using template $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4 for cells of type $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
Using template $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4 for cells of type $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
Using template $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4 for cells of type $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
Using template $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4 for cells of type $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
Using template $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4 for cells of type $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
Using template $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4 for cells of type $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.
Using template $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4 for cells of type $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
Using template $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4 for cells of type $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
Using template $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4 for cells of type $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
Using template $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4 for cells of type $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
Using template $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4 for cells of type $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
Using template $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4 for cells of type $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
Using template $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4 for cells of type $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
Using template $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4 for cells of type $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~1104 debug messages>

22.42.35. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

22.42.36. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

22.42.37. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.38. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

22.42.39. Executing TECHMAP pass (map to technology primitives).

22.42.39.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

22.42.39.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~251 debug messages>

22.42.40. Executing OPT pass (performing simple optimizations).

22.42.40.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~18 debug messages>

22.42.40.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

22.42.40.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.42.40.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.42.40.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.42.40.6. Executing OPT_DFF pass (perform DFF optimizations).

22.42.40.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

22.42.40.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.42.40.9. Rerunning OPT passes. (Maybe there is more to do..)

22.42.40.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.42.40.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.42.40.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.42.40.13. Executing OPT_DFF pass (perform DFF optimizations).

22.42.40.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.42.40.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.42.40.16. Finished OPT passes. (There is nothing left to do.)

22.42.41. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

22.42.42. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 7843 cells with 49024 new cells, skipped 5496 cells.
  replaced 3 cell types:
    1959 $_OR_
      96 $_XOR_
    5788 $_MUX_
  not replaced 59 cell types:
      30 $scopeinfo
     430 $_NOT_
    1674 $_AND_
       6 $_TBUF_
       1 $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4
       1 $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4
       1 $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4
     833 TRELLIS_FF
       1 $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4
       1 $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4
       1 $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4
       1 $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4
       1 $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4
       1 $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4
       1 $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4
       1 $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4
       1 $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4
       1 $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4_$abc9_byp
      24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4_$abc9_byp
    1028 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4_$abc9_byp
     370 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
       1 $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4
       1 $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4
       1 $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4
       1 $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4
       1 $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4
       1 $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4
       1 $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4
       1 $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4
       1 $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4
       1 $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4
       1 $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4
       1 $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4
    1028 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
      24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4
       1 $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4_$abc9_byp
       1 $__ABC9_SCC_BREAKER

22.42.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.42.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 21285 AND gates and 62421 wires from module `top' to a netlist network with 5154 inputs and 904 outputs.

22.42.42.4. Executing ABC9_EXE pass (technology mapping using ABC9).

22.42.42.5. Executing ABC9.
read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1317.090 ; gain = 0.023 ; free physical = 3915 ; free virtual = 27761
# read_verilog ../../debug/reset.v
# read_verilog ../../src/core/alu_control.v
# read_verilog ../../src/core/alu.v
# read_verilog ../../src/core/control_unit.v
# read_verilog ../../src/core/core.v
# read_verilog ../../src/core/immediate_generator.v
# read_verilog ../../src/core/mux.v
# read_verilog ../../src/core/pc.v
# read_verilog ../../src/core/registers.v
# read_verilog ../../src/core/csr_unit.v
# read_verilog ../../src/peripheral/bus.v
# read_verilog ../../src/peripheral/gpio.v
# read_verilog ../../src/peripheral/gpios.v
# read_verilog ../../src/peripheral/leds.v
# read_verilog ../../src/peripheral/memory.v
# read_verilog ../../src/peripheral/soc.v
# read_verilog ../../src/peripheral/uart_rx.v
# read_verilog ../../src/peripheral/uart_tx.v
# read_verilog ../../src/peripheral/uart.v
# read_verilog ../../src/peripheral/fifo.v
# read_xdc "digilent_nexys4_ddr.xdc"
# set_property PROCESSING_ORDER EARLY [get_files digilent_nexys4_ddr.xdc]
# synth_design -top "top" -part "xc7a100tcsg324-1"
Command: synth_design -top top -part xc7a100tcsg324-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 59077
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   5154/    904  and =   19696  lev =   50 (7.14)  mem = 0.58 MB  box = 1446  bb = 1076
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   5154/    904  and =   25639  lev =   62 (4.97)  mem = 0.64 MB  ch = 2433  box = 1369  bb = 1076
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   60. Obj =  140. Set =  636. CutMin = no
ABC: Node =   25639.  Ch =  1741.  Total mem =    7.16 MB. Peak cut mem =    0.32 MB.
ABC: P:  Del = 7379.00.  Ar =   27439.0.  Edge =    34463.  Cut =   278390.  T =     0.07 sec
ABC: P:  Del = 7340.00.  Ar =   21643.0.  Edge =    28687.  Cut =   262436.  T =     0.07 sec
ABC: P:  Del = 7340.00.  Ar =   11553.0.  Edge =    24639.  Cut =   875165.  T =     0.22 sec
ABC: F:  Del = 7340.00.  Ar =    7822.0.  Edge =    21840.  Cut =   598488.  T =     0.16 sec
ABC: A:  Del = 7340.00.  Ar =    7197.0.  Edge =    20112.  Cut =   603372.  T =     0.26 sec
ABC: A:  Del = 7340.00.  Ar =    7121.0.  Edge =    20036.  Cut =   599655.  T =     0.26 sec
ABC: Total time =     1.04 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   5154/    904  and =   16398  lev =   47 (5.75)  mem = 0.53 MB  box = 1369  bb = 1076
ABC: Mapping (K=7)  :  lut =   5019  edge =   19928  lev =   15 (1.92)  levB =   42  mem = 0.26 MB
ABC: LUT = 5019 : 2=494 9.8 %  3=592 11.8 %  4=2876 57.3 %  5=798 15.9 %  6=143 2.8 %  7=116 2.3 %  Ave = 3.97
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 10.96 seconds, total: 10.96 seconds

22.42.42.6. Executing AIGER frontend.
<suppressed ~12205 debug messages>
Removed 21754 unused cells and 48915 unused wires.

22.42.42.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     5044
ABC RESULTS:   $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells:       24
ABC RESULTS:   $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:     1028
ABC RESULTS:   $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      293
ABC RESULTS:   $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:           input signals:     1124
ABC RESULTS:          output signals:      138
Removing temp directory.

22.42.43. Executing TECHMAP pass (map to technology primitives).

22.42.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

22.42.43.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4 for cells of type $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4.
Using template $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4 for cells of type $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4.
Using template $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4 for cells of type $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4.
Using template $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4 for cells of type $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4.
Using template $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4 for cells of type $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4.
Using template $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4 for cells of type $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4.
Using template $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4 for cells of type $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4.
Using template $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4 for cells of type $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4.
Using template $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4 for cells of type $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4.
Using template $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4 for cells of type $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4.
Using template $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4 for cells of type $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4.
Using template $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4 for cells of type $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4.
Using template $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4 for cells of type $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4.
Using template $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4 for cells of type $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4.
Using template $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4 for cells of type $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4.
Using template $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4 for cells of type $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4.
Using template $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4 for cells of type $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4.
Using template $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4 for cells of type $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4.
Using template $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4 for cells of type $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4.
Using template $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4 for cells of type $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4.
Using template $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4 for cells of type $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4.
Using template $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4 for cells of type $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4.
Using template $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4 for cells of type $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4.
Using template $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4 for cells of type $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001000 for cells of type $__ABC9_SCC_BREAKER.
Using template $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$a6a99185e1fedffc87cde4557b06ff4be2d95250\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d6b0e45f4efee955e698060f1331a4646b9f3909\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$9c1eb998868909d5a2ae048ff30751f04b009b72\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$31004c6226af0adba9a5013bab029c2f66d46d93\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$caede141f0115807872e02b8427eb5782ff4d567\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$806e12edc1d882128bd10837d67daf5fed565337\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$02e5e6adf90b3bfe165ed2dd65461baee23d2f29\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2eda5aa2ba7258200740863c7d4919e46b7e1260\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$67bdbac1c829589abee098ed95196513df2eb7b8\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$4a8014b9b59d879d08ba076acefffc2db409de36\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$f477fb84752899c0c13d10270dd1514d0cd358da\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$effd67288d415bd8b2af53bf708e95150afd3681\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$6a767d1ff47b2cab58bd1b3131eaa733ca4d5fc7\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d941cc1f4a0a756fb6a67c22405d0ef5bd4c76c6\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$3ebb853b9dd118c10a5ffb8204501f06a96c2df9\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$25ff5039110cb175d228bc33925b353d56f8021a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$e71a09747771d3fd21ba78d4b6f1a3d5cd00425d\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$fe15ff23ad9b86d22fd5e1c912eb817d5c64a51f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$26e53ceb85125d23708ee73d3e3ad5297a9a3fa2\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$45da04a82449b203872ac158d8676656b764e3d2\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$f40d32d3f62a824248ced7d35c3c2d1f8f2267dd\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$55d13b5a62bdf1421a34a963e4f334335fc67e81\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$73540f2f6149b6cc0fa7a932b6ff9fb4d9e2f6e8\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$107034c68d29476cb9923e27654872763622f33f\TRELLIS_DPR16X4_$abc9_byp.
No more expansions possible.
<suppressed ~2515 debug messages>
Removed 316 unused cells and 78520 unused wires.

22.43. Executing TECHMAP pass (map to technology primitives).

22.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

22.43.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$c70958afe0c33f9a04adee3280f5503846888c70\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$7ec889ba57d2663308885a4e6d8c3dee55c99695\$lut for cells of type $lut.
Using template $paramod$75ae9627805e0c99d176bdce0ae8ff0c02687aab\$lut for cells of type $lut.
Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut.
Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$e0e16f0e69ba9e6596b61d072bd230c598f46f32\$lut for cells of type $lut.
Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d\$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut.
Using template $paramod$d9922e15eb5da1acc26e937540cc16b16c2ad42c\$lut for cells of type $lut.
Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut.
Using template $paramod$83c1b6108170249166239e09804c5f4542556524\$lut for cells of type $lut.
Using template $paramod$32dee08328e8b29c9284c987432b771d306144c4\$lut for cells of type $lut.
Using template $paramod$8e1c82b304528085a78e4651c993ce9e1ef6b8a8\$lut for cells of type $lut.
Using template $paramod$bde6c96e44b0f8e6d9db97eafdf28d77ceaa9a96\$lut for cells of type $lut.
Using template $paramod$73168779d124d0e86f3f4da4f351086f6646bb40\$lut for cells of type $lut.
Using template $paramod$a743caf801766df40bcc22d49baa12a0bdc2f7fe\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$faba0cf60f1c89602d59ba2d491152c8f0d36384\$lut for cells of type $lut.
Using template $paramod$1221ecddf806ed98cf6cee2f2b5a80f38aeb4bee\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod$774a669204184147b38453b69c15da44a7cf748f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut.
Using template $paramod$e8e38e13ba4ca36ee2f40f244789338dfa28acd1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$b5a47d8cbfa131ec0581330a805a294b896377f4\$lut for cells of type $lut.
Using template $paramod$49de9c6586d4afac9224520d21dca4266902474f\$lut for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut.
Using template $paramod$bccf6f63f1f947f8d5a8817f13336731e7c3d1df\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$9a8855b22366cbd3367af17a25fe0def507b1d15\$lut for cells of type $lut.
Using template $paramod$620586420e818d3afa7e5b51fcf19f5c6ea83ad4\$lut for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut.
Using template $paramod$1bbd183b0383643c2e2e2173ffd5fb36a25f1f94\$lut for cells of type $lut.
Using template $paramod$6023c671e114c4eb0467aa8a0b08e183f33ec2fd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut.
Using template $paramod$ccd3e15dc00d71b9284dff48e88ccef5be7362c8\$lut for cells of type $lut.
Using template $paramod$56d1a78632b07077a5fde81946aeef0a806ae664\$lut for cells of type $lut.
Using template $paramod$198f6d63db4ff0ec2340235fead75c9bd1aebcd1\$lut for cells of type $lut.
Using template $paramod$5552b23a89809fed2b1588e8f91bb3893be2e6ce\$lut for cells of type $lut.
Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut.
Using template $paramod$fb7bbfbe62f17d1abd6f8eaee546f5a966c46c29\$lut for cells of type $lut.
Using template $paramod$8bdb7745306e6818fee64745fa19828bf7ad70cf\$lut for cells of type $lut.
Using template $paramod$aab39790b62671319da2ab3f1a143bf90ec3eea7\$lut for cells of type $lut.
Using template $paramod$ee3ba3939f6ccdb74bf420a252d58cdb86511937\$lut for cells of type $lut.
Using template $paramod$489c9c73c2147b125c3fb354aeed1b94c93a65e8\$lut for cells of type $lut.
Using template $paramod$54c2aa49795b98cefbe8e98f3e2a484efde48010\$lut for cells of type $lut.
Using template $paramod$22641603d8fa727856e499ecf3ff9bfa826a5891\$lut for cells of type $lut.
Using template $paramod$1cc93b1b33cd29a0510960887fd944373313728b\$lut for cells of type $lut.
Using template $paramod$f6c21e015fbe9b4df6c2401a87d2ec2bca33f94c\$lut for cells of type $lut.
Using template $paramod$c1b720ec874edd6fc39cce7310f3ee92d6e9d55e\$lut for cells of type $lut.
Using template $paramod$043a5a6e44cd8aa3c9e716e2f57f2e4f94d6e7b4\$lut for cells of type $lut.
Using template $paramod$90dc599eed99da511e64ad217d69e7ff2c1e56cc\$lut for cells of type $lut.
Using template $paramod$f64d959466b1b27921d569605021418d0255a379\$lut for cells of type $lut.
Using template $paramod$af6bfc66edfa832be553173935a94fd15de7c168\$lut for cells of type $lut.
Using template $paramod$240af9a1e3518839ea26843689dc51c451570852\$lut for cells of type $lut.
Using template $paramod$fef639961010220782cb5dc187da065d88f69127\$lut for cells of type $lut.
Using template $paramod$13fa9273f1d4ad6050109d02dc87cffc90450a95\$lut for cells of type $lut.
Using template $paramod$96af7fcf683741387ef6996b3953b5a06c5cffc7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut.
Using template $paramod$0f19b1c588a47c675d00132b243b5e3308ffab5d\$lut for cells of type $lut.
Using template $paramod$38400b76de2b00d7d5f8f09de118b82fd1b8be0a\$lut for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut.
Using template $paramod$800c315b50c56727f5877366081fa1fc315ff6c3\$lut for cells of type $lut.
Using template $paramod$d07b370dde847ff102dfeea99a3d78ed7f287f4e\$lut for cells of type $lut.
Using template $paramod$737669e4d3be4811bcf223101039449bd6e24467\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$7ffc04c088a4897014506d1e561a14b627924059\$lut for cells of type $lut.
Using template $paramod$70f68cc10fbeada9b6fa90c3bb75475e348ca467\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod$609f6931b3d6593b69e4d571a4fdbe0139468ec4\$lut for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$bce98cbc4c7663d9534fcdf870483176065e0cfd\$lut for cells of type $lut.
Using template $paramod$879fd67b160f52e4b579032970cf8abb58ec1d36\$lut for cells of type $lut.
Using template $paramod$90d77ee08e66b421e8ee3e61bd2911be326eefe3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut.
Using template $paramod$0af662e2f4838a57f45fc753edf2aa9f014fd124\$lut for cells of type $lut.
Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut.
Using template $paramod$0a5a9f29eb47b2807f3193c03bd9a8e1d6027644\$lut for cells of type $lut.
Using template $paramod$95dc2852ab6e84fdfb8b1b1839f8f9cac3fb23be\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut.
Using template $paramod$df5c8730c0a53792c3f54c2192a2221c27162fb5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
Using template $paramod$0a7817d70895c67313a5df1d76db8357ea7a02a0\$lut for cells of type $lut.
Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut.
Using template $paramod$0268fc68f2d6e7f87d528d5eecc7c2cd45c533db\$lut for cells of type $lut.
Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707\$lut for cells of type $lut.
Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut.
Using template $paramod$1078665aa144cf7ff525a892db61e5cee078ce7c\$lut for cells of type $lut.
Using template $paramod$8833253c105c1f3ff9a03a20302d6d0a2f4d9c5b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$d7856980c8e3df62f97c26ab34037f33a9e831b5\$lut for cells of type $lut.
Using template $paramod$8e224a63a74b6daf8fc2e441cb0688a65e7a4073\$lut for cells of type $lut.
Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut.
Using template $paramod$9fc14cb0ba5120a1da0c687a9fb19472f206fdfe\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$3db826965e677cc72a454d5e910d68e35d246aa3\$lut for cells of type $lut.
Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut.
Using template $paramod$c07d61aaf1d93e15249de987e8fd0ca391dbd52a\$lut for cells of type $lut.
Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$6c51c1ba6c39f0c09b896d52432b366f116bd3c1\$lut for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut.
Using template $paramod$7e8d331d1e06632d29fbdf6c3afc2de1856d3c67\$lut for cells of type $lut.
Using template $paramod$c97e738df958f490eb8461efe944668c310ecac5\$lut for cells of type $lut.
Using template $paramod$3c17557fcd213346f7b38856ecb30fe49bafcccd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$8384e66d408d22ab39dfb451efb7879731befeb8\$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod$d77ed6ee97ee637e059d4c865314c2fbcd7e2b1c\$lut for cells of type $lut.
Using template $paramod$33844396c65e360198a3f6cab98eb67cf799695c\$lut for cells of type $lut.
Using template $paramod$94e65f323749ab2f501acf5577af42456678fff9\$lut for cells of type $lut.
Using template $paramod$f28c2e49975958241d4d835ef97e799ed72256e5\$lut for cells of type $lut.
Using template $paramod$b4d0f4738a5ce50c7f36c2aa2ecc09cfb874f2b6\$lut for cells of type $lut.
Using template $paramod$7202672b7332febf25cdbe5424cf24593f5449be\$lut for cells of type $lut.
Using template $paramod$394086530b97e2ede4325cfef07483589916f736\$lut for cells of type $lut.
Using template $paramod$2c1875de701f39453798b76f5b327fe456cc0991\$lut for cells of type $lut.
Using template $paramod$deb68ff2e8fd9ff8da03271d1a71173f689317cc\$lut for cells of type $lut.
Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71\$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$9f57c44aff327a056bdf6cc2053e1a9bff5b6300\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$e9863d9c3988af414d2c8995cbddf45c78456af9\$lut for cells of type $lut.
Using template $paramod$6a7ba17da004b5e822ede1582f4eb1a52425caa1\$lut for cells of type $lut.
Using template $paramod$dd95acdea9c10e4d143ea0b05f5efd28d4461683\$lut for cells of type $lut.
Using template $paramod$a82d41f3401352f5e810f04b23be0f37f48ac2f6\$lut for cells of type $lut.
Using template $paramod$af9b16067ef87a0a01d6fe6536bdaa410bc7abc0\$lut for cells of type $lut.
Using template $paramod$b089060a61c5d29ddce66d73edb5ee493ec9de27\$lut for cells of type $lut.
Using template $paramod$d119410bab96963da0139669592048db2c09198b\$lut for cells of type $lut.
Using template $paramod$248033a46ebf6dc76732193c2e311fb0164bb61d\$lut for cells of type $lut.
Using template $paramod$cc2a095eb455a4b3d2a771dcc8d049b19888952d\$lut for cells of type $lut.
Using template $paramod$fbee2e2a9861170f1cb68c75c8a3378effe59a9f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$4da2782c2e024b3eded45331a6607870b9d0254f\$lut for cells of type $lut.
Using template $paramod$fbffc3e42b3faa1e0f4cad085b43900c06168af5\$lut for cells of type $lut.
Using template $paramod$12f84d6ded1d2981ce11b5110688894c9e2d3586\$lut for cells of type $lut.
Using template $paramod$a82b1ace85eb66afc4f8328903689063eb641158\$lut for cells of type $lut.
Using template $paramod$a8b7516c4ccadf4ab65906113028f2819d14ea8b\$lut for cells of type $lut.
Using template $paramod$d5c7dda3e544463bf43ed73dadb51262f5dcf2fe\$lut for cells of type $lut.
Using template $paramod$035b6b6a3626b495f9b67874d98a2122db15ae25\$lut for cells of type $lut.
Using template $paramod$fd3ed3a223484aac184d1b7412ec4cfe4ca64c32\$lut for cells of type $lut.
Using template $paramod$5c79a880ebcfaf6a23810f3d462a8d4512359e14\$lut for cells of type $lut.
Using template $paramod$7da6a3d375590798104e6970494bd85e29d896ab\$lut for cells of type $lut.
Using template $paramod$daa7472b95cb1878c5a9143b00c17cb617d72006\$lut for cells of type $lut.
Using template $paramod$3b374b0454c507d1efadee363d480c52c3b3f58f\$lut for cells of type $lut.
Using template $paramod$d51622885e772dfcea400f263b15aea50e45af9f\$lut for cells of type $lut.
Using template $paramod$b97dea647725901eed851280e5a3889ea3e50a3d\$lut for cells of type $lut.
Using template $paramod$e374f099c1946d555f0a6a12c0ce5d3ec931f9a3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$91835f20beb56819eb0afb0e18869f29b999e46a\$lut for cells of type $lut.
Using template $paramod$d39daf56a31b2e8ce06533aad96ed54894dfed59\$lut for cells of type $lut.
Using template $paramod$50c04e0d9d4d18fa1d48fde34511146cb9a57d39\$lut for cells of type $lut.
Using template $paramod$90418f71a1b3e98f36d147df874dd839b0e31579\$lut for cells of type $lut.
Using template $paramod$a2f01eec25eb92d08608e73046bdb01195b11a42\$lut for cells of type $lut.
Using template $paramod$ee700feb78d1f78a2275689013e0e783764ce7f3\$lut for cells of type $lut.
Using template $paramod$fdb7d2f78b1b1d86177579c82e917e4e8af6f77d\$lut for cells of type $lut.
Using template $paramod$a3a9fa3a508929216557519db89b3e276f6c2b2b\$lut for cells of type $lut.
Using template $paramod$1bb26330f94b9f62b6acb8cc6af86c50c7c3906f\$lut for cells of type $lut.
Using template $paramod$60b99ddfae8ffcebbb1fe7f9e676a60f7472edd5\$lut for cells of type $lut.
Using template $paramod$9851cb11f88bbbf4a516c0595f3b0113b1f100c4\$lut for cells of type $lut.
Using template $paramod$5289dac6f25369a9a495c69c724c25ee83ad0e78\$lut for cells of type $lut.
Using template $paramod$c362ad8dedc7d166ed978091aca319ab1e81a2d4\$lut for cells of type $lut.
Using template $paramod$ef02ea28c4f9766a22068d6502e87f79cf2d9131\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$ea8c3614309befced1c4cfc4249e324e2d77ca4c\$lut for cells of type $lut.
Using template $paramod$fd16523b66efc91890bfb23f6b1dcc83fa36d799\$lut for cells of type $lut.
Using template $paramod$4637f78518a334255f9075a6f84bda1541a68aea\$lut for cells of type $lut.
Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut.
Using template $paramod$afbb78ea2f898aa3cffa65de18f43b6b53d33ce1\$lut for cells of type $lut.
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut.
Using template $paramod$2b47d6f0645f6c0eac4d0fed1097d370ff2ad02d\$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$7da7d7bde408365fd9edb48231a23e665dbb7ed8\$lut for cells of type $lut.
Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e\$lut for cells of type $lut.
Using template $paramod$023d9d13c9ddd8e6cbda8fa49753038bbbacbfa4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$1843b3c15f2447d117e2d5de9b00f791ef5f9fa3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$0278a98173912fa2967bc63171a4195b9cf931a0\$lut for cells of type $lut.
Using template $paramod$70a934594406e8042bf2854c778fef542ef3ea5f\$lut for cells of type $lut.
Using template $paramod$97108e3cc0d0482a6e72e932e86430aa2177750b\$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$8cb91cbdb27a134cadb0a6f504fee8b3a31c5a5c\$lut for cells of type $lut.
Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut.
Using template $paramod$e41a1c3bacff80a48375deebe7952ac964af1315\$lut for cells of type $lut.
Using template $paramod$428455bf683af997b0aced216a36aa68a8816e79\$lut for cells of type $lut.
Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0\$lut for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$04f7bbc226e820bcc7d089b32c7d35bf3a496fd2\$lut for cells of type $lut.
Using template $paramod$8d64e576629e8d7c655e0c65958ea61e649cd93e\$lut for cells of type $lut.
Using template $paramod$e04d88ad99ef3b3a37e50c3d05f39e80a10f1520\$lut for cells of type $lut.
Using template $paramod$9e0d5e3cbbbadb2b139aaae0b912cff38011856c\$lut for cells of type $lut.
Using template $paramod$4db8e9f6768cc0f49eeabffd6db44f73af7ae008\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$56c6fc98268f6966dd23dcb4af9b8f5298fa7ead\$lut for cells of type $lut.
Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000100 for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$5625c0c6def530beb96c16e17997d6d42e5e6d89\$lut for cells of type $lut.
Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$769bdbbde83614df0f4ab5f54e777ded51bb10ce\$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod$d646cd5cb36fb1f9dd2b06f584b3b88b2dec1d24\$lut for cells of type $lut.
Using template $paramod$7d9463029205e00c8cc3ab5e7029e0e3bd30c738\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$e8f04aa93deb6aa077b1364bd7ddec17553d6e97\$lut for cells of type $lut.
Using template $paramod$b34f0e72bf5675ebb8f7a9ba088658d5c50a0625\$lut for cells of type $lut.
Using template $paramod$ba82fb3eadd5cbe40f1451e04a124c85f0c6bc85\$lut for cells of type $lut.
Using template $paramod$2754a21a217ccdc1a0cbf27b2e8b19266cadc23f\$lut for cells of type $lut.
Using template $paramod$3e47095d5e4595d7ab8a4253212381e2a67acff0\$lut for cells of type $lut.
Using template $paramod$4dd4a9d54065b1696fc5e1c7ca18ff772310a315\$lut for cells of type $lut.
Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut.
Using template $paramod$b8113752b08bd47f69a1c8c2bca1cfb157e800c9\$lut for cells of type $lut.
Using template $paramod$20235ca863361fbc253329cfc7eeea38c77404dc\$lut for cells of type $lut.
Using template $paramod$9cc51547ab44a72dd506ee5bb84a864365a103da\$lut for cells of type $lut.
Using template $paramod$c4a4cf1f67c598049dd5cb5cdb183838e000e772\$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$7ed3d685a887e531dc8f4f21b9907d4766cf861f\$lut for cells of type $lut.
Using template $paramod$6e3799a6a01b70fbcc232caaef230f79dc347b39\$lut for cells of type $lut.
Using template $paramod$70a6f8b5e7c26d543ee5df54b2e21d28a007a4bc\$lut for cells of type $lut.
Using template $paramod$f52df4b90f46c2ab9e801e1f39516c9cb1bb6ae7\$lut for cells of type $lut.
Using template $paramod$dff8e7e8854dc948604d9ed7dea9d198697a573d\$lut for cells of type $lut.
Using template $paramod$530e84e711d00ee94a04273b459e87c8d074784e\$lut for cells of type $lut.
Using template $paramod$4e92aaae4d6dc82ec4f0a8579ea7380954206873\$lut for cells of type $lut.
Using template $paramod$91d6743ceb0f093b57d242b538f7f23d2346d4c9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut.
Using template $paramod$74694eae42ad20ffde2b28a68195eb4a58a31695\$lut for cells of type $lut.
Using template $paramod$df77845ebe3e3b565b4a7ed224fe16cf4fddf4c4\$lut for cells of type $lut.
Using template $paramod$09ff6bc38860bc684248b0f5479347794277f7f7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111001 for cells of type $lut.
Using template $paramod$a62a4e75ab45a27922ffbd6dc81aadc18f20928f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011101 for cells of type $lut.
Using template $paramod$1976322b9337edd6ea13def11a60caa0c4fb9f51\$lut for cells of type $lut.
Using template $paramod$b2153d8b4466d4a8f8649eafb88b32b9356a5968\$lut for cells of type $lut.
Using template $paramod$d72b39aae547bf5473b4f5b33fc824040e0dc79c\$lut for cells of type $lut.
Using template $paramod$17087967d5b06f73682a4be57fe09ecae078cdf7\$lut for cells of type $lut.
Using template $paramod$c1a909080ec76944fa258a19c3ca35c98563249f\$lut for cells of type $lut.
Using template $paramod$14f974524b5f147582c86c7d4800b3673d5b8bc5\$lut for cells of type $lut.
Using template $paramod$127d42c61791e2b6b8fd39133e126a67cbdb52bc\$lut for cells of type $lut.
Using template $paramod$cf46a7ee144df3dda17a0bed51b4df2a63f4b081\$lut for cells of type $lut.
Using template $paramod$c7b80ba430fcbff15d6bf260d454531db01b4698\$lut for cells of type $lut.
Using template $paramod$20c02f259989f4e399cea90bda2c52630b09a643\$lut for cells of type $lut.
Using template $paramod$3a2d5a98ab1592b96e36a874f2893a88b535b517\$lut for cells of type $lut.
Using template $paramod$1787073a8d6c9daff7a2f10fc76bfb616dfb4c8e\$lut for cells of type $lut.
Using template $paramod$5a7378348bb6609faf237026d17f16554763e541\$lut for cells of type $lut.
Using template $paramod$2c692825df285188d32c681dfddd915462566b6f\$lut for cells of type $lut.
Using template $paramod$f24ba3ced4b870f8e829f5ac5a8af88573350e6f\$lut for cells of type $lut.
Using template $paramod$2ec6422db00d358fc7469efce6208bffbc8521cd\$lut for cells of type $lut.
Using template $paramod$86336d0ceffef72e4e4eef16a79bb1f71489a34a\$lut for cells of type $lut.
Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod$e760f6dffed78f5decab96fba807f9beded134e1\$lut for cells of type $lut.
Using template $paramod$9c65fdfac74256c2eb67dd209b598e25d1f0a099\$lut for cells of type $lut.
Using template $paramod$3b56205e0e57b3ea26d80fc7983017f83663129e\$lut for cells of type $lut.
Using template $paramod$358458fc9290ec33cf88be5cf5ea4b322cdc8c11\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$2405c96da6619e6393882c62a16149199aaf885f\$lut for cells of type $lut.
Using template $paramod$9d3f1b7ccc10f44d7a470c921f48fc669223bc34\$lut for cells of type $lut.
Using template $paramod$9754422de62e5f46b1224496b225c68aeb5874c2\$lut for cells of type $lut.
Using template $paramod$a5436fdf437daf9262e49985e441d6da280fd8bb\$lut for cells of type $lut.
Using template $paramod$b21af956e406e2b64d24aece260d73818e7c7318\$lut for cells of type $lut.
Using template $paramod$325bb4a8737975ab1a0980ac4dd3572231166eca\$lut for cells of type $lut.
Using template $paramod$b205bd6fb9725b00939a27a901a72b1e096ed83e\$lut for cells of type $lut.
Using template $paramod$5ce0e12212acf3d48f5b3484383857fd34cbaa0b\$lut for cells of type $lut.
Using template $paramod$4a51bea2506d77acaff9190214a54938546c9310\$lut for cells of type $lut.
Using template $paramod$f258f431a7c2fc52205873e71cd6683fdc689824\$lut for cells of type $lut.
Using template $paramod$dc327062330ee79aecc5e2013660e3b5909921a1\$lut for cells of type $lut.
Using template $paramod$dac2b36172bbd20f05e296cffd37b075993d3ab4\$lut for cells of type $lut.
Using template $paramod$3cb61ddb98996dc838245d21b53c60e24f1ca3cc\$lut for cells of type $lut.
Using template $paramod$2e275b44ade5fad054ab9e2853e9673aaf704694\$lut for cells of type $lut.
Using template $paramod$9cf976b4f3a576aa2cd6b51304cf5de7fc836fbd\$lut for cells of type $lut.
Using template $paramod$f9d6cf7b82717ecd056d1083bbabf4567325a5dd\$lut for cells of type $lut.
Using template $paramod$aa68400bf0358909e27b2c6217e56427186cae57\$lut for cells of type $lut.
Using template $paramod$47625e0d44d1185ccf6831eac035c8dd510efc5d\$lut for cells of type $lut.
Using template $paramod$8b2d4da05a775f7705e7bcda27120d70b71d57db\$lut for cells of type $lut.
Using template $paramod$08cdfef047b5b1e16510f02749c0f62c50467dde\$lut for cells of type $lut.
Using template $paramod$de157981d1ff0357ce91bae7484e1779e32fbafd\$lut for cells of type $lut.
Using template $paramod$12aa301644723b08a86cf26ed85bac8fc5d01a8c\$lut for cells of type $lut.
Using template $paramod$9c0ff60f0b33db0b28db7db0e594cd4118d99363\$lut for cells of type $lut.
Using template $paramod$73f837ea3e53430f33d1a454b63163239392c8c1\$lut for cells of type $lut.
Using template $paramod$613206cb40fe42304bed37fbae16c0de71cb0a66\$lut for cells of type $lut.
Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut.
Using template $paramod$4c0221505c29b55a66f4801128a7e9ab143964dc\$lut for cells of type $lut.
Using template $paramod$469e5449f421a6d4ce864b18148ed2a4e2247a7d\$lut for cells of type $lut.
Using template $paramod$41507c1a929bcba96bd65ccd96b53c4157b3b237\$lut for cells of type $lut.
Using template $paramod$53ddbe9035287cc567a5999d375841eba660e8b6\$lut for cells of type $lut.
Using template $paramod$be95f3a2132281eadd1adcfe6229e43dbc3353c9\$lut for cells of type $lut.
Using template $paramod$d0eb1bd038160853fd13d77fd06df2bbca4164fe\$lut for cells of type $lut.
Using template $paramod$efc036109a0594430a1324e0fec30f7cda65a054\$lut for cells of type $lut.
Using template $paramod$6ccc0790b9b01073c0c8ce6283daef323e914803\$lut for cells of type $lut.
Using template $paramod$26df82e1601e8867218520cd443aa8bd7e538772\$lut for cells of type $lut.
Using template $paramod$a88cbe275ca0f24a28b776a3819125328c2b6eb0\$lut for cells of type $lut.
Using template $paramod$90d74b1183382cb8fc2d796fac575c93ebaf4dd8\$lut for cells of type $lut.
Using template $paramod$d76ec2b146b1ed7c1169034b8e7b95141940c193\$lut for cells of type $lut.
Using template $paramod$55c459d0e02f18e159efd3c29a7808240c668886\$lut for cells of type $lut.
Using template $paramod$7fcca76ec7b59d34b2437ba6ff0f23cfef2914c3\$lut for cells of type $lut.
Using template $paramod$f8af7a783767baccc79938dbe6fbfb54437f700b\$lut for cells of type $lut.
Using template $paramod$7f0125821bf1676e1e7a9e160604b043f73a73b2\$lut for cells of type $lut.
Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut.
Using template $paramod$5a67e84fff981e07b6cad46c38d51c9f5329eba7\$lut for cells of type $lut.
Using template $paramod$b38e61f9baff20f8b08cc4b2be7e4d9f7fb4da52\$lut for cells of type $lut.
Using template $paramod$b304cf58995814bfcb142bd23c9043c6fb0fd926\$lut for cells of type $lut.
Using template $paramod$fe0ec6cf52a74b8e9115c7ff11adb77b1122b4e4\$lut for cells of type $lut.
Using template $paramod$4617522c047c473a70c863dc11e360795f3509cb\$lut for cells of type $lut.
Using template $paramod$6382f7860648fdb6f8a8dc690c25a62882cc501b\$lut for cells of type $lut.
Using template $paramod$7ab9990e447a92f0817942e45bfb8b646848e027\$lut for cells of type $lut.
Using template $paramod$8891d1eeef3d8d713e19c7e57dc96930c14ee8df\$lut for cells of type $lut.
Using template $paramod$66fa5f0091ddf0e95fc21f4cc02805ddf33c3024\$lut for cells of type $lut.
Using template $paramod$4f8edd664328039cee7936fba43b73a91069e069\$lut for cells of type $lut.
Using template $paramod$16709c7277a90cf041bff64ab2ca758c41bc27be\$lut for cells of type $lut.
Using template $paramod$312c8bab003b975d614e2bfaf49ff0fa7926f2d1\$lut for cells of type $lut.
Using template $paramod$37bac9dbfeca7057c37e5fd5c0af3364f646bd96\$lut for cells of type $lut.
Using template $paramod$c35ad3063d5038410210ddc72c1fd5fed46413b4\$lut for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut.
Using template $paramod$58c25e2634f0f7e1ddeab945ab08aaf2c35514a7\$lut for cells of type $lut.
Using template $paramod$d510684d5c3b0b3a1a9e37579660fa537554f476\$lut for cells of type $lut.
Using template $paramod$cd6868d2af519fa6cc24514f8efa4b2a1add763a\$lut for cells of type $lut.
Using template $paramod$ec77ef2f39e0c5347eaada9711f26fca6a276050\$lut for cells of type $lut.
Using template $paramod$de2b92d66e62d2468c774d4959d51c030800288f\$lut for cells of type $lut.
Using template $paramod$6b62468353a716e43972563d3074fa328b3ddcae\$lut for cells of type $lut.
Using template $paramod$de97368890ede8e57dda90b22a77a439c105d451\$lut for cells of type $lut.
Using template $paramod$0c8ca179830091c5e617fa87fec5eda52bbb802e\$lut for cells of type $lut.
Using template $paramod$a48d96b3084901aac1f541d9be59ab6aad37df36\$lut for cells of type $lut.
Using template $paramod$5050f70d78e29f4c2caab4bdc486ea89578b2de1\$lut for cells of type $lut.
Using template $paramod$940b33005aafff526c093734cc534afdf7e25fac\$lut for cells of type $lut.
Using template $paramod$728e616c918eb05878d70b2bb240e381ea2847b9\$lut for cells of type $lut.
Using template $paramod$ce889c8d5c07b71200e76d466eeb985864887754\$lut for cells of type $lut.
Using template $paramod$d25b3331c7122041a08ac214d36aecda341cdfa6\$lut for cells of type $lut.
Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut.
Using template $paramod$a082ef5357a6e6f35e787964d27e5026b1c00629\$lut for cells of type $lut.
Using template $paramod$0a88df013769295f3d65f0dd47c099bb258805e8\$lut for cells of type $lut.
Using template $paramod$52941da75a52793ea61fac00dc77d1f0c9714ecd\$lut for cells of type $lut.
Using template $paramod$6be830f9262a68b40d0f25b42a4a698df48aed91\$lut for cells of type $lut.
Using template $paramod$b9f12dba701f3d134861fa586d952f346181c8d5\$lut for cells of type $lut.
Using template $paramod$39b878f1c87901632109d169af51eff5b01a511f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704\$lut for cells of type $lut.
Using template $paramod$5c36a508e8885449eeca65fa0c02b7154f6a3130\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$4834046533425f54583d6bd31e49deb63455e1a5\$lut for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
Using template $paramod$d62f8509c00fbbf0d1da40c84edcad02aef37478\$lut for cells of type $lut.
Using template $paramod$00da6ee835349555028231ae835c9b401a5c1dee\$lut for cells of type $lut.
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut.
Using template $paramod$84c5cfa8d7481774250caab0fcdd6d249a376a31\$lut for cells of type $lut.
Using template $paramod$723be7177967d6866729df0ff463a602326a012e\$lut for cells of type $lut.
Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod$413d040dcd860cd74ca61a70644516a95d328ae7\$lut for cells of type $lut.
Using template $paramod$4ebbf381cf64b08e3304ae8194da41d0cd1eaa92\$lut for cells of type $lut.
Using template $paramod$00621a3c55d483214eef3eec42a14cc6a616135c\$lut for cells of type $lut.
Using template $paramod$1d653d970c0fe76fb8e3619c96f4bfecbdad0308\$lut for cells of type $lut.
Using template $paramod$7d813eb49700f971f2635a434700eafdfa816bc3\$lut for cells of type $lut.
Using template $paramod$2ae22ed255cc0f3746c71b5da2407ee38a2a66e6\$lut for cells of type $lut.
Using template $paramod$a5627e8ad36aa9b4fe2f6188097d151d45fefa8a\$lut for cells of type $lut.
Using template $paramod$3156f2d69ee2a18bf68b5d292ef83b87c67861f2\$lut for cells of type $lut.
Using template $paramod$52fa1b2073b9054923f466bbb768e0ea7c69c9e3\$lut for cells of type $lut.
Using template $paramod$e46703b423a661cd7d311c41833ea655969702cc\$lut for cells of type $lut.
Using template $paramod$037be5c00d8a02858cdb1ab049b58a0133287ff1\$lut for cells of type $lut.
Using template $paramod$57400e123f0147f905d2ec980ae5b64230fc0a43\$lut for cells of type $lut.
Using template $paramod$6e424bd4a747f8421ac946af3d9bb3a47fd0b233\$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut.
Using template $paramod$783a32e06dbe4954dfbf52b07969e74098d1411b\$lut for cells of type $lut.
Using template $paramod$7289316a4306bdfb85f512ed8eda484940498513\$lut for cells of type $lut.
Using template $paramod$2a4b250d89be3556c74aa0e719a4f6242369d42f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut.
Using template $paramod$06fb08c70801e9d845556f8ab61298d2406a9d80\$lut for cells of type $lut.
Using template $paramod$34e326867bb04eb7166eb385de03f3f07fdc4c23\$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut.
Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290\$lut for cells of type $lut.
Using template $paramod$ab910cb79a390aba76b1686e43f5fa50a0dc1ac6\$lut for cells of type $lut.
Using template $paramod$b68f9800cc1bf69afcfbc0567a25e43ebb01456c\$lut for cells of type $lut.
Using template $paramod$9dd298ae76fb41ac94779a83c068607fbc09ce4f\$lut for cells of type $lut.
Using template $paramod$77c2a0573790d304ab2299da6d598e8d2e184867\$lut for cells of type $lut.
Using template $paramod$f546bd96bcec6e3bf1b78bdea64b0f5bbbaff6df\$lut for cells of type $lut.
Using template $paramod$5dc1dd2a2307e3866b2f9a674fd9134301e1466f\$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod$7a1a06469cf74f4b4be6debf13360988e7608d2d\$lut for cells of type $lut.
Using template $paramod$f7a897257decedfb6cc642e53d65fef7fc0df390\$lut for cells of type $lut.
Using template $paramod$e2922126afb3c6df9be8375bf6f36b929cdc98c3\$lut for cells of type $lut.
Using template $paramod$56b959391fb6ba5d14caa92a556be83e259bff64\$lut for cells of type $lut.
Using template $paramod$d4a10f4d68398423b0e46fe25242045c70531988\$lut for cells of type $lut.
Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut.
Using template $paramod$3e895991b845b8c620b8c9e0068c52e372d1fbc1\$lut for cells of type $lut.
Using template $paramod$29e6d4598488760861f6b73d2b7f65cb302fdcde\$lut for cells of type $lut.
Using template $paramod$df29fe9e6d6d694a9cc5697e4251bf7d8cd4d8e4\$lut for cells of type $lut.
Using template $paramod$b66af2b8158579d12b02bd7ae4b5161b219e1924\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$57cf7fbf84518d9e7604ec42b59ba9511e1f3caf\$lut for cells of type $lut.
Using template $paramod$8abe21ee38ced38064203ce27d377b5c4dcd9cc2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111011 for cells of type $lut.
Using template $paramod$adce9c89515a4e83641fc3471eb3c01ec7b082ff\$lut for cells of type $lut.
Using template $paramod$b75e8306635d621cb7e96e5d2ad1327ab1afa025\$lut for cells of type $lut.
Using template $paramod$ee730f1987348ee2ecd88154e663e0a095492078\$lut for cells of type $lut.
Using template $paramod$4e0dac06d9d9602cfb659e01e0850b77eec5b798\$lut for cells of type $lut.
Using template $paramod$c9355c14671e8569b2b55b2828d4fd95591ab987\$lut for cells of type $lut.
Using template $paramod$ab2d8c2b9d8aa7f76721394c261b87284f763090\$lut for cells of type $lut.
Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$fed23357d0c102870fdc9fff85a3f48bb97c4807\$lut for cells of type $lut.
Using template $paramod$21a1ca6f9f5c15b304c8c46ce6cda8b91e063cf1\$lut for cells of type $lut.
Using template $paramod$fe4e24b614c63965c11dc88a1deafdb9e255213c\$lut for cells of type $lut.
Using template $paramod$55f7d9850b8564509bff49b617d7ca817e320dc2\$lut for cells of type $lut.
Using template $paramod$2f2481b7fca4770eaee19e04e3397c2cff19d25c\$lut for cells of type $lut.
Using template $paramod$a7aaa0668a0450b62ae456c748f06a4078603381\$lut for cells of type $lut.
Using template $paramod$f75c7b38d2d3323f79c38414792398adffdc4836\$lut for cells of type $lut.
Using template $paramod$7cf0a5d44d66991d3936d5be60777cdc87502022\$lut for cells of type $lut.
Using template $paramod$afddf753bc06379024ae15bcee2a9be2a1e56428\$lut for cells of type $lut.
Using template $paramod$49f93da3bc72e2487024a93848b25121b5791efb\$lut for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut.
Using template $paramod$b5e4160f46ee05a5659db8a4bfa269190c14ebb2\$lut for cells of type $lut.
Using template $paramod$3258fabf91107b4a007ae89b2246a16c31e8ae28\$lut for cells of type $lut.
Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut.
Using template $paramod$d3be1fc2f0d4e985bc49244552adad1e21f34e88\$lut for cells of type $lut.
Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut.
Using template $paramod$39825c5ed3d135e502be79829033166f1762d78b\$lut for cells of type $lut.
Using template $paramod$424d6e5504f284c1c9fcb89924a2758a91d0d4e2\$lut for cells of type $lut.
Using template $paramod$2e94bd3f26faa1418da468862c21d0f40579ac6d\$lut for cells of type $lut.
Using template $paramod$6de442abe246ff8c0692702d40d84ce1c07479d9\$lut for cells of type $lut.
Using template $paramod$71443dd9ce6d822783b911babf9e9dab228ad54a\$lut for cells of type $lut.
Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut.
Using template $paramod$f405ee362848dd1a47c58160f854302f6ecf95ff\$lut for cells of type $lut.
Using template $paramod$7b733f5b3466ec911060896fccc5c2626cbe3d64\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
Using template $paramod$7328ff5203bb4525167eadf490aae4f747ef08ad\$lut for cells of type $lut.
Using template $paramod$6e3a03c79073e44642e8ed2dab4ee82dfd40dfba\$lut for cells of type $lut.
Using template $paramod$617c9f46425fd7237bd74bd8a02feb7d87fdd1bf\$lut for cells of type $lut.
Using template $paramod$18ac3ef27a3b9646cd1a73a01cd2bd222a2d6e6d\$lut for cells of type $lut.
Using template $paramod$ea74080f8ebc8f3ea8275fd61051fa8e4bd0300d\$lut for cells of type $lut.
Using template $paramod$655e7cdf1fce9923e771969f28446489197085e2\$lut for cells of type $lut.
Using template $paramod$f25cfc29453e54091ece2586f82661c6c404bcba\$lut for cells of type $lut.
Using template $paramod$dc10581988ca640d0fb32ac47d12e56acfff793a\$lut for cells of type $lut.
Using template $paramod$82ed25b11a6a11eb861f4dd3d46f5fc9aa1eebaf\$lut for cells of type $lut.
Using template $paramod$61e71a6b219041f218388451735d309581e08c5a\$lut for cells of type $lut.
Using template $paramod$2f23ee9496edbb044d48f324aa9a472e448048c6\$lut for cells of type $lut.
Using template $paramod$e412821338883e25f2e0d1a1d7fada158db69807\$lut for cells of type $lut.
Using template $paramod$bf8991299172b5d97b8e0448d29fa95793cad69c\$lut for cells of type $lut.
Using template $paramod$72999a7ffa547571d7240ef55378d6675343dc1c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101101 for cells of type $lut.
Using template $paramod$a30576fd1c5042d945ea216dbc9784cd45da020d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut.
Using template $paramod$cd57648d49394fcd9e5dcdaef695452a2ec6eb29\$lut for cells of type $lut.
Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut.
Using template $paramod$787fee9cee5ae31d40349de74edc310e2bfdfc70\$lut for cells of type $lut.
Using template $paramod$6cafb465f31c34f6bb6b9412b7e75000e2a2081c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut.
Using template $paramod$48c19eb209dd8ad2c18334e4df384d3b3b74d5ec\$lut for cells of type $lut.
Using template $paramod$1f6c33323ad6130a71a2bb667b0fdfb99f50281f\$lut for cells of type $lut.
Using template $paramod$3651917fe7dc3a82f0cf3bed65c6cf31a62706f8\$lut for cells of type $lut.
Using template $paramod$ba87c4255c69c22ea2c27ada47be7b450a91f1f8\$lut for cells of type $lut.
Using template $paramod$8f87fd1c60e0e6eacbe12f91c6c6a82b9299ed94\$lut for cells of type $lut.
Using template $paramod$4f6ef5838c139220e91b3d9534b74e9d61193cac\$lut for cells of type $lut.
Using template $paramod$d0cfbfa794431f7e2ccafbbeaaefbd5ed7deeac7\$lut for cells of type $lut.
Using template $paramod$4976b94884fb984911ddd3ea3f74eb965ec3ed53\$lut for cells of type $lut.
Using template $paramod$138253370bae6007e6e519350af9f987329e0b68\$lut for cells of type $lut.
Using template $paramod$2a0e9830506418f5e4c5f66917d75cc61f44d1a8\$lut for cells of type $lut.
Using template $paramod$95e069858cb2e42f0b23620675213cfe73b02fff\$lut for cells of type $lut.
Using template $paramod$7c047b89d420b3ed2898ef0d740ba255e557620d\$lut for cells of type $lut.
Using template $paramod$561d2773f8d56e396c30ee941900c9935428585f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut.
Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$034a69dd110db95ee917f313eafd6833fc6595f9\$lut for cells of type $lut.
Using template $paramod$6eaa285474ca0c16a33be004e48a6a32f35674a1\$lut for cells of type $lut.
Using template $paramod$ec4a21f896d8babdcea50998bb320a7741366e32\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut.
Using template $paramod$863f41f551a5816159b16156be2ce40a67f3ea1f\$lut for cells of type $lut.
Using template $paramod$79c07f33332eb22a8097edbeb83111f7ff1ddc78\$lut for cells of type $lut.
Using template $paramod$c79aec6bf66334ca918f85c196e004c918c371ef\$lut for cells of type $lut.
Using template $paramod$8b24fb07373c4ee224b517e500c9710a464b35dc\$lut for cells of type $lut.
Using template $paramod$00dfa99b7aecc2e72490719b192118cbd6549a2c\$lut for cells of type $lut.
Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26\$lut for cells of type $lut.
Using template $paramod$75020cdf7715bd4a5f7067d80cafc74eabba6a01\$lut for cells of type $lut.
Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$833582361e14b3ee2e66ad676022ab35d7aa7e28\$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$651e836885d95717c36e69441422c3fe04ee5f4d\$lut for cells of type $lut.
Using template $paramod$318ce56045c3ec104fad87e6630922080fac93cc\$lut for cells of type $lut.
Using template $paramod$6a918133ba74318cfa73886b5f460bbb893fa357\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~12033 debug messages>

22.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137910.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137929.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137943.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137905.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137916.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$24476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$22805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$22805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$22805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$22805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$22805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$22774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$22774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$22774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$22120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$22082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$21422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$21422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$21422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$21422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$21422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$21416.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$21013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$21002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$20991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$20663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$20663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$20663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$20663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$20663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$20279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$19272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$18621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$18621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$18614.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[10].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$17936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$17936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$17929.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$17877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$17871.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$17491.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17491.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$16799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$16799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$16799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$16799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$16799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$16470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$16470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$16470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$16470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$16470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$15979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$15927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$15927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$15927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$15927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137834$lut$auto$fsm_map.cc:170:map_fsm$3420[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$15235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.Pc.load.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$15116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$15074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$15074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$15074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$15054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14162.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14162.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138056.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14099.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$13960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$13960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$13960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$13960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$13960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$13960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$13949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$13860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$13785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$13785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$13728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13686.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$13552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$13536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13524.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$13511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$12908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$12472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$12401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$12183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$12183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$12183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$12183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$12183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$12107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12039.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12039.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12039.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12039.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12039.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12006.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12006.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14350.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138141.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$11600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$11575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$11568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138128.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$11690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137924.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137900.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$11511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$11305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11277.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11277.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$11209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$11090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11037.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$11020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$11008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$10990.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$10986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$10964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10515.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$10407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$10892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$10822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$10822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$10789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$10454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$10454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$10438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$10438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12686.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$10438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$10424.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$10438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$10474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10515.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$10523.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$10567.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$10648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$10454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$10712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$10789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10822.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$10878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10878.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10929.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$10460.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$10973.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$10977.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$11015.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$11020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$11037.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11046.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11050.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$11068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$11075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$11037.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$11090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11111.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138095.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11277.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$11305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11346.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$11511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11519.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11575.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11743.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11844.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$13776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11914.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12006.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12011.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$12039.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12039.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12107.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12139.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$12170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$12210.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138130.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$12284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12401.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$12406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12410.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$12424.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12430.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12464.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12472.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$12489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$12646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$12908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17676.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13133.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13310.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13385.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13414.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13477.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$13556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13568.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13584.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13601.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$13608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13620.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$13635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$13635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$13690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13710.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$13728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13737.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13744.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$13851.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$13860.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$13894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13902.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$13949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$13960.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$13971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14005.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14162.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14197.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14222.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14269.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14331.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14340.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14504.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14549.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14642.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14674.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14796.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14817.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$14926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$14935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14975.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$14980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15018.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$15024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$15074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$15074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$15086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$15101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$15101.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$15116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$15276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15467.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15777.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15879.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15907.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$15927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$15969.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$15979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$15985.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$16051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$16464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$16470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16633.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$16640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$16793.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$16799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16806.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16938.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$16989.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$17041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17257.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17412.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$17491.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$17563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17640.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17709.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$17864.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$17922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$17972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$17988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18073.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$18271.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18457.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18508.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$18578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[10].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$18607.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$18644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18798.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18859.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$18866.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$18952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19079.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$19236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$19267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$19272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19278.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$19298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$19305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$19332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$19356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19620.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$19650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19765.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19813.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19820.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$19958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19966.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$19992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20008.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20053.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$20060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$20279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20286.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$20314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20439.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20443.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20476.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20483.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$20587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$20652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$20657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$20663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20754.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20832.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20938.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$20951.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$20991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$21002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21002.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$21058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21221.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$21364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$21393.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$21411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$21422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$21448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21532.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21616.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21695.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21702.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21754.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21834.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$21841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$21995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22021.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$22071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$22076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$22101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$22114.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22133.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22175.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22467.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22483.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$22688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$22774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22874.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$22979.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$23148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$23165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23335.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23415.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$23445.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$23493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23561.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23680.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$23773.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$23810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$23984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$23994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24020.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$24170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24277.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24357.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24476.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24463.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$24542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24592.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24627.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24637.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$24661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24680.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$24997.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25013.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25029.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25057.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25083.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25267.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25335.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25342.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25349.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25498.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$25544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$25576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25608.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$25660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$25677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25711.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$25746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$25799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25855.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25861.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$25892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$25944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25970.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$25993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$26021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$26028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$26038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$26045.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$26081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$26088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$26098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$26114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$26130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$26149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$26165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$26181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$26227.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$auto$fsm_map.cc:170:map_fsm$3420[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.Pc.load.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$20318.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut$aiger137833$17898.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[10].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[11].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut\SOC.Core.Pc.load.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$23133.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137834$lut$aiger137833$24812.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut$aiger137833$25831.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137909.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137913.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137917.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$14357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137928.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137949.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137940.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137965.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$137834$lut\SOC.Core.CSR_Unit.csr_write_data[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138015.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137962.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138058.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138059.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$137950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12016.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138139.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$12128.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11703.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$138150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$137834$lut$aiger137833$11474.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
Removed 0 unused cells and 15322 unused wires.

22.45. Executing AUTONAME pass.
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2028.844 ; gain = 404.715 ; free physical = 2831 ; free virtual = 26676
---------------------------------------------------------------------------------
INFO: [Synth 8-11241] undeclared symbol 'pc_source', assumed default net type 'wire' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:142]
WARNING: [Synth 8-11065] parameter 'SET_DIRECTION' becomes localparam in 'GPIOS' with formal parameter declaration list [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:17]
WARNING: [Synth 8-11065] parameter 'READ' becomes localparam in 'GPIOS' with formal parameter declaration list [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:18]
WARNING: [Synth 8-9400] empty statement in sequential block [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:54]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:17]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:16]
INFO: [Synth 8-6157] synthesizing module 'top' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1]
	Parameter CYCLES bound to: 20 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1]
WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:22]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 3 connections declared, but only 2 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:22]
INFO: [Synth 8-6157] synthesizing module 'Risco_5_SOC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
	Parameter CLOCK_FREQ bound to: 100000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter MEMORY_SIZE bound to: 2048 - type: integer 
	Parameter MEMORY_FILE bound to: ../../software/memory/fpga_test_3.hex - type: string 
	Parameter GPIO_WIDHT bound to: 8 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:1]
	Parameter BOOT_ADDRESS bound to: 0 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'PC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'PC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6157] synthesizing module 'MUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:15]
INFO: [Synth 8-6155] done synthesizing module 'MUX' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1]
INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1]
INFO: [Synth 8-6157] synthesizing module 'Control_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:1]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:152]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:328]
INFO: [Synth 8-6155] done synthesizing module 'Control_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:1]
INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:33]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:10]
INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6157] synthesizing module 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:132]
INFO: [Synth 8-6155] done synthesizing module 'CSR_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
WARNING: [Synth 8-7071] port 'save_pc' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:228]
WARNING: [Synth 8-7071] port 'interrupt_on_hold' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:228]
WARNING: [Synth 8-7023] instance 'CSR_Unit' of module 'CSR_Unit' has 15 connections declared, but only 13 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:228]
INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:1]
WARNING: [Synth 8-7071] port 'halt' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:44]
WARNING: [Synth 8-7071] port 'instruction_request_external' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:44]
WARNING: [Synth 8-7071] port 'instruction_request_timer' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:44]
WARNING: [Synth 8-7071] port 'instruction_request_software' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:44]
WARNING: [Synth 8-7071] port 'instruction_request_fast' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:44]
WARNING: [Synth 8-7023] instance 'Core' of module 'Core' has 14 connections declared, but only 9 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:44]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
	Parameter MEMORY_FILE bound to: ../../software/memory/fpga_test_3.hex - type: string 
	Parameter MEMORY_SIZE bound to: 2048 - type: integer 
INFO: [Synth 8-3876] $readmem data file '../../software/memory/fpga_test_3.hex' is read successfully [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:35]
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
INFO: [Synth 8-6157] synthesizing module 'BUS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6155] done synthesizing module 'BUS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6157] synthesizing module 'LEDs' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6155] done synthesizing module 'LEDs' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
	Parameter CLOCK_FREQ bound to: 100000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
	Parameter DEPTH bound to: 8 - type: integer 
	Parameter WIDTH bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_rx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 100000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_rx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_tx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 100000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_tx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'GPIOS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
	Parameter WIDHT bound to: 8 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'GPIO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIOS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Risco_5_SOC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
WARNING: [Synth 8-3848] Net interrupt_on_hold in module/entity CSR_Unit does not have driver. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:20]
WARNING: [Synth 8-6014] Unused sequential element buffer_full_reg was removed.  [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:49]
WARNING: [Synth 8-6014] Unused sequential element tx_fifo_read_reg was removed.  [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:43]
Renamed 489857 objects in module top (301 iterations).
<suppressed ~18692 debug messages>

22.46. Executing HIERARCHY pass (managing design hierarchy).

22.46.1. Analyzing design hierarchy..
Top module:  \top

22.46.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

22.47. Printing statistics.

=== top ===

   Number of wires:               8701
   Number of wire bits:          24846
   Number of public wires:        8701
   Number of public wire bits:   24846
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              11361
     $_TBUF_                         6
     $scopeinfo                     30
     CCU2C                         293
     L6MUX21                       491
     LUT4                         7084
     PFUMX                        1548
     TRELLIS_DPR16X4              1076
     TRELLIS_FF                    833

22.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

22.49. Executing JSON backend.
WARNING: [Synth 8-7129] Port address[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[4] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[3] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[2] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[16] in module UART is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2116.812 ; gain = 492.684 ; free physical = 2709 ; free virtual = 26565
---------------------------------------------------------------------------------

Warnings: 21 unique messages, 22 total
End of script. Logfile hash: 49293dbcce, CPU: user 13.53s system 0.12s, MEM: 297.16 MB peak
Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)
Time spent: 44% 1x abc9_exe (10 sec), 10% 11x techmap (2 sec), ...
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2134.625 ; gain = 510.496 ; free physical = 2703 ; free virtual = 26562
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2134.625 ; gain = 510.496 ; free physical = 2703 ; free virtual = 26562
---------------------------------------------------------------------------------
[Pipeline] }
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2134.625 ; gain = 0.000 ; free physical = 2974 ; free virtual = 26832
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (NextPNR)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:     14126/43848    32%
Info:         logic LUTs:   7084/43848    16%
Info:         carry LUTs:    586/43848     1%
Info:           RAM LUTs:   4304/ 5481    78%
Info:          RAMW LUTs:   2152/10962    19%

Info:      Total DFFs:       833/43848     1%

Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     331 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x7b980230

Info: Device utilisation:
Info: 	          TRELLIS_IO:    18/  245     7%
Info: 	                DCCA:     1/   56     1%
Info: 	              DP16KD:     0/  108     0%
Info: 	          MULT18X18D:     0/   72     0%
Info: 	              ALU54B:     0/   36     0%
Info: 	             EHXPLLL:     0/    4     0%
Info: 	             EXTREFB:     0/    2     0%
Info: 	                DCUA:     0/    2     0%
Info: 	           PCSCLKDIV:     0/    2     0%
Info: 	             IOLOGIC:     0/  160     0%
Info: 	            SIOLOGIC:     0/   85     0%
Info: 	                 GSR:     0/    1     0%
Info: 	               JTAGG:     0/    1     0%
Info: 	                OSCG:     0/    1     0%
Info: 	               SEDGA:     0/    1     0%
Info: 	                 DTR:     0/    1     0%
Info: 	             USRMCLK:     0/    1     0%
Info: 	             CLKDIVF:     0/    4     0%
Info: 	           ECLKSYNCB:     0/   10     0%
Info: 	             DLLDELD:     0/    8     0%
Info: 	              DDRDLL:     0/    4     0%
Info: 	             DQSBUFM:     0/   10     0%
Info: 	     TRELLIS_ECLKBUF:     0/    8     0%
Info: 	        ECLKBRIDGECS:     0/    2     0%
Info: 	                DCSC:     0/    2     0%
Info: 	          TRELLIS_FF:   833/43848     1%
Info: 	        TRELLIS_COMB: 14210/43848    32%
Info: 	        TRELLIS_RAMW:  1076/ 5481    19%

INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2280.375 ; gain = 0.000 ; free physical = 2652 ; free virtual = 26510
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2280.410 ; gain = 0.000 ; free physical = 2652 ; free virtual = 26510
Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 6650 cells, random placement wirelen = 618541.
Info:     at initial placer iter 0, wirelen = 2103
Info:     at initial placer iter 1, wirelen = 1880
Info:     at initial placer iter 2, wirelen = 2337
Info:     at initial placer iter 3, wirelen = 1858
Info: Running main analytical placer, max placement attempts per cell = 32554380.
Info:     at iteration #1, type ALL: wirelen solved = 2364, spread = 111050, legal = 112178; time = 0.47s
Info:     at iteration #2, type ALL: wirelen solved = 6610, spread = 85114, legal = 86373; time = 0.46s
Info:     at iteration #3, type ALL: wirelen solved = 15233, spread = 72389, legal = 73706; time = 0.51s
Info:     at iteration #4, type ALL: wirelen solved = 19249, spread = 67455, legal = 68761; time = 0.55s
Info:     at iteration #5, type ALL: wirelen solved = 22157, spread = 63740, legal = 65189; time = 0.42s
Info:     at iteration #6, type ALL: wirelen solved = 24645, spread = 64164, legal = 65126; time = 0.44s
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.410 ; gain = 656.281 ; free physical = 2617 ; free virtual = 26475
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.410 ; gain = 656.281 ; free physical = 2617 ; free virtual = 26475
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.410 ; gain = 656.281 ; free physical = 2617 ; free virtual = 26475
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
           RESET_COUNTER |                               00 |                               01
                    IDLE |                               01 |                               10
                    INIT |                               10 |                               00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                   FETCH | 0000000000000000000000000000000000000000000001 |                           000000
                  DECODE | 0000000000000000000000000000000000000000000010 |                           000001
                  MEMADR | 0000000000000000000000000000000000000000000100 |                           000010
       MEMREAD_UNALIGNED | 0000000000000000000000000000000000000000001000 |                           010110
        LOAD_FIRST_BLOCK | 0000000000000000000000000000000000000000010000 |                           010000
        SAVE_FIRST_BLOCK | 0000000000000000000000000000000000000000100000 |                           010001
       CALC_NEXT_ADDRESS | 0000000000000000000000000000000000000001000000 |                           010010
       READ_SECOND_BLOCK | 0000000000000000000000000000000000000010000000 |                           010011
       LOAD_SECOND_BLOCK | 0000000000000000000000000000000000000100000000 |                           010100
            MERGE_BLOCKS | 0000000000000000000000000000000000001000000000 |                           010101
           FILTER_ALU_WB | 0000000000000000000000000000000000010000000000 |                           010111
                 MEMREAD | 0000000000000000000000000000000000100000000000 |                           000011
                   MEMWB | 0000000000000000000000000000000001000000000000 |                           000100
      MEMWRITE_UNALIGNED | 0000000000000000000000000000000010000000000000 |                           011000
  GEN_FIRST_BLOCK_PART_1 | 0000000000000000000000000000000100000000000000 |                           011001
  GEN_FIRST_BLOCK_PART_2 | 0000000000000000000000000000001000000000000000 |                           011010
 GEN_SECOND_BLOCK_PART_1 | 0000000000000000000000000000010000000000000000 |                           011011
 GEN_SECOND_BLOCK_PART_2 | 0000000000000000000000000000100000000000000000 |                           011100
      MERGE_WRITE_BLOCKS | 0000000000000000000000000001000000000000000000 |                           011101
    SWAP_VALUE_DIRECTION | 0000000000000000000000000010000000000000000000 |                           011110
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK | 0000000000000000000000000100000000000000000000 |                           100010
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_2 | 0000000000000000000000001000000000000000000000 |                           100011
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_3 | 0000000000000000000000010000000000000000000000 |                           100100
             CLEAR_VALUE | 0000000000000000000000100000000000000000000000 |                           011111
     MERGE_WRITE_VALUE_1 | 0000000000000000000001000000000000000000000000 |                           100000
           WRITE_VALUE_1 | 0000000000000000000010000000000000000000000000 |                           100001
CALC_SECOND_BLOCK_ADDRESS_TO_WRITE | 0000000000000000000100000000000000000000000000 |                           100101
READ_SECOND_BLOCK_TO_WRITE | 0000000000000000001000000000000000000000000000 |                           100110
LOAD_SECOND_BLOCK_TO_WRITE | 0000000000000000010000000000000000000000000000 |                           100111
LOAD_SECOND_BLOCK_TO_WRITE_2 | 0000000000000000100000000000000000000000000000 |                           101000
  SWAP_VALUE_DIRECTION_2 | 0000000000000001000000000000000000000000000000 |                           101001
      CLEAR_VALUE_PART_2 | 0000000000000010000000000000000000000000000000 |                           101010
    CLEAR_VALUE_PART_2_1 | 0000000000000100000000000000000000000000000000 |                           101011
     MERGE_WRITE_VALUE_2 | 0000000000001000000000000000000000000000000000 |                           101100
           WRITE_VALUE_2 | 0000000000010000000000000000000000000000000000 |                           101101
                MEMWRITE | 0000000000100000000000000000000000000000000000 |                           000101
                EXECUTER | 0000000001000000000000000000000000000000000000 |                           000110
                EXECUTEI | 0000000010000000000000000000000000000000000000 |                           001000
                     JAL | 0000000100000000000000000000000000000000000000 |                           001001
                     BEQ | 0000001000000000000000000000000000000000000000 |                           001010
                   AUIPC | 0000010000000000000000000000000000000000000000 |                           001100
                     LUI | 0000100000000000000000000000000000000000000000 |                           001101
                 JALR_PC | 0001000000000000000000000000000000000000000000 |                           001110
                    JALR | 0010000000000000000000000000000000000000000000 |                           001011
                   ALUWB | 0100000000000000000000000000000000000000000000 |                           000111
              EXECUTECSR | 1000000000000000000000000000000000000000000000 |                           001111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
WARNING: [Synth 8-327] inferring latch for variable 'aluop_out_reg' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:12]
Info:     at iteration #7, type ALL: wirelen solved = 28242, spread = 63554, legal = 64785; time = 0.53s
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_RECV |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_SEND |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2280.410 ; gain = 656.281 ; free physical = 2608 ; free virtual = 26467
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input   32 Bit       Adders := 1     
	   3 Input   32 Bit       Adders := 1     
	   2 Input   11 Bit       Adders := 2     
	   2 Input    6 Bit       Adders := 4     
	   2 Input    5 Bit       Adders := 1     
	   2 Input    4 Bit       Adders := 2     
	   2 Input    3 Bit       Adders := 1     
	   2 Input    2 Bit       Adders := 1     
+---XORs : 
	   2 Input     32 Bit         XORs := 1     
+---XORs : 
	                2 Bit    Wide XORs := 1     
+---Registers : 
	               33 Bit    Registers := 1     
	               32 Bit    Registers := 48    
	               16 Bit    Registers := 2     
	               11 Bit    Registers := 2     
	                8 Bit    Registers := 8     
	                6 Bit    Registers := 1     
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 19    
+---RAMs : 
	              16K Bit	(512 X 32 bit)          RAMs := 1     
	               64 Bit	(8 X 8 bit)          RAMs := 2     
+---Muxes : 
	  46 Input   46 Bit        Muxes := 1     
	   2 Input   46 Bit        Muxes := 17    
	  11 Input   46 Bit        Muxes := 1     
	   3 Input   33 Bit        Muxes := 1     
	   2 Input   32 Bit        Muxes := 35    
	   8 Input   32 Bit        Muxes := 1     
	   4 Input   32 Bit        Muxes := 13    
	  16 Input   32 Bit        Muxes := 1     
	   6 Input   32 Bit        Muxes := 1     
	   2 Input    8 Bit        Muxes := 3     
	   5 Input    8 Bit        Muxes := 1     
	   3 Input    6 Bit        Muxes := 1     
	   2 Input    6 Bit        Muxes := 4     
	   2 Input    5 Bit        Muxes := 1     
	  46 Input    4 Bit        Muxes := 1     
	  10 Input    4 Bit        Muxes := 1     
	   8 Input    4 Bit        Muxes := 1     
	  23 Input    4 Bit        Muxes := 1     
	   2 Input    4 Bit        Muxes := 1     
	   5 Input    3 Bit        Muxes := 1     
	   2 Input    3 Bit        Muxes := 3     
	   4 Input    3 Bit        Muxes := 2     
	  46 Input    3 Bit        Muxes := 3     
	  10 Input    3 Bit        Muxes := 1     
	   3 Input    2 Bit        Muxes := 1     
	   2 Input    2 Bit        Muxes := 14    
	  46 Input    2 Bit        Muxes := 2     
	   4 Input    2 Bit        Muxes := 4     
	   3 Input    1 Bit        Muxes := 6     
	   2 Input    1 Bit        Muxes := 49    
	  46 Input    1 Bit        Muxes := 12    
	   4 Input    1 Bit        Muxes := 2     
	  13 Input    1 Bit        Muxes := 2     
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
Info:     at iteration #8, type ALL: wirelen solved = 30431, spread = 59888, legal = 61354; time = 0.59s
Info:     at iteration #9, type ALL: wirelen solved = 29550, spread = 61457, legal = 62811; time = 0.40s
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
Info:     at iteration #10, type ALL: wirelen solved = 32697, spread = 60250, legal = 61407; time = 0.43s
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template. 
Info:     at iteration #11, type ALL: wirelen solved = 33684, spread = 58714, legal = 60218; time = 0.43s
Info:     at iteration #12, type ALL: wirelen solved = 34958, spread = 56540, legal = 58186; time = 0.57s
Info:     at iteration #13, type ALL: wirelen solved = 34950, spread = 57063, legal = 58599; time = 0.41s
Info:     at iteration #14, type ALL: wirelen solved = 35677, spread = 57793, legal = 59369; time = 0.40s
Info:     at iteration #15, type ALL: wirelen solved = 36995, spread = 57171, legal = 58542; time = 0.41s
Info:     at iteration #16, type ALL: wirelen solved = 37639, spread = 56017, legal = 57446; time = 0.47s
Info:     at iteration #17, type ALL: wirelen solved = 37632, spread = 55425, legal = 56777; time = 0.51s
Info:     at iteration #18, type ALL: wirelen solved = 37670, spread = 55666, legal = 57061; time = 0.40s
Info:     at iteration #19, type ALL: wirelen solved = 38213, spread = 56197, legal = 57620; time = 0.41s
Info:     at iteration #20, type ALL: wirelen solved = 38942, spread = 55813, legal = 57193; time = 0.41s
Info:     at iteration #21, type ALL: wirelen solved = 39393, spread = 55549, legal = 56885; time = 0.57s
Info:     at iteration #22, type ALL: wirelen solved = 39320, spread = 53417, legal = 55274; time = 0.41s
Info:     at iteration #23, type ALL: wirelen solved = 38176, spread = 54253, legal = 55715; time = 0.40s
Info:     at iteration #24, type ALL: wirelen solved = 39128, spread = 54484, legal = 55781; time = 0.40s
Info:     at iteration #25, type ALL: wirelen solved = 39725, spread = 54886, legal = 56215; time = 0.51s
Info:     at iteration #26, type ALL: wirelen solved = 39569, spread = 53314, legal = 54940; time = 0.50s
Info:     at iteration #27, type ALL: wirelen solved = 39277, spread = 53320, legal = 54981; time = 0.41s
Info:     at iteration #28, type ALL: wirelen solved = 40208, spread = 53428, legal = 54905; time = 0.41s
Info:     at iteration #29, type ALL: wirelen solved = 40367, spread = 52961, legal = 54558; time = 0.42s
Info:     at iteration #30, type ALL: wirelen solved = 40439, spread = 53217, legal = 54808; time = 0.55s
Info:     at iteration #31, type ALL: wirelen solved = 40927, spread = 53210, legal = 54679; time = 0.39s
Info:     at iteration #32, type ALL: wirelen solved = 40860, spread = 53013, legal = 54449; time = 0.42s
Info:     at iteration #33, type ALL: wirelen solved = 41453, spread = 52720, legal = 54273; time = 0.39s
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN  (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":226)
WARN  (NL0002) : The module "MUX" instantiated to "MemoryAddressMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":100)
WARN  (NL0002) : The module "MUX" instantiated to "PCSourceMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":152)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
[95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
[100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg"
Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Processing netlist completed
Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst"
Physical Constraint parsed completed
Running placement......
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2280.410 ; gain = 656.281 ; free physical = 2513 ; free virtual = 26382
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object                  | Inference | Size (Depth x Width) | Primitives      | 
+------------+-----------------------------+-----------+----------------------+-----------------+
|top         | SOC/Memory/memory_reg       | Implied   | 512 x 32             | RAM256X1S x 64  | 
|top         | SOC/Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
|top         | SOC/Uart/TX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
+------------+-----------------------------+-----------+----------------------+-----------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Info:     at iteration #34, type ALL: wirelen solved = 40951, spread = 52813, legal = 54361; time = 0.56s
Info:     at iteration #35, type ALL: wirelen solved = 41553, spread = 52757, legal = 54288; time = 0.39s
Info:     at iteration #36, type ALL: wirelen solved = 41332, spread = 52786, legal = 54300; time = 0.39s
Info:     at iteration #37, type ALL: wirelen solved = 41633, spread = 52409, legal = 53965; time = 0.39s
Info:     at iteration #38, type ALL: wirelen solved = 41241, spread = 52308, legal = 53818; time = 0.42s
Info:     at iteration #39, type ALL: wirelen solved = 41401, spread = 52342, legal = 53814; time = 0.53s
Info:     at iteration #40, type ALL: wirelen solved = 41599, spread = 52485, legal = 54023; time = 0.39s
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2280.410 ; gain = 656.281 ; free physical = 2504 ; free virtual = 26374
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
Info:     at iteration #41, type ALL: wirelen solved = 41599, spread = 52489, legal = 53976; time = 0.39s
Info:     at iteration #42, type ALL: wirelen solved = 41973, spread = 52299, legal = 53672; time = 0.40s
Info:     at iteration #43, type ALL: wirelen solved = 41947, spread = 52338, legal = 53918; time = 0.56s
[10%] Placement Phase 0 completed
Info:     at iteration #44, type ALL: wirelen solved = 42085, spread = 52658, legal = 54122; time = 0.40s
Info:     at iteration #45, type ALL: wirelen solved = 42267, spread = 52298, legal = 53852; time = 0.39s
[20%] Placement Phase 1 completed
Info:     at iteration #46, type ALL: wirelen solved = 42117, spread = 52661, legal = 53961; time = 0.39s
Info:     at iteration #47, type ALL: wirelen solved = 42365, spread = 52188, legal = 53611; time = 0.41s
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2280.410 ; gain = 656.281 ; free physical = 2426 ; free virtual = 26296
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object                  | Inference | Size (Depth x Width) | Primitives      | 
+------------+-----------------------------+-----------+----------------------+-----------------+
|top         | SOC/Memory/memory_reg       | Implied   | 512 x 32             | RAM256X1S x 64  | 
|top         | SOC/Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
|top         | SOC/Uart/TX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
+------------+-----------------------------+-----------+----------------------+-----------------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
Info:     at iteration #48, type ALL: wirelen solved = 42317, spread = 52270, legal = 53559; time = 0.53s
Info:     at iteration #49, type ALL: wirelen solved = 42693, spread = 52194, legal = 53551; time = 0.39s
Info:     at iteration #50, type ALL: wirelen solved = 42693, spread = 52057, legal = 53513; time = 0.39s
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2280.410 ; gain = 656.281 ; free physical = 2416 ; free virtual = 26286
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
Info:     at iteration #51, type ALL: wirelen solved = 42781, spread = 54039, legal = 55366; time = 0.40s
Info:     at iteration #52, type ALL: wirelen solved = 43983, spread = 53864, legal = 55466; time = 0.57s
Info:     at iteration #53, type ALL: wirelen solved = 42966, spread = 52527, legal = 54338; time = 0.39s
Info:     at iteration #54, type ALL: wirelen solved = 43589, spread = 52271, legal = 53899; time = 0.41s
Info: HeAP Placer Time: 35.97s
Info:   of which solving equations: 20.65s
Info:   of which spreading cells: 2.93s
Info:   of which strict legalisation: 0.81s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 20362, wirelen = 53513
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:48 ; elapsed = 00:00:48 . Memory (MB): peak = 2280.410 ; gain = 656.281 ; free physical = 2303 ; free virtual = 26173
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:48 ; elapsed = 00:00:48 . Memory (MB): peak = 2280.410 ; gain = 656.281 ; free physical = 2303 ; free virtual = 26173
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:48 ; elapsed = 00:00:48 . Memory (MB): peak = 2280.410 ; gain = 656.281 ; free physical = 2303 ; free virtual = 26173
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:48 ; elapsed = 00:00:48 . Memory (MB): peak = 2280.410 ; gain = 656.281 ; free physical = 2303 ; free virtual = 26173
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 2280.410 ; gain = 656.281 ; free physical = 2303 ; free virtual = 26173
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 2280.410 ; gain = 656.281 ; free physical = 2303 ; free virtual = 26173
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+----------+------+
|      |Cell      |Count |
+------+----------+------+
|1     |BUFG      |     2|
|2     |CARRY4    |    55|
|3     |LUT1      |    15|
|4     |LUT2      |   167|
|5     |LUT3      |   245|
|6     |LUT4      |   294|
|7     |LUT5      |   440|
|8     |LUT6      |  1451|
|9     |MUXF7     |   387|
|10    |MUXF8     |    28|
|11    |RAM256X1S |    64|
|12    |RAM32M    |     2|
|13    |RAM32X1D  |     4|
|14    |FDRE      |  1871|
|15    |FDSE      |     5|
|16    |LD        |     4|
|17    |IBUF      |     2|
|18    |OBUF      |     9|
|19    |OBUFT     |     8|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 2280.410 ; gain = 656.281 ; free physical = 2303 ; free virtual = 26173
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 44 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 2280.410 ; gain = 510.496 ; free physical = 2303 ; free virtual = 26173
Synthesis Optimization Complete : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 2280.410 ; gain = 656.281 ; free physical = 2303 ; free virtual = 26173
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2280.410 ; gain = 0.000 ; free physical = 2569 ; free virtual = 26439
INFO: [Netlist 29-17] Analyzing 544 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2352.406 ; gain = 0.000 ; free physical = 2562 ; free virtual = 26431
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 74 instances were transformed.
  LD => LDCE: 4 instances
  RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances

Synth Design complete | Checksum: 9a768a6
INFO: [Common 17-83] Releasing license: Synthesis
75 Infos, 121 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:00:55 . Memory (MB): peak = 2352.441 ; gain = 1035.352 ; free physical = 2562 ; free virtual = 26431
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2021.187; main = 1756.836; forked = 423.232
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3218.020; main = 2352.410; forked = 969.656
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors, 8 Warnings
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.74 . Memory (MB): peak = 2416.438 ; gain = 63.996 ; free physical = 2562 ; free virtual = 26431

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1bbc9ccb5

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2522.250 ; gain = 105.812 ; free physical = 2508 ; free virtual = 26378
Info:   at iteration #5: temp = 0.000000, timing cost = 21951, wirelen = 47997

Starting Logic Optimization Task

Phase 1 Initialization

Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 1bbc9ccb5

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2769.188 ; gain = 0.000 ; free physical = 2233 ; free virtual = 26103

Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1bbc9ccb5

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2769.188 ; gain = 0.000 ; free physical = 2233 ; free virtual = 26103
Phase 1 Initialization | Checksum: 1bbc9ccb5

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2769.188 ; gain = 0.000 ; free physical = 2233 ; free virtual = 26103

Phase 2 Timer Update And Timing Data Collection

Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 1bbc9ccb5

Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2769.188 ; gain = 0.000 ; free physical = 2233 ; free virtual = 26103

Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 1bbc9ccb5

Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2769.188 ; gain = 0.000 ; free physical = 2233 ; free virtual = 26103
Phase 2 Timer Update And Timing Data Collection | Checksum: 1bbc9ccb5

Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2769.188 ; gain = 0.000 ; free physical = 2233 ; free virtual = 26103

Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 1 inverters resulting in an inversion of 4 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 29873a049

Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2769.188 ; gain = 0.000 ; free physical = 2233 ; free virtual = 26103
Retarget | Checksum: 29873a049
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 9 cells

Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 29873a049

Time (s): cpu = 00:00:00.35 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2769.188 ; gain = 0.000 ; free physical = 2233 ; free virtual = 26103
Constant propagation | Checksum: 29873a049
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 5 Sweep
Phase 5 Sweep | Checksum: 20271f92d

Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2769.188 ; gain = 0.000 ; free physical = 2233 ; free virtual = 26103
Sweep | Checksum: 20271f92d
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 1 cells

Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 20271f92d

Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2801.203 ; gain = 32.016 ; free physical = 2233 ; free virtual = 26102
BUFG optimization | Checksum: 20271f92d
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 20271f92d

Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2801.203 ; gain = 32.016 ; free physical = 2233 ; free virtual = 26102
Shift Register Optimization | Checksum: 20271f92d
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 26b3a7663

Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2801.203 ; gain = 32.016 ; free physical = 2233 ; free virtual = 26102
Post Processing Netlist | Checksum: 26b3a7663
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells

Phase 9 Finalization

Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 295e54300

Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2801.203 ; gain = 32.016 ; free physical = 2233 ; free virtual = 26102

Phase 9.2 Verifying Netlist Connectivity

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2801.203 ; gain = 0.000 ; free physical = 2233 ; free virtual = 26102
Phase 9.2 Verifying Netlist Connectivity | Checksum: 295e54300

Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2801.203 ; gain = 32.016 ; free physical = 2233 ; free virtual = 26102
Phase 9 Finalization | Checksum: 295e54300

Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2801.203 ; gain = 32.016 ; free physical = 2233 ; free virtual = 26102
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |               9  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               8  |               1  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------


Ending Logic Optimization Task | Checksum: 295e54300

Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2801.203 ; gain = 32.016 ; free physical = 2233 ; free virtual = 26102
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2801.203 ; gain = 0.000 ; free physical = 2233 ; free virtual = 26102

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 295e54300

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2801.203 ; gain = 0.000 ; free physical = 2233 ; free virtual = 26102

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 295e54300

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2801.203 ; gain = 0.000 ; free physical = 2233 ; free virtual = 26102

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2801.203 ; gain = 0.000 ; free physical = 2233 ; free virtual = 26102
Ending Netlist Obfuscation Task | Checksum: 295e54300

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2801.203 ; gain = 0.000 ; free physical = 2233 ; free virtual = 26102
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2801.203 ; gain = 448.762 ; free physical = 2233 ; free virtual = 26102
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 8 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2833.219 ; gain = 0.000 ; free physical = 2231 ; free virtual = 26101
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1d00b5f36

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2833.219 ; gain = 0.000 ; free physical = 2231 ; free virtual = 26101
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2833.219 ; gain = 0.000 ; free physical = 2231 ; free virtual = 26101

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b25fb3a0

Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.78 . Memory (MB): peak = 2833.219 ; gain = 0.000 ; free physical = 2191 ; free virtual = 26060

Phase 1.3 Build Placer Netlist Model
[30%] Placement Phase 2 completed
Phase 1.3 Build Placer Netlist Model | Checksum: e661f65d

Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2185 ; free virtual = 26055

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: e661f65d

Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2185 ; free virtual = 26055
Phase 1 Placer Initialization | Checksum: e661f65d

Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2185 ; free virtual = 26055

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 11e037c0f

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2182 ; free virtual = 26052

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 155c6d0a1

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2182 ; free virtual = 26052

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 155c6d0a1

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2182 ; free virtual = 26052

Phase 2.4 Global Placement Core

Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 197850230

Time (s): cpu = 00:00:15 ; elapsed = 00:00:05 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2160 ; free virtual = 26030

Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 68 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 29 nets or LUTs. Breaked 0 LUT, combined 29 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2168 ; free virtual = 26038

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            0  |             29  |                    29  |           0  |           1  |  00:00:00  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            0  |             29  |                    29  |           0  |           4  |  00:00:00  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.2 Physical Synthesis In Placer | Checksum: 9a4b326a

Time (s): cpu = 00:00:15 ; elapsed = 00:00:05 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2168 ; free virtual = 26038
Phase 2.4 Global Placement Core | Checksum: 89355008

Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2168 ; free virtual = 26037
Phase 2 Global Placement | Checksum: 89355008

Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2168 ; free virtual = 26037

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 10281d1bd

Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2167 ; free virtual = 26037

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: e6768742

Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2167 ; free virtual = 26037

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 17ab67479

Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2167 ; free virtual = 26036

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 162002af2

Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2167 ; free virtual = 26036

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 141baaea6

Time (s): cpu = 00:00:22 ; elapsed = 00:00:08 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2168 ; free virtual = 26038

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 10950e876

Time (s): cpu = 00:00:22 ; elapsed = 00:00:08 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2168 ; free virtual = 26038

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 103172eff

Time (s): cpu = 00:00:22 ; elapsed = 00:00:08 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2168 ; free virtual = 26038
Phase 3 Detail Placement | Checksum: 103172eff

Time (s): cpu = 00:00:22 ; elapsed = 00:00:08 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2168 ; free virtual = 26038

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: fe2fae3c

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.882 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 1bbb49bf2

Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2168 ; free virtual = 26038
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 1bbb49bf2

Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.2 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2168 ; free virtual = 26038
Phase 4.1.1.1 BUFG Insertion | Checksum: fe2fae3c

Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2168 ; free virtual = 26038

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.882. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1047be65b

Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2168 ; free virtual = 26038

Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2168 ; free virtual = 26038
Phase 4.1 Post Commit Optimization | Checksum: 1047be65b

Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2168 ; free virtual = 26038

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1047be65b

Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2168 ; free virtual = 26038

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                2x2|
|___________|___________________|___________________|
|      South|                1x1|                1x1|
|___________|___________________|___________________|
|       East|                1x1|                1x1|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 1047be65b

Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2168 ; free virtual = 26038
Phase 4.3 Placer Reporting | Checksum: 1047be65b

Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2166 ; free virtual = 26035

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2165 ; free virtual = 26035

Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2165 ; free virtual = 26035
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18ed22daf

Time (s): cpu = 00:00:26 ; elapsed = 00:00:09 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2160 ; free virtual = 26030
Ending Placer Task | Checksum: 18030ff7c

Time (s): cpu = 00:00:26 ; elapsed = 00:00:09 . Memory (MB): peak = 2840.246 ; gain = 7.027 ; free physical = 2157 ; free virtual = 26027
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:10 . Memory (MB): peak = 2840.246 ; gain = 39.043 ; free physical = 2156 ; free virtual = 26026
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
report_io: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2161 ; free virtual = 26031
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2159 ; free virtual = 26029
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
Info:   at iteration #10: temp = 0.000000, timing cost = 21482, wirelen = 46500
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs

Phase 1 Build RT Design
Checksum: PlaceDB: ac1bb603 ConstDB: 0 ShapeSum: d4154979 RouteDB: 0
Info:   at iteration #15: temp = 0.000000, timing cost = 21263, wirelen = 45941
[50%] Placement Phase 3 completed
Running routing......
Info:   at iteration #20: temp = 0.000000, timing cost = 19871, wirelen = 45746
[60%] Routing Phase 0 completed
Info:   at iteration #23: temp = 0.000000, timing cost = 19494, wirelen = 45683 
Info: SA placement time 45.07s

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 27.05 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.60 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 9.32 ns

Info: Slack histogram:
Info:  legend: * represents 169 endpoint(s)
Info:          + represents [1,169) endpoint(s)
Info: [  3037,   4848) |+
Info: [  4848,   6659) |**+
Info: [  6659,   8470) |*****+
Info: [  8470,  10281) |***+
Info: [ 10281,  12092) |+
Info: [ 12092,  13903) |*+
Info: [ 13903,  15714) |***********+
Info: [ 15714,  17525) |*******************+
Info: [ 17525,  19336) |************************************************************ 
Info: [ 19336,  21147) |*****************************************+
Info: [ 21147,  22958) |**+
Info: [ 22958,  24769) |*+
Info: [ 24769,  26580) |+
Info: [ 26580,  28391) |***+
Info: [ 28391,  30202) |*+
Info: [ 30202,  32013) |+
Info: [ 32013,  33824) |*+
Info: [ 33824,  35635) |**+
Info: [ 35635,  37446) |*+
Info: [ 37446,  39257) |*+
Info: Checksum: 0x5c775faa
Info: Routing globals...
Info:     routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0

Info: Routing..
Info: Setting up routing queue.
Info: Routing 70113 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |      216        783 |  216   783 |     69519|       1.36       1.36|
Info:       2000 |      371       1628 |  155   845 |     68937|       0.40       1.76|
Info:       3000 |      541       2458 |  170   830 |     68875|       0.37       2.13|
Info:       4000 |      697       3302 |  156   844 |     68860|       0.35       2.48|
Info:       5000 |      819       4180 |  122   878 |     68477|       0.35       2.83|
[70%] Routing Phase 1 completed
Info:       6000 |     1038       4961 |  219   781 |     68267|       0.42       3.25|
Info:       7000 |     1147       5852 |  109   891 |     67621|       0.43       3.68|
Info:       8000 |     1276       6723 |  129   871 |     66905|       0.50       4.18|
Info:       9000 |     1422       7577 |  146   854 |     67030|       0.53       4.71|
Info:      10000 |     1546       8453 |  124   876 |     66405|       0.61       5.32|
Info:      11000 |     1672       9327 |  126   874 |     66208|       0.49       5.81|
Info:      12000 |     1781      10218 |  109   891 |     65584|       0.67       6.48|
Info:      13000 |     1907      11092 |  126   874 |     65045|       0.58       7.05|
Info:      14000 |     2037      11962 |  130   870 |     64412|       0.47       7.52|
Info:      15000 |     2194      12805 |  157   843 |     63915|       0.37       7.89|
Post Restoration Checksum: NetGraph: 5ae7c01f | NumContArr: 756a9276 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 255a447cf

Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2076 ; free virtual = 25946

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 255a447cf

Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2076 ; free virtual = 25946

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 255a447cf

Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2076 ; free virtual = 25946
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 14dbaa9cc

Time (s): cpu = 00:00:39 ; elapsed = 00:00:30 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2046 ; free virtual = 25916
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797  | TNS=0.000  | WHS=0.008  | THS=0.000  |


Router Utilization Summary
  Global Vertical Routing Utilization    = 0.000304652 %
  Global Horizontal Routing Utilization  = 0.000213129 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 3784
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 3780
  Number of Partially Routed Nets     = 4
  Number of Node Overlaps             = 1

Phase 2 Router Initialization | Checksum: 1b34de596

Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2042 ; free virtual = 25912

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 1b34de596

Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2042 ; free virtual = 25912

Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 17b265583

Time (s): cpu = 00:00:43 ; elapsed = 00:00:31 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2042 ; free virtual = 25912
Phase 3 Initial Routing | Checksum: 17b265583

Time (s): cpu = 00:00:43 ; elapsed = 00:00:31 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2042 ; free virtual = 25912

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 537
 Number of Nodes with overlaps = 8
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.540  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 28d88d834

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2038 ; free virtual = 25908
Phase 4 Rip-up And Reroute | Checksum: 28d88d834

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2038 ; free virtual = 25908

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 28d88d834

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2037 ; free virtual = 25907

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 28d88d834

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2037 ; free virtual = 25907
Phase 5 Delay and Skew Optimization | Checksum: 28d88d834

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2037 ; free virtual = 25907

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 2edf1f0a2

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2040 ; free virtual = 25910
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.636  | TNS=0.000  | WHS=0.364  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 2edf1f0a2

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2039 ; free virtual = 25910
Phase 6 Post Hold Fix | Checksum: 2edf1f0a2

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2039 ; free virtual = 25909

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.817905 %
  Global Horizontal Routing Utilization  = 1.00945 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 2edf1f0a2

Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2045 ; free virtual = 25915

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 2edf1f0a2

Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2045 ; free virtual = 25915

Phase 9 Depositing Routes
Info:      16000 |     2374      13625 |  180   820 |     63407|       0.52       8.41|
Info:      17000 |     2523      14476 |  149   851 |     63034|       0.48       8.89|
Phase 9 Depositing Routes | Checksum: 337bde8f8

Time (s): cpu = 00:00:47 ; elapsed = 00:00:33 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2043 ; free virtual = 25914

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.636  | TNS=0.000  | WHS=0.364  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 337bde8f8

Time (s): cpu = 00:00:48 ; elapsed = 00:00:33 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2043 ; free virtual = 25914
INFO: [Route 35-16] Router Completed Successfully

Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 19857a58c

Time (s): cpu = 00:00:48 ; elapsed = 00:00:33 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2044 ; free virtual = 25914
Ending Routing Task | Checksum: 19857a58c

Time (s): cpu = 00:00:48 ; elapsed = 00:00:33 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2044 ; free virtual = 25914

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:34 . Memory (MB): peak = 2840.246 ; gain = 0.000 ; free physical = 2044 ; free virtual = 25914
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Info:      18000 |     2643      15356 |  120   880 |     62792|       0.59       9.48|
Info:      19000 |     2754      16245 |  111   889 |     62344|       0.43       9.91|
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (2175)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (7062)
5. checking no_input_delay (1)
6. checking no_output_delay (9)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (2175)
---------------------------
 There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[36]/Q (HIGH)

 There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[37]/Q (HIGH)

 There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[39]/Q (HIGH)

 There are 2163 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (7062)
---------------------------------------------------
 There are 7062 pins that are not constrained for maximum delay. (HIGH)

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (1)
------------------------------
 There is 1 input port with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (9)
-------------------------------
 There are 9 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      8.661        0.000                      0                    1        0.380        0.000                      0                    1        4.500        0.000                       0                     2  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock        Waveform(ns)       Period(ns)      Frequency(MHz)
-----        ------------       ----------      --------------
sys_clk_pin  {0.000 5.000}      10.000          100.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
sys_clk_pin         8.661        0.000                      0                    1        0.380        0.000                      0                    1        4.500        0.000                       0                     2  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


# report_route_status -file digilent_nexys4ddr_route_status.rpt
Info:      20000 |     2966      17033 |  212   788 |     62279|       0.58      10.48|
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
Info:      21000 |     3082      17917 |  116   884 |     61859|       0.49      10.97|
Info:      22000 |     3253      18746 |  171   829 |     61712|       0.53      11.50|
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Info:      23000 |     3333      19666 |   80   920 |     61706|       0.65      12.15|
Running Vector-less Activity Propagation...
Info:      24000 |     3457      20542 |  124   876 |     61159|       0.50      12.65|

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Info:      25000 |     3604      21395 |  147   853 |     60994|       0.49      13.14|
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
Info:      26000 |     3734      22265 |  130   870 |     60698|       0.49      13.62|
Info:      27000 |     3838      23161 |  104   896 |     60501|       0.43      14.05|
Info:      28000 |     3961      24038 |  123   877 |     59953|       0.34      14.40|
Info:      29000 |     4094      24905 |  133   867 |     59443|       0.37      14.77|
Info:      30000 |     4301      25698 |  207   793 |     59171|       0.35      15.12|
Info:      31000 |     4495      26504 |  194   806 |     58921|       0.35      15.47|
Info:      32000 |     4598      27401 |  103   897 |     58898|       0.43      15.90|
Info:      33000 |     4717      28282 |  119   881 |     58272|       0.39      16.29|
Info:      34000 |     4826      29173 |  109   891 |     58371|       0.44      16.73|
Info:      35000 |     4899      30100 |   73   927 |     57868|       0.43      17.16|
Info:      36000 |     5009      30990 |  110   890 |     57538|       0.42      17.58|
Info:      37000 |     5102      31897 |   93   907 |     57787|       0.30      17.88|
Info:      38000 |     5198      32801 |   96   904 |     57174|       0.31      18.19|
Info:      39000 |     5354      33645 |  156   844 |     56787|       0.34      18.53|
Info:      40000 |     5521      34478 |  167   833 |     56610|       0.41      18.94|
Info:      41000 |     5631      35368 |  110   890 |     56152|       0.43      19.37|
Info:      42000 |     5787      36212 |  156   844 |     55870|       0.33      19.70|
Info:      43000 |     5888      37111 |  101   899 |     55543|       0.32      20.01|
Info:      44000 |     6085      37914 |  197   803 |     55147|       0.36      20.38|
Info:      45000 |     6280      38719 |  195   805 |     54771|       0.35      20.72|
[80%] Routing Phase 2 completed
Info:      46000 |     6345      39654 |   65   935 |     54952|       0.31      21.04|
Info:      47000 |     6457      40542 |  112   888 |     54281|       0.33      21.37|
Info:      48000 |     6608      41391 |  151   849 |     53738|       0.40      21.77|
Info:      49000 |     6818      42181 |  210   790 |     54882|       0.42      22.19|
Info:      50000 |     7045      42954 |  227   773 |     54558|       0.39      22.58|
Info:      51000 |     7217      43782 |  172   828 |     54226|       0.34      22.92|
Info:      52000 |     7384      44615 |  167   833 |     53673|       0.30      23.22|
Info:      53000 |     7554      45445 |  170   830 |     53077|       0.40      23.63|
Info:      54000 |     7690      46309 |  136   864 |     52652|       0.40      24.02|
Info:      55000 |     7841      47158 |  151   849 |     52117|       0.46      24.48|
Info:      56000 |     7954      48045 |  113   887 |     53411|       0.67      25.15|
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
WARNING: [DRC PDRC-153] Gated clock check: Net SOC/Core/Control_Unit/FSM_onehot_state_reg[39]_1[0] is a gated clock net sourced by a combinational pin SOC/Core/Control_Unit/aluop_out_reg[3]_i_2/O, cell SOC/Core/Control_Unit/aluop_out_reg[3]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Info:      57000 |     8043      48956 |   89   911 |     52962|       0.66      25.81|
Info:      58000 |     8085      49914 |   42   958 |     53314|       0.50      26.31|
Info:      59000 |     8214      50785 |  129   871 |     53506|       0.54      26.85|
Info:      60000 |     8299      51700 |   85   915 |     53804|       0.59      27.44|
Loading site data...
Info:      61000 |     8335      52664 |   36   964 |     52928|       0.56      28.00|
Info:      62000 |     8416      53583 |   81   919 |     52244|       0.54      28.54|
Info:      63000 |     8540      54459 |  124   876 |     51583|       0.48      29.02|
Info:      64000 |     8667      55332 |  127   873 |     51331|       0.47      29.50|
Loading route data...
Processing options...
Creating bitmap...
Info:      65000 |     8805      56194 |  138   862 |     50848|       0.79      30.29|
Info:      66000 |     8950      57049 |  145   855 |     50763|       0.54      30.83|
Info:      67000 |     9137      57862 |  187   813 |     50201|       0.40      31.23|
Creating bitstream...
Info:      68000 |     9281      58718 |  144   856 |     50098|       0.52      31.74|
Info:      69000 |     9381      59618 |  100   900 |     50100|       0.56      32.31|
Writing bitstream ./build/out.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
Info:      70000 |     9514      60485 |  133   867 |     49461|       0.38      32.69|
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 3157.270 ; gain = 247.176 ; free physical = 1679 ; free virtual = 25553
INFO: [Common 17-206] Exiting Vivado at Tue Apr 23 02:07:33 2024...
[Pipeline] }
Info:      71000 |     9647      61352 |  133   867 |     48764|       0.41      33.10|
[Pipeline] // stage
[Pipeline] }
Info:      72000 |     9784      62215 |  137   863 |     48161|       0.39      33.49|
Info:      73000 |     9908      63091 |  124   876 |     48412|       0.39      33.89|
Info:      74000 |    10033      63966 |  125   875 |     47705|       0.36      34.24|
Info:      75000 |    10207      64792 |  174   826 |     47784|       0.41      34.66|
Info:      76000 |    10424      65575 |  217   783 |     47477|       0.39      35.04|
Info:      77000 |    10575      66424 |  151   849 |     46858|       0.37      35.42|
WARN  (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
[90%] Routing Phase 3 completed
Running timing analysis......
Info:      78000 |    10719      67280 |  144   856 |     46718|       0.38      35.80|
Info:      79000 |    10883      68116 |  164   836 |     46387|       0.42      36.22|
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Info:      80000 |    11036      68963 |  153   847 |     47683|       0.36      36.58|
Info:      81000 |    11083      69916 |   47   953 |     46841|       0.44      37.02|
Info:      82000 |    11162      70837 |   79   921 |     46018|       0.38      37.40|
Info:      83000 |    11292      71707 |  130   870 |     46543|       0.35      37.75|
Info:      84000 |    11358      72641 |   66   934 |     45638|       0.31      38.06|
Info:      85000 |    11578      73421 |  220   780 |     45046|       0.39      38.46|
Info:      86000 |    11732      74267 |  154   846 |     44426|       0.42      38.87|
Info:      87000 |    11889      75110 |  157   843 |     44407|       0.43      39.31|
Info:      88000 |    12063      75936 |  174   826 |     43784|       0.38      39.68|
Info:      89000 |    12272      76727 |  209   791 |     45258|       0.49      40.17|
Info:      90000 |    12298      77701 |   26   974 |     44294|       0.50      40.67|
Info:      91000 |    12405      78594 |  107   893 |     43721|       0.45      41.13|
Info:      92000 |    12526      79473 |  121   879 |     43027|       0.38      41.50|
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Tue Apr 23 02:07:41 2024

[Pipeline] }
[Pipeline] // stage
Info:      93000 |    12688      80311 |  162   838 |     42668|       0.42      41.92|
[Pipeline] }
Info:      94000 |    12830      81169 |  142   858 |     41977|       0.44      42.36|
Info:      95000 |    13041      81958 |  211   789 |     41504|       0.38      42.74|
Info:      96000 |    13199      82800 |  158   842 |     40790|       0.34      43.08|
Info:      97000 |    13348      83651 |  149   851 |     40446|       0.34      43.42|
Info:      98000 |    13505      84494 |  157   843 |     40339|       0.35      43.77|
Info:      99000 |    13683      85316 |  178   822 |     39830|       0.41      44.18|
Info:     100000 |    13880      86119 |  197   803 |     39475|       0.42      44.60|
Info:     101000 |    14053      86946 |  173   827 |     38817|       0.39      44.98|
Info:     102000 |    14232      87767 |  179   821 |     38658|       0.40      45.39|
Info:     103000 |    14467      88532 |  235   765 |     38083|       0.37      45.76|
Info:     104000 |    14705      89294 |  238   762 |     37508|       0.37      46.13|
Info:     105000 |    15000      89999 |  295   705 |     37262|       0.46      46.59|
Info:     106000 |    15178      90821 |  178   822 |     36991|       0.42      47.01|
Info:     107000 |    15401      91598 |  223   777 |     36594|       0.48      47.49|
Info:     108000 |    15565      92434 |  164   836 |     36394|       0.41      47.90|
Info:     109000 |    15809      93190 |  244   756 |     35920|       0.37      48.27|
Info:     110000 |    15932      94067 |  123   877 |     36609|       0.47      48.74|
Info:     111000 |    16050      94949 |  118   882 |     35905|       0.42      49.16|
Info:     112000 |    16268      95731 |  218   782 |     35605|       0.52      49.68|
Info:     113000 |    16498      96501 |  230   770 |     35173|       0.42      50.10|
Info:     114000 |    16754      97245 |  256   744 |     34695|       0.43      50.53|
Info:     115000 |    17035      97964 |  281   719 |     34261|       0.49      51.02|
Info:     116000 |    17297      98702 |  262   738 |     33698|       0.43      51.45|
Info:     117000 |    17542      99457 |  245   755 |     33491|       0.42      51.88|
Info:     118000 |    17794     100205 |  252   748 |     33097|       0.50      52.38|
Info:     119000 |    18076     100923 |  282   718 |     32618|       0.41      52.78|
Info:     120000 |    18423     101576 |  347   653 |     32209|       0.43      53.22|
Info:     121000 |    18754     102245 |  331   669 |     31896|       0.49      53.70|
Info:     122000 |    19023     102976 |  269   731 |     32140|       0.52      54.22|
Info:     123000 |    19212     103787 |  189   811 |     31413|       0.44      54.66|
Info:     124000 |    19567     104432 |  355   645 |     31109|       0.46      55.12|
Info:     125000 |    19859     105140 |  292   708 |     31009|       0.45      55.57|
Info:     126000 |    20194     105805 |  335   665 |     30585|       0.49      56.06|
Info:     127000 |    20605     106394 |  411   589 |     30226|       0.46      56.52|
Info:     128000 |    20949     107050 |  344   656 |     29931|       0.45      56.97|
Info:     129000 |    21223     107776 |  274   726 |     29747|       0.43      57.40|
Info:     130000 |    21603     108396 |  380   620 |     29413|       0.46      57.86|
Info:     131000 |    22022     108977 |  419   581 |     29025|       0.44      58.30|
Info:     132000 |    22360     109639 |  338   662 |     28885|       0.55      58.86|
Info:     133000 |    22713     110286 |  353   647 |     28771|       0.47      59.32|
Info:     134000 |    23135     110864 |  422   578 |     28324|       0.44      59.76|
Info:     135000 |    23475     111524 |  340   660 |     28316|       0.58      60.33|
Info:     136000 |    23775     112224 |  300   700 |     28186|       0.51      60.84|
Info:     137000 |    24073     112926 |  298   702 |     27852|       0.41      61.26|
Info:     138000 |    24373     113626 |  300   700 |     27651|       0.45      61.70|
Info:     139000 |    24810     114189 |  437   563 |     27405|       0.45      62.16|
Info:     140000 |    25274     114725 |  464   536 |     27087|       0.45      62.61|
Info:     141000 |    25743     115256 |  469   531 |     26840|       0.53      63.14|
Info:     142000 |    26245     115754 |  502   498 |     26562|       0.49      63.63|
Info:     143000 |    26782     116217 |  537   463 |     26296|       0.45      64.08|
Info:     144000 |    27318     116681 |  536   464 |     25996|       0.45      64.53|
Info:     145000 |    27717     117282 |  399   601 |     25728|       0.48      65.02|
Info:     146000 |    28229     117770 |  512   488 |     25482|       0.47      65.49|
Info:     147000 |    28694     118305 |  465   535 |     25214|       0.47      65.96|
Info:     148000 |    29206     118793 |  512   488 |     25218|       0.47      66.42|
Info:     149000 |    29433     119566 |  227   773 |     26874|       0.48      66.90|
Info:     150000 |    29528     120471 |   95   905 |     26020|       0.43      67.33|
Info:     151000 |    29590     121409 |   62   938 |     25143|       0.37      67.70|
Info:     152000 |    29925     122074 |  335   665 |     25638|       0.52      68.21|
Info:     153000 |    30229     122770 |  304   696 |     26140|       0.64      68.85|
Info:     154000 |    30501     123498 |  272   728 |     25755|       0.65      69.50|
Info:     155000 |    30721     124278 |  220   780 |     25905|       0.50      69.99|
Info:     156000 |    31044     124955 |  323   677 |     25884|       0.65      70.64|
Info:     157000 |    31260     125739 |  216   784 |     25264|       0.54      71.18|
Info:     158000 |    31679     126320 |  419   581 |     24844|       0.52      71.70|
Info:     159000 |    32217     126782 |  538   462 |     24479|       0.43      72.13|
Info:     160000 |    32685     127314 |  468   532 |     24126|       0.46      72.58|
Info:     161000 |    33223     127776 |  538   462 |     23771|       0.47      73.05|
Info:     162000 |    33741     128258 |  518   482 |     23454|       0.51      73.56|
Info:     163000 |    34191     128793 |  450   535 |     23077|       0.44      74.00|
Info:     164000 |    34585     129381 |  394   588 |     22560|       0.39      74.39|
Info:     165000 |    34883     130059 |  298   678 |     22225|       0.42      74.81|
Info:     166000 |    35218     130703 |  335   644 |     21635|       0.32      75.14|
Info:     167000 |    35481     131380 |  263   677 |     20971|       0.29      75.42|
Info:     168000 |    35774     132010 |  293   630 |     20306|       0.30      75.73|
Info:     169000 |    36131     132584 |  357   574 |     19757|       0.37      76.10|
Info:     170000 |    36455     133174 |  324   590 |     19195|       0.34      76.44|
Info:     171000 |    36902     133644 |  447   470 |     18742|       0.39      76.83|
Info:     172000 |    37317     134136 |  415   492 |     18307|       0.40      77.23|
Info:     173000 |    37603     134820 |  286   684 |     18171|       0.56      77.80|
Info:     174000 |    38061     135294 |  458   474 |     17797|       0.41      78.21|
Info:     175000 |    38554     135707 |  493   413 |     17359|       0.41      78.62|
Info:     176000 |    39093     136108 |  539   401 |     16953|       0.44      79.06|
Info:     177000 |    39521     136646 |  428   538 |     16744|       0.58      79.64|
Info:     178000 |    40005     137101 |  484   455 |     16389|       0.51      80.15|
Info:     179000 |    40460     137584 |  455   483 |     15965|       0.40      80.55|
Info:     180000 |    40766     138105 |  306   521 |     15332|       0.35      80.90|
Info:     181000 |    40956     138854 |  190   749 |     14570|       0.27      81.17|
Info:     182000 |    40990     139806 |   34   952 |     13608|       0.16      81.32|
Info:     183000 |    41007     140788 |   17   982 |     12625|       0.15      81.47|
Info:     184000 |    41035     141757 |   28   969 |     11654|       0.15      81.63|
Info:     185000 |    41048     142742 |   13   985 |     10679|       0.17      81.79|
Info:     186000 |    41068     143717 |   20   975 |      9700|       0.16      81.95|
Info:     187000 |    41079     144689 |   11   972 |      8711|       0.16      82.11|
Info:     188000 |    41096     145665 |   17   976 |      7732|       0.16      82.27|
Info:     189000 |    41104     146650 |    8   985 |      6741|       0.15      82.42|
Info:     190000 |    41108     147643 |    4   993 |      5745|       0.15      82.57|
Info:     191000 |    41117     148625 |    9   982 |      4754|       0.15      82.72|
Info:     192000 |    41141     149589 |   24   964 |      3783|       0.18      82.90|
Info:     193000 |    41283     150388 |  142   799 |      2931|       0.34      83.23|
Info:     194000 |    41406     151234 |  123   846 |      2058|       0.33      83.56|
Info:     195000 |    41551     151979 |  145   745 |      1243|       0.40      83.96|
Info:     196000 |    41589     152674 |   38   695 |       290|       0.29      84.24|
Info:     196291 |    41591     152821 |    2   147 |         0|       0.19      84.43|
Info: Routing complete.
Info: Router1 time 84.43s
Info: Checksum: 0x350bd394

Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_3.Q
Info:  1.1  1.6    Net SOC.Core.ALU_Control.aluop_out_LUT4_Z_1_D_LUT4_Z_B[1] (8,6) -> (8,5)
Info:                Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  1.9  Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info:  0.0  1.9    Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT (8,5) -> (8,5)
Info:                Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.30-141.32
Info:  0.2  2.0  Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.0  2.0    Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_D1 (8,5) -> (8,5)
Info:                Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info:  0.2  2.3  Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  2.6  4.8    Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D[2] (8,5) -> (26,25)
Info:                Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  5.1  Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_LUT4_Z.F
Info:  2.4  7.5    Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1 (26,25) -> (34,9)
Info:                Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_COMB0.B
Info:  0.4  7.9  Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_COMB0.FCO
Info:  0.0  7.9    Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_FCI_INT (34,9) -> (34,9)
Info:                Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_COMB1.FCI
Info:  0.0  7.9  Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_COMB1.FCO
Info:  0.0  7.9    Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT (34,9) -> (34,9)
Info:                Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  8.0  Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_COMB0.FCO
Info:  0.0  8.0    Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_FCI_INT (34,9) -> (34,9)
Info:                Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_COMB1.FCI
Info:  0.0  8.0  Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_COMB1.FCO
Info:  0.0  8.0    Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN_COUT (34,9) -> (34,9)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  8.1  Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  8.1    Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (34,9) -> (34,9)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  8.1  Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  8.1    Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (34,9) -> (35,9)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  8.1  Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  8.1    Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (35,9) -> (35,9)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  8.1  Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  8.1    Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (35,9) -> (35,9)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  8.2  Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  8.2    Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (35,9) -> (35,9)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  8.2  Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  8.2    Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (35,9) -> (35,9)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  8.3  Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  8.3    Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (35,9) -> (35,9)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  8.3  Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  8.3    Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (35,9) -> (35,9)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  8.4  Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  8.4    Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (35,9) -> (35,9)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  8.4  Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  8.4    Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (35,9) -> (36,9)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  8.4  Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  8.4    Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (36,9) -> (36,9)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  8.4  Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  8.4    Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1_CIN (36,9) -> (36,9)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  Risco-5/src/peripheral/bus.v:54.5-54.37
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.1  8.5  Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info:  0.0  8.5    Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (36,9) -> (36,9)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info:  0.0  8.5  Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info:  0.0  8.5    Net $nextpnr_CCU2C_1$CIN (36,9) -> (36,9)
Info:                Sink $nextpnr_CCU2C_1$CCU2_COMB0.FCI
Info:  0.4  8.9  Source $nextpnr_CCU2C_1$CCU2_COMB0.F
Info:  1.0 10.0    Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B0_CCU2C_B1_COUT (36,9) -> (36,17)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B1_LUT4_C.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 10.2  Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_2_D_CCU2C_COUT_B1_LUT4_C.F
Info:  2.6 12.8    Net SOC.Memory.address_LUT4_Z_C[1] (36,17) -> (25,40)
Info:                Sink SOC.Memory.address_LUT4_Z_3.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 13.1  Source SOC.Memory.address_LUT4_Z_3.F
Info:  2.4 15.5    Net SOC.slave_address[2] (25,40) -> (15,56)
Info:                Sink SOC.Memory.memory.0.937$DPRAM_COMB3.D
Info:                Defined in:
Info:                  Risco-5/src/peripheral/soc.v:22.5-22.18
Info:  0.2 15.7  Source SOC.Memory.memory.0.937$DPRAM_COMB3.F
Info:  0.6 16.3    Net SOC.Memory.memory.0.937_DO[3] (15,56) -> (16,56)
Info:                Sink SOC.Memory.memory.0.913_DO_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 16.6  Source SOC.Memory.memory.0.913_DO_LUT4_Z.F
Info:  0.7 17.3    Net SOC.Memory.memory.0.913_DO[4] (16,56) -> (16,55)
Info:                Sink SOC.Memory.memory.0.905_DO_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 17.5  Source SOC.Memory.memory.0.905_DO_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.2 17.7    Net SOC.Memory.memory.0.905_DO_LUT4_C_Z[3] (16,55) -> (16,55)
Info:                Sink SOC.Memory.memory.0.849_DO_LUT4_C_Z_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 18.0  Source SOC.Memory.memory.0.849_DO_LUT4_C_Z_LUT4_Z.F
Info:  0.8 18.7    Net SOC.Memory.memory.0.849_DO_LUT4_C_Z[4] (16,55) -> (18,54)
Info:                Sink SOC.Memory.memory.0.849_DO_LUT4_C_Z_LUT4_B.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 19.0  Source SOC.Memory.memory.0.849_DO_LUT4_C_Z_LUT4_B.OFX
Info:  0.8 19.8    Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_C_LUT4_C_Z_LUT4_Z_2_B[3] (18,54) -> (18,54)
Info:                Sink SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_C_LUT4_C_Z_LUT4_Z_2.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 20.0  Source SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_C_LUT4_C_Z_LUT4_Z_2.F
Info:  1.6 21.6    Net SOC.Uart.RX_FIFO.memory.0.1_DO_3_LUT4_Z_C_LUT4_C_Z[3] (18,54) -> (22,42)
Info:                Sink SOC.Core.read_data_LUT4_Z_7_D_PFUMX_Z_ALUT_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 21.9  Source SOC.Core.read_data_LUT4_Z_7_D_PFUMX_Z_ALUT_LUT4_Z.F
Info:  0.0 21.9    Net SOC.Core.read_data_LUT4_Z_7_D_PFUMX_Z_ALUT (22,42) -> (22,42)
Info:                Sink SOC.Core.read_data_LUT4_Z_7_D_PFUMX_Z_BLUT_LUT4_Z.F1
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info:  0.2 22.0  Source SOC.Core.read_data_LUT4_Z_7_D_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  2.0 24.0    Net SOC.Core.read_data_LUT4_Z_7_C[3] (22,42) -> (26,25)
Info:                Sink SOC.Core.read_data_LUT4_Z_15_C_PFUMX_Z_C0_LUT4_C_Z_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 24.2  Source SOC.Core.read_data_LUT4_Z_15_C_PFUMX_Z_C0_LUT4_C_Z_LUT4_Z.F
Info:  2.2 26.4    Net SOC.Core.read_data_LUT4_Z_10_D[2] (26,25) -> (41,16)
Info:                Sink SOC.Core.read_data_PFUMX_Z_13_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 26.6  Source SOC.Core.read_data_PFUMX_Z_13_BLUT_LUT4_Z.OFX
Info:  0.8 27.4    Net SOC.read_data[31] (41,16) -> (33,16)
Info:                Sink SOC.Core.instruction_register_TRELLIS_FF_Q.M
Info:                Defined in:
Info:                  Risco-5/src/peripheral/soc.v:21.34-21.43
Info:  0.0 27.4  Setup SOC.Core.instruction_register_TRELLIS_FF_Q.M
Info: 5.7 ns logic, 21.7 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source rx$tr_io.O
Info:  1.7  1.7    Net rx$TRELLIS_IO_IN (90,20) -> (70,11)
Info:                Sink SOC.Uart.i_uart_rx.rxd_reg_0_TRELLIS_FF_Q.M
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:4.16-4.18
Info:  0.0  1.7  Setup SOC.Uart.i_uart_rx.rxd_reg_0_TRELLIS_FF_Q.M
Info: 0.0 ns logic, 1.7 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source SOC.Leds.data_TRELLIS_FF_Q_29.Q
Info:  2.8  3.3    Net SOC.Core.read_data_LUT4_Z_2_C[0] (43,16) -> (78,21)
Info:                Sink led_LUT4_Z_6.D
Info:                Defined in:
Info:                  Risco-5/src/peripheral/leds.v:15.12-15.16
Info:  0.2  3.5  Source led_LUT4_Z_6.F
Info:  2.8  6.4    Net led[2]$TRELLIS_IO_OUT (78,21) -> (90,44)
Info:                Sink led[2]$tr_io.I
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 5.6 ns routing

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 36.49 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 1.73 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 6.36 ns

Info: Slack histogram:
Info:  legend: * represents 193 endpoint(s)
Info:          + represents [1,193) endpoint(s)
Info: [ 12596,  13919) |+
Info: [ 13919,  15242) |*****+
Info: [ 15242,  16565) |****+
Info: [ 16565,  17888) |+
Info: [ 17888,  19211) |+
Info: [ 19211,  20534) |*+
Info: [ 20534,  21857) |************+
Info: [ 21857,  23180) |********+
Info: [ 23180,  24503) |**********************************+
Info: [ 24503,  25826) |************************************************************ 
Info: [ 25826,  27149) |***+
Info: [ 27149,  28472) |+
Info: [ 28472,  29795) |***+
Info: [ 29795,  31118) |*+
Info: [ 31118,  32441) |+
Info: [ 32441,  33764) |+
Info: [ 33764,  35087) |+
Info: [ 35087,  36410) |**+
Info: [ 36410,  37733) |**+
Info: [ 37733,  39056) |*+

Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
	0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] sh
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz   -> real 6.00MHz  
Open file DONE
Parse file DONE
load program
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] }

Loading: [====                                              ] 7.65%[Pipeline] // script

Load SRAM: [=========                                         ] 18.00%[Pipeline] }
[Pipeline] // stage
[Pipeline] }

Loading: [========                                          ] 15.29%
Load SRAM: [===================                               ] 38.00%
Loading: [============                                      ] 22.94%
Load SRAM: [=============================                     ] 58.00%
Loading: [================                                  ] 30.58%
Load SRAM: [=======================================           ] 78.00%
Loading: [====================                              ] 38.23%
Load SRAM: [================================================= ] 98.00%
Load SRAM: [===================================================] 100.00%
Done
[Pipeline] }
Lock released on resource [nexys4]

Loading: [=======================                           ] 45.87%[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }

Loading: [===========================                       ] 53.52%[Pipeline] // stage
[Pipeline] }

Loading: [===============================                   ] 61.16%
Loading: [===================================               ] 68.81%
Loading: [=======================================           ] 76.46%
Loading: [===========================================       ] 84.10%
Loading: [==============================================    ] 91.75%
Loading: [==================================================] 99.39%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
Rodando teste na Nexys 4
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ echo testando na ecp5
testando na ecp5
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo testando na tang nano
testando na tang nano
[Pipeline] sh
+ echo testando na tang nano
testando na tang nano
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // script
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS