Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/lib/jenkins/workspace/Risco_5 [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -Rf Risco-5/ build/ [Pipeline] sh + git clone https://github.com/JN513/Risco-5 Cloning into 'Risco-5'... [Pipeline] sh + cd Risco-5 [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (IVerilog) [Pipeline] sh + mkdir -p build [Pipeline] sh + cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/csr_unit.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/fifo.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v [Pipeline] sh + /eda/oss-cad-suite/bin/vvp build/soc_test.o ERROR: Risco-5/src/peripheral/memory.v:35: $readmemh: Unable to open software/memory/generic.hex for reading. VCD info: dumpfile build/soc.vcd opened for output. Risco-5/tests/soc_test.v:34: $finish called at 3606 (1s) [Pipeline] sh + rm -f Risco-5/software/memory/generic.hex [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Síntese) [Pipeline] parallel [Pipeline] { (Branch: OSS-Cad-Suite) [Pipeline] { (Branch: Gowin) [Pipeline] { (Branch: Vivado) [Pipeline] stage [Pipeline] { (OSS-Cad-Suite) [Pipeline] stage [Pipeline] { (Gowin) [Pipeline] stage [Pipeline] { (Vivado) [Pipeline] stage [Pipeline] { (Yosys) [Pipeline] sh [Pipeline] sh + rm -rf Risco-5/impl/pnr [Pipeline] sh + cd Risco-5/fpga/nexys4_ddr + mkdir build + /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source run.tcl + /eda/oss-cad-suite/bin/yosys -p read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf <claire@yosyshq.com> | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) -- Running command ` read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 ' -- 1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: Risco-5/debug/reset.v Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation. Generating RTLIL representation for module `\ResetBootSystem'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation. Generating RTLIL representation for module `\Alu'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation. Generating RTLIL representation for module `\ALU_Control'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation. Generating RTLIL representation for module `\Control_Unit'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: Risco-5/src/core/core.v Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation. Generating RTLIL representation for module `\Core'. Risco-5/src/core/core.v:142: Warning: Identifier `\pc_source' is implicitly declared. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: Risco-5/src/core/csr_unit.v Parsing Verilog input from `Risco-5/src/core/csr_unit.v' to AST representation. Generating RTLIL representation for module `\CSR_Unit'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation. Generating RTLIL representation for module `\Immediate_Generator'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation. Generating RTLIL representation for module `\MUX'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation. Generating RTLIL representation for module `\PC'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation. Generating RTLIL representation for module `\Registers'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation. Generating RTLIL representation for module `\BUS'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/fifo.v Parsing Verilog input from `Risco-5/src/peripheral/fifo.v' to AST representation. Generating RTLIL representation for module `\FIFO'. Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9) Generating RTLIL representation for module `\GPIO'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation. Generating RTLIL representation for module `\GPIOS'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation. Generating RTLIL representation for module `\LEDs'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation. Generating RTLIL representation for module `\Memory'. Successfully finished Verilog frontend. 18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation. Generating RTLIL representation for module `\Risco_5_SOC'. Successfully finished Verilog frontend. 19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation. Generating RTLIL representation for module `\UART'. Successfully finished Verilog frontend. 20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_tool_rx'. Successfully finished Verilog frontend. 21. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tool_tx'. Successfully finished Verilog frontend. 22. Executing SYNTH_ECP5 pass. 22.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\DP16KD'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 22.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCUA'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Successfully finished Verilog frontend. 22.3. Executing HIERARCHY pass (managing design hierarchy). 22.3.1. Finding top of design hierarchy.. root of 0 design levels: uart_tool_tx root of 0 design levels: uart_tool_rx root of 1 design levels: UART root of 2 design levels: Risco_5_SOC root of 0 design levels: Memory root of 0 design levels: LEDs root of 1 design levels: GPIOS root of 0 design levels: GPIO root of 0 design levels: FIFO root of 0 design levels: BUS root of 0 design levels: Registers root of 0 design levels: PC root of 0 design levels: MUX root of 0 design levels: Immediate_Generator root of 0 design levels: CSR_Unit root of 1 design levels: Core root of 0 design levels: Control_Unit root of 0 design levels: ALU_Control root of 0 design levels: Alu root of 0 design levels: ResetBootSystem root of 3 design levels: top Automatically selected top as design top module. 22.3.2. Analyzing design hierarchy.. Top module: \top Used module: \Risco_5_SOC Used module: \GPIOS Used module: \GPIO Used module: \UART Used module: \uart_tool_tx Used module: \uart_tool_rx Used module: \FIFO Used module: \LEDs Used module: \BUS Used module: \Memory Used module: \Core Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: \ResetBootSystem Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \MEMORY_SIZE = 8192 Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000 Parameter \GPIO_WIDHT = 6 22.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \MEMORY_SIZE = 8192 Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000 Parameter \GPIO_WIDHT = 6 Generating RTLIL representation for module `$paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC'. Parameter \CYCLES = 20 22.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'. Parameter \CYCLES = 20 Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'. Parameter \WIDHT = 5 22.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'. Parameter \WIDHT = 5 Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 9600 22.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Generating RTLIL representation for module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 22.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \BOOT_ADDRESS = 0 22.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'. Parameter \BOOT_ADDRESS = 0 Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'. Risco-5/src/core/core.v:142: Warning: Identifier `\pc_source' is implicitly declared. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 22.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 22.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 22.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 22.3.12. Analyzing design hierarchy.. Top module: \top Used module: $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC Used module: \GPIOS Used module: \GPIO Used module: \UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \LEDs Used module: \BUS Used module: \Memory Used module: \Core Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Parameter \WIDHT = 6 22.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'. Parameter \WIDHT = 6 Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 115200 22.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Generating RTLIL representation for module `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART'. Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000 Parameter \MEMORY_SIZE = 8192 22.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = 296'00101110001011100010111100101110001011100010111101110011011011110110011001110100011101110110000101110010011001010010111101101101011001010110110101101111011100100111100100101111011001100111000001100111011000010101111101110100011001010111001101110100010111110011001100101110011010000110010101111000 Parameter \MEMORY_SIZE = 8192 Generating RTLIL representation for module `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory'. Parameter \BOOT_ADDRESS = 0 Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'. 22.3.16. Analyzing design hierarchy.. Top module: \top Used module: $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART Used module: \uart_tool_tx Used module: \uart_tool_rx Used module: \FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 22.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 22.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 22.3.19. Analyzing design hierarchy.. Top module: \top Used module: $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 22.3.20. Analyzing design hierarchy.. Top module: \top Used module: $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'. Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'. Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Removing unused module `$paramod$52971eb2e95dac24f82b6c2004e3d2e007b453cd\UART'. Removing unused module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'. Removing unused module `\uart_tool_tx'. Removing unused module `\uart_tool_rx'. Removing unused module `\UART'. Removing unused module `\Risco_5_SOC'. Removing unused module `\Memory'. Removing unused module `\GPIOS'. Removing unused module `\FIFO'. Removing unused module `\Core'. Removing unused module `\ResetBootSystem'. Removed 14 unused modules. 22.4. Executing PROC pass (convert processes to netlists). 22.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$548'. Found and cleaned up 1 empty switch in `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:0$968'. Removing empty process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:0$968'. Cleaned up 2 empty switches. 22.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$655 in module TRELLIS_FF. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$607 in module DPR16X4C. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$549 in module TRELLIS_DPR16X4. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/fifo.v:24$876 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:189$1061 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:178$1059 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:163$1051 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:152$1048 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:140$1042 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:125$1037 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:108$1032 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:89$1023 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:167$1010 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:156$1008 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:141$1000 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:124$986 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:109$980 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:92$975 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:244$761 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:59$966 in module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:47$929 in module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$266 in module LEDs. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:79$918 in module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:44$904 in module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:31$901 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:24$170 in module Registers. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:15$159 in module PC. Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:18$142 in module Immediate_Generator. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:189$132 in module CSR_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:180$128 in module CSR_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:143$126 in module CSR_Unit. Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:104$124 in module CSR_Unit. Marked 5 switch rules as full_case in process $proc$Risco-5/debug/reset.v:24$658 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:628$86 in module Control_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:618$85 in module Control_Unit. Marked 19 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:141$40 in module Control_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:133$39 in module Control_Unit. Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:9$31 in module ALU_Control. Marked 5 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:9$31 in module ALU_Control. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:26$11 in module Alu. Removed a total of 1 dead cases. 22.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 14 redundant assignments. Promoted 143 assignments to connections. 22.4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$656'. Set init value: \Q = 1'0 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:124$1063'. Set init value: \i = 0 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:108$1016'. Set init value: \i = 0 Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$769'. Set init value: \instruction_register = 0 Set init value: \memory_register = 0 Set init value: \alu_out_register = 0 Set init value: \register_data_1 = 0 Set init value: \register_data_2 = 0 Set init value: \pc_old = 0 Set init value: \temp_address = 0 Set init value: \temp_reg2 = 0 Set init value: \temp_write_value = 0 Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$269'. Set init value: \data = 33'000000000000000000000000000000000 Found init rule in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$921'. Set init value: \uart_tx_en = 1'0 Set init value: \tx_fifo_read = 1'0 Set init value: \tx_fifo_write = 1'0 Set init value: \rx_fifo_read = 1'0 Set init value: \rx_fifo_write = 1'0 Set init value: \buffer_full = 1'0 Set init value: \uart_tx_data = 8'00000000 Set init value: \tx_fifo_write_data = 8'00000000 Set init value: \rx_fifo_write_data = 8'00000000 Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$162'. Set init value: \Output = 0 Found init rule in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$141'. Set init value: \csr_mcause = 0 Set init value: \csr_mepc = 0 Set init value: \csr_mie_mfie = 16'0000000000000000 Set init value: \csr_mie_meie = 1'0 Set init value: \csr_mie_msie = 1'0 Set init value: \csr_mie_mtie = 1'0 Set init value: \csr_mip_mfip = 16'0000000000000000 Set init value: \csr_mip_meip = 1'0 Set init value: \csr_mip_mtip = 1'0 Set init value: \csr_mip_msip = 1'0 Set init value: \csr_mscratch = 0 Set init value: \csr_mstatus_mie = 1'0 Set init value: \csr_mstatus_mpie = 1'0 Set init value: \csr_mtvec = 0 Set init value: \csr_mtval = 0 Set init value: \csr_write_data = 0 Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$664'. Set init value: \reset_o = 1'0 Set init value: \state = 2'01 Set init value: \counter = 6'000000 Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$87'. Set init value: \state = 6'000000 Set init value: \is_immediate = 1'0 Set init value: \pc_write = 1'0 Set init value: \ir_write = 1'0 Set init value: \pc_source = 1'0 Set init value: \reg_write = 1'0 Set init value: \memory_read = 1'0 Set init value: \memory_write = 1'0 Set init value: \pc_write_cond = 1'0 Set init value: \csr_write_enable = 1'0 Set init value: \alu_input_selector = 1'0 Set init value: \save_address = 1'0 Set init value: \save_value = 1'0 Set init value: \save_value_2 = 1'0 Set init value: \save_write_value = 1'0 Set init value: \control_memory_op = 1'0 Set init value: \write_data_in = 1'0 Set init value: \lorD = 2'00 Set init value: \aluop = 2'00 Set init value: \alu_src_a = 3'000 Set init value: \alu_src_b = 3'000 Set init value: \memory_to_reg = 3'000 Set init value: \control_unit_memory_op = 3'010 Set init value: \control_unit_aluop = 4'0000 Set init value: \clear_hal_byte_one_block_option = 3'000 Set init value: \clear_hal_byte_one_block_option_2 = 3'000 Set init value: \nextstate = 6'000000 22.4.5. Executing PROC_ARST pass (detect async resets in processes). 22.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~110 debug messages> 22.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$656'. Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$655'. 1/1: $0\Q[0:0] Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$607'. 1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$606_EN[3:0]$613 2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$606_DATA[3:0]$612 3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$606_ADDR[3:0]$611 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$549'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$547_EN[3:0]$555 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$547_DATA[3:0]$554 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$547_ADDR[3:0]$553 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$548'. Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$876'. 1/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$888 2/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_DATA[7:0]$887 3/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_ADDR[5:0]$886 4/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$883 5/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_DATA[7:0]$882 6/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_ADDR[5:0]$881 7/8: $0\write_ptr[5:0] 8/8: $0\read_ptr[5:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:124$1063'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1061'. 1/2: $0\rxd_reg_0[0:0] 2/2: $0\rxd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1059'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1051'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1048'. 1/1: $0\bit_sample[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1042'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1037'. 1/11: $3\i[31:0] 2/11: $0\recieved_data[7:0] [1] 3/11: $0\recieved_data[7:0] [0] 4/11: $0\recieved_data[7:0] [2] 5/11: $0\recieved_data[7:0] [3] 6/11: $0\recieved_data[7:0] [4] 7/11: $0\recieved_data[7:0] [5] 8/11: $0\recieved_data[7:0] [6] 9/11: $0\recieved_data[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1032'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1023'. 1/1: $0\uart_rx_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:108$1016'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$1010'. 1/1: $0\txd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$1008'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$1000'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$986'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$980'. 1/11: $3\i[31:0] 2/11: $0\data_to_send[7:0] [1] 3/11: $0\data_to_send[7:0] [0] 4/11: $0\data_to_send[7:0] [2] 5/11: $0\data_to_send[7:0] [3] 6/11: $0\data_to_send[7:0] [4] 7/11: $0\data_to_send[7:0] [5] 8/11: $0\data_to_send[7:0] [6] 9/11: $0\data_to_send[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$975'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$769'. Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$761'. 1/10: $0\alu_out_register[31:0] 2/10: $0\register_data_2[31:0] 3/10: $0\register_data_1[31:0] 4/10: $0\memory_register[31:0] 5/10: $0\temp_write_value[31:0] 6/10: $0\temp_reg3[31:0] 7/10: $0\temp_reg2[31:0] 8/10: $0\temp_address[31:0] 9/10: $0\pc_old[31:0] 10/10: $0\instruction_register[31:0] Creating decoders for process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:59$966'. 1/1: $1\read_data[31:0] Creating decoders for process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$929'. 1/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$962 2/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_DATA[31:0]$961 3/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_ADDR[31:0]$960 4/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$965 5/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_DATA[31:0]$964 6/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_ADDR[31:0]$963 7/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$952 8/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_DATA[31:0]$951 9/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_ADDR[31:0]$950 10/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$958 11/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_DATA[31:0]$957 12/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_ADDR[31:0]$956 13/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$955 14/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_DATA[31:0]$954 15/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_ADDR[31:0]$953 16/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$948 17/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_DATA[31:0]$947 18/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_ADDR[31:0]$946 19/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$945 20/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_DATA[31:0]$944 21/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_ADDR[31:0]$943 22/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$942 23/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_DATA[31:0]$941 24/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_ADDR[31:0]$940 Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$269'. Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$266'. 1/1: $0\data[32:0] Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$921'. Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:79$918'. 1/1: $1\read_data[31:0] Creating decoders for process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:44$904'. 1/9: $0\rx_fifo_write[0:0] 2/9: $0\rx_fifo_read[0:0] 3/9: $0\tx_fifo_write[0:0] 4/9: $0\tx_fifo_read[0:0] 5/9: $0\uart_tx_en[0:0] 6/9: $0\rx_fifo_write_data[7:0] 7/9: $0\tx_fifo_write_data[7:0] 8/9: $0\uart_tx_data[7:0] 9/9: $0\buffer_full[0:0] Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:31$901'. 1/2: $0\gpio_value[5:0] 2/2: $0\gpio_direction[5:0] Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$188'. Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:24$170'. 1/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$185 2/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$165_DATA[31:0]$184 3/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$165_ADDR[4:0]$183 4/9: $2$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$186 5/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$177 6/9: $1$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$181 7/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$180 8/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$165_DATA[31:0]$179 9/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$165_ADDR[4:0]$178 Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$162'. Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:15$159'. 1/1: $0\Output[31:0] Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$142'. 1/2: $2\immediate[31:0] 2/2: $1\immediate[31:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$141'. Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:189$132'. 1/1: $1\csr_data_out[31:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128'. 1/1: $1\csr_write_data[31:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:143$126'. 1/4: $0\csr_mip_msip[0:0] 2/4: $0\csr_mip_mtip[0:0] 3/4: $0\csr_mip_meip[0:0] 4/4: $0\csr_mip_mfip[15:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'. 1/11: $0\csr_mtval[31:0] 2/11: $0\csr_mtvec[31:0] 3/11: $0\csr_mstatus_mpie[0:0] 4/11: $0\csr_mstatus_mie[0:0] 5/11: $0\csr_mscratch[31:0] 6/11: $0\csr_mie_mtie[0:0] 7/11: $0\csr_mie_msie[0:0] 8/11: $0\csr_mie_meie[0:0] 9/11: $0\csr_mie_mfie[15:0] 10/11: $0\csr_mepc[31:0] 11/11: $0\csr_mcause[31:0] Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$664'. Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$658'. 1/3: $0\counter[5:0] 2/3: $0\state[1:0] 3/3: $0\reset_o[0:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$87'. Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86'. 1/2: $0\clear_hal_byte_one_block_option_2[2:0] 2/2: $0\clear_hal_byte_one_block_option[2:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:618$85'. 1/1: $0\wb_filter[2:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. 1/22: $0\save_write_value[0:0] 2/22: $0\write_data_in[0:0] 3/22: $0\save_value_2[0:0] 4/22: $0\save_value[0:0] 5/22: $0\control_memory_op[0:0] 6/22: $0\save_address[0:0] 7/22: $0\control_unit_aluop[3:0] 8/22: $0\alu_input_selector[0:0] 9/22: $0\csr_write_enable[0:0] 10/22: $0\is_immediate[0:0] 11/22: $0\reg_write[0:0] 12/22: $0\alu_src_a[2:0] 13/22: $0\alu_src_b[2:0] 14/22: $0\aluop[1:0] 15/22: $0\pc_source[0:0] 16/22: $0\memory_to_reg[2:0] 17/22: $0\memory_write[0:0] 18/22: $0\memory_read[0:0] 19/22: $0\lorD[1:0] 20/22: $0\ir_write[0:0] 21/22: $0\pc_write[0:0] 22/22: $0\pc_write_cond[0:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40'. 1/19: $19\nextstate[5:0] 2/19: $18\nextstate[5:0] 3/19: $17\nextstate[5:0] 4/19: $16\nextstate[5:0] 5/19: $15\nextstate[5:0] 6/19: $14\nextstate[5:0] 7/19: $13\nextstate[5:0] 8/19: $12\nextstate[5:0] 9/19: $11\nextstate[5:0] 10/19: $10\nextstate[5:0] 11/19: $9\nextstate[5:0] 12/19: $8\nextstate[5:0] 13/19: $7\nextstate[5:0] 14/19: $6\nextstate[5:0] 15/19: $5\nextstate[5:0] 16/19: $4\nextstate[5:0] 17/19: $3\nextstate[5:0] 18/19: $2\nextstate[5:0] 19/19: $1\nextstate[5:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:133$39'. 1/1: $0\state[5:0] Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'. 1/5: $5\aluop_out[3:0] 2/5: $4\aluop_out[3:0] 3/5: $3\aluop_out[3:0] 4/5: $2\aluop_out[3:0] 5/5: $1\aluop_out[3:0] Creating decoders for process `\Alu.$proc$Risco-5/src/core/alu.v:26$11'. 1/1: $1\ALU_out_S[31:0] 22.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1032'. No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$975'. No latch inferred for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.\read_data' from process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:59$966'. No latch inferred for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\read_data' from process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:79$918'. No latch inferred for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:17$163_EN' from process `\Registers.$proc$Risco-5/src/core/registers.v:0$188'. No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$142'. No latch inferred for signal `\CSR_Unit.\csr_mcause_code' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$141'. No latch inferred for signal `\CSR_Unit.\csr_mcause_interrupt_flag' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$141'. No latch inferred for signal `\CSR_Unit.\csr_data_out' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:189$132'. No latch inferred for signal `\CSR_Unit.\csr_write_data' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128'. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [0]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [1]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [2]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [3]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [4]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [5]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [6]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [7]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [8]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [9]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [10]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [11]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [12]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [13]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [14]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [15]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [16]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [17]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [18]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [19]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [20]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [21]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [22]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [23]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [24]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [25]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [26]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [27]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [28]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [29]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [30]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [31]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`. No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86`. No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option_2' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86`. No latch inferred for signal `\Control_Unit.\wb_filter' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:618$85'. No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\csr_write_enable` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\alu_input_selector' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_input_selector` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\save_address' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_address` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\save_value' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\save_value_2' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value_2` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\save_write_value' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_write_value` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\control_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_memory_op` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\write_data_in' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\write_data_in` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\control_unit_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. Removing init bit 1'1 for non-memory siginal `\Control_Unit.\control_unit_memory_op [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\control_unit_aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`. No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [4]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [5]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40`. Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31': $auto$proc_dlatch.cc:433:proc_dlatch$3073 No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$Risco-5/src/core/alu.v:26$11'. 22.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$655'. created $dff cell `$procdff$3096' with positive edge clock. Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$591_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$592_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$593_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$594_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$595_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$596_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$597_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$598_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$599_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$600_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$601_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$602_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$603_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$604_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$605_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$606_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$607'. created $dff cell `$procdff$3097' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$606_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$607'. created $dff cell `$procdff$3098' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$606_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$607'. created $dff cell `$procdff$3099' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$531_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$532_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$533_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$534_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$535_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$536_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$537_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$538_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$539_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$540_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$541_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$542_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$543_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$544_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$545_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$546_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$547_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$549'. created $dff cell `$procdff$3100' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$547_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$549'. created $dff cell `$procdff$3101' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$547_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$549'. created $dff cell `$procdff$3102' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$548'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$876'. created $dff cell `$procdff$3103' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$876'. created $dff cell `$procdff$3104' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$876'. created $dff cell `$procdff$3105' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$876'. created $dff cell `$procdff$3106' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$876'. created $dff cell `$procdff$3107' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1061'. created $dff cell `$procdff$3108' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1061'. created $dff cell `$procdff$3109' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1059'. created $dff cell `$procdff$3110' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1051'. created $dff cell `$procdff$3111' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1048'. created $dff cell `$procdff$3112' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1042'. created $dff cell `$procdff$3113' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1037'. created $dff cell `$procdff$3114' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1037'. created $dff cell `$procdff$3115' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1023'. created $dff cell `$procdff$3116' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$1010'. created $dff cell `$procdff$3117' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$1008'. created $dff cell `$procdff$3118' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$1000'. created $dff cell `$procdff$3119' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$986'. created $dff cell `$procdff$3120' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$980'. created $dff cell `$procdff$3121' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$980'. created $dff cell `$procdff$3122' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$761'. created $dff cell `$procdff$3123' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$761'. created $dff cell `$procdff$3124' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$761'. created $dff cell `$procdff$3125' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$761'. created $dff cell `$procdff$3126' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$761'. created $dff cell `$procdff$3127' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$761'. created $dff cell `$procdff$3128' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_address' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$761'. created $dff cell `$procdff$3129' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_reg2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$761'. created $dff cell `$procdff$3130' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_reg3' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$761'. created $dff cell `$procdff$3131' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_write_value' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$761'. created $dff cell `$procdff$3132' with positive edge clock. Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_ADDR' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$929'. created $dff cell `$procdff$3133' with positive edge clock. Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_DATA' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$929'. created $dff cell `$procdff$3134' with positive edge clock. Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$929'. created $dff cell `$procdff$3135' with positive edge clock. Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_ADDR' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$929'. created $dff cell `$procdff$3136' with positive edge clock. Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_DATA' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$929'. created $dff cell `$procdff$3137' with positive edge clock. Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$929'. created $dff cell `$procdff$3138' with positive edge clock. Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_ADDR' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$929'. created $dff cell `$procdff$3139' with positive edge clock. Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_DATA' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$929'. created $dff cell `$procdff$3140' with positive edge clock. Creating register for signal `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN' using process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$929'. created $dff cell `$procdff$3141' with positive edge clock. Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$266'. created $dff cell `$procdff$3142' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\uart_tx_en' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:44$904'. created $dff cell `$procdff$3143' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_read' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:44$904'. created $dff cell `$procdff$3144' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_write' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:44$904'. created $dff cell `$procdff$3145' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_read' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:44$904'. created $dff cell `$procdff$3146' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_write' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:44$904'. created $dff cell `$procdff$3147' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\buffer_full' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:44$904'. created $dff cell `$procdff$3148' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\uart_tx_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:44$904'. created $dff cell `$procdff$3149' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\tx_fifo_write_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:44$904'. created $dff cell `$procdff$3150' with positive edge clock. Creating register for signal `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.\rx_fifo_write_data' using process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:44$904'. created $dff cell `$procdff$3151' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:31$901'. created $dff cell `$procdff$3152' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:31$901'. created $dff cell `$procdff$3153' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$170'. created $dff cell `$procdff$3154' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$165_ADDR' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$170'. created $dff cell `$procdff$3155' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$165_DATA' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$170'. created $dff cell `$procdff$3156' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$170'. created $dff cell `$procdff$3157' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$170'. created $dff cell `$procdff$3158' with positive edge clock. Creating register for signal `\PC.\Output' using process `\PC.$proc$Risco-5/src/core/pc.v:15$159'. created $dff cell `$procdff$3159' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mip_mfip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:143$126'. created $dff cell `$procdff$3160' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mip_meip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:143$126'. created $dff cell `$procdff$3161' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mip_mtip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:143$126'. created $dff cell `$procdff$3162' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mip_msip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:143$126'. created $dff cell `$procdff$3163' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mcause' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'. created $dff cell `$procdff$3164' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mepc' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'. created $dff cell `$procdff$3165' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mie_mfie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'. created $dff cell `$procdff$3166' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mie_meie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'. created $dff cell `$procdff$3167' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mie_msie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'. created $dff cell `$procdff$3168' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mie_mtie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'. created $dff cell `$procdff$3169' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mscratch' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'. created $dff cell `$procdff$3170' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mstatus_mie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'. created $dff cell `$procdff$3171' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mstatus_mpie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'. created $dff cell `$procdff$3172' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mtvec' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'. created $dff cell `$procdff$3173' with positive edge clock. Creating register for signal `\CSR_Unit.\csr_mtval' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'. created $dff cell `$procdff$3174' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$658'. created $dff cell `$procdff$3175' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$658'. created $dff cell `$procdff$3176' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$658'. created $dff cell `$procdff$3177' with positive edge clock. Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:133$39'. created $dff cell `$procdff$3178' with positive edge clock. 22.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$656'. Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$655'. Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$655'. Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$630'. Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$607'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$573'. Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$549'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$548'. Found and cleaned up 3 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$876'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$876'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:124$1063'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1061'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1061'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1059'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1059'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1051'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1051'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1048'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1048'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1042'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1042'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1037'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1037'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1032'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1032'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1023'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1023'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:108$1016'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$1010'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$1010'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$1008'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$1008'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$1000'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$1000'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$986'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$986'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$980'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$980'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$975'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$975'. Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$769'. Found and cleaned up 6 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$761'. Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$761'. Found and cleaned up 1 empty switch in `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:59$966'. Removing empty process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:59$966'. Found and cleaned up 3 empty switches in `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$929'. Removing empty process `$paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory.$proc$Risco-5/src/peripheral/memory.v:47$929'. Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$269'. Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$266'. Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$266'. Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:0$921'. Found and cleaned up 1 empty switch in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:79$918'. Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:79$918'. Found and cleaned up 5 empty switches in `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:44$904'. Removing empty process `$paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART.$proc$Risco-5/src/peripheral/uart.v:44$904'. Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:31$901'. Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:31$901'. Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$188'. Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:24$170'. Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:24$170'. Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$162'. Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:15$159'. Removing empty process `PC.$proc$Risco-5/src/core/pc.v:15$159'. Found and cleaned up 2 empty switches in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$142'. Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$142'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$141'. Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:189$132'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:189$132'. Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128'. Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:143$126'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:143$126'. Found and cleaned up 4 empty switches in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$664'. Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$658'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$658'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$87'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:618$85'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:618$85'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'. Found and cleaned up 19 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:133$39'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:133$39'. Found and cleaned up 5 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'. Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'. Found and cleaned up 1 empty switch in `\Alu.$proc$Risco-5/src/core/alu.v:26$11'. Removing empty process `Alu.$proc$Risco-5/src/core/alu.v:26$11'. Cleaned up 110 empty switches. 22.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. <suppressed ~4 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. <suppressed ~21 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. <suppressed ~19 debug messages> Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. <suppressed ~10 debug messages> Optimizing module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory. <suppressed ~5 debug messages> Optimizing module LEDs. <suppressed ~3 debug messages> Optimizing module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART. <suppressed ~9 debug messages> Optimizing module GPIO. <suppressed ~3 debug messages> Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. <suppressed ~4 debug messages> Optimizing module BUS. <suppressed ~4 debug messages> Optimizing module Registers. <suppressed ~2 debug messages> Optimizing module PC. <suppressed ~2 debug messages> Optimizing module MUX. <suppressed ~1 debug messages> Optimizing module Immediate_Generator. Optimizing module CSR_Unit. <suppressed ~3 debug messages> Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. <suppressed ~7 debug messages> Optimizing module Control_Unit. <suppressed ~26 debug messages> Optimizing module ALU_Control. <suppressed ~18 debug messages> Optimizing module Alu. <suppressed ~1 debug messages> Optimizing module $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC. Optimizing module top. 22.5. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Deleting now unused module $paramod$a07613431e23162c609b9ee00e6e363790c7d61f\Memory. Deleting now unused module LEDs. Deleting now unused module $paramod$b73ee994e450547d16ed8fd6fef8d5bfbfc58fbb\UART. Deleting now unused module GPIO. Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. Deleting now unused module BUS. Deleting now unused module Registers. Deleting now unused module PC. Deleting now unused module MUX. Deleting now unused module Immediate_Generator. Deleting now unused module CSR_Unit. Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Deleting now unused module Control_Unit. Deleting now unused module ALU_Control. Deleting now unused module Alu. Deleting now unused module $paramod$e9dfa710fcacae80ffe1b3f1d66a3af1fb37df92\Risco_5_SOC. <suppressed ~30 debug messages> 22.6. Executing TRIBUF pass. [Pipeline] sh 22.7. Executing DEMINOUT pass (demote inout ports to input or output). 22.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~47 debug messages> 22.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 57 unused cells and 837 unused wires. <suppressed ~71 debug messages> 22.10. Executing CHECK pass (checking for obvious problems). Checking module top... Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [15] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [14] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [13] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [12] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [11] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [10] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [9] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [8] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [7] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [6] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [5] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [4] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [3] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [2] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [1] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [0] is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_external is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_timer is used but has no driver. Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_software is used but has no driver. Found and reported 19 problems. 22.11. Executing OPT pass (performing simple optimizations). 22.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~21 debug messages> 22.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~753 debug messages> Removed a total of 251 cells. 22.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2353. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2366. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2382. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2384. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2399. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2417. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2438. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2463. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2490. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2520. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2553. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2598. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2645. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2693. dead port 1/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2743. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2745. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2795. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2797. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2846. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2905. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2956. dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1698. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1649. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1655. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1661. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1667. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1446. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1448. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1455. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1457. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1464. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1466. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1473. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1475. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1482. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1484. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1491. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1493. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1499. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1505. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1511. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1517. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1523. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1529. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1535. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1541. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1547. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1091. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1097. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1103. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1091. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1097. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1103. Removed 53 multiplexer ports. <suppressed ~142 debug messages> 22.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1961: $auto$opt_reduce.cc:134:opt_pmux$3229 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1975: $auto$opt_reduce.cc:134:opt_pmux$3231 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1993: $auto$opt_reduce.cc:134:opt_pmux$3233 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2042: $auto$opt_reduce.cc:134:opt_pmux$3235 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2068: $auto$opt_reduce.cc:134:opt_pmux$3237 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2085: { $auto$opt_reduce.cc:134:opt_pmux$3241 $auto$opt_reduce.cc:134:opt_pmux$3239 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2113: $auto$opt_reduce.cc:134:opt_pmux$3243 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2133: $auto$opt_reduce.cc:134:opt_pmux$3245 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2136: $auto$opt_reduce.cc:134:opt_pmux$3247 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2143: { $flatten\SOC.\Core.\Control_Unit.$procmux$1996_CMP $auto$opt_reduce.cc:134:opt_pmux$3259 $auto$opt_reduce.cc:134:opt_pmux$3257 $auto$opt_reduce.cc:134:opt_pmux$3255 $auto$opt_reduce.cc:134:opt_pmux$3253 $auto$opt_reduce.cc:134:opt_pmux$3251 $auto$opt_reduce.cc:134:opt_pmux$3249 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3030: { $flatten\SOC.\Core.\ALU_Control.$procmux$3037_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3036_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3035_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3034_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3033_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3032_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3031_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2177: { $flatten\SOC.\Core.\Control_Unit.$procmux$2170_CMP $auto$opt_reduce.cc:134:opt_pmux$3273 $auto$opt_reduce.cc:134:opt_pmux$3271 $auto$opt_reduce.cc:134:opt_pmux$3269 $flatten\SOC.\Core.\Control_Unit.$procmux$2092_CMP $auto$opt_reduce.cc:134:opt_pmux$3267 $flatten\SOC.\Core.\Control_Unit.$procmux$2089_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2088_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2087_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2086_CMP $auto$opt_reduce.cc:134:opt_pmux$3265 $auto$opt_reduce.cc:134:opt_pmux$3263 $auto$opt_reduce.cc:134:opt_pmux$3261 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3053: { $flatten\SOC.\Core.\ALU_Control.$procmux$3055_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3054_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2212: { $auto$opt_reduce.cc:134:opt_pmux$3275 $flatten\SOC.\Core.\Control_Unit.$procmux$2148_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2219: $auto$opt_reduce.cc:134:opt_pmux$3277 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2223: { $flatten\SOC.\Core.\Control_Unit.$procmux$2141_CMP $auto$opt_reduce.cc:134:opt_pmux$3279 $flatten\SOC.\Core.\Control_Unit.$procmux$2129_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2239: $auto$opt_reduce.cc:134:opt_pmux$3281 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2261: $auto$opt_reduce.cc:134:opt_pmux$3283 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2279: $auto$opt_reduce.cc:134:opt_pmux$3285 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2338: $auto$opt_reduce.cc:134:opt_pmux$3287 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2894: { $auto$opt_reduce.cc:134:opt_pmux$3289 $flatten\SOC.\Core.\Control_Unit.$procmux$2902_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2901_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2900_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2899_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2898_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2897_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2896_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2895_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2959: { $flatten\SOC.\Core.\Control_Unit.$procmux$2206_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2175_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2071_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2266_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2048_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2242_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2147_CMP $auto$opt_reduce.cc:134:opt_pmux$3293 $flatten\SOC.\Core.\Control_Unit.$procmux$2099_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2140_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2070_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2047_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2098_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2170_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2046_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2030_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1997_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1996_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2094_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2165_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1995_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2092_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2091_CMP $auto$opt_reduce.cc:134:opt_pmux$3291 $flatten\SOC.\Core.\Control_Unit.$procmux$1963_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1977_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2069_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2044_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2089_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2088_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1994_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2087_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2086_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1962_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$1976_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1701: { $flatten\SOC.\Core.\Control_Unit.$procmux$2899_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2900_CMP $auto$opt_reduce.cc:134:opt_pmux$3297 $flatten\SOC.\Core.\Control_Unit.$procmux$2901_CMP $auto$opt_reduce.cc:134:opt_pmux$3295 $flatten\SOC.\Core.\Control_Unit.$procmux$2895_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2903_CMP } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1646: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1664: Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1670: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1443: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1443_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1443_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1443_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] $flatten\SOC.\Memory.$procmux$1443_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1470: Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Memory.$procmux$1470_Y New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Memory.$procmux$1470_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1470_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] $flatten\SOC.\Memory.$procmux$1470_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1497: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1497_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1497_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1497_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] $flatten\SOC.\Memory.$procmux$1497_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1088: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1088_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1088_Y [0] New connections: $flatten\SOC.\Uart.\RX_FIFO.$procmux$1088_Y [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$procmux$1088_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1088_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1088_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1088_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1088_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1088_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1088_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1088: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1088_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1088_Y [0] New connections: $flatten\SOC.\Uart.\TX_FIFO.$procmux$1088_Y [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$procmux$1088_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1088_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1088_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1088_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1088_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1088_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1088_Y [0] } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1939: { $flatten\SOC.\Core.\Control_Unit.$procmux$1936_CMP $auto$opt_reduce.cc:134:opt_pmux$3299 } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1673: Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$186, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1664_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1676: Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$185, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1646_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1515: Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$965, B=0, Y=$flatten\SOC.\Memory.$procmux$1515_Y New ports: A=$flatten\SOC.\Memory.$procmux$1470_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1515_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1515_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] $flatten\SOC.\Memory.$procmux$1515_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1533: Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$962, B=0, Y=$flatten\SOC.\Memory.$procmux$1533_Y New ports: A=$flatten\SOC.\Memory.$procmux$1443_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1533_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1533_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] $flatten\SOC.\Memory.$procmux$1533_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1568: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$952, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1497_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_EN[31:0]$932 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1106: Old ports: A=$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$888, B=8'00000000, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 New ports: A=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1088_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [0] New connections: $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1106: Old ports: A=$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$888, B=8'00000000, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 New ports: A=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1088_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [0] New connections: $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_EN[7:0]$879 [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1550: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$958, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1515_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_EN[31:0]$938 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1559: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$955, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1533_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_EN[31:0]$935 [0] } Optimizing cells in module \top. Performed a total of 41 changes. 22.11.5. Executing OPT_MERGE pass (detect identical cells). + mkdir -p Risco-5/impl/pnr [Pipeline] sh Finding identical cells in module `\top'. <suppressed ~21 debug messages> Removed a total of 7 cells. 22.11.6. Executing OPT_DFF pass (perform DFF optimizations). 22.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 331 unused wires. <suppressed ~1 debug messages> 22.11.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.11.9. Rerunning OPT passes. (Maybe there is more to do..) 22.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~141 debug messages> 22.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\SOC.\Core.\Alu.$procmux$3058: { $flatten\SOC.\Core.\Alu.$procmux$3072_CMP $flatten\SOC.\Core.\Alu.$procmux$3071_CMP $flatten\SOC.\Core.\Alu.$procmux$3070_CMP $flatten\SOC.\Core.\Alu.$procmux$3069_CMP $auto$opt_reduce.cc:134:opt_pmux$3303 $flatten\SOC.\Core.\Alu.$procmux$3066_CMP $flatten\SOC.\Core.\Alu.$procmux$3065_CMP $flatten\SOC.\Core.\Alu.$procmux$3064_CMP $flatten\SOC.\Core.\Alu.$procmux$3063_CMP $flatten\SOC.\Core.\Alu.$procmux$3062_CMP $flatten\SOC.\Core.\Alu.$procmux$3061_CMP $auto$opt_reduce.cc:134:opt_pmux$3301 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2177: { $flatten\SOC.\Core.\Control_Unit.$procmux$2170_CMP $auto$opt_reduce.cc:134:opt_pmux$3273 $auto$opt_reduce.cc:134:opt_pmux$3271 $auto$opt_reduce.cc:134:opt_pmux$3269 $flatten\SOC.\Core.\Control_Unit.$procmux$2092_CMP $auto$opt_reduce.cc:134:opt_pmux$3267 $auto$opt_reduce.cc:134:opt_pmux$3307 $auto$opt_reduce.cc:134:opt_pmux$3305 $auto$opt_reduce.cc:134:opt_pmux$3265 $auto$opt_reduce.cc:134:opt_pmux$3263 $auto$opt_reduce.cc:134:opt_pmux$3261 } Optimizing cells in module \top. Performed a total of 2 changes. 22.11.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.11.13. Executing OPT_DFF pass (perform DFF optimizations). 22.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.11.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.11.16. Rerunning OPT passes. (Maybe there is more to do..) 22.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~141 debug messages> 22.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.11.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.11.20. Executing OPT_DFF pass (perform DFF optimizations). 22.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.11.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.11.23. Finished OPT passes. (There is nothing left to do.) 22.12. Executing FSM pass (extract and optimize FSM). 22.12.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking top.ResetBootSystem.state as FSM state register: Register has an initialization value. Circuit seems to be self-resetting. Not marking top.SOC.Core.CSR_Unit.csr_mip_mfip as FSM state register: Users of register don't seem to benefit from recoding. Register has an initialization value. Not marking top.SOC.Core.Control_Unit.state as FSM state register: Register has an initialization value. Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state. Not marking top.SOC.Uart.i_uart_tx.fsm_state as FSM state register: Users of register don't seem to benefit from recoding. 22.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'. found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$3110 root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1027_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1040_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1053_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1039_Y found state code: 3'000 found ctrl input: \SOC.Uart.i_uart_rx.next_bit found state code: 3'011 found ctrl input: \SOC.Uart.i_uart_rx.payload_done found state code: 3'010 found state code: 3'001 found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1053_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:143$1044_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1040_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1039_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1027_Y ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o } ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1027_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1039_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1040_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:143$1044_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1053_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] } transition: 3'000 4'0--0 -> 3'001 8'01010001 transition: 3'000 4'1--0 -> 3'000 8'01010000 transition: 3'000 4'---1 -> 3'000 8'01010000 transition: 3'010 4'--00 -> 3'010 8'00100010 transition: 3'010 4'--10 -> 3'011 8'00100011 transition: 3'010 4'---1 -> 3'000 8'00100000 transition: 3'001 4'-0-0 -> 3'001 8'00011001 transition: 3'001 4'-1-0 -> 3'010 8'00011010 transition: 3'001 4'---1 -> 3'000 8'00011000 transition: 3'011 4'-0-0 -> 3'011 8'10010011 transition: 3'011 4'-1-0 -> 3'000 8'10010000 transition: 3'011 4'---1 -> 3'000 8'10010000 22.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3308' from module `\top'. 22.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 7 unused cells and 7 unused wires. <suppressed ~8 debug messages> 22.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3308' from module `\top'. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2]. 22.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3308' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ---1 010 -> --1- 001 -> -1-- 011 -> 1--- 22.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3308' from module `top': ------------------------------------- Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$3308 (\SOC.Uart.i_uart_rx.fsm_state): Number of input signals: 4 Number of output signals: 5 Number of state bits: 4 Input signals: 0: \ResetBootSystem.reset_o 1: \SOC.Uart.i_uart_rx.payload_done 2: \SOC.Uart.i_uart_rx.next_bit 3: \SOC.Uart.i_uart_rx.rxd_reg Output signals: 0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1053_Y 1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:143$1044_Y 2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1040_Y 3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1039_Y 4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1027_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'1--0 -> 0 5'01010 1: 0 4'---1 -> 0 5'01010 2: 0 4'0--0 -> 2 5'01010 3: 1 4'---1 -> 0 5'00100 4: 1 4'--00 -> 1 5'00100 5: 1 4'--10 -> 3 5'00100 6: 2 4'---1 -> 0 5'00011 7: 2 4'-1-0 -> 1 5'00011 8: 2 4'-0-0 -> 2 5'00011 9: 3 4'-1-0 -> 0 5'10010 10: 3 4'---1 -> 0 5'10010 11: 3 4'-0-0 -> 3 5'10010 ------------------------------------- 22.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3308' from module `\top'. 22.13. Executing OPT pass (performing simple optimizations). 22.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5 debug messages> 22.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 22.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~140 debug messages> 22.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.13.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3122 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1372_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1366_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1357_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1348_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1339_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1330_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1312_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1321_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3358 ($sdff) from module top (D = \SOC.Uart.uart_tx_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]). Adding EN signal on $auto$ff.cc:266:slice$3358 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1366_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1357_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1348_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1339_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1330_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1312_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1321_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3120 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1288_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$3363 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1288_Y, Q = \SOC.Uart.i_uart_tx.bit_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3119 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1277_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$3369 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$1007_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3118 ($dff) from module top (D = \SOC.Uart.i_uart_tx.n_fsm_state, Q = \SOC.Uart.i_uart_tx.fsm_state, rval = 3'000). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3117 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1266_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$3374 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1266_Y, Q = \SOC.Uart.i_uart_tx.txd_reg). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3116 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1255_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3380 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3114 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$1232_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1223_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1214_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1205_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1196_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1187_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1169_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1178_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3382 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3113 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1151_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$3386 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1047_Y, Q = \SOC.Uart.i_uart_rx.bit_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3112 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1146_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$3390 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3111 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1138_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$3392 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1058_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3109 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3108 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1). Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$3104 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1115_Y, Q = \SOC.Uart.TX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3398 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$891_Y, Q = \SOC.Uart.TX_FIFO.write_ptr). Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$3103 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1120_Y, Q = \SOC.Uart.TX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3400 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$896_Y [5:0], Q = \SOC.Uart.TX_FIFO.read_ptr). Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$3104 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1115_Y, Q = \SOC.Uart.RX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3402 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$891_Y, Q = \SOC.Uart.RX_FIFO.write_ptr). Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$3103 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1120_Y, Q = \SOC.Uart.RX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3404 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$896_Y [5:0], Q = \SOC.Uart.RX_FIFO.read_ptr). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3151 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1611_Y, Q = \SOC.Uart.rx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3406 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.uart_rx_data, Q = \SOC.Uart.rx_fifo_write_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3150 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1616_Y, Q = \SOC.Uart.tx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3408 ($sdff) from module top (D = { \SOC.Leds.write_data [7:6] \SOC.GPIOS.write_data [5:0] }, Q = \SOC.Uart.tx_fifo_write_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3149 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1621_Y, Q = \SOC.Uart.uart_tx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3410 ($sdff) from module top (D = \SOC.Uart.tx_fifo_read_data, Q = \SOC.Uart.uart_tx_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3147 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1586_Y, Q = \SOC.Uart.rx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3146 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1591_Y, Q = \SOC.Uart.rx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3145 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1596_Y, Q = \SOC.Uart.tx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3143 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1601_Y, Q = \SOC.Uart.uart_tx_en, rval = 1'0). Adding SRST signal on $flatten\SOC.\Leds.$procdff$3142 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$1576_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$3416 ($sdff) from module top (D = { 1'0 \SOC.GPIOS.write_data [31] \SOC.Leds.write_data [30:6] \SOC.GPIOS.write_data [5:0] }, Q = \SOC.Leds.data). Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$3153 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1632_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3418 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_value). Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$3152 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1640_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3422 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_direction). Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$3159 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$1684_Y, Q = \SOC.Core.Pc.Output, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3428 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.Output). Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$3178 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 6'000000). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3174 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1748_Y, Q = \SOC.Core.CSR_Unit.csr_mtval, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3431 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mtval). Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3173 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 1'0 \SOC.Core.CSR_Unit.csr_write_data [0] }, Q = \SOC.Core.CSR_Unit.csr_mtvec). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3172 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1774_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$3444 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3171 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1789_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mie, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$3450 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mstatus_mie). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3170 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1803_Y, Q = \SOC.Core.CSR_Unit.csr_mscratch, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3456 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mscratch). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3169 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1819_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mtie, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$3462 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mie_mtie). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3168 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1835_Y, Q = \SOC.Core.CSR_Unit.csr_mie_msie, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$3468 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mie_msie). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3167 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1851_Y, Q = \SOC.Core.CSR_Unit.csr_mie_meie, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$3474 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [11], Q = \SOC.Core.CSR_Unit.csr_mie_meie). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3166 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1867_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mfie, rval = 16'0000000000000000). Adding EN signal on $auto$ff.cc:266:slice$3480 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [31:16], Q = \SOC.Core.CSR_Unit.csr_mie_mfie). Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3165 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 2'00 }, Q = \SOC.Core.CSR_Unit.csr_mepc). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3164 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1887_Y, Q = \SOC.Core.CSR_Unit.csr_mcause, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3493 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mcause). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3163 ($dff) from module top (D = \SOC.Core.CSR_Unit.interruption_request_software, Q = \SOC.Core.CSR_Unit.csr_mip_msip, rval = 1'0). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3162 ($dff) from module top (D = \SOC.Core.CSR_Unit.interruption_request_timer, Q = \SOC.Core.CSR_Unit.csr_mip_mtip, rval = 1'0). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3161 ($dff) from module top (D = \SOC.Core.CSR_Unit.interruption_request_external, Q = \SOC.Core.CSR_Unit.csr_mip_meip, rval = 1'0). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3160 ($dff) from module top (D = \SOC.Core.CSR_Unit.interruption_request_fast, Q = \SOC.Core.CSR_Unit.csr_mip_mfip, rval = 16'0000000000000000). Adding SRST signal on $flatten\SOC.\Core.$procdff$3132 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1404_Y, Q = \SOC.Core.temp_write_value, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3503 ($sdff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.temp_write_value). Adding SRST signal on $flatten\SOC.\Core.$procdff$3131 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1409_Y, Q = \SOC.Core.temp_reg3, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3505 ($sdff) from module top (D = \SOC.Core.alu_out_register, Q = \SOC.Core.temp_reg3). Adding SRST signal on $flatten\SOC.\Core.$procdff$3130 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1414_Y, Q = \SOC.Core.temp_reg2, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3507 ($sdff) from module top (D = \SOC.Core.memory_register, Q = \SOC.Core.temp_reg2). Adding SRST signal on $flatten\SOC.\Core.$procdff$3129 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1419_Y, Q = \SOC.Core.temp_address, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3509 ($sdff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.temp_address). Adding SRST signal on $flatten\SOC.\Core.$procdff$3128 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1424_Y, Q = \SOC.Core.pc_old, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3511 ($sdff) from module top (D = \SOC.Core.Pc.Output, Q = \SOC.Core.pc_old). Adding SRST signal on $flatten\SOC.\Core.$procdff$3127 ($dff) from module top (D = \SOC.Core.register_data_2_out, Q = \SOC.Core.register_data_2, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$3126 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$3125 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$3124 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$3123 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1429_Y, Q = \SOC.Core.instruction_register, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3517 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register). Adding EN signal on $flatten\ResetBootSystem.$procdff$3177 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter). Adding EN signal on $flatten\ResetBootSystem.$procdff$3176 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state). Adding EN signal on $flatten\ResetBootSystem.$procdff$3175 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o). Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3486 ($dffe) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3486 ($dffe) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3437 ($dffe) from module top. Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$3417 ($sdffe) from module top. 22.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 147 unused cells and 143 unused wires. <suppressed ~148 debug messages> 22.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5 debug messages> 22.13.9. Rerunning OPT passes. (Maybe there is more to do..) 22.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~92 debug messages> 22.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$3388: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o } Optimizing cells in module \top. Performed a total of 1 changes. 22.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~42 debug messages> Removed a total of 14 cells. 22.13.13. Executing OPT_DFF pass (perform DFF optimizations). 22.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 15 unused wires. <suppressed ~2 debug messages> 22.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.13.16. Rerunning OPT passes. (Maybe there is more to do..) 22.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~92 debug messages> 22.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.13.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.13.20. Executing OPT_DFF pass (perform DFF optimizations). 22.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.13.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. + cd Risco-5/fpga/tangnano20k/ + /eda/gowin/IDE/bin/gw_sh run.tcl *** GOWIN Tcl Command Line Console *** current device: GW2AR-18C GW2AR-LV18QN88C8/I7 add new file: "pinout.cst" add new file: "top.sdc" add new file: "main.v" add new file: "../../debug/reset.v" add new file: "../../src/core/alu_control.v" add new file: "../../src/core/alu.v" add new file: "../../src/core/control_unit.v" add new file: "../../src/core/core.v" add new file: "../../src/core/immediate_generator.v" add new file: "../../src/core/mux.v" add new file: "../../src/core/pc.v" add new file: "../../src/core/registers.v" add new file: "../../src/core/csr_unit.v" add new file: "../../src/peripheral/bus.v" add new file: "../../src/peripheral/gpio.v" add new file: "../../src/peripheral/gpios.v" add new file: "../../src/peripheral/leds.v" add new file: "../../src/peripheral/memory.v" add new file: "../../src/peripheral/soc.v" add new file: "../../src/peripheral/uart_rx.v" add new file: "../../src/peripheral/uart_tx.v" add new file: "../../src/peripheral/uart.v" add new file: "../../src/peripheral/fifo.v" GowinSynthesis start Running parser ... Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v' Undeclared symbol 'pc_source', assumed default net type 'wire'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":142) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v' WARN (EX3801) : Parameter 'SET_DIRECTION' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":19) WARN (EX3801) : Parameter 'READ' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":20) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v' WARN (EX3012) : Empty statement in sequential block("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":54) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v' WARN (EX3073) : Port 'resetn_o' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":18) Compiling module 'top'("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":1) Compiling module 'ResetBootSystem'("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":1) WARN (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":37) Compiling module 'Risco_5_SOC(CLOCK_FREQ=27000000,MEMORY_SIZE=2048,MEMORY_FILE="../../software/memory/fpga_test_3.hex")'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":1) WARN (EX3073) : Port 'interrupt_on_hold' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":242) Compiling module 'Core(BOOT_ADDRESS=32'b00000000000000000000000000000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":1) Compiling module 'PC'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v":1) Compiling module 'MUX'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v":1) Compiling module 'Registers'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v":1) Compiling module 'Control_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":1) WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":507) WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":514) WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":527) WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":534) Compiling module 'ALU_Control'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":1) WARN (EX2420) : Latch inferred for net 'aluop_out[3]'; We do not recommend the use of latches in FPGA designs, as they may lead to timing problems("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":60) Compiling module 'Alu'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v":1) Compiling module 'Immediate_Generator'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v":1) Compiling module 'CSR_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":1) WARN (EX3780) : Using initial value of 'csr_mcause_code' since it is never assigned("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":100) WARN (EX2565) : Input 'save_pc' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":242) Compiling module 'Memory(MEMORY_FILE="../../software/memory/fpga_test_3.hex",MEMORY_SIZE=2048)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":1) Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":16) Compiling module 'BUS'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v":1) Compiling module 'LEDs'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":1) WARN (EX3791) : Expression size 33 truncated to fit in target size 32("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":21) Compiling module 'UART(CLOCK_FREQ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v":1) 22.13.23. Finished OPT passes. (There is nothing left to do.) 22.14. Executing WREDUCE pass (reducing word size of cells). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$3183 (SOC.Core.RegisterBank.registers). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$3185 (SOC.Core.RegisterBank.registers). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$meminit$\registers$Risco-5/src/core/registers.v:17$187 (SOC.Core.RegisterBank.registers). Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3180 (SOC.Memory.memory). Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3181 (SOC.Memory.memory). Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3182 (SOC.Memory.memory). Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$967 (SOC.Memory.memory). Removed top 21 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:24$927 (SOC.Memory.memory). Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$3179 (SOC.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$875 (SOC.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$3179 (SOC.Uart.TX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\TX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$875 (SOC.Uart.TX_FIFO.memory). Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$1924_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$662 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$661 ($add). Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$661 ($add). Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$660 ($lt). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$3530 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$3525 ($ne). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:22$900 ($mux). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$1583_CMP0 ($eq). Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Uart.$procmux$1582 ($pmux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1112 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1100 ($mux). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$896 ($mux). Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$895 ($add). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$889 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$871 ($eq). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1112 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1100 ($mux). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$896 ($mux). Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$895 ($add). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$889 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$871 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:113$1036 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:112$1035 ($mux). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:111$1034 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:110$1033 ($mux). Removed top 2 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:103$1028 ($eq). Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:101$1026 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:146$1002 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:131$994 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:129$992 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:127$989 ($ne). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:127$988 ($ne). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:114$984 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:97$979 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:96$978 ($mux). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:95$977 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:94$976 ($mux). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:88$972 ($eq). Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:86$970 ($eq). Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$265 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Bus.$eq$Risco-5/src/peripheral/bus.v:53$194 ($eq). Removed top 24 bits (of 32) from mux cell top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:69$209 ($mux). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Memory.$procmux$1439_CMP0 ($eq). Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1556 ($mux). Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1565 ($mux). Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1574 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\MemoryAddressMUX.$eq$Risco-5/src/core/mux.v:15$144 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$eq$Risco-5/src/core/mux.v:17$146 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$eq$Risco-5/src/core/mux.v:16$145 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$eq$Risco-5/src/core/mux.v:15$144 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$eq$Risco-5/src/core/mux.v:17$146 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$eq$Risco-5/src/core/mux.v:16$145 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$eq$Risco-5/src/core/mux.v:15$144 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:17$146 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:16$145 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:15$144 ($eq). Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2954 ($mux). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2903_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2902_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2901_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2898_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2897_CMP0 ($eq). Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2894 ($pmux). Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2793 ($mux). Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2740 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2691 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2643 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2596 ($mux). Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2551 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2518 ($mux). Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2488 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2461 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2415 ($mux). Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2364 ($mux). Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2266_CMP0 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2242_CMP0 ($eq). Removed top 5 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2175_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2170_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2165_CMP0 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2151_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2149_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2148_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2147_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2145_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2144_CMP0 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2141_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2140_CMP0 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2139_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2138_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2135_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2134_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2129_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2099_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2098_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2094_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2093_CMP0 ($eq). Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2071_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2070_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2048_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2047_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2046_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2030_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1997_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1996_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1995_CMP0 ($eq). Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1939 ($pmux). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1937_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1936_CMP0 ($eq). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:527$81 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:507$75 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:238$54 ($eq). Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:166$41 ($eq). Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:101$38 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3055_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3037_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3036_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3035_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3023 ($mux). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3071_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3070_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3069_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3068_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3061_CMP0 ($eq). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:53$28 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:37$17 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1728_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1721_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1720_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1719_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1718_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1717_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1716_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1715_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1714_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1713_CMP0 ($eq). Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1509 ($mux). Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1527 ($mux). Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1545 ($mux). Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1461 ($mux). Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1488 ($mux). Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$661_Y. Removed top 24 bits (of 32) from wire top.$flatten\SOC.\Bus.$ternary$Risco-5/src/peripheral/bus.v:69$209_Y. Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0]. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:37$17_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:53$28_Y. Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$10\nextstate[5:0]. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$11\nextstate[5:0]. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$13\nextstate[5:0]. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$15\nextstate[5:0]. Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$18\nextstate[5:0]. Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0]. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0]. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0]. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$5\nextstate[5:0]. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$6\nextstate[5:0]. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$7\nextstate[5:0]. Removed top 4 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$8\nextstate[5:0]. Removed top 4 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$9\nextstate[5:0]. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:507$75_Y. Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_ADDR[31:0]$930. Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_ADDR[31:0]$933. Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_ADDR[31:0]$936. Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$922_ADDR[31:0]$950. Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_ADDR[31:0]$953. Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_ADDR[31:0]$956. Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$923_ADDR[31:0]$960. Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$924_ADDR[31:0]$963. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_ADDR[5:0]$877. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_ADDR[5:0]$886. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$895_Y. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$896_Y. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_ADDR[5:0]$877. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$865_ADDR[5:0]$886. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$895_Y. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$896_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:110$1033_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:111$1034_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:112$1035_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:113$1036_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:94$976_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:95$977_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:96$978_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:97$979_Y. 22.15. Executing PEEPOPT pass (run peephole optimizers). 22.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 45 unused wires. <suppressed ~1 debug messages> 22.17. Executing SHARE pass (SAT-based resource sharing). Found 6 cells in module top that may be considered for resource sharing. Analyzing resource sharing options for $flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$875 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\SOC.\Bus.$eq$Risco-5/src/peripheral/bus.v:58$198_Y $flatten\SOC.\Bus.$eq$Risco-5/src/peripheral/bus.v:53$194_Y $flatten\SOC.\Bus.$eq$Risco-5/src/peripheral/bus.v:48$190_Y $flatten\SOC.\Uart.$procmux$1585_CMP $flatten\SOC.\Uart.$procmux$1584_CMP $flatten\SOC.\Uart.$procmux$1583_CMP }. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:24$927 ($memrd): Found 7 activation_patterns using ctrl signal { $flatten\SOC.\Memory.$procmux$1440_CMP $flatten\SOC.\Memory.$procmux$1439_CMP $flatten\SOC.\Memory.$procmux$1438_CMP $flatten\SOC.\Memory.$procmux$1437_CMP \SOC.Memory.option [1:0] \SOC.Memory.memory_write \SOC.Memory.memory_read $flatten\SOC.\Bus.$eq$Risco-5/src/peripheral/bus.v:48$190_Y }. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\RegisterBank.$memrd$\registers$Risco-5/src/core/registers.v:22$169 ($memrd): Found 12 activation_patterns using ctrl signal { $flatten\SOC.\Core.\Alu.$procmux$3061_CMP $flatten\SOC.\Core.\Alu.$procmux$3062_CMP $flatten\SOC.\Core.\Alu.$procmux$3063_CMP $flatten\SOC.\Core.\Alu.$procmux$3064_CMP $flatten\SOC.\Core.\Alu.$procmux$3065_CMP $flatten\SOC.\Core.\Alu.$procmux$3066_CMP $flatten\SOC.\Core.\Alu.$procmux$3069_CMP $flatten\SOC.\Core.\Alu.$procmux$3070_CMP $flatten\SOC.\Core.\Alu.$procmux$3071_CMP $flatten\SOC.\Core.\Alu.$procmux$3072_CMP $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:14$143_Y $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:15$144_Y $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:16$145_Y $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:17$146_Y $auto$opt_reduce.cc:134:opt_pmux$3303 $auto$opt_reduce.cc:134:opt_pmux$3301 }. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$sshr$Risco-5/src/core/alu.v:51$26 ($sshr): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3061_CMP. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:49$25 ($shr): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3062_CMP. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:47$24 ($shl): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3063_CMP. No candidates found. 22.18. Executing TECHMAP pass (map to technology primitives). 22.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 22.18.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~88 debug messages> 22.19. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.20. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.21. Executing TECHMAP pass (map to technology primitives). 22.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 22.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation. Generating RTLIL representation for module `\$__MUL18X18'. Successfully finished Verilog frontend. 22.21.3. Continuing TECHMAP pass. No more expansions possible. <suppressed ~5 debug messages> 22.22. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$661 ($add). creating $macc model for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$750 ($add). creating $macc model for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$749 ($sub). creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14 ($add). creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15 ($sub). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$868 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$890 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$895 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$868 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$890 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$895 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1047 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1058 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:132$996 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$1007 ($add). creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$1007. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:132$996. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1058. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1047. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$895. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$890. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$868. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$895. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$890. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$868. creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15. creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14. creating $alu model for $macc $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$749. creating $alu model for $macc $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$750. creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$661. creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$660 ($lt): new $alu creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:53$27 ($ge): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15. creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:37$16 ($lt): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15. creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$662 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$660. creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23 ($eq): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15. creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$660, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$662: $auto$alumacc.cc:485:replace_alu$3591 creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$661: $auto$alumacc.cc:485:replace_alu$3602 creating $alu cell for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$750: $auto$alumacc.cc:485:replace_alu$3605 creating $alu cell for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$749: $auto$alumacc.cc:485:replace_alu$3608 creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14: $auto$alumacc.cc:485:replace_alu$3611 creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15, $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:53$27, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:37$16, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23: $auto$alumacc.cc:485:replace_alu$3614 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$890: $auto$alumacc.cc:485:replace_alu$3627 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$868: $auto$alumacc.cc:485:replace_alu$3630 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$895: $auto$alumacc.cc:485:replace_alu$3633 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$890: $auto$alumacc.cc:485:replace_alu$3636 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$868: $auto$alumacc.cc:485:replace_alu$3639 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$895: $auto$alumacc.cc:485:replace_alu$3642 creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1047: $auto$alumacc.cc:485:replace_alu$3645 creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1058: $auto$alumacc.cc:485:replace_alu$3648 creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:132$996: $auto$alumacc.cc:485:replace_alu$3651 creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$1007: $auto$alumacc.cc:485:replace_alu$3654 created 16 $alu and 0 $macc cells. 22.23. Executing OPT pass (performing simple optimizations). 22.23.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~3 debug messages> 22.23.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~10 debug messages> Removed a total of 2 cells. 22.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~92 debug messages> 22.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.23.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~9 debug messages> Removed a total of 3 cells. 22.23.6. Executing OPT_DFF pass (perform DFF optimizations). 22.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 14 unused wires. <suppressed ~1 debug messages> 22.23.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.23.9. Rerunning OPT passes. (Maybe there is more to do..) 22.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~92 debug messages> 22.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.23.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.23.13. Executing OPT_DFF pass (perform DFF optimizations). 22.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.23.15. Executing OPT_EXPR pass (perform const folding). Compiling module 'FIFO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":1) Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":15) WARN (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":35) Compiling module 'uart_tool_rx(CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v":10) Compiling module 'uart_tool_tx(CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v":10) Compiling module 'GPIOS(WIDHT=5)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":1) Compiling module 'GPIO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v":1) WARN (EX2565) : Input 'halt' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_external' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_timer' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_software' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_fast[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_fast[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_fast[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_fast[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_fast[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_fast[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_fast[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_fast[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_fast[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_fast[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_fast[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_fast[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_fast[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_fast[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_fast[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) WARN (EX2565) : Input 'interruption_request_fast[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42) NOTE (EX0101) : Current top module is "top" WARN (EX0211) : The output port "interrupt_on_hold" of module "CSR_Unit" has no driver, assigning undriven bits to Z, simulation mismatch possible("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":20) [5%] Running netlist conversion ... WARN (CV0016) : Input reset is unused("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":3) Running device independent optimization ... Optimizing module top. 22.23.16. Finished OPT passes. (There is nothing left to do.) 22.24. Executing MEMORY pass. 22.24.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 22.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 22.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing top.SOC.Core.RegisterBank.registers write port 0. Analyzing top.SOC.Core.RegisterBank.registers write port 1. Analyzing top.SOC.Core.RegisterBank.registers write port 2. Analyzing top.SOC.Memory.memory write port 0. Analyzing top.SOC.Memory.memory write port 1. Analyzing top.SOC.Memory.memory write port 2. Analyzing top.SOC.Uart.RX_FIFO.memory write port 0. Analyzing top.SOC.Uart.TX_FIFO.memory write port 0. 22.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 22.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\SOC.Core.RegisterBank.registers'[0] in module `\top': no output FF found. Checking read port `\SOC.Core.RegisterBank.registers'[1] in module `\top': no output FF found. Checking read port `\SOC.Core.RegisterBank.registers'[2] in module `\top': merging output FF to cell. Write port 0: don't care on collision. Write port 1: non-transparent. Write port 2: non-transparent. Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found. Checking read port `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': no output FF found. Checking read port `\SOC.Uart.TX_FIFO.memory'[0] in module `\top': merging output FF to cell. Write port 0: non-transparent. Checking read port address `\SOC.Core.RegisterBank.registers'[0] in module `\top': address FF has fully-defined init value, not supported. Checking read port address `\SOC.Core.RegisterBank.registers'[1] in module `\top': address FF has fully-defined init value, not supported. Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found. Checking read port address `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': merged address FF to cell. 22.24.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 44 unused wires. <suppressed ~7 debug messages> 22.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating read ports of memory top.SOC.Core.RegisterBank.registers by address: Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address: Merging ports 0, 2 (address 5'00000). Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address: Consolidating write ports of memory top.SOC.Memory.memory by address: Merging ports 0, 1 (address \SOC.Memory.address [12:2]). Merging ports 0, 2 (address \SOC.Memory.address [12:2]). Consolidating write ports of memory top.SOC.Core.RegisterBank.registers using sat-based resource sharing: Checking group clocked with posedge \clk, width 32: ports 0, 1. Common input cone for all EN signals: 13 cells. Size of unconstrained SAT problem: 103 variables, 281 clauses Merging port 1 into port 0. 22.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 22.24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 8 unused cells and 8 unused wires. <suppressed ~9 debug messages> 22.24.10. Executing MEMORY_COLLECT pass (generating $mem cells). 22.25. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.26. Executing MEMORY_LIBMAP pass (mapping memories to cells). mapping memory top.SOC.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_ Extracted data FF from read port 2 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[2] mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_ mapping memory top.SOC.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted addr FF from read port 0 of top.SOC.Uart.RX_FIFO.memory: $\SOC.Uart.RX_FIFO.memory$rdreg[0] mapping memory top.SOC.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of top.SOC.Uart.TX_FIFO.memory: $\SOC.Uart.TX_FIFO.memory$rdreg[0] <suppressed ~1084 debug messages> 22.27. Executing TECHMAP pass (map to technology primitives). 22.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation. Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 22.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ECP5_DP16KD_'. Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'. Successfully finished Verilog frontend. 22.27.3. Continuing TECHMAP pass. Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$644d5a9523079415c07adb2635972ab7c199792d\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$e681eac4f4d255fd22c62075e24df964b44460ba\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$ce64818b7295e613c929df05e44d10b0b69f5382\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$43cebc486abd65f2fd3a78cc09aafb1f075b4e89\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$d569301d4e8795e3936ec17220c388adf669bbc4\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$2f948e4dc9e14ac19149710dd5e10b7283defc0f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$dfb216f5ddf96b641cce67f4783f48d992080c53\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$1b6ba3a81f052ed6ad97f2677a072f9216f4d7a4\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$20b12ad4cb36dc64e089b0b7b569cc62dc1056d0\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$78badcf83728704e0e5edb503cec389bf456e078\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$a8faa7a46110bbacc4488e44214d0cd1790a66a5\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$905216fa396aa162ec9455f9f3a422b77fe82006\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$d795c9831c7b2f07a770247e346e9e8b296fe740\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$0b085a2e4499589260a28f60ba05869edeb014d2\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$cd00e871bf6bf811558e50173c214a2eb80ee2fa\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$7fc87590a4f2efa63de62a1c4bf54c098989bbe1\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$e4580b38b291c797b4ba19791a6bd10a4b40ffd6\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$d63b4cad9ccd4b2aebf7ba8995dee86f86af2b6c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$cc9ff9c7f3c31f0366bfc024e75ef38b2b717df7\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$c26f1b3ea7412126166b31b04d223688e4852547\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$b30a4b611d547df4d37d47f168c663fbda8f59be\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$778eeb7016a9b3b39a969f7f7e690271e3516974\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$ebb41bfb0abcd413f0345424f8d7363b3a84a0e2\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$cff78d4401cacaf3aa3faace760e5d6455420f87\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. No more expansions possible. <suppressed ~1419 debug messages> 22.28. Executing OPT pass (performing simple optimizations). 22.28.1. Executing OPT_EXPR pass (perform const folding). [10%] Optimizing Phase 0 completed [15%] Optimizing Phase 1 completed [25%] Optimizing Phase 2 completed Running inference ... Optimizing module top. <suppressed ~96 debug messages> 22.28.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~15 debug messages> Removed a total of 5 cells. 22.28.3. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $\SOC.Uart.RX_FIFO.memory$rdreg[0] ($dff) from module top (D = $auto$rtlil.cc:2582:Mux$3708, Q = $\SOC.Uart.RX_FIFO.memory$rdreg[0]$q, rval = 3'000). Adding SRST signal on $auto$ff.cc:266:slice$3519 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$1904_Y, Q = \ResetBootSystem.counter, rval = 6'000000). Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3499 ($sdff) from module top. Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3502 ($sdff) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3502 ($sdff) from module top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3502 ($sdff) from module top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$3502 ($sdff) from module top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$3502 ($sdff) from module top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$3502 ($sdff) from module top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$3502 ($sdff) from module top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$3502 ($sdff) from module top. Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$3502 ($sdff) from module top. Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$3502 ($sdff) from module top. Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$3502 ($sdff) from module top. Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$3502 ($sdff) from module top. Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$3502 ($sdff) from module top. Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$3502 ($sdff) from module top. Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$3502 ($sdff) from module top. Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$3502 ($sdff) from module top. 22.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 3 unused cells and 7611 unused wires. <suppressed ~4 debug messages> 22.28.5. Rerunning OPT passes. (Removed registers in this run.) 22.28.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~17 debug messages> 22.28.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.28.8. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$6160 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$3545 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000). 22.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). [30%] Inferring Phase 0 completed [40%] Inferring Phase 1 completed [50%] Inferring Phase 2 completed [55%] Inferring Phase 3 completed Running technical mapping ... Finding unused cells or wires in module \top.. Removed 1 unused cells and 10 unused wires. <suppressed ~2 debug messages> 22.28.10. Rerunning OPT passes. (Removed registers in this run.) 22.28.11. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.28.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.28.13. Executing OPT_DFF pass (perform DFF optimizations). 22.28.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.28.15. Finished fast OPT passes. 22.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 22.30. Executing OPT pass (performing simple optimizations). 22.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$3730: $auto$rtlil.cc:2489:ReduceOr$3724 -> 1'1 Analyzing evaluation results. dead port 2/2 on $mux $flatten\SOC.\Core.\PCSourceMUX.$ternary$Risco-5/src/core/mux.v:15$157. Removed 1 multiplexer ports. <suppressed ~58 debug messages> 22.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$3715: Old ports: A={ \SOC.Memory.buffer [31:16] \SOC.Leds.write_data [15:6] \SOC.GPIOS.write_data [5:0] }, B={ \SOC.GPIOS.write_data [31] \SOC.Leds.write_data [30:6] \SOC.GPIOS.write_data [5:0] }, Y=$auto$rtlil.cc:2582:Mux$3716 New ports: A=\SOC.Memory.buffer [31:16], B={ \SOC.GPIOS.write_data [31] \SOC.Leds.write_data [30:16] }, Y=$auto$rtlil.cc:2582:Mux$3716 [31:16] New connections: $auto$rtlil.cc:2582:Mux$3716 [15:0] = { \SOC.Leds.write_data [15:6] \SOC.GPIOS.write_data [5:0] } New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$1913: { $flatten\ResetBootSystem.$procmux$1908_CMP $flatten\ResetBootSystem.$procmux$1907_CMP } Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1916: Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$1916_Y New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$1916_Y [1] New connections: $flatten\ResetBootSystem.$procmux$1916_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3008: Old ports: A=4'1001, B=4'0011, Y=$flatten\SOC.\Core.\ALU_Control.$5\aluop_out[3:0] New ports: A=2'10, B=2'01, Y={ $flatten\SOC.\Core.\ALU_Control.$5\aluop_out[3:0] [3] $flatten\SOC.\Core.\ALU_Control.$5\aluop_out[3:0] [1] } New connections: { $flatten\SOC.\Core.\ALU_Control.$5\aluop_out[3:0] [2] $flatten\SOC.\Core.\ALU_Control.$5\aluop_out[3:0] [0] } = 2'01 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3023: Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$3547 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3547 [2] New connections: $auto$wreduce.cc:461:run$3547 [1:0] = 2'10 New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1712: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1723_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1722_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1721_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1720_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1719_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1718_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1717_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1716_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1715_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1714_CMP } Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2085: Old ports: A=4'0000, B=8'10001001, Y=\SOC.Core.control_unit_aluop New ports: A=2'00, B=4'1011, Y={ \SOC.Core.control_unit_aluop [3] \SOC.Core.control_unit_aluop [0] } New connections: \SOC.Core.control_unit_aluop [2:1] = 2'00 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2279: Old ports: A=2'00, B=2'10, Y=\SOC.Core.lorD New ports: A=1'0, B=1'1, Y=\SOC.Core.lorD [1] New connections: \SOC.Core.lorD [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2351: Old ports: A=6'101101, B=6'000000, Y=$flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] New connections: $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [5:1] = { $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] 1'0 $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2380: Old ports: A=6'000000, B=6'100101, Y=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] New connections: $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [5:1] = { $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] 2'00 $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2415: Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$3554 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3554 [2] New connections: $auto$wreduce.cc:461:run$3554 [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2436: Old ports: A=6'011111, B=6'100010, Y=$flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] New ports: A=2'01, B=2'10, Y={ $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [5] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] } New connections: $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [4:1] = { $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] 1'1 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2461: Old ports: A=3'110, B=3'011, Y=$auto$wreduce.cc:461:run$3553 [2:0] New ports: A=2'10, B=2'01, Y={ $auto$wreduce.cc:461:run$3553 [2] $auto$wreduce.cc:461:run$3553 [0] } New connections: $auto$wreduce.cc:461:run$3553 [1] = 1'1 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2518: Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$3552 [2:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3552 [2] $auto$wreduce.cc:461:run$3552 [0] } New connections: $auto$wreduce.cc:461:run$3552 [1] = $auto$wreduce.cc:461:run$3552 [0] Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2551: Old ports: A=5'00000, B=5'10010, Y=$auto$wreduce.cc:461:run$3551 [4:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3551 [1] New connections: { $auto$wreduce.cc:461:run$3551 [4:2] $auto$wreduce.cc:461:run$3551 [0] } = { $auto$wreduce.cc:461:run$3551 [1] 3'000 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2596: Old ports: A=3'101, B=3'000, Y=$auto$wreduce.cc:461:run$3563 [2:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3563 [0] New connections: $auto$wreduce.cc:461:run$3563 [2:1] = { $auto$wreduce.cc:461:run$3563 [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2643: Old ports: A=3'110, B=3'000, Y=$auto$wreduce.cc:461:run$3562 [2:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3562 [1] New connections: { $auto$wreduce.cc:461:run$3562 [2] $auto$wreduce.cc:461:run$3562 [0] } = { $auto$wreduce.cc:461:run$3562 [1] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2740: Old ports: A=5'00101, B=5'11000, Y=$auto$wreduce.cc:461:run$3560 [4:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3560 [3] $auto$wreduce.cc:461:run$3560 [0] } New connections: { $auto$wreduce.cc:461:run$3560 [4] $auto$wreduce.cc:461:run$3560 [2:1] } = { $auto$wreduce.cc:461:run$3560 [3] $auto$wreduce.cc:461:run$3560 [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2793: Old ports: A=5'00011, B=5'10110, Y=$auto$wreduce.cc:461:run$3559 [4:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3559 [2] $auto$wreduce.cc:461:run$3559 [0] } New connections: { $auto$wreduce.cc:461:run$3559 [4:3] $auto$wreduce.cc:461:run$3559 [1] } = { $auto$wreduce.cc:461:run$3559 [2] 2'01 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2844: Old ports: A={ 1'0 $auto$wreduce.cc:461:run$3560 [4:0] }, B={ 1'0 $auto$wreduce.cc:461:run$3559 [4:0] }, Y=$auto$wreduce.cc:461:run$3558 New ports: A=$auto$wreduce.cc:461:run$3560 [4:0], B=$auto$wreduce.cc:461:run$3559 [4:0], Y=$auto$wreduce.cc:461:run$3558 [4:0] New connections: $auto$wreduce.cc:461:run$3558 [5] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:101$38: Old ports: A=2'11, B=2'01, Y=\SOC.Core.Control_Unit.second_block_write_src_b [1:0] New ports: A=1'1, B=1'0, Y=\SOC.Core.Control_Unit.second_block_write_src_b [1] New connections: \SOC.Core.Control_Unit.second_block_write_src_b [0] = 1'1 Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1694: Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:20] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] 20'00000000000000000000 \SOC.Core.instruction_register [31:20] 27'000000000000000000000000000 \SOC.Core.instruction_register [24:20] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] New ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:25] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] 1'0 \SOC.Core.instruction_register [31:25] 8'00000000 }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12:5] New connections: { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [31:13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] \SOC.Core.instruction_register [24:20] } Consolidated identical input bits for $pmux cell $flatten\SOC.\Memory.$procmux$1436: Old ports: A=\SOC.Memory.buffer, B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7:0] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:0] 24'000000000000000000000000 \SOC.Memory.buffer [7:0] 16'0000000000000000 \SOC.Memory.buffer [15:0] }, Y=\SOC.Bus.slave_0_read_data New ports: A=\SOC.Memory.buffer [31:8], B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:8] 40'0000000000000000000000000000000000000000 \SOC.Memory.buffer [15:8] }, Y=\SOC.Bus.slave_0_read_data [31:8] New connections: \SOC.Bus.slave_0_read_data [7:0] = \SOC.Memory.buffer [7:0] Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_rx.$procmux$1250: Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$3581 [0] 1'0 $auto$wreduce.cc:461:run$3582 [1:0] 2'01 \SOC.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$3584 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$3581 [0] $auto$wreduce.cc:461:run$3582 [1:0] 1'1 \SOC.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$3584 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state [1:0] New connections: \SOC.Uart.i_uart_rx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:113$1036: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3584 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3584 [0] New connections: $auto$wreduce.cc:461:run$3584 [1] = $auto$wreduce.cc:461:run$3584 [0] Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$1387: Old ports: A=3'000, B={ 2'00 \SOC.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$3586 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$3588 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state New ports: A=2'00, B={ 1'0 \SOC.Uart.uart_tx_en $auto$wreduce.cc:461:run$3586 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$3588 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0] New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:97$979: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3588 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3588 [0] New connections: $auto$wreduce.cc:461:run$3588 [1] = $auto$wreduce.cc:461:run$3588 [0] Optimizing cells in module \top. Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$3719: Old ports: A=$auto$rtlil.cc:2582:Mux$3716, B={ \SOC.Memory.buffer [31:8] \SOC.Leds.write_data [7:6] \SOC.GPIOS.write_data [5:0] }, Y=$auto$rtlil.cc:2582:Mux$3720 New ports: A={ $auto$rtlil.cc:2582:Mux$3716 [31:16] \SOC.Leds.write_data [15:8] }, B=\SOC.Memory.buffer [31:8], Y=$auto$rtlil.cc:2582:Mux$3720 [31:8] New connections: $auto$rtlil.cc:2582:Mux$3720 [7:0] = { \SOC.Leds.write_data [7:6] \SOC.GPIOS.write_data [5:0] } Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1922: Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$1916_Y, Y=$flatten\ResetBootSystem.$procmux$1922_Y New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$1916_Y [1], Y=$flatten\ResetBootSystem.$procmux$1922_Y [1] New connections: $flatten\ResetBootSystem.$procmux$1922_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2397: Old ports: A=6'100001, B=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0], Y=$flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] New ports: A=2'01, B={ $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] }, Y={ $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [2] $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [0] } New connections: { $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [5:3] $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [1] } = { $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [0] 3'000 } Optimizing cells in module \top. Performed a total of 33 changes. 22.30.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~9 debug messages> Removed a total of 3 cells. 22.30.6. Executing OPT_DFF pass (perform DFF optimizations). 22.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 5 unused wires. <suppressed ~2 debug messages> 22.30.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~8 debug messages> 22.30.9. Rerunning OPT passes. (Maybe there is more to do..) 22.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $flatten\SOC.\Core.\MemoryAddressMUX.$ternary$Risco-5/src/core/mux.v:16$156. Removed 1 multiplexer ports. <suppressed ~60 debug messages> 22.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2844: Old ports: A={ $auto$wreduce.cc:461:run$3559 [4] $auto$wreduce.cc:461:run$3559 [4] $auto$wreduce.cc:461:run$3559 [0] 1'0 $auto$wreduce.cc:461:run$3559 [0] }, B={ $auto$wreduce.cc:461:run$3559 [4] 1'0 $auto$wreduce.cc:461:run$3559 [4] 1'1 $auto$wreduce.cc:461:run$3559 [0] }, Y=$auto$wreduce.cc:461:run$3558 [4:0] New ports: A={ $auto$wreduce.cc:461:run$3559 [4] $auto$wreduce.cc:461:run$3559 [0] 1'0 }, B={ 1'0 $auto$wreduce.cc:461:run$3559 [4] 1'1 }, Y=$auto$wreduce.cc:461:run$3558 [3:1] New connections: { $auto$wreduce.cc:461:run$3558 [4] $auto$wreduce.cc:461:run$3558 [0] } = { $auto$wreduce.cc:461:run$3559 [4] $auto$wreduce.cc:461:run$3559 [0] } Optimizing cells in module \top. Performed a total of 1 changes. 22.30.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.30.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3373 ($sdff) from module top. 22.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 7 unused wires. <suppressed ~1 debug messages> 22.30.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~2 debug messages> 22.30.16. Rerunning OPT passes. (Maybe there is more to do..) 22.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~61 debug messages> 22.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.30.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.30.20. Executing OPT_DFF pass (perform DFF optimizations). 22.30.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.30.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.30.23. Finished OPT passes. (There is nothing left to do.) 22.31. Executing TECHMAP pass (map to technology primitives). 22.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 22.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ecp5_alu'. Successfully finished Verilog frontend. 22.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $eq. Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $reduce_bool. Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu. Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu. Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux. Using extmapper simplemap for cells of type $bmux. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $or. Using template $paramod$bf541dd3c0ba8228982b61e7bfbc350a2c253f4c\_90_demux for cells of type $demux. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $sdffce. Using extmapper simplemap for cells of type $and. Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $tribuf. Using extmapper simplemap for cells of type $logic_and. Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $sdff. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_or. Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux. Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu. Using template $paramod$19e9557905baa9d3741d0daa66e2ef076e9bab7d\_90_pmux for cells of type $pmux. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. Using template $paramod$2116a631f856d4d4902c2618dca73dafa3b8c9c0\_90_alu for cells of type $alu. Using template $paramod$4d45682f6d5f8751d24fc75184ef72226da353f7\_90_pmux for cells of type $pmux. Using template $paramod$382ee18765329ac2a4237df67c8ed074f3b7e946\_90_pmux for cells of type $pmux. Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux. Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux. Using template $paramod$e25898cce02b4d043ab08e065e45db8cf66c901c\_90_pmux for cells of type $pmux. Using template $paramod$a285b5a57fe61eabc57c91b8c412748ee1151a85\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $reduce_xor. Using template $paramod$95ab7b964273918a033d1324366ecc612d202989\_90_pmux for cells of type $pmux. Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\_90_pmux for cells of type $pmux. Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $dlatch. Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$f5c0c5233796d8af9071458034942fe6bc61211e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr. Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$56955d0f36f77738c952d3505dc563df3ee11b94\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr. Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod$ed6389a5938b09f91843a91d67becca5abedb1bd\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $xor. Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux. Using template $paramod$104d3d1e82b09b030a785dad8a5e608a6d4401f7\_90_pmux for cells of type $pmux. Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. [60%] Tech-Mapping Phase 0 completed [65%] Tech-Mapping Phase 1 completed [75%] Tech-Mapping Phase 2 completed Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. Using template $paramod$e4e871699ef984d49b67460a907fd39b385c5c53\_90_demux for cells of type $demux. Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux. Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux. No more expansions possible. <suppressed ~4121 debug messages> 22.32. Executing OPT pass (performing simple optimizations). 22.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~8836 debug messages> 22.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~3969 debug messages> Removed a total of 1323 cells. 22.32.3. Executing OPT_DFF pass (perform DFF optimizations). 22.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 191 unused cells and 3027 unused wires. <suppressed ~192 debug messages> 22.32.5. Finished fast OPT passes. 22.33. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 22.35. Executing TECHMAP pass (map to technology primitives). 22.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 22.35.2. Continuing TECHMAP pass. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_. Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_. Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_. No more expansions possible. <suppressed ~819 debug messages> 22.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~19 debug messages> 22.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 22.38. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in top. 22.39. Executing ATTRMVCP pass (move or copy attributes). 22.40. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 4005 unused wires. <suppressed ~1 debug messages> 22.41. Executing TECHMAP pass (map to technology primitives). 22.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 22.41.2. Continuing TECHMAP pass. 22.41.3. Executing SIMPLEMAP pass (map simple cells to gate primitives). Mapping \$_DLATCH_N_.$ternary$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$30765 ($mux). Mapping \$_DLATCH_N_.$logic_not$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$30764 ($logic_not). <suppressed ~4 debug messages> 22.41.4. Executing OPT pass (performing simple optimizations). 22.41.4.1. Executing OPT_EXPR pass (perform const folding). Optimizing module \$_DLATCH_N_. <suppressed ~1 debug messages> 22.41.4.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\$_DLATCH_N_'. Removed a total of 0 cells. 22.41.4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \$_DLATCH_N_.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 22.41.4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \$_DLATCH_N_. Performed a total of 0 changes. 22.41.4.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\$_DLATCH_N_'. Removed a total of 0 cells. 22.41.4.6. Executing OPT_DFF pass (perform DFF optimizations). 22.41.4.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \$_DLATCH_N_.. Removed 1 unused cells and 2 unused wires. <suppressed ~2 debug messages> 22.41.4.8. Executing OPT_EXPR pass (perform const folding). Optimizing module \$_DLATCH_N_. 22.41.4.9. Rerunning OPT passes. (Maybe there is more to do..) 22.41.4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \$_DLATCH_N_.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 22.41.4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \$_DLATCH_N_. Performed a total of 0 changes. 22.41.4.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\$_DLATCH_N_'. Removed a total of 0 cells. 22.41.4.13. Executing OPT_DFF pass (perform DFF optimizations). 22.41.4.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \$_DLATCH_N_.. 22.41.4.15. Executing OPT_EXPR pass (perform const folding). Optimizing module \$_DLATCH_N_. 22.41.4.16. Finished OPT passes. (There is nothing left to do.) ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source run.tcl # read_verilog "main.v" Using template \$_DLATCH_N_ for cells of type $_DLATCH_N_. No more expansions possible. <suppressed ~4 debug messages> 22.42. Executing ABC9 pass. 22.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.3. Executing PROC pass (convert processes to netlists). 22.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30869'. Cleaned up 1 empty switch. 22.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30870 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.3.4. Executing PROC_INIT pass (extract init attributes). 22.42.3.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30870'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30868_EN[3:0]$30875 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30868_DATA[3:0]$30876 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30868_ADDR[3:0]$30874 Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30869'. 22.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30864_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30859_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30853_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30861_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30857_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30856_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30852_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30862_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30865_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30860_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30855_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30866_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30854_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30863_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30867_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30858_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30868_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30870'. created $dff cell `$procdff$30920' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30868_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30870'. created $dff cell `$procdff$30921' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30868_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30870'. created $dff cell `$procdff$30922' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30869'. created direct connection (no actual register cell created). 22.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30894'. Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30870'. Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30869'. Cleaned up 1 empty switch. 22.42.3.12. Executing OPT_EXPR pass (perform const folding). 22.42.4. Executing PROC pass (convert processes to netlists). 22.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30940'. Cleaned up 1 empty switch. 22.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30941 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.4.4. Executing PROC_INIT pass (extract init attributes). 22.42.4.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30941'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30939_EN[3:0]$30946 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30939_DATA[3:0]$30947 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30939_ADDR[3:0]$30945 Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30940'. 22.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30923_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30937_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30938_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30933_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30928_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30932_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30927_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30924_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30930_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30936_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30935_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30925_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30931_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30929_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30934_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30926_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30939_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30941'. created $dff cell `$procdff$30991' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30939_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30941'. created $dff cell `$procdff$30992' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30939_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30941'. created $dff cell `$procdff$30993' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30940'. created direct connection (no actual register cell created). 22.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30965'. Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30941'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30940'. Cleaned up 1 empty switch. 22.42.4.12. Executing OPT_EXPR pass (perform const folding). 22.42.5. Executing PROC pass (convert processes to netlists). 22.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31011'. Cleaned up 1 empty switch. 22.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31012 in module $paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.5.4. Executing PROC_INIT pass (extract init attributes). 22.42.5.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.5.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. Creating decoders for process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31012'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31010_EN[3:0]$31017 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31010_DATA[3:0]$31016 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31010_ADDR[3:0]$31018 Creating decoders for process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31011'. 22.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.\i' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31006_EN' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31000_EN' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30994_EN' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31005_EN' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31004_EN' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30999_EN' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31009_EN' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30998_EN' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31008_EN' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31007_EN' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31003_EN' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31002_EN' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31001_EN' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30997_EN' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30996_EN' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30995_EN' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31010_DATA' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31012'. created $dff cell `$procdff$31062' with positive edge clock. Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31010_EN' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31012'. created $dff cell `$procdff$31063' with positive edge clock. Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31010_ADDR' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31012'. created $dff cell `$procdff$31064' with positive edge clock. Creating register for signal `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.\muxwre' using process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31011'. created direct connection (no actual register cell created). 22.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31036'. Found and cleaned up 1 empty switch in `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31012'. Removing empty process `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31011'. Cleaned up 1 empty switch. 22.42.5.12. Executing OPT_EXPR pass (perform const folding). 22.42.6. Executing PROC pass (convert processes to netlists). 22.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31082'. Cleaned up 1 empty switch. 22.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31083 in module $paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.6.4. Executing PROC_INIT pass (extract init attributes). 22.42.6.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.6.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. Creating decoders for process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31083'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31081_EN[3:0]$31088 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31081_DATA[3:0]$31089 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31081_ADDR[3:0]$31087 Creating decoders for process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31082'. 22.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.\i' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31080_EN' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31075_EN' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31074_EN' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31069_EN' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31079_EN' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31068_EN' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31078_EN' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31077_EN' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31073_EN' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31072_EN' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31071_EN' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31067_EN' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31066_EN' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31065_EN' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31076_EN' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31070_EN' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31081_ADDR' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31083'. created $dff cell `$procdff$31133' with positive edge clock. Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31081_EN' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31083'. created $dff cell `$procdff$31134' with positive edge clock. Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31081_DATA' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31083'. created $dff cell `$procdff$31135' with positive edge clock. Creating register for signal `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31082'. created direct connection (no actual register cell created). 22.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31107'. Found and cleaned up 1 empty switch in `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31083'. Removing empty process `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31082'. Cleaned up 1 empty switch. 22.42.6.12. Executing OPT_EXPR pass (perform const folding). 22.42.7. Executing PROC pass (convert processes to netlists). 22.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31153'. Cleaned up 1 empty switch. 22.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31154 in module $paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.7.4. Executing PROC_INIT pass (extract init attributes). 22.42.7.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.7.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. Creating decoders for process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31154'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31152_EN[3:0]$31160 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31152_DATA[3:0]$31158 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31152_ADDR[3:0]$31159 Creating decoders for process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31153'. 22.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.\i' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. created direct connection (no actual register cell created). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31151_EN' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. created direct connection (no actual register cell created). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31150_EN' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. created direct connection (no actual register cell created). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31145_EN' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. created direct connection (no actual register cell created). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31144_EN' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. created direct connection (no actual register cell created). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31139_EN' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. created direct connection (no actual register cell created). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31149_EN' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. created direct connection (no actual register cell created). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31138_EN' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. created direct connection (no actual register cell created). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31148_EN' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. created direct connection (no actual register cell created). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31147_EN' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. created direct connection (no actual register cell created). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31143_EN' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. created direct connection (no actual register cell created). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31142_EN' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. created direct connection (no actual register cell created). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31141_EN' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. created direct connection (no actual register cell created). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31137_EN' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. created direct connection (no actual register cell created). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31136_EN' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. created direct connection (no actual register cell created). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31146_EN' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. created direct connection (no actual register cell created). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31140_EN' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. created direct connection (no actual register cell created). Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31152_DATA' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31154'. created $dff cell `$procdff$31204' with positive edge clock. Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31152_ADDR' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31154'. created $dff cell `$procdff$31205' with positive edge clock. Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31152_EN' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31154'. created $dff cell `$procdff$31206' with positive edge clock. Creating register for signal `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31153'. created direct connection (no actual register cell created). 22.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31178'. Found and cleaned up 1 empty switch in `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31154'. Removing empty process `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31153'. Cleaned up 1 empty switch. 22.42.7.12. Executing OPT_EXPR pass (perform const folding). 22.42.8. Executing PROC pass (convert processes to netlists). 22.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31224'. Cleaned up 1 empty switch. 22.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31225 in module $paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.8.4. Executing PROC_INIT pass (extract init attributes). 22.42.8.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.8.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. Creating decoders for process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31225'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31223_EN[3:0]$31229 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31223_DATA[3:0]$31231 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31223_ADDR[3:0]$31230 Creating decoders for process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31224'. 22.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.\i' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31221_EN' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31220_EN' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31215_EN' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31214_EN' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31209_EN' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31219_EN' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31208_EN' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31218_EN' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31213_EN' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31212_EN' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31211_EN' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31222_EN' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31216_EN' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31210_EN' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31207_EN' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31217_EN' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. created direct connection (no actual register cell created). Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31223_EN' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31225'. created $dff cell `$procdff$31275' with positive edge clock. Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31223_ADDR' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31225'. created $dff cell `$procdff$31276' with positive edge clock. Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31223_DATA' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31225'. created $dff cell `$procdff$31277' with positive edge clock. Creating register for signal `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.\muxwre' using process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31224'. created direct connection (no actual register cell created). 22.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31249'. Found and cleaned up 1 empty switch in `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31225'. Removing empty process `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31224'. Cleaned up 1 empty switch. 22.42.8.12. Executing OPT_EXPR pass (perform const folding). 22.42.9. Executing PROC pass (convert processes to netlists). 22.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31295'. Cleaned up 1 empty switch. 22.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31296 in module $paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.9.4. Executing PROC_INIT pass (extract init attributes). 22.42.9.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.9.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. Creating decoders for process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31296'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31294_EN[3:0]$31300 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31294_DATA[3:0]$31301 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31294_ADDR[3:0]$31302 Creating decoders for process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31295'. 22.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.\i' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31291_EN' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31290_EN' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31285_EN' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31284_EN' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31279_EN' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31293_EN' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31289_EN' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31288_EN' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31287_EN' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31283_EN' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31282_EN' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31281_EN' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31292_EN' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31286_EN' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31280_EN' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31278_EN' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31294_EN' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31296'. created $dff cell `$procdff$31346' with positive edge clock. Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31294_DATA' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31296'. created $dff cell `$procdff$31347' with positive edge clock. Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31294_ADDR' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31296'. created $dff cell `$procdff$31348' with positive edge clock. Creating register for signal `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.\muxwre' using process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31295'. created direct connection (no actual register cell created). 22.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31320'. Found and cleaned up 1 empty switch in `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31296'. Removing empty process `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31295'. Cleaned up 1 empty switch. 22.42.9.12. Executing OPT_EXPR pass (perform const folding). 22.42.10. Executing PROC pass (convert processes to netlists). 22.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31366'. Cleaned up 1 empty switch. 22.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31367 in module $paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.10.4. Executing PROC_INIT pass (extract init attributes). 22.42.10.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.10.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. Creating decoders for process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31367'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31365_EN[3:0]$31371 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31365_DATA[3:0]$31372 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31365_ADDR[3:0]$31373 Creating decoders for process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31366'. 22.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.\i' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31349_EN' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31361_EN' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31360_EN' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31355_EN' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31354_EN' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31364_EN' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31363_EN' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31359_EN' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31358_EN' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31357_EN' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31353_EN' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31352_EN' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31351_EN' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31362_EN' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31356_EN' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31350_EN' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31365_EN' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31367'. created $dff cell `$procdff$31417' with positive edge clock. Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31365_DATA' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31367'. created $dff cell `$procdff$31418' with positive edge clock. Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31365_ADDR' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31367'. created $dff cell `$procdff$31419' with positive edge clock. Creating register for signal `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.\muxwre' using process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31366'. created direct connection (no actual register cell created). 22.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31391'. Found and cleaned up 1 empty switch in `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31367'. Removing empty process `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31366'. Cleaned up 1 empty switch. 22.42.10.12. Executing OPT_EXPR pass (perform const folding). 22.42.11. Executing PROC pass (convert processes to netlists). 22.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31437'. Cleaned up 1 empty switch. 22.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31438 in module $paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.11.4. Executing PROC_INIT pass (extract init attributes). 22.42.11.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.11.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. Creating decoders for process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31438'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31436_EN[3:0]$31442 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31436_DATA[3:0]$31443 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31436_ADDR[3:0]$31444 Creating decoders for process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31437'. 22.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.\i' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. created direct connection (no actual register cell created). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31432_EN' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. created direct connection (no actual register cell created). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31431_EN' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. created direct connection (no actual register cell created). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31430_EN' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. created direct connection (no actual register cell created). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31425_EN' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. created direct connection (no actual register cell created). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31435_EN' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. created direct connection (no actual register cell created). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31424_EN' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. created direct connection (no actual register cell created). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31434_EN' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. created direct connection (no actual register cell created). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31433_EN' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. created direct connection (no actual register cell created). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31429_EN' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. created direct connection (no actual register cell created). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31428_EN' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. created direct connection (no actual register cell created). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31427_EN' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. created direct connection (no actual register cell created). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31423_EN' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. created direct connection (no actual register cell created). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31422_EN' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. created direct connection (no actual register cell created). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31421_EN' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. created direct connection (no actual register cell created). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31420_EN' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. created direct connection (no actual register cell created). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31426_EN' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. created direct connection (no actual register cell created). Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31436_EN' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31438'. created $dff cell `$procdff$31488' with positive edge clock. Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31436_DATA' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31438'. created $dff cell `$procdff$31489' with positive edge clock. Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31436_ADDR' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31438'. created $dff cell `$procdff$31490' with positive edge clock. Creating register for signal `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.\muxwre' using process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31437'. created direct connection (no actual register cell created). 22.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31462'. Found and cleaned up 1 empty switch in `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31438'. Removing empty process `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31437'. Cleaned up 1 empty switch. 22.42.11.12. Executing OPT_EXPR pass (perform const folding). 22.42.12. Executing PROC pass (convert processes to netlists). 22.42.12.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31508'. Cleaned up 1 empty switch. 22.42.12.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31509 in module $paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.12.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.12.4. Executing PROC_INIT pass (extract init attributes). 22.42.12.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.12.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.12.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. Creating decoders for process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31509'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31507_EN[3:0]$31515 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31507_DATA[3:0]$31514 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31507_ADDR[3:0]$31513 Creating decoders for process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31508'. 22.42.12.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.12.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31495_EN' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31500_EN' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.\i' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31501_EN' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31506_EN' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31502_EN' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31496_EN' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31505_EN' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31494_EN' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31504_EN' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31503_EN' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31499_EN' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31498_EN' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31497_EN' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31493_EN' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31492_EN' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31491_EN' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31507_ADDR' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31509'. created $dff cell `$procdff$31559' with positive edge clock. Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31507_DATA' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31509'. created $dff cell `$procdff$31560' with positive edge clock. Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31507_EN' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31509'. created $dff cell `$procdff$31561' with positive edge clock. Creating register for signal `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.\muxwre' using process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31508'. created direct connection (no actual register cell created). 22.42.12.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.12.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31533'. Found and cleaned up 1 empty switch in `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31509'. Removing empty process `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31508'. Cleaned up 1 empty switch. 22.42.12.12. Executing OPT_EXPR pass (perform const folding). 22.42.13. Executing PROC pass (convert processes to netlists). 22.42.13.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31579'. Cleaned up 1 empty switch. 22.42.13.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31580 in module $paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.13.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.13.4. Executing PROC_INIT pass (extract init attributes). 22.42.13.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.13.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.13.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. Creating decoders for process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31580'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31578_EN[3:0]$31585 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31578_DATA[3:0]$31584 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31578_ADDR[3:0]$31586 Creating decoders for process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31579'. 22.42.13.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.13.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.\i' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. created direct connection (no actual register cell created). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31562_EN' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. created direct connection (no actual register cell created). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31563_EN' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. created direct connection (no actual register cell created). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31567_EN' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. created direct connection (no actual register cell created). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31568_EN' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. created direct connection (no actual register cell created). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31569_EN' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. created direct connection (no actual register cell created). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31573_EN' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. created direct connection (no actual register cell created). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31574_EN' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. created direct connection (no actual register cell created). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31564_EN' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. created direct connection (no actual register cell created). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31575_EN' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. created direct connection (no actual register cell created). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31565_EN' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. created direct connection (no actual register cell created). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31570_EN' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. created direct connection (no actual register cell created). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31571_EN' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. created direct connection (no actual register cell created). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31576_EN' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. created direct connection (no actual register cell created). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31577_EN' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. created direct connection (no actual register cell created). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31572_EN' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. created direct connection (no actual register cell created). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31566_EN' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. created direct connection (no actual register cell created). Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31578_DATA' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31580'. created $dff cell `$procdff$31630' with positive edge clock. Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31578_EN' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31580'. created $dff cell `$procdff$31631' with positive edge clock. Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31578_ADDR' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31580'. created $dff cell `$procdff$31632' with positive edge clock. Creating register for signal `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.\muxwre' using process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31579'. created direct connection (no actual register cell created). 22.42.13.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.13.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31604'. Found and cleaned up 1 empty switch in `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31580'. Removing empty process `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31579'. Cleaned up 1 empty switch. 22.42.13.12. Executing OPT_EXPR pass (perform const folding). 22.42.14. Executing PROC pass (convert processes to netlists). 22.42.14.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31650'. Cleaned up 1 empty switch. 22.42.14.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31651 in module $paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.14.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.14.4. Executing PROC_INIT pass (extract init attributes). 22.42.14.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.14.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.14.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. Creating decoders for process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31651'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31649_EN[3:0]$31655 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31649_DATA[3:0]$31657 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31649_ADDR[3:0]$31656 Creating decoders for process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31650'. 22.42.14.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.14.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.\i' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31646_EN' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31641_EN' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31636_EN' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31633_EN' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31637_EN' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31638_EN' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31642_EN' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31634_EN' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31643_EN' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31647_EN' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31639_EN' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31648_EN' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31635_EN' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31644_EN' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31640_EN' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31645_EN' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. created direct connection (no actual register cell created). Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31649_EN' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31651'. created $dff cell `$procdff$31701' with positive edge clock. Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31649_ADDR' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31651'. created $dff cell `$procdff$31702' with positive edge clock. Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31649_DATA' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31651'. created $dff cell `$procdff$31703' with positive edge clock. Creating register for signal `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.\muxwre' using process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31650'. created direct connection (no actual register cell created). 22.42.14.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.14.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31675'. Found and cleaned up 1 empty switch in `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31651'. Removing empty process `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31650'. Cleaned up 1 empty switch. 22.42.14.12. Executing OPT_EXPR pass (perform const folding). 22.42.15. Executing PROC pass (convert processes to netlists). 22.42.15.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31721'. Cleaned up 1 empty switch. 22.42.15.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31722 in module $paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.15.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.15.4. Executing PROC_INIT pass (extract init attributes). 22.42.15.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.15.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.15.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. Creating decoders for process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31722'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31720_EN[3:0]$31728 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31720_DATA[3:0]$31726 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31720_ADDR[3:0]$31727 Creating decoders for process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31721'. 22.42.15.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.15.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.\i' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. created direct connection (no actual register cell created). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31713_EN' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. created direct connection (no actual register cell created). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31712_EN' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. created direct connection (no actual register cell created). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31708_EN' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. created direct connection (no actual register cell created). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31707_EN' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. created direct connection (no actual register cell created). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31718_EN' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. created direct connection (no actual register cell created). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31710_EN' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. created direct connection (no actual register cell created). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31714_EN' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. created direct connection (no actual register cell created). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31719_EN' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. created direct connection (no actual register cell created). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31709_EN' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. created direct connection (no actual register cell created). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31715_EN' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. created direct connection (no actual register cell created). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31705_EN' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. created direct connection (no actual register cell created). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31716_EN' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. created direct connection (no actual register cell created). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31717_EN' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. created direct connection (no actual register cell created). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31711_EN' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. created direct connection (no actual register cell created). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31706_EN' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. created direct connection (no actual register cell created). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31704_EN' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. created direct connection (no actual register cell created). Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31720_DATA' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31722'. created $dff cell `$procdff$31772' with positive edge clock. Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31720_ADDR' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31722'. created $dff cell `$procdff$31773' with positive edge clock. Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31720_EN' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31722'. created $dff cell `$procdff$31774' with positive edge clock. Creating register for signal `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.\muxwre' using process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31721'. created direct connection (no actual register cell created). 22.42.15.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.15.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31746'. Found and cleaned up 1 empty switch in `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31722'. Removing empty process `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31721'. Cleaned up 1 empty switch. 22.42.15.12. Executing OPT_EXPR pass (perform const folding). 22.42.16. Executing PROC pass (convert processes to netlists). 22.42.16.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31792'. Cleaned up 1 empty switch. 22.42.16.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31793 in module $paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.16.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.16.4. Executing PROC_INIT pass (extract init attributes). 22.42.16.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.16.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.16.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. Creating decoders for process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31793'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31791_EN[3:0]$31799 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31791_DATA[3:0]$31797 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31791_ADDR[3:0]$31798 Creating decoders for process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31792'. 22.42.16.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.16.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.\i' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. created direct connection (no actual register cell created). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31780_EN' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. created direct connection (no actual register cell created). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31775_EN' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. created direct connection (no actual register cell created). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31779_EN' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. created direct connection (no actual register cell created). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31777_EN' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. created direct connection (no actual register cell created). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31778_EN' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. created direct connection (no actual register cell created). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31787_EN' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. created direct connection (no actual register cell created). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31783_EN' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. created direct connection (no actual register cell created). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31784_EN' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. created direct connection (no actual register cell created). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31785_EN' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. created direct connection (no actual register cell created). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31781_EN' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. created direct connection (no actual register cell created). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31789_EN' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. created direct connection (no actual register cell created). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31790_EN' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. created direct connection (no actual register cell created). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31786_EN' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. created direct connection (no actual register cell created). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31788_EN' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. created direct connection (no actual register cell created). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31782_EN' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. created direct connection (no actual register cell created). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31776_EN' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. created direct connection (no actual register cell created). Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31791_DATA' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31793'. created $dff cell `$procdff$31843' with positive edge clock. Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31791_ADDR' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31793'. created $dff cell `$procdff$31844' with positive edge clock. Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31791_EN' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31793'. created $dff cell `$procdff$31845' with positive edge clock. Creating register for signal `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.\muxwre' using process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31792'. created direct connection (no actual register cell created). 22.42.16.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.16.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31817'. Found and cleaned up 1 empty switch in `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31793'. Removing empty process `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31792'. Cleaned up 1 empty switch. 22.42.16.12. Executing OPT_EXPR pass (perform const folding). 22.42.17. Executing PROC pass (convert processes to netlists). 22.42.17.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31863'. Cleaned up 1 empty switch. 22.42.17.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31864 in module $paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.17.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.17.4. Executing PROC_INIT pass (extract init attributes). 22.42.17.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.17.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.17.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. Creating decoders for process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31864'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31862_EN[3:0]$31870 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31862_DATA[3:0]$31868 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31862_ADDR[3:0]$31869 Creating decoders for process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31863'. 22.42.17.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.17.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.\i' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31853_EN' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31857_EN' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31849_EN' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31858_EN' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31852_EN' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31850_EN' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31854_EN' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31848_EN' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31855_EN' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31859_EN' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31860_EN' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31847_EN' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31846_EN' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31861_EN' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31856_EN' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31851_EN' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31862_DATA' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31864'. created $dff cell `$procdff$31914' with positive edge clock. Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31862_ADDR' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31864'. created $dff cell `$procdff$31915' with positive edge clock. Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31862_EN' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31864'. created $dff cell `$procdff$31916' with positive edge clock. Creating register for signal `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31863'. created direct connection (no actual register cell created). 22.42.17.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.17.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31888'. Found and cleaned up 1 empty switch in `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31864'. Removing empty process `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31863'. Cleaned up 1 empty switch. 22.42.17.12. Executing OPT_EXPR pass (perform const folding). 22.42.18. Executing PROC pass (convert processes to netlists). 22.42.18.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31934'. Cleaned up 1 empty switch. 22.42.18.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31935 in module $paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.18.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.18.4. Executing PROC_INIT pass (extract init attributes). 22.42.18.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.18.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.18.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. Creating decoders for process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31935'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31933_EN[3:0]$31941 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31933_DATA[3:0]$31940 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31933_ADDR[3:0]$31939 Creating decoders for process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31934'. 22.42.18.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.18.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.\i' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31923_EN' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31928_EN' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31927_EN' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31922_EN' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31931_EN' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31919_EN' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31930_EN' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31926_EN' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31920_EN' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31921_EN' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31925_EN' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31929_EN' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31918_EN' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31917_EN' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31932_EN' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31924_EN' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. created direct connection (no actual register cell created). Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31933_ADDR' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31935'. created $dff cell `$procdff$31985' with positive edge clock. Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31933_DATA' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31935'. created $dff cell `$procdff$31986' with positive edge clock. Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31933_EN' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31935'. created $dff cell `$procdff$31987' with positive edge clock. Creating register for signal `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.\muxwre' using process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31934'. created direct connection (no actual register cell created). 22.42.18.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.18.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31959'. Found and cleaned up 1 empty switch in `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31935'. Removing empty process `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31934'. Cleaned up 1 empty switch. 22.42.18.12. Executing OPT_EXPR pass (perform const folding). 22.42.19. Executing PROC pass (convert processes to netlists). 22.42.19.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32005'. Cleaned up 1 empty switch. 22.42.19.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32006 in module $paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.19.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.19.4. Executing PROC_INIT pass (extract init attributes). 22.42.19.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.19.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.19.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. Creating decoders for process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32006'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32004_EN[3:0]$32011 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32004_DATA[3:0]$32012 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32004_ADDR[3:0]$32010 Creating decoders for process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32005'. 22.42.19.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.19.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.\i' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31990_EN' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31994_EN' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31995_EN' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31999_EN' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32000_EN' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31996_EN' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31991_EN' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32001_EN' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32002_EN' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31997_EN' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31992_EN' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32003_EN' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31998_EN' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31993_EN' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31989_EN' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31988_EN' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. created direct connection (no actual register cell created). Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32004_ADDR' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32006'. created $dff cell `$procdff$32056' with positive edge clock. Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32004_EN' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32006'. created $dff cell `$procdff$32057' with positive edge clock. Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32004_DATA' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32006'. created $dff cell `$procdff$32058' with positive edge clock. Creating register for signal `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32005'. created direct connection (no actual register cell created). 22.42.19.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.19.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32030'. Found and cleaned up 1 empty switch in `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32006'. Removing empty process `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32005'. Cleaned up 1 empty switch. 22.42.19.12. Executing OPT_EXPR pass (perform const folding). 22.42.20. Executing PROC pass (convert processes to netlists). 22.42.20.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32076'. Cleaned up 1 empty switch. 22.42.20.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32077 in module $paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.20.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.20.4. Executing PROC_INIT pass (extract init attributes). 22.42.20.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.20.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.20.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. Creating decoders for process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32077'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32075_EN[3:0]$32083 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32075_DATA[3:0]$32082 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32075_ADDR[3:0]$32081 Creating decoders for process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32076'. 22.42.20.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.20.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.\i' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32063_EN' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32064_EN' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32065_EN' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32069_EN' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32060_EN' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32070_EN' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32071_EN' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32061_EN' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32072_EN' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32073_EN' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32066_EN' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32067_EN' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32074_EN' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32068_EN' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32062_EN' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32059_EN' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. created direct connection (no actual register cell created). Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32075_ADDR' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32077'. created $dff cell `$procdff$32127' with positive edge clock. Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32075_DATA' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32077'. created $dff cell `$procdff$32128' with positive edge clock. Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32075_EN' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32077'. created $dff cell `$procdff$32129' with positive edge clock. Creating register for signal `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.\muxwre' using process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32076'. created direct connection (no actual register cell created). 22.42.20.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.20.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32101'. Found and cleaned up 1 empty switch in `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32077'. Removing empty process `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32076'. Cleaned up 1 empty switch. 22.42.20.12. Executing OPT_EXPR pass (perform const folding). 22.42.21. Executing PROC pass (convert processes to netlists). 22.42.21.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32147'. Cleaned up 1 empty switch. 22.42.21.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32148 in module $paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.21.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.21.4. Executing PROC_INIT pass (extract init attributes). 22.42.21.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.21.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.21.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. Creating decoders for process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32148'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32146_EN[3:0]$32154 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32146_DATA[3:0]$32153 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32146_ADDR[3:0]$32152 Creating decoders for process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32147'. 22.42.21.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.21.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.\i' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. created direct connection (no actual register cell created). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32133_EN' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. created direct connection (no actual register cell created). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32138_EN' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. created direct connection (no actual register cell created). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32139_EN' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. created direct connection (no actual register cell created). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32144_EN' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. created direct connection (no actual register cell created). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32135_EN' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. created direct connection (no actual register cell created). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32140_EN' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. created direct connection (no actual register cell created). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32134_EN' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. created direct connection (no actual register cell created). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32136_EN' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. created direct connection (no actual register cell created). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32131_EN' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. created direct connection (no actual register cell created). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32143_EN' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. created direct connection (no actual register cell created). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32145_EN' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. created direct connection (no actual register cell created). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32141_EN' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. created direct connection (no actual register cell created). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32142_EN' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. created direct connection (no actual register cell created). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32137_EN' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. created direct connection (no actual register cell created). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32132_EN' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. created direct connection (no actual register cell created). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32130_EN' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. created direct connection (no actual register cell created). Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32146_ADDR' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32148'. created $dff cell `$procdff$32198' with positive edge clock. Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32146_DATA' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32148'. created $dff cell `$procdff$32199' with positive edge clock. Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32146_EN' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32148'. created $dff cell `$procdff$32200' with positive edge clock. Creating register for signal `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.\muxwre' using process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32147'. created direct connection (no actual register cell created). 22.42.21.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.21.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32172'. Found and cleaned up 1 empty switch in `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32148'. Removing empty process `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32147'. Cleaned up 1 empty switch. 22.42.21.12. Executing OPT_EXPR pass (perform const folding). 22.42.22. Executing PROC pass (convert processes to netlists). 22.42.22.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32218'. Cleaned up 1 empty switch. 22.42.22.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32219 in module $paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.22.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.22.4. Executing PROC_INIT pass (extract init attributes). 22.42.22.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.22.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.22.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. Creating decoders for process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32219'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32217_EN[3:0]$32223 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32217_DATA[3:0]$32225 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32217_ADDR[3:0]$32224 Creating decoders for process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32218'. 22.42.22.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.22.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.\i' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32201_EN' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32202_EN' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32207_EN' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32209_EN' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32214_EN' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32204_EN' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32205_EN' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32203_EN' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32210_EN' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32208_EN' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32211_EN' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32216_EN' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32213_EN' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32215_EN' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32212_EN' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32206_EN' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. created direct connection (no actual register cell created). Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32217_EN' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32219'. created $dff cell `$procdff$32269' with positive edge clock. Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32217_ADDR' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32219'. created $dff cell `$procdff$32270' with positive edge clock. Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32217_DATA' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32219'. created $dff cell `$procdff$32271' with positive edge clock. Creating register for signal `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.\muxwre' using process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32218'. created direct connection (no actual register cell created). 22.42.22.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.22.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32243'. Found and cleaned up 1 empty switch in `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32219'. Removing empty process `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32218'. Cleaned up 1 empty switch. 22.42.22.12. Executing OPT_EXPR pass (perform const folding). 22.42.23. Executing PROC pass (convert processes to netlists). 22.42.23.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32289'. Cleaned up 1 empty switch. 22.42.23.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32290 in module $paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.23.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.23.4. Executing PROC_INIT pass (extract init attributes). 22.42.23.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.23.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.23.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. Creating decoders for process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32290'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32288_EN[3:0]$32296 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32288_DATA[3:0]$32294 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32288_ADDR[3:0]$32295 Creating decoders for process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32289'. 22.42.23.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.23.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.\i' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. created direct connection (no actual register cell created). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32272_EN' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. created direct connection (no actual register cell created). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32273_EN' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. created direct connection (no actual register cell created). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32285_EN' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. created direct connection (no actual register cell created). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32286_EN' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. created direct connection (no actual register cell created). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32287_EN' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. created direct connection (no actual register cell created). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32282_EN' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. created direct connection (no actual register cell created). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32276_EN' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. created direct connection (no actual register cell created). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32277_EN' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. created direct connection (no actual register cell created). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32278_EN' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. created direct connection (no actual register cell created). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32279_EN' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. created direct connection (no actual register cell created). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32283_EN' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. created direct connection (no actual register cell created). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32284_EN' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. created direct connection (no actual register cell created). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32274_EN' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. created direct connection (no actual register cell created). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32275_EN' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. created direct connection (no actual register cell created). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32280_EN' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. created direct connection (no actual register cell created). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32281_EN' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. created direct connection (no actual register cell created). Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32288_DATA' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32290'. created $dff cell `$procdff$32340' with positive edge clock. Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32288_ADDR' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32290'. created $dff cell `$procdff$32341' with positive edge clock. Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32288_EN' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32290'. created $dff cell `$procdff$32342' with positive edge clock. Creating register for signal `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.\muxwre' using process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32289'. created direct connection (no actual register cell created). 22.42.23.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.23.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32314'. Found and cleaned up 1 empty switch in `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32290'. Removing empty process `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32289'. Cleaned up 1 empty switch. 22.42.23.12. Executing OPT_EXPR pass (perform const folding). 22.42.24. Executing PROC pass (convert processes to netlists). 22.42.24.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32360'. Cleaned up 1 empty switch. 22.42.24.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32361 in module $paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.24.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.24.4. Executing PROC_INIT pass (extract init attributes). 22.42.24.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.24.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.24.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. Creating decoders for process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32361'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32359_EN[3:0]$32366 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32359_DATA[3:0]$32367 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32359_ADDR[3:0]$32365 Creating decoders for process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32360'. 22.42.24.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.24.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.\i' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. created direct connection (no actual register cell created). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32353_EN' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. created direct connection (no actual register cell created). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32344_EN' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. created direct connection (no actual register cell created). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32348_EN' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. created direct connection (no actual register cell created). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32349_EN' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. created direct connection (no actual register cell created). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32350_EN' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. created direct connection (no actual register cell created). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32354_EN' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. created direct connection (no actual register cell created). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32355_EN' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. created direct connection (no actual register cell created). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32345_EN' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. created direct connection (no actual register cell created). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32347_EN' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. created direct connection (no actual register cell created). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32351_EN' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. created direct connection (no actual register cell created). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32352_EN' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. created direct connection (no actual register cell created). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32357_EN' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. created direct connection (no actual register cell created). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32358_EN' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. created direct connection (no actual register cell created). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32343_EN' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. created direct connection (no actual register cell created). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32356_EN' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. created direct connection (no actual register cell created). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32346_EN' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. created direct connection (no actual register cell created). Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32359_ADDR' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32361'. created $dff cell `$procdff$32411' with positive edge clock. Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32359_EN' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32361'. created $dff cell `$procdff$32412' with positive edge clock. Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32359_DATA' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32361'. created $dff cell `$procdff$32413' with positive edge clock. Creating register for signal `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.\muxwre' using process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32360'. created direct connection (no actual register cell created). 22.42.24.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.24.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32385'. Found and cleaned up 1 empty switch in `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32361'. Removing empty process `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32360'. Cleaned up 1 empty switch. 22.42.24.12. Executing OPT_EXPR pass (perform const folding). 22.42.25. Executing PROC pass (convert processes to netlists). 22.42.25.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32431'. Cleaned up 1 empty switch. 22.42.25.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32432 in module $paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.25.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.25.4. Executing PROC_INIT pass (extract init attributes). 22.42.25.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.25.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.25.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. Creating decoders for process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32432'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32430_EN[3:0]$32436 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32430_DATA[3:0]$32438 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32430_ADDR[3:0]$32437 Creating decoders for process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32431'. 22.42.25.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.25.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.\i' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. created direct connection (no actual register cell created). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32423_EN' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. created direct connection (no actual register cell created). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32417_EN' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. created direct connection (no actual register cell created). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32414_EN' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. created direct connection (no actual register cell created). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32418_EN' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. created direct connection (no actual register cell created). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32419_EN' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. created direct connection (no actual register cell created). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32420_EN' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. created direct connection (no actual register cell created). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32424_EN' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. created direct connection (no actual register cell created). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32425_EN' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. created direct connection (no actual register cell created). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32415_EN' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. created direct connection (no actual register cell created). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32426_EN' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. created direct connection (no actual register cell created). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32416_EN' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. created direct connection (no actual register cell created). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32422_EN' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. created direct connection (no actual register cell created). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32427_EN' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. created direct connection (no actual register cell created). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32428_EN' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. created direct connection (no actual register cell created). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32429_EN' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. created direct connection (no actual register cell created). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32421_EN' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. created direct connection (no actual register cell created). Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32430_EN' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32432'. created $dff cell `$procdff$32482' with positive edge clock. Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32430_ADDR' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32432'. created $dff cell `$procdff$32483' with positive edge clock. Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32430_DATA' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32432'. created $dff cell `$procdff$32484' with positive edge clock. Creating register for signal `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32431'. created direct connection (no actual register cell created). 22.42.25.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.25.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32456'. Found and cleaned up 1 empty switch in `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32432'. Removing empty process `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32431'. Cleaned up 1 empty switch. 22.42.25.12. Executing OPT_EXPR pass (perform const folding). 22.42.26. Executing PROC pass (convert processes to netlists). 22.42.26.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32502'. Cleaned up 1 empty switch. 22.42.26.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32503 in module $paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.26.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.26.4. Executing PROC_INIT pass (extract init attributes). 22.42.26.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.26.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.26.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. Creating decoders for process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32503'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32501_EN[3:0]$32509 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32501_DATA[3:0]$32508 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32501_ADDR[3:0]$32507 Creating decoders for process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32502'. 22.42.26.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.26.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.\i' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32499_EN' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32487_EN' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32485_EN' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32493_EN' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32488_EN' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32489_EN' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32490_EN' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32494_EN' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32495_EN' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32496_EN' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32500_EN' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32486_EN' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32491_EN' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32492_EN' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32497_EN' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32498_EN' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. created direct connection (no actual register cell created). Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32501_ADDR' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32503'. created $dff cell `$procdff$32553' with positive edge clock. Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32501_DATA' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32503'. created $dff cell `$procdff$32554' with positive edge clock. Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32501_EN' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32503'. created $dff cell `$procdff$32555' with positive edge clock. Creating register for signal `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.\muxwre' using process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32502'. created direct connection (no actual register cell created). 22.42.26.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.26.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32527'. Found and cleaned up 1 empty switch in `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32503'. Removing empty process `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32502'. Cleaned up 1 empty switch. 22.42.26.12. Executing OPT_EXPR pass (perform const folding). 22.42.27. Executing PROC pass (convert processes to netlists). 22.42.27.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32573'. Cleaned up 1 empty switch. 22.42.27.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32574 in module $paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.27.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.27.4. Executing PROC_INIT pass (extract init attributes). 22.42.27.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.27.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.27.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. Creating decoders for process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32574'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32572_EN[3:0]$32579 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32572_DATA[3:0]$32578 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32572_ADDR[3:0]$32580 Creating decoders for process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32573'. 22.42.27.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.27.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.\i' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32567_EN' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32561_EN' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32556_EN' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32557_EN' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32558_EN' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32562_EN' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32563_EN' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32564_EN' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32568_EN' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32569_EN' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32559_EN' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32570_EN' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32560_EN' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32565_EN' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32566_EN' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32571_EN' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32572_DATA' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32574'. created $dff cell `$procdff$32624' with positive edge clock. Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32572_EN' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32574'. created $dff cell `$procdff$32625' with positive edge clock. Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32572_ADDR' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32574'. created $dff cell `$procdff$32626' with positive edge clock. Creating register for signal `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.\muxwre' using process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32573'. created direct connection (no actual register cell created). 22.42.27.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.27.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32598'. Found and cleaned up 1 empty switch in `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32574'. Removing empty process `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32573'. Cleaned up 1 empty switch. 22.42.27.12. Executing OPT_EXPR pass (perform const folding). 22.42.28. Executing PROC pass (convert processes to netlists). 22.42.28.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32644'. Cleaned up 1 empty switch. 22.42.28.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32645 in module $paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.28.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.28.4. Executing PROC_INIT pass (extract init attributes). 22.42.28.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.28.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.28.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. Creating decoders for process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32645'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32643_EN[3:0]$32650 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32643_DATA[3:0]$32651 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32643_ADDR[3:0]$32649 Creating decoders for process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32644'. 22.42.28.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.28.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.\i' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32638_EN' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32639_EN' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32633_EN' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32628_EN' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32629_EN' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32631_EN' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32641_EN' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32640_EN' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32637_EN' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32636_EN' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32635_EN' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32642_EN' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32632_EN' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32634_EN' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32630_EN' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$32627_EN' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32643_ADDR' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32645'. created $dff cell `$procdff$32695' with positive edge clock. Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32643_EN' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32645'. created $dff cell `$procdff$32696' with positive edge clock. Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$32643_DATA' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32645'. created $dff cell `$procdff$32697' with positive edge clock. Creating register for signal `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.\muxwre' using process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32644'. created direct connection (no actual register cell created). 22.42.28.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.28.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$32669'. Found and cleaned up 1 empty switch in `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$32645'. Removing empty process `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$32644'. Cleaned up 1 empty switch. 22.42.28.12. Executing OPT_EXPR pass (perform const folding). 22.42.29. Executing SCC pass (detecting logic loops). Found an SCC: $techmap$auto$ff.cc:266:slice$15528.$auto$simplemap.cc:267:simplemap_mux$30767 Found an SCC: $techmap$auto$ff.cc:266:slice$15527.$auto$simplemap.cc:267:simplemap_mux$30767 Found an SCC: $techmap$auto$ff.cc:266:slice$15526.$auto$simplemap.cc:267:simplemap_mux$30767 Found an SCC: $techmap$auto$ff.cc:266:slice$15525.$auto$simplemap.cc:267:simplemap_mux$30767 Found an SCC: $auto$ff.cc:266:slice$11645 $auto$opt_expr.cc:613:replace_const_cells$29898 $auto$ff.cc:266:slice$11644 $auto$simplemap.cc:126:simplemap_reduce$11739 $auto$simplemap.cc:126:simplemap_reduce$11766 $auto$opt_expr.cc:613:replace_const_cells$29896 $auto$ff.cc:266:slice$11643 $auto$opt_expr.cc:613:replace_const_cells$29904 $auto$ff.cc:266:slice$11642 $auto$simplemap.cc:126:simplemap_reduce$11742 $auto$simplemap.cc:126:simplemap_reduce$11738 $auto$ff.cc:266:slice$11641 $auto$opt_expr.cc:613:replace_const_cells$29892 $auto$ff.cc:266:slice$11640 $auto$simplemap.cc:126:simplemap_reduce$11737 $auto$opt_expr.cc:613:replace_const_cells$29900 $auto$simplemap.cc:126:simplemap_reduce$11764 $auto$ff.cc:266:slice$11639 $auto$ff.cc:266:slice$11638 $auto$simplemap.cc:225:simplemap_logbin$11721 $auto$simplemap.cc:196:simplemap_lognot$11748 $auto$simplemap.cc:126:simplemap_reduce$11746 $auto$simplemap.cc:126:simplemap_reduce$11744 $auto$simplemap.cc:126:simplemap_reduce$11741 $auto$simplemap.cc:126:simplemap_reduce$11736 $auto$simplemap.cc:126:simplemap_reduce$11768 $auto$simplemap.cc:126:simplemap_reduce$11763 $auto$opt_expr.cc:613:replace_const_cells$30000 $auto$ff.cc:266:slice$11637 $auto$simplemap.cc:167:logic_reduce$11068 $auto$simplemap.cc:225:simplemap_logbin$11720 $auto$simplemap.cc:196:simplemap_lognot$11775 $auto$simplemap.cc:126:simplemap_reduce$11773 $auto$simplemap.cc:126:simplemap_reduce$11771 $auto$simplemap.cc:126:simplemap_reduce$11769 $auto$simplemap.cc:126:simplemap_reduce$11765 $auto$simplemap.cc:38:simplemap_not$22093 Found an SCC: $auto$ff.cc:266:slice$11783 $auto$simplemap.cc:126:simplemap_reduce$11919 $auto$simplemap.cc:126:simplemap_reduce$11934 $auto$opt_expr.cc:613:replace_const_cells$29916 $auto$ff.cc:266:slice$11784 $auto$ff.cc:266:slice$11782 $auto$opt_expr.cc:613:replace_const_cells$29932 $auto$simplemap.cc:267:simplemap_mux$22125 $auto$simplemap.cc:126:simplemap_reduce$22110 $auto$simplemap.cc:126:simplemap_reduce$22107 $auto$simplemap.cc:75:simplemap_bitop$22123 $auto$simplemap.cc:267:simplemap_mux$11901 $auto$simplemap.cc:225:simplemap_logbin$11904 $auto$simplemap.cc:196:simplemap_lognot$11923 $auto$simplemap.cc:126:simplemap_reduce$11921 $auto$simplemap.cc:126:simplemap_reduce$11918 $auto$opt_expr.cc:613:replace_const_cells$29994 $auto$simplemap.cc:126:simplemap_reduce$22115 $auto$simplemap.cc:126:simplemap_reduce$22112 $auto$simplemap.cc:75:simplemap_bitop$22120 $auto$simplemap.cc:196:simplemap_lognot$11938 $auto$simplemap.cc:126:simplemap_reduce$11936 $auto$simplemap.cc:126:simplemap_reduce$11933 $auto$ff.cc:266:slice$11781 $auto$simplemap.cc:126:simplemap_reduce$11063 $auto$simplemap.cc:126:simplemap_reduce$11061 $auto$simplemap.cc:225:simplemap_logbin$11858 $auto$simplemap.cc:196:simplemap_lognot$11868 $auto$simplemap.cc:126:simplemap_reduce$11866 $auto$opt_expr.cc:613:replace_const_cells$29930 $auto$simplemap.cc:267:simplemap_mux$22124 Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$10975 $auto$simplemap.cc:38:simplemap_not$21808 $auto$ff.cc:266:slice$11035 $auto$ff.cc:479:convert_ce_over_srst$30054 $auto$simplemap.cc:38:simplemap_not$23823 $auto$ff.cc:266:slice$11033 $auto$ff.cc:479:convert_ce_over_srst$30050 $auto$simplemap.cc:126:simplemap_reduce$10484 $auto$ff.cc:266:slice$11034 $auto$ff.cc:479:convert_ce_over_srst$30052 $auto$simplemap.cc:126:simplemap_reduce$10483 $auto$ff.cc:266:slice$11032 $auto$ff.cc:479:convert_ce_over_srst$30048 $auto$opt_expr.cc:613:replace_const_cells$29852 $auto$ff.cc:266:slice$11030 $auto$ff.cc:479:convert_ce_over_srst$30044 $auto$alumacc.cc:485:replace_alu$3591.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$3591.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$3591.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$11004 $auto$simplemap.cc:126:simplemap_reduce$10488 $auto$simplemap.cc:126:simplemap_reduce$10486 $auto$simplemap.cc:126:simplemap_reduce$10482 $auto$simplemap.cc:38:simplemap_not$21804 $auto$ff.cc:266:slice$11031 $auto$ff.cc:479:convert_ce_over_srst$30046 $auto$simplemap.cc:126:simplemap_reduce$10988 $auto$simplemap.cc:126:simplemap_reduce$10986 $auto$simplemap.cc:126:simplemap_reduce$11007 $auto$simplemap.cc:126:simplemap_reduce$11005 $auto$simplemap.cc:38:simplemap_not$11072 $auto$simplemap.cc:75:simplemap_bitop$11083 $auto$simplemap.cc:38:simplemap_not$11084 Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$29928 $auto$ff.cc:266:slice$11792 $auto$ff.cc:266:slice$11793 $auto$ff.cc:266:slice$11790 $auto$simplemap.cc:126:simplemap_reduce$11956 $auto$opt_expr.cc:613:replace_const_cells$29926 $auto$ff.cc:266:slice$11791 $auto$opt_expr.cc:613:replace_const_cells$29922 $auto$ff.cc:266:slice$11788 $auto$simplemap.cc:126:simplemap_reduce$11959 $auto$simplemap.cc:126:simplemap_reduce$11955 $auto$opt_expr.cc:613:replace_const_cells$29924 $auto$ff.cc:266:slice$11789 $auto$ff.cc:266:slice$11786 $auto$simplemap.cc:126:simplemap_reduce$11954 $auto$ff.cc:266:slice$11787 $auto$simplemap.cc:126:simplemap_reduce$11953 $auto$simplemap.cc:38:simplemap_not$22171 $auto$ff.cc:266:slice$11785 $auto$simplemap.cc:126:simplemap_reduce$11057 $auto$simplemap.cc:196:simplemap_lognot$11965 $auto$simplemap.cc:126:simplemap_reduce$11963 $auto$simplemap.cc:126:simplemap_reduce$11961 $auto$simplemap.cc:126:simplemap_reduce$11958 Found 8 SCCs in module top. Found 8 SCCs. 22.42.30. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.31. Executing PROC pass (convert processes to netlists). 22.42.31.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 22.42.31.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 22.42.31.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 22.42.31.4. Executing PROC_INIT pass (extract init attributes). 22.42.31.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.31.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 22.42.31.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 22.42.31.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.31.9. Executing PROC_DFF pass (convert process syncs to FFs). 22.42.31.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.31.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 22.42.31.12. Executing OPT_EXPR pass (perform const folding). 22.42.32. Executing TECHMAP pass (map to technology primitives). 22.42.32.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 22.42.32.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~212 debug messages> 22.42.33. Executing OPT pass (performing simple optimizations). 22.42.33.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing module $paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4. Optimizing module $paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4. Optimizing module $paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4. Optimizing module $paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4. Optimizing module $paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4. Optimizing module $paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4. Optimizing module $paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4. Optimizing module $paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4. Optimizing module $paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4. Optimizing module $paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4. Optimizing module $paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4. Optimizing module $paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4. Optimizing module $paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4. Optimizing module $paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4. Optimizing module $paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4. Optimizing module $paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4. Optimizing module $paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4. Optimizing module $paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4. Optimizing module $paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4. Optimizing module $paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4. Optimizing module $paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4. Optimizing module $paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4. Optimizing module $paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4. Optimizing module $paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4. 22.42.33.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4'. Removed a total of 0 cells. 22.42.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 22.42.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing cells in module $paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4. Optimizing cells in module $paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4. Optimizing cells in module $paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4. Optimizing cells in module $paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4. Optimizing cells in module $paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4. Optimizing cells in module $paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4. Optimizing cells in module $paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4. Optimizing cells in module $paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4. Optimizing cells in module $paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4. Optimizing cells in module $paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4. Optimizing cells in module $paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4. Optimizing cells in module $paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4. Optimizing cells in module $paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4. Optimizing cells in module $paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4. Optimizing cells in module $paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4. Optimizing cells in module $paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4. Optimizing cells in module $paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4. Optimizing cells in module $paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4. Optimizing cells in module $paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4. Optimizing cells in module $paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4. Optimizing cells in module $paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4. Optimizing cells in module $paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4. Optimizing cells in module $paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4. Optimizing cells in module $paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4. Performed a total of 0 changes. 22.42.33.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4'. Removed a total of 0 cells. 22.42.33.6. Executing OPT_DFF pass (perform DFF optimizations). 22.42.33.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4.. 22.42.33.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4. Optimizing module $paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4. Optimizing module $paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4. Optimizing module $paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4. Optimizing module $paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4. Optimizing module $paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4. Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing module $paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4. Optimizing module $paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4. Optimizing module $paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4. Optimizing module $paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4. Optimizing module $paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4. Optimizing module $paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4. Optimizing module $paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4. Optimizing module $paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4. Optimizing module $paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4. Optimizing module $paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4. Optimizing module $paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4. Optimizing module $paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4. Optimizing module $paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4. Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing module $paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4. Optimizing module $paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4. Optimizing module $paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4. Optimizing module $paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4. Optimizing module $paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4. 22.42.33.9. Finished OPT passes. (There is nothing left to do.) 22.42.34. Executing TECHMAP pass (map to technology primitives). 22.42.34.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 22.42.34.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Using template $paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4 for cells of type $paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4. Using template $paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4 for cells of type $paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4. Using template $paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4 for cells of type $paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4. Using template $paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4 for cells of type $paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4. Using template $paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4 for cells of type $paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4. Using template $paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4 for cells of type $paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4. Using template $paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4 for cells of type $paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4. Using template $paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4 for cells of type $paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4. Using template $paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4 for cells of type $paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4. Using template $paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4 for cells of type $paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4. Using template $paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4 for cells of type $paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4. Using template $paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4 for cells of type $paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4. Using template $paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4 for cells of type $paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4. Using template $paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4 for cells of type $paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4. Using template $paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4 for cells of type $paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4. Using template $paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4 for cells of type $paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4. Using template $paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4 for cells of type $paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4. Using template $paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4 for cells of type $paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4. Using template $paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4 for cells of type $paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4. Using template $paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4 for cells of type $paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4. Using template $paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4 for cells of type $paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4. Using template $paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4 for cells of type $paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4. Using template $paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4 for cells of type $paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4. Using template $paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4 for cells of type $paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4. No more expansions possible. <suppressed ~1104 debug messages> 22.42.35. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 22.42.36. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 22.42.37. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.38. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 22.42.39. Executing TECHMAP pass (map to technology primitives). 22.42.39.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 22.42.39.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $mux. No more expansions possible. <suppressed ~251 debug messages> 22.42.40. Executing OPT pass (performing simple optimizations). 22.42.40.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~18 debug messages> 22.42.40.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 22.42.40.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 22.42.40.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.42.40.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.42.40.6. Executing OPT_DFF pass (perform DFF optimizations). 22.42.40.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 55 unused wires. <suppressed ~1 debug messages> 22.42.40.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.42.40.9. Rerunning OPT passes. (Maybe there is more to do..) 22.42.40.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 22.42.40.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.42.40.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.42.40.13. Executing OPT_DFF pass (perform DFF optimizations). 22.42.40.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.42.40.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.42.40.16. Finished OPT passes. (There is nothing left to do.) 22.42.41. Executing AIGMAP pass (map logic to AIG). Module top: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 2 $_OR_ 2 $_XOR_ 14 $_MUX_ not replaced 3 cell types: 31 $specify2 4 $_NOT_ 4 $_AND_ 22.42.42. Executing AIGMAP pass (map logic to AIG). Module top: replaced 7672 cells with 49258 new cells, skipped 4402 cells. replaced 3 cell types: 1482 $_OR_ 96 $_XOR_ 6094 $_MUX_ not replaced 59 cell types: 30 $scopeinfo 362 $_NOT_ 1087 $_AND_ 6 $_TBUF_ 1 $paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4 704 TRELLIS_FF 1 $paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4_$abc9_byp 1 $__ABC9_SCC_BREAKER 1 $paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4 1 $paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4 1 $paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4 1 $paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4 1 $paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4 1 $paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4 1 $paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4 1 $paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4 24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 1 $paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4 1 $paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4 1 $paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4 1 $paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4 1 $paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4 1 $paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4 1 $paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4 1 $paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4_$abc9_byp 1028 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4 60 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 1 $paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4 1 $paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4 1 $paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4 1 $paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4 1 $paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4 1 $paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4 1 $paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4 1 $paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4_$abc9_byp 1028 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4_$abc9_byp 22.42.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.42.3. Executing XAIGER backend. <suppressed ~11 debug messages> Extracted 21139 AND gates and 60755 wires from module `top' to a netlist network with 5025 inputs and 753 outputs. 22.42.42.4. Executing ABC9_EXE pass (technology mapping using ABC9). 22.42.42.5. Executing ABC9. read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1317.090 ; gain = 0.023 ; free physical = 2256 ; free virtual = 26016 # read_verilog ../../debug/reset.v # read_verilog ../../src/core/alu_control.v # read_verilog ../../src/core/alu.v # read_verilog ../../src/core/control_unit.v # read_verilog ../../src/core/core.v # read_verilog ../../src/core/immediate_generator.v # read_verilog ../../src/core/mux.v # read_verilog ../../src/core/pc.v # read_verilog ../../src/core/registers.v # read_verilog ../../src/core/csr_unit.v # read_verilog ../../src/peripheral/bus.v # read_verilog ../../src/peripheral/gpio.v # read_verilog ../../src/peripheral/gpios.v # read_verilog ../../src/peripheral/leds.v # read_verilog ../../src/peripheral/memory.v # read_verilog ../../src/peripheral/soc.v # read_verilog ../../src/peripheral/uart_rx.v # read_verilog ../../src/peripheral/uart_tx.v # read_verilog ../../src/peripheral/uart.v # read_verilog ../../src/peripheral/fifo.v # read_xdc "digilent_nexys4_ddr.xdc" # set_property PROCESSING_ORDER EARLY [get_files digilent_nexys4_ddr.xdc] # synth_design -top "top" -part "xc7a100tcsg324-1" Command: synth_design -top top -part xc7a100tcsg324-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 3931323 Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_lut <abc-temp-dir>/input.lut ABC: + read_box <abc-temp-dir>/input.box ABC: + &read <abc-temp-dir>/input.xaig ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 5025/ 753 and = 19250 lev = 57 (4.63) mem = 0.52 MB box = 1136 bb = 1076 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 5025/ 753 and = 24134 lev = 38 (4.68) mem = 0.57 MB ch = 2304 box = 1136 bb = 1076 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 60. Obj = 140. Set = 636. CutMin = no ABC: Node = 24134. Ch = 1657. Total mem = 6.48 MB. Peak cut mem = 0.27 MB. ABC: P: Del = 6734.00. Ar = 19108.0. Edge = 24322. Cut = 248137. T = 0.07 sec ABC: P: Del = 6345.00. Ar = 19022.0. Edge = 24288. Cut = 243142. T = 0.07 sec ABC: P: Del = 6345.00. Ar = 11260.0. Edge = 22690. Cut = 817116. T = 0.21 sec ABC: F: Del = 6345.00. Ar = 7602.0. Edge = 20297. Cut = 399684. T = 0.11 sec ABC: A: Del = 6345.00. Ar = 6890.0. Edge = 19098. Cut = 389922. T = 0.17 sec ABC: A: Del = 6345.00. Ar = 6757.0. Edge = 18937. Cut = 394790. T = 0.17 sec ABC: Total time = 0.79 sec ABC: + &write -n <abc-temp-dir>/output.aig ABC: + &mfs ABC: + &ps -l ABC: <abc-temp-dir>/input : i/o = 5025/ 753 and = 15534 lev = 44 (5.16) mem = 0.47 MB box = 1136 bb = 1076 ABC: Mapping (K=7) : lut = 4642 edge = 18545 lev = 13 (2.51) levB = 25 mem = 0.24 MB ABC: LUT = 4642 : 2=382 8.2 % 3=530 11.4 % 4=2776 59.8 % 5=759 16.4 % 6=73 1.6 % 7=122 2.6 % Ave = 4.00 ABC: + &write -n <abc-temp-dir>/output.aig ABC: + time ABC: elapse: 10.44 seconds, total: 10.44 seconds 22.42.42.6. Executing AIGER frontend. <suppressed ~11568 debug messages> Removed 21157 unused cells and 45119 unused wires. 22.42.42.7. Executing ABC9_OPS pass (helper functions for ABC9). ABC RESULTS: $lut cells: 4666 ABC RESULTS: $paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 1028 ABC RESULTS: $paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 60 ABC RESULTS: $paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells: 24 ABC RESULTS: $paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: input signals: 1121 ABC RESULTS: output signals: 133 Removing temp directory. 22.42.43. Executing TECHMAP pass (map to technology primitives). 22.42.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 22.42.43.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001010 for cells of type $__ABC9_SCC_BREAKER. Using template $paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4 for cells of type $paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4. Using template $paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4 for cells of type $paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4. Using template $paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4 for cells of type $paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4. Using template $paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4 for cells of type $paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4. Using template $paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4 for cells of type $paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4. Using template $paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4 for cells of type $paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4. Using template $paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4 for cells of type $paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4. Using template $paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4 for cells of type $paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4. Using template $paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4 for cells of type $paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4. Using template $paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4 for cells of type $paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4. Using template $paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4 for cells of type $paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4. Using template $paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4 for cells of type $paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4. Using template $paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4 for cells of type $paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4. Using template $paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4 for cells of type $paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4. Using template $paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4 for cells of type $paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4. Using template $paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4 for cells of type $paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4. Using template $paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4 for cells of type $paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4. Using template $paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4 for cells of type $paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4. Using template $paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4 for cells of type $paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4. Using template $paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4 for cells of type $paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4. Using template $paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4 for cells of type $paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4. Using template $paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4 for cells of type $paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4. Using template $paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4 for cells of type $paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4. Using template $paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4 for cells of type $paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4. Using template $paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$391f4871e3743b43707ce82579a3b70a097b8eef\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$4c5840355e4f809500e8a576c74d11cdcbc14f46\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$3b8004f1633cd69817f06ce4b1a7cbb6caaa2c60\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$18189603812f67194085e7af4200145826f7b617\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$a5cbc08df95199a21947c9a12813d8a79b4d19c0\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$744005191b28a9a82c3cc18799e85d56bca23c40\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$e61921e360dcd64ea95819974c3f1a849f157cd9\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$bf534370b0b4e6c1d40c724d583d7a221581e8a9\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$7cb6ad52dc6bb33604a9ce413a6890b8b5d619a4\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$128d990b290f75aa7ebf15bdc20663f48e172e5e\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$fc5374a821b98182f9aa018b45b6c6a36bfc9c4c\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$c057daea12209e104f46cc87824f105acb0ce7a6\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$55e7b4cb1673d855f440ca32d6b1f4e9842fd832\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$36b6d53974d80239e6424767924b3c765eedba9f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$ea720958700fbed28f89c51d77eb16d583918999\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$0a0d89faff0306f83dbe50fd80896b8e682d4333\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$c1880ce00f8a601689808701709f4966c9256160\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$14aea674b113890068a87d5d84958b08e83ba42a\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$146a90b096486a1b40dbb60daff65741d38318ca\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$70a4eaf4853ae980bb727b292b0e7c3640032791\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$f64cc816c1a9484ddb6e7eef088031f30ecb6409\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2d65dc0049e72e8ff5a64793b719ef1da6b8735b\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$e806578642590b54352bf89dd0ca41ce2611672c\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$18a9cb7a0c00900057b39971489937f51ddc9108\TRELLIS_DPR16X4_$abc9_byp. No more expansions possible. <suppressed ~2282 debug messages> Removed 174 unused cells and 75376 unused wires. 22.43. Executing TECHMAP pass (map to technology primitives). 22.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 22.43.2. Continuing TECHMAP pass. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$5bbc8d49c3fc31cf6661312d1516e2aaafe308a4\$lut for cells of type $lut. Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod$a190dca018ce780c5999f1c3eec1f4ceecdfe178\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$71a8bb06bab8fce4311ac49bca22cb16e2d06e87\$lut for cells of type $lut. Using template $paramod$28a3680a6e7e9e48ff40bdc068c8febc180aaa90\$lut for cells of type $lut. Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut. Using template $paramod$922278002c2b7bbee214021e993d64bedc018ebe\$lut for cells of type $lut. Using template $paramod$54136f6cee1a1e0b4fc331323dd7df9166dbefde\$lut for cells of type $lut. Using template $paramod$9851cb11f88bbbf4a516c0595f3b0113b1f100c4\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011011 for cells of type $lut. Using template $paramod$4313d6a4df5be8d101d4989de89eeec5b7d9f7b3\$lut for cells of type $lut. Using template $paramod$a8b7516c4ccadf4ab65906113028f2819d14ea8b\$lut for cells of type $lut. Using template $paramod$3c6be0cecca529b904c273ae6983e0f6d0361b11\$lut for cells of type $lut. Using template $paramod$a743caf801766df40bcc22d49baa12a0bdc2f7fe\$lut for cells of type $lut. Using template $paramod$b9d1c3ab552c7cef2bdf5b9ac9095f98b438d3c2\$lut for cells of type $lut. Using template $paramod$774a669204184147b38453b69c15da44a7cf748f\$lut for cells of type $lut. Using template $paramod$8e1c82b304528085a78e4651c993ce9e1ef6b8a8\$lut for cells of type $lut. Using template $paramod$bd57e9718a938c253993cb582d13218a9bcdcc54\$lut for cells of type $lut. Using template $paramod$effe89018a09206b34e4ce114d402d2322056617\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut. Using template $paramod$e8e38e13ba4ca36ee2f40f244789338dfa28acd1\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$2bc8bd3fc6674de4d3c20a549add3907ac7fb248\$lut for cells of type $lut. Using template $paramod$e412821338883e25f2e0d1a1d7fada158db69807\$lut for cells of type $lut. Using template $paramod$bde6c96e44b0f8e6d9db97eafdf28d77ceaa9a96\$lut for cells of type $lut. Using template $paramod$c8f2b00a2feb859040935d06cafa51f6c4e20e0d\$lut for cells of type $lut. Using template $paramod$5d51a4434f8f9c68249a1b11026c966f0ccfc64a\$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. Using template $paramod$a4ffb9cf9bdbd0f9cc0dafff3e65b459d11b85f6\$lut for cells of type $lut. Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b\$lut for cells of type $lut. Using template $paramod$03d0edf20ed1469b09ef5ea8e93986bf65c1867c\$lut for cells of type $lut. Using template $paramod$bce98cbc4c7663d9534fcdf870483176065e0cfd\$lut for cells of type $lut. Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut. Using template $paramod$9411ab5f327581bfd24ad527703788c82debb01f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut. Using template $paramod$32abbd1d449a67fb913b4733374e345d4c17175b\$lut for cells of type $lut. Using template $paramod$cad8f5c808e91f937dcf797b89e646787b39867a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. Using template $paramod$da01499be2a7b74c3bef718d44ef92a02b0fe6cd\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod$d25b6a61417853a871ede48916b22db597f063bb\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111001 for cells of type $lut. Using template $paramod$001d9634602f00137f774620efde4c651c7a59ca\$lut for cells of type $lut. Using template $paramod$e484b1e0bd351ba5af34f5fd66a8e850cc5b8335\$lut for cells of type $lut. Using template $paramod$d41eccd4fc885e72afab41b1a402a918127de8a9\$lut for cells of type $lut. Using template $paramod$2e98e5a6d7f45ee893f79b7c519ac83ef624c175\$lut for cells of type $lut. Using template $paramod$6c22e4c9acd607e1249c5e3017b6703f378da140\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod$835b481f851e62d27eb3f60e4771d55796942207\$lut for cells of type $lut. Using template $paramod$576843ec5da9d065ef43831af18f1bac63825d80\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. Using template $paramod$3e5b1dfa757318981849f44afadba30ff6d2b586\$lut for cells of type $lut. Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. Using template $paramod$afb8959a93937986ded51b1cddcab9e31c6ea2ed\$lut for cells of type $lut. Using template $paramod$ee3ba3939f6ccdb74bf420a252d58cdb86511937\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod$d315acbf930db7c20b3f4ac2dad3b7982b1f437c\$lut for cells of type $lut. Using template $paramod$046183db49766efba42be79105539fe6416a5702\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod$e2d4399e1e149b2bd3c04b32fc0d847bb8cdd6d6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut. Using template $paramod$60de7b16da27f5c6bc743801ecd3eff3a64b78cc\$lut for cells of type $lut. Using template $paramod$73b4ad7952143efe54e1c3ab135feafb5eff57bf\$lut for cells of type $lut. Using template $paramod$b0969e4b829aa2286ccce660aa055f1c4b1825bb\$lut for cells of type $lut. Using template $paramod$5e37a5dec54babb6ed53b84738ba38cb0344b498\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101101 for cells of type $lut. Using template $paramod$6d64e1ec6781f33f9cd3a4b38c777bb42630023e\$lut for cells of type $lut. Using template $paramod$acd43fba7f71b1295de78a2178234108f5c1feb6\$lut for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut. Using template $paramod$0f7c39b46c8bd20506f7e0e0a42b04005cf939be\$lut for cells of type $lut. Using template $paramod$6e85bfb9231e5e54fadbf817772621af24a1aefd\$lut for cells of type $lut. Using template $paramod$5c7cc04aef034825f69eec1b9ef84498bd881f81\$lut for cells of type $lut. Using template $paramod$9f1e4f5e0ca55f3ded7bc06324b529ec02785f32\$lut for cells of type $lut. Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9\$lut for cells of type $lut. Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut. Using template $paramod$f110e1863aa3e47da4afc6040b76646985fee7bb\$lut for cells of type $lut. Using template $paramod$701bdd2a176f99a223efa70a10296db6cfa9e9ea\$lut for cells of type $lut. Using template $paramod$15347ed7385bf3cbbaf3dfabb41219d5252f509e\$lut for cells of type $lut. Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut. Using template $paramod$d296b9f68d1e09f71066a566f9d7df9acc346f2b\$lut for cells of type $lut. Using template $paramod$5ff5c25c21f250f782a91d9433493387f404c6b8\$lut for cells of type $lut. Using template $paramod$b56fc3ff7d60b1981f9bde0de1d6026b0f4b1355\$lut for cells of type $lut. Using template $paramod$b7712ad66490a50bf0f0eb1278d478652991d6c1\$lut for cells of type $lut. Using template $paramod$fd612331c30e9d253090fdb1f8a32e43d927e731\$lut for cells of type $lut. Using template $paramod$0260ba258d9e1a608f5e349a51c65fb9e84b9283\$lut for cells of type $lut. Using template $paramod$2844c7fef2a755a9af80c70990cd830291c4b71c\$lut for cells of type $lut. Using template $paramod$8384e66d408d22ab39dfb451efb7879731befeb8\$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. Using template $paramod$c6877cca211c96bd98fd8e58ef57c17dd114bfc3\$lut for cells of type $lut. Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut. Using template $paramod$0ae7705354ab4bfd071e2551e0df024a40a698f7\$lut for cells of type $lut. Using template $paramod$2955ab75367a3dc9d6f50d3655eebcd4f615031f\$lut for cells of type $lut. Using template $paramod$0d0678626c1c93b9ceb2745feafb3dd40f1601ce\$lut for cells of type $lut. Using template $paramod$6375ab94b303a3f3c8d7ca6946328cb3c0b443a7\$lut for cells of type $lut. Using template $paramod$94853dfead6b7a481be0009f1c6c056e332752b3\$lut for cells of type $lut. Using template $paramod$d0aba71a7ea9c43ba4e04d936be46de775c59df0\$lut for cells of type $lut. Using template $paramod$5c3294d2efb88caf0474e72690e5c12ab871a3e8\$lut for cells of type $lut. Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542\$lut for cells of type $lut. Using template $paramod$f062eaa72b3e84676ddb50246949e3133302085e\$lut for cells of type $lut. Using template $paramod$6a3d1b4c6389888034ca851571f0d03f46d1c4e9\$lut for cells of type $lut. Using template $paramod$8bf24758f49602c9d2141db05a7f0057cae035a8\$lut for cells of type $lut. Using template $paramod$b8a267e029098a57073dfcc5e754badd67f46051\$lut for cells of type $lut. Using template $paramod$ed6e5e00552ba602b93cd729133661ebe64f51df\$lut for cells of type $lut. Using template $paramod$016c6b3e48d8831902f83ae4b26b25597f23e8f6\$lut for cells of type $lut. Using template $paramod$e0286d7bdebdb6346cb367bb1962e01892ba2e32\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. Using template $paramod$af574ac083faf8d8036edb1d34eb40d28d20ac3a\$lut for cells of type $lut. Using template $paramod$723eb79ef8d5d376f3f196f4acfa8e347145a0fa\$lut for cells of type $lut. Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut. Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut. Using template $paramod$df5c8730c0a53792c3f54c2192a2221c27162fb5\$lut for cells of type $lut. Using template $paramod$18df3812bc12364e5ebcb6c3ed05c0294e4c26fc\$lut for cells of type $lut. Using template $paramod$6b0d0b63d10b79a0754837329a0dde50bf2ae17f\$lut for cells of type $lut. Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut. Using template $paramod$b18a3edb490ff3a49fefc94182a05f36efbdbba2\$lut for cells of type $lut. Using template $paramod$89af1381ff50ed0e33c5fb9a3d2e869fee1019cd\$lut for cells of type $lut. Using template $paramod$1b2d33c7048d527093ca6279ca85547152df05b9\$lut for cells of type $lut. Using template $paramod$f448600bfc793f55473c7a2fe6a6bbaa5c70ddb1\$lut for cells of type $lut. Using template $paramod$0e08559afdc378cdf4a52ac2a55f2a13fc127904\$lut for cells of type $lut. Using template $paramod$01045c5a43abe7b6c83089ccc37c40d317348d62\$lut for cells of type $lut. Using template $paramod$45d35c067ded9854bad436d064758afc38659286\$lut for cells of type $lut. Using template $paramod$bdaf823c2b63b6abd253588435447f6d6dafd586\$lut for cells of type $lut. Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef\$lut for cells of type $lut. Using template $paramod$025eee2caa755b0b3cce8749e2ac0c3a95762737\$lut for cells of type $lut. Using template $paramod$de0499dcf1613c175db5c9bc998b8a7cdce56a97\$lut for cells of type $lut. Using template $paramod$7987b306da12c34d9b2e9337e04edbcd51be4369\$lut for cells of type $lut. Using template $paramod$f6123793946929f7d435cd55bd29e15437d21621\$lut for cells of type $lut. Using template $paramod$39348d1fda97f361a213fc489bfe6d58dd773c96\$lut for cells of type $lut. Using template $paramod$5234eea34206fcc0e1a72e26ef8bcf507349dd3c\$lut for cells of type $lut. Using template $paramod$e248291670c00115763480598e06a874c14498d6\$lut for cells of type $lut. Using template $paramod$64584a54ce192893535cc122840281ff55072f9f\$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. Using template $paramod$dc8eb389b2fc3ec6a78d93ff9b548b7fd27b6950\$lut for cells of type $lut. Using template $paramod$20f3f4b8e32f8a8b038b0056872dc94926194798\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. Using template $paramod$2c1875de701f39453798b76f5b327fe456cc0991\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut. Using template $paramod$6e2b27a23561eba4d5d7a3612a01502854865858\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$1e66e926164e6462a8179be1078ea3b9daa3e399\$lut for cells of type $lut. Using template $paramod$b2a4860cd839ff40d9dca4c3f237b2b534267028\$lut for cells of type $lut. Using template $paramod$5592e32ec588080518282546fe4472f0960034a5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod$3d98cbd933baee327b5d76a0c6e6cddc5563d2bd\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000101 for cells of type $lut. Using template $paramod$076deb7b432146fc56a2825020bc1b0504424a0f\$lut for cells of type $lut. Using template $paramod$25dec793a32cd1fe285093391d674488c0882bcd\$lut for cells of type $lut. Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut. Using template $paramod$90119d56b257e314528ef9fad6d905983c86ddfd\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$98d1771eb4814b2b8eb39dd0f309d94c514a3a55\$lut for cells of type $lut. Using template $paramod$f8cfc0cf2fe9042f3d2a22988630f603b85823b8\$lut for cells of type $lut. Using template $paramod$dd77df37fceba74b0f4cca98ae909be7afc8f7e8\$lut for cells of type $lut. Using template $paramod$481a7067d8729bde8a8ae0fbb48db83f66b515cd\$lut for cells of type $lut. Using template $paramod$d790a05e278f008dbc6abe4a699affdaba125e87\$lut for cells of type $lut. Using template $paramod$ee6937a50b9fd9c1fb3db9076268c3e7d787433f\$lut for cells of type $lut. Using template $paramod$256f3f936b752cf569dca900ae92c3ac452c7e57\$lut for cells of type $lut. Using template $paramod$267e9607fb2bb3118fb62f510ff3d4e27c5acea7\$lut for cells of type $lut. Using template $paramod$2bf40184ebe79d76d79e29300a096b90343ce5e4\$lut for cells of type $lut. Using template $paramod$145ba78407dd34014b3ae93ab3a01040024f1f86\$lut for cells of type $lut. Using template $paramod$10ee07cc0fb48ffe9fd58bde076417ca16389284\$lut for cells of type $lut. Using template $paramod$d47b514fbc6ed3f39d202fcf445d83b5cdfb969a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110010 for cells of type $lut. Using template $paramod$4457efb53cba86293d649f6b92240f4b90f17314\$lut for cells of type $lut. Using template $paramod$d76edc10344198fdbbc083cbc9765a888a1f48f2\$lut for cells of type $lut. Using template $paramod$47b714a1ff88320f59f1e98482278e84e0c78ed6\$lut for cells of type $lut. Using template $paramod$a8b00335f4d228c69bd06c17e43bf5dda1cbc096\$lut for cells of type $lut. Using template $paramod$82687d3ad8130b5b49618b6a28f43c60b5130fe1\$lut for cells of type $lut. Using template $paramod$694c95659b447cef99dd4cdbd49b87dfd5f6c806\$lut for cells of type $lut. Using template $paramod$c412934e1de517beef63ec24e28dacd550e4339a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut. Using template $paramod$5a2475f0ff8adfa6c48e46c1977dad3962daa33d\$lut for cells of type $lut. Using template $paramod$f87bcf1791971b4eaa30f3f28437044fef878a04\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod$9cf83e29ae1c8f8c5630302af14d44e670567a7f\$lut for cells of type $lut. Using template $paramod$d7d3023cdffb68086828ba9a023fb894dedc08c4\$lut for cells of type $lut. Using template $paramod$d40331a2bf23f4ac3ddaa661cc4b2a04ad4e217f\$lut for cells of type $lut. Using template $paramod$76c1c31d15142b183e538266fcb243b33259f7b8\$lut for cells of type $lut. Using template $paramod$5eabc64aad8eb0b1bdbddb7c6d819106efc76f97\$lut for cells of type $lut. Using template $paramod$ae93efe8d4cd860e45f35a4bf3ffc1571de89069\$lut for cells of type $lut. Using template $paramod$21a1ca6f9f5c15b304c8c46ce6cda8b91e063cf1\$lut for cells of type $lut. Using template $paramod$946e6a6550bc3aa62077efe3e7de5ea9cb9f3578\$lut for cells of type $lut. Using template $paramod$a81214d57778fa2acfa0c02858dc5118507bdec3\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011001 for cells of type $lut. Using template $paramod$9b0526c517406adf43dfede1ca1f1acd4ed76997\$lut for cells of type $lut. Using template $paramod$e952a59059edee781e193fb378957db784e26ad0\$lut for cells of type $lut. Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut. Using template $paramod$3b42eb1f31168862f225ae230268813be6d767ff\$lut for cells of type $lut. Using template $paramod$efe8e6522858192ad208465f2cc042527dc2999a\$lut for cells of type $lut. Using template $paramod$a2412177faafab8553bb61d8afd3ae92536f5ea0\$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut. Using template $paramod$863999528fd1a232b18557af2215a18efa04993d\$lut for cells of type $lut. Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut. Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$a467e3aee4b54a60cdec89714694957109e0405d\$lut for cells of type $lut. Using template $paramod$432f26b811c14bf54c5e87c8670ec65cbcaf38ac\$lut for cells of type $lut. Using template $paramod$b089060a61c5d29ddce66d73edb5ee493ec9de27\$lut for cells of type $lut. Using template $paramod$5013a2928ac29f53ce752728bdde47ba76cde3f5\$lut for cells of type $lut. Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut. Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut. Using template $paramod$828096678386a4453f064d41cbed89443fa1b5d0\$lut for cells of type $lut. Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut. Using template $paramod$60f71d0a99399e4fbb1d686477fbfd5769226a53\$lut for cells of type $lut. Using template $paramod$dc976353173719d4dd8d5c043661f2d4d2730689\$lut for cells of type $lut. Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d\$lut for cells of type $lut. Using template $paramod$8fd8efe0a495790cc9ddc97266933ea8a8cd7b45\$lut for cells of type $lut. Using template $paramod$9b95e14569a0fdd16433ba1f53d34c01df034682\$lut for cells of type $lut. Using template $paramod$d575d3554e876f643193272ee6813447059f103f\$lut for cells of type $lut. Using template $paramod$87340448ca8f23f248b0dd8c91569f04725ead93\$lut for cells of type $lut. Using template $paramod$d7856980c8e3df62f97c26ab34037f33a9e831b5\$lut for cells of type $lut. Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut. Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. Using template $paramod$ea79e410ad0f4fc3326666c891e1f3992816d636\$lut for cells of type $lut. Using template $paramod$5a621b016c894274d07edef48c49b401a15fd796\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011101 for cells of type $lut. Using template $paramod$620586420e818d3afa7e5b51fcf19f5c6ea83ad4\$lut for cells of type $lut. Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$b1680225cc6a5792caa95f54b8b3218fae21705d\$lut for cells of type $lut. Using template $paramod$abb431c2f750d341a856ff4171c01e8d1285db4f\$lut for cells of type $lut. Using template $paramod$adc0b354bb960519a616db7423a6274fc380540e\$lut for cells of type $lut. Using template $paramod$b8113752b08bd47f69a1c8c2bca1cfb157e800c9\$lut for cells of type $lut. Using template $paramod$b97dea647725901eed851280e5a3889ea3e50a3d\$lut for cells of type $lut. Using template $paramod$af0e77ed704529a8b8c89a9a361eee89099fc0f9\$lut for cells of type $lut. Using template $paramod$e48900e6416c0940d0bb569f6e8b7c4fb547bfeb\$lut for cells of type $lut. Using template $paramod$be890c21f2c4d30e642da2b8f1692f7983c02ea2\$lut for cells of type $lut. Using template $paramod$325bb4a8737975ab1a0980ac4dd3572231166eca\$lut for cells of type $lut. Using template $paramod$3b374b0454c507d1efadee363d480c52c3b3f58f\$lut for cells of type $lut. Using template $paramod$52341f6017db69268706bfd5a5ad5f208704cdde\$lut for cells of type $lut. Using template $paramod$1f341ba724cdf3f8415c749973ce9d95520d8e2a\$lut for cells of type $lut. Using template $paramod$f4257f9b9dfe762de25d0a149f2ea6e405c888f2\$lut for cells of type $lut. Using template $paramod$95e3b069aff4a6adc0a3d90d66a109cc8ab110fa\$lut for cells of type $lut. Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut. Using template $paramod$e718d2f5eb562e6029d6a1b1e060511bf1c65df1\$lut for cells of type $lut. Using template $paramod$88dc513e2d8d4fc4b71904699ba466e2c2c724fc\$lut for cells of type $lut. Using template $paramod$5ad5dab2319eaa393748d74a6ae3cf6d24e40054\$lut for cells of type $lut. Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut. Using template $paramod$21b3744c9ed62992c107ac7210966deda971a387\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$d3e8bb6d235f74996a6dc91d192fba44c919e86d\$lut for cells of type $lut. Using template $paramod$7ed3d685a887e531dc8f4f21b9907d4766cf861f\$lut for cells of type $lut. Using template $paramod$dff8e7e8854dc948604d9ed7dea9d198697a573d\$lut for cells of type $lut. Using template $paramod$530e84e711d00ee94a04273b459e87c8d074784e\$lut for cells of type $lut. Using template $paramod$338ce46cf7ff44b9974887dd2adee6c4e0530bed\$lut for cells of type $lut. Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut. Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut. Using template $paramod$20235ca863361fbc253329cfc7eeea38c77404dc\$lut for cells of type $lut. Using template $paramod$3a0a392069bc969f34c65c546a8c56fbbb67e282\$lut for cells of type $lut. Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. Using template $paramod$183ec76ed3429a430a8be24b57f3de734985f568\$lut for cells of type $lut. Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$1843b3c15f2447d117e2d5de9b00f791ef5f9fa3\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$181733d3e31dcdcea8c52d0a4fc252b3aa453564\$lut for cells of type $lut. Using template $paramod$7ca4db46d3cd57dbe2541a389808e6d33af02319\$lut for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut. Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut. Using template $paramod$f8b5a2092e0c5e20cb9d3c609617b439b0653eaf\$lut for cells of type $lut. Using template $paramod$2c1c2183c0558f2e63975c2497071b95f690b06d\$lut for cells of type $lut. Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut. Using template $paramod$b56552b15644de250f928c7e882226531acd70c9\$lut for cells of type $lut. Using template $paramod$ba4b1c9b57f942a38af35848615a2f06189d3bfe\$lut for cells of type $lut. Using template $paramod$441303b76529b811f79601ae0eb6114c8c594cf6\$lut for cells of type $lut. Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut. Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut. Using template $paramod$c5c749f7bea55a249ebdd405230f07638b5a2316\$lut for cells of type $lut. Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut. Using template $paramod$e277a522d8a930c8c8c8cdb56d33d42914aefec4\$lut for cells of type $lut. Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. Using template $paramod$ef40c88c17fd9dafc15b58ac013920ba3ecb927b\$lut for cells of type $lut. Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut. Using template $paramod$95d283d266cb57fe65712761425d251bfc701ce0\$lut for cells of type $lut. Using template $paramod$413d040dcd860cd74ca61a70644516a95d328ae7\$lut for cells of type $lut. Using template $paramod$54a853cac0e65b945d96d7dd0e9cca8bb9f3a21e\$lut for cells of type $lut. Using template $paramod$8e224a63a74b6daf8fc2e441cb0688a65e7a4073\$lut for cells of type $lut. Using template $paramod$181d49f34bcb31fbb5a26e11f31af35e57e71eb0\$lut for cells of type $lut. Using template $paramod$da8978f6d5bd3450de7985a113299bc7608e3009\$lut for cells of type $lut. Using template $paramod$4e5eddc6113cbcbdcf3b94940ed5d75c4ecd6180\$lut for cells of type $lut. Using template $paramod$f8ea567ed8f5aac81f3d2562d28b02171b0ea76f\$lut for cells of type $lut. Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut. Using template $paramod$5502a85110dbca29ac631107f0b0635e7fade476\$lut for cells of type $lut. Using template $paramod$863c404e3b83348ee34171710337d8e8efb7f8b2\$lut for cells of type $lut. Using template $paramod$ec77ef2f39e0c5347eaada9711f26fca6a276050\$lut for cells of type $lut. Using template $paramod$6d75272b1d7e81b21151dfdd423c987fc1a31054\$lut for cells of type $lut. Using template $paramod$434ab1680fd1f385fa8045923f0a261a706651b4\$lut for cells of type $lut. Using template $paramod$5630eb7681b4d1157fe1436fc615ed235b6ced94\$lut for cells of type $lut. Using template $paramod$96f437953172f5b9054aadb7949794bc8a5da56d\$lut for cells of type $lut. Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut. Using template $paramod$9fc14cb0ba5120a1da0c687a9fb19472f206fdfe\$lut for cells of type $lut. Using template $paramod$8075729953f49b6cb1b4d863b2fb20da9818d304\$lut for cells of type $lut. Using template $paramod$655e7cdf1fce9923e771969f28446489197085e2\$lut for cells of type $lut. Using template $paramod$41b777a122fa6162fe05e453fac63a5bd726825e\$lut for cells of type $lut. Using template $paramod$7cd2eb6a7d66e3dc32689a836e66ef851f6abf28\$lut for cells of type $lut. Using template $paramod$6b2890cdbb9fbde2051f214a3ef8951c84726e43\$lut for cells of type $lut. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut. Using template $paramod$3338c0be041e11344b9f33d0a7ec0d700c86a5ae\$lut for cells of type $lut. Using template $paramod$e14d97f5a9455f0cc49e0c82a2a9bb0e067f5197\$lut for cells of type $lut. Using template $paramod$415e222a12b303e67849afa76b3b77c687e431a8\$lut for cells of type $lut. Using template $paramod$3dc8df1b07971bda7726ddf94f6377e60804ab64\$lut for cells of type $lut. Using template $paramod$b831bcea202ffe191b9cfca325ae473ce1968012\$lut for cells of type $lut. Using template $paramod$fcdea2bd59a14f5c1c8afbee9caf6cd327f03387\$lut for cells of type $lut. Using template $paramod$c8918d7907f74c0cc433074a727daed8c71a96e9\$lut for cells of type $lut. Using template $paramod$f0ca35fea44426ec088a4a7886a306b7fcf54c38\$lut for cells of type $lut. Using template $paramod$d0e2cda39391606d46b58a28438fbf4233177490\$lut for cells of type $lut. Using template $paramod$7929d818ff6cdab401756b40b10229878e94bd76\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod$20ba583962918fa0136fc97b1558cc45cc91cc29\$lut for cells of type $lut. Using template $paramod$c5d791b2dd3d8afd456f4384acfd996b0f093f14\$lut for cells of type $lut. Using template $paramod$1b4942fad7257f60532954b1eb94a6b84f2e5ae3\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut. Using template $paramod$15fcde2bb753f14be8fd3d47a949d01b0412baec\$lut for cells of type $lut. Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut. Using template $paramod$71443dd9ce6d822783b911babf9e9dab228ad54a\$lut for cells of type $lut. Using template $paramod$b45308ffeb4031bc5d55ef31b149afd94d3d7565\$lut for cells of type $lut. Using template $paramod$a50983bc2d916c31a7d4beac5feb90028d16502d\$lut for cells of type $lut. Using template $paramod$9121ce01630c3ca8583fc82f729fbf1ade868ca5\$lut for cells of type $lut. Using template $paramod$c98da1ab510f98f1bdbbe5a79169ddcc9bfb334b\$lut for cells of type $lut. Using template $paramod$1f6f4e0c38a68ed22c0391bff11c5390c4beec3c\$lut for cells of type $lut. Using template $paramod$7a81ecf77e290f23576b1e6595684c225dc3c6d7\$lut for cells of type $lut. Using template $paramod$78b4324556f6321a85bd440441a5392f271ea218\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut. Using template $paramod$edfdd002d369b276282ba114ad80081aeb01c009\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut. Using template $paramod$2ca60e9b1b240ddd49cdfe31911f88dee84206c9\$lut for cells of type $lut. Using template $paramod$3ec5e45cb3e54de9dbe908707155b5f9917c9370\$lut for cells of type $lut. Using template $paramod$2fc44403459b9c93ee79bcfa44dba4c147e1879c\$lut for cells of type $lut. Using template $paramod$00b8dd8b73561ad6988b03b6600fc178778f4822\$lut for cells of type $lut. Using template $paramod$de07eb062963514b9c819aacc3e74a1253bffd53\$lut for cells of type $lut. Using template $paramod$fa9a0f1507dac5c8a305028cd7286d96e6efef74\$lut for cells of type $lut. Using template $paramod$ddb2e05c39fb5845e7c1a5681e0eb77e93113919\$lut for cells of type $lut. Using template $paramod$340dd78699f03ab43ee3aabaeecd0da716285e24\$lut for cells of type $lut. Using template $paramod$ebad17c442e6c79dab21712b37a4ddd445bcdb99\$lut for cells of type $lut. Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut. Using template $paramod$ebc35666df6e2075cc5e52cf906e32ebdf9bb453\$lut for cells of type $lut. Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut. Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut. Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut. Using template $paramod$74c0f3179b5cebe485563ea55e9b637e7ee5c0c3\$lut for cells of type $lut. Using template $paramod$8abe21ee38ced38064203ce27d377b5c4dcd9cc2\$lut for cells of type $lut. Using template $paramod$84c5cfa8d7481774250caab0fcdd6d249a376a31\$lut for cells of type $lut. Using template $paramod$ea5280fce2698f0f291737e66fca69a1d9d058e1\$lut for cells of type $lut. Using template $paramod$7491e7206ae8c682d288373efe06a43b67c277cf\$lut for cells of type $lut. Using template $paramod$1a10df59f43f252ae2ee713b788731ad5d18c6f5\$lut for cells of type $lut. Using template $paramod$5348912da867a611a8088b6b8b27a62d65f1de6e\$lut for cells of type $lut. Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut. Using template $paramod$48fd1c84ac21f870a06c7b4320aeda50820653cd\$lut for cells of type $lut. Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut. Using template $paramod$e7e7670a2b712cde199d46a408e7b41c9ac56df1\$lut for cells of type $lut. Using template $paramod$4c0221505c29b55a66f4801128a7e9ab143964dc\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut. Using template $paramod$b667944c8c1582e99ba530d8f9f5f294c96298ff\$lut for cells of type $lut. Using template $paramod$64ff9dbc9e2b5643cf88f225944724f13faf3844\$lut for cells of type $lut. Using template $paramod$d8119e7cf18bdd1d72e1822e569d9c40a2fc5848\$lut for cells of type $lut. Using template $paramod$f4ba8de7672e0668bd193576a3326c2f73778f52\$lut for cells of type $lut. Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut. Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut. Using template $paramod$bf8344c4eead49f5de1b64d00f36a560a632cff7\$lut for cells of type $lut. Using template $paramod$31f0a66a4b242b524303bfb4ac95c05ad74158f8\$lut for cells of type $lut. Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707\$lut for cells of type $lut. Using template $paramod$623c7ef4722655cb50add3cb84a3642ba0dcb50d\$lut for cells of type $lut. Using template $paramod$333972bd8f7637b8cf38f0fc32364ec7a4dd1c02\$lut for cells of type $lut. Using template $paramod$edff38987bda213b1bc8b9f42c6aa1469cc09348\$lut for cells of type $lut. Using template $paramod$8833253c105c1f3ff9a03a20302d6d0a2f4d9c5b\$lut for cells of type $lut. Using template $paramod$02750f8d568bd99efbda01449a05e084a3143ca8\$lut for cells of type $lut. Using template $paramod$79bf6531fa230138d3c495b75a4186ea1d429196\$lut for cells of type $lut. Using template $paramod$c16f370ae7798b1bdf00bba0fa0d15e5edfce48d\$lut for cells of type $lut. Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut. Using template $paramod$a191129d10a368b82781b98ff31865427345b51c\$lut for cells of type $lut. Using template $paramod$ea8c3614309befced1c4cfc4249e324e2d77ca4c\$lut for cells of type $lut. Using template $paramod$4b4486d8ab11b47d1172748e8d60d63ef1eb2086\$lut for cells of type $lut. Using template $paramod$3b56205e0e57b3ea26d80fc7983017f83663129e\$lut for cells of type $lut. Using template $paramod$30caa5615ac52efdf43dfbf1b1a633232eb131b1\$lut for cells of type $lut. Using template $paramod$d6c6e341b10d108eb56e4bbfecfbcc09b447833e\$lut for cells of type $lut. Using template $paramod$4e0dac06d9d9602cfb659e01e0850b77eec5b798\$lut for cells of type $lut. Using template $paramod$059968be1ef12c596bb5d360a749040b6777bf4a\$lut for cells of type $lut. Using template $paramod$1632c1c0242796acfc963a05742c4acd2f475c4e\$lut for cells of type $lut. Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut. Using template $paramod$d637970ae6c46c1cba9f112484c464e534062158\$lut for cells of type $lut. Using template $paramod$02ff9f4247884711a4d4a8ca1946e7ed15035152\$lut for cells of type $lut. Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b\$lut for cells of type $lut. Using template $paramod$2e91260c662bedefee0c75d5d1389234e222db20\$lut for cells of type $lut. Using template $paramod$095712d9745fb923510eeeb7a674dd08c58758d0\$lut for cells of type $lut. Using template $paramod$55c4ca9781b8fc4b3368db68d2b09565a75eb97d\$lut for cells of type $lut. Using template $paramod$5ce87e29bae748062baa41381cf4ce4a3da3a267\$lut for cells of type $lut. Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut. Using template $paramod$88ba822b87bd70d3225072de5ea87081a7ce4cf4\$lut for cells of type $lut. Using template $paramod$ec0df19840033c8b18208b7471309a53c2b25de8\$lut for cells of type $lut. Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut. Using template $paramod$133ad27679cc12d115c56a20436ffefcefb608a9\$lut for cells of type $lut. Using template $paramod$f7a897257decedfb6cc642e53d65fef7fc0df390\$lut for cells of type $lut. Using template $paramod$f231543d5aad7866c059e8ae768210b14e421524\$lut for cells of type $lut. Using template $paramod$d52cb446bc89fafcaa49f2b908e540f513a4d760\$lut for cells of type $lut. Using template $paramod$648d5b3c4c08a2b5e6752f60f9134dd7da5b02b9\$lut for cells of type $lut. Using template $paramod$424d6e5504f284c1c9fcb89924a2758a91d0d4e2\$lut for cells of type $lut. Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut. Using template $paramod$6b62468353a716e43972563d3074fa328b3ddcae\$lut for cells of type $lut. Using template $paramod$b431bfd938e35871dd0b7668e1503c7e8b9d491c\$lut for cells of type $lut. Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut. Using template $paramod$c39c6573830a79e8a4d0ada9e4f039c34fcfb5b9\$lut for cells of type $lut. Using template $paramod$6c51c1ba6c39f0c09b896d52432b366f116bd3c1\$lut for cells of type $lut. Using template $paramod$3774ca4b9dc2cd8733efd43d0d39fb00093ab9db\$lut for cells of type $lut. Using template $paramod$8ed00b090baf9dd1e8d4f94958614a6930f315ba\$lut for cells of type $lut. Using template $paramod$7bee76741eb51df66260977432d861248a5c6f1e\$lut for cells of type $lut. Using template $paramod$f39b8ca7b5d76b51a97d51c784ffe8ef759c2d90\$lut for cells of type $lut. Using template $paramod$908d8f06064587c39525d88e5396bdd9f1e27dcf\$lut for cells of type $lut. Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut. Using template $paramod$832803f2a65700892a12287ffb94f8698e0aabe8\$lut for cells of type $lut. Using template $paramod$86d1a43c2f1d620ff2cef866448dd1258c868fad\$lut for cells of type $lut. Using template $paramod$cb09784515928778cdbede4a59367758a84cefc2\$lut for cells of type $lut. Using template $paramod$129f5b55fa9a45614df91b4a79acd963ccf442b9\$lut for cells of type $lut. Using template $paramod$57cf7fbf84518d9e7604ec42b59ba9511e1f3caf\$lut for cells of type $lut. Using template $paramod$4bb876346cbc5d13aef9f873277f12d388c5d51a\$lut for cells of type $lut. Using template $paramod$7da5ab5deff78535a42a86ddb6651a407968109e\$lut for cells of type $lut. Using template $paramod$dcd78fd0c80de98c7f7a4dbe5c4c9bc061d1c5fa\$lut for cells of type $lut. Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut. Using template $paramod$2ec6422db00d358fc7469efce6208bffbc8521cd\$lut for cells of type $lut. Using template $paramod$bacc3ac4ee561384b85bf8c85cdd3d88bf0abeee\$lut for cells of type $lut. Using template $paramod$ad6b380091b845c2d88af2e9f3169885b8e3c508\$lut for cells of type $lut. Using template $paramod$f58e0d90afc57a738914697b6a4a7319b30d7e7e\$lut for cells of type $lut. Using template $paramod$8d64e576629e8d7c655e0c65958ea61e649cd93e\$lut for cells of type $lut. Using template $paramod$b371aa2997b244625a2303fc9a11f6bbb7cd058d\$lut for cells of type $lut. Using template $paramod$221832ea6a41a3208cd6f3411a952b5811695f4c\$lut for cells of type $lut. Using template $paramod$990f0fb2b3d003f8b16e47a6e2203c03f05c2581\$lut for cells of type $lut. Using template $paramod$f9b07159f0b2b2c55b0269e6dd95e01802595872\$lut for cells of type $lut. Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut. Using template $paramod$7c085cdbf0919cd3ad402d9495d97f0d71e4db93\$lut for cells of type $lut. Using template $paramod$683e1b7ebaba4a77cacad4964f7dd5fcd611079f\$lut for cells of type $lut. Using template $paramod$323dbb47a6d14615772fecb6fe7c4bec277e6c6b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26\$lut for cells of type $lut. Using template $paramod$7855bb4a9085da42c58c827ab70bdd4df7d24dda\$lut for cells of type $lut. Using template $paramod$4868a4ceeb6e23451cb4274a7aac5eeb700b0dc9\$lut for cells of type $lut. Using template $paramod$14e62338c0694b7d80cbb5d0fd29f7c0d24a02a6\$lut for cells of type $lut. Using template $paramod$0328e568d609989242dcb98a1c5328d4372a6e9c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. Using template $paramod$a175789408df1730afdaf4183d06de700f9dd2fb\$lut for cells of type $lut. Using template $paramod$e6fe3557f918973b23743b8c73432b4ea68998bd\$lut for cells of type $lut. Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a\$lut for cells of type $lut. Using template $paramod$18c84b272211d36f28b8ca7fdb33f896aac962f2\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111011 for cells of type $lut. Using template $paramod$73e46140bc46423d53c1be587f8191c9327a7b17\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$9c91b41f3eb4f6f66a7812477f556d4c72a69d7a\$lut for cells of type $lut. Using template $paramod$dbed627a1ca1346878535372c4022b0277014df3\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut. Using template $paramod$41a991bdf076ba30730fdb3fa7bfc30c3a8de839\$lut for cells of type $lut. Using template $paramod$8cf5abd26d1707a9c07dc9ce14e52d0756539cf9\$lut for cells of type $lut. Using template $paramod$8e3e9a427b2bc0e7d837447fde19028feb6ec6fc\$lut for cells of type $lut. Using template $paramod$add7808b4c4734d06d6b069a0095855a676d215c\$lut for cells of type $lut. Using template $paramod$8a6c5abb40b09da1df21fc05a960226e3ed6de8c\$lut for cells of type $lut. Using template $paramod$5f6eb11925e6a648832498cf89c8e0856ca5ed27\$lut for cells of type $lut. Using template $paramod$263b613d26e59958a0d1e36903a2016b82f2f359\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod$651e836885d95717c36e69441422c3fe04ee5f4d\$lut for cells of type $lut. Using template $paramod$ab4188c7524eec831e9177bc675d62b21a3ccd8b\$lut for cells of type $lut. Using template $paramod$918160def04c8a8c7a547e5e7ed0475448041b30\$lut for cells of type $lut. Using template $paramod$899a7d400185b4f778bea81a50f62c95a0b19d77\$lut for cells of type $lut. Using template $paramod$8b24fb07373c4ee224b517e500c9710a464b35dc\$lut for cells of type $lut. Using template $paramod$9a844ff4fab313de5f6983da14e109424759ae5e\$lut for cells of type $lut. Using template $paramod$02b63907fb626de3e5f6572173cbabd407ece191\$lut for cells of type $lut. Using template $paramod$b25ee4364fce1e5830af8da2757f561246eae010\$lut for cells of type $lut. Using template $paramod$1514847cbc89c04810abf351b20444ce638868f2\$lut for cells of type $lut. Using template $paramod$f03663c7f91be924d1e9df8220b895406b3f6489\$lut for cells of type $lut. Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut. Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut. Using template $paramod$50ec6039d9de561a6d0a8dc470847f22a306b04f\$lut for cells of type $lut. Using template $paramod$800c315b50c56727f5877366081fa1fc315ff6c3\$lut for cells of type $lut. Using template $paramod$aa9cf2f501984f3d23676491f808fe20bb38f6a7\$lut for cells of type $lut. Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee\$lut for cells of type $lut. Using template $paramod$03a9885a61e46980831d2c64059eb66aa27bbfee\$lut for cells of type $lut. Using template $paramod$5e0b307f14366a17a93679427a5c75920beb8023\$lut for cells of type $lut. Using template $paramod$0cfa7c77e7407929207db4aa01b0a94b3d8651db\$lut for cells of type $lut. Using template $paramod$031639056602a9dab4a0894878194a35372df974\$lut for cells of type $lut. Using template $paramod$d3de57c682a0913c02fe8721427a454c5b640f0c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010111 for cells of type $lut. Using template $paramod$370d1745c644a8d78b147b9a3fa9464fdd7e00bf\$lut for cells of type $lut. Using template $paramod$70d0e79dcc87154af4bb27dcb4180dd388ecc671\$lut for cells of type $lut. Using template $paramod$5877b7c16fde3cb88ae4b2db269772e62817d645\$lut for cells of type $lut. Using template $paramod$d2a1a3b18350dd0754abc41ae3ec8d880a85d26a\$lut for cells of type $lut. Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut. Using template $paramod$54e583dd1825becdcff3a2ef81dfe99c0fd2983b\$lut for cells of type $lut. Using template $paramod$68ed3377c388a0b224eb9e507fd563205c51ac9b\$lut for cells of type $lut. No more expansions possible. <suppressed ~11435 debug messages> 22.44. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in top. Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132928.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132846.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132847.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132853.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132883.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132888.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132891.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$23372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$23372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$23372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$23372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$23043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$23026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$23026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$23026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$23026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$22666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$22648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$22283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$22283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$22283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$22283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$21578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$21578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$21578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$21578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$21204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$20817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$20817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$20817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$20817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$20483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$20454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$20050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19667.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$19361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$19361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$19361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$19361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$19273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$19273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$19273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$19261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$19261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$19261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$19261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$18886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$18886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$18886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$18886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$18502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$18502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$18502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$18502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$17821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$17821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$17821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$17821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$17756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$17756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$17756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$17756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$17698.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$17372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$17372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$17372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$16971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$16971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$16971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$16971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$16337.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$16308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$16301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$16301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$16301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$16250.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$16245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$16245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$16245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$16227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$15866.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$15555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$15555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$15555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$15555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$15502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$15502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$15502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$15502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$15492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$15492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$15461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$15075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$15075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$15075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$15075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$15062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$15055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$15055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$15055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$15055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$14375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$14375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$14375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$14375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$14233.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$14213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$14196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$14196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$14196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$14186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$14186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$14186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$14186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$14176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$14176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$14176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$14176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$14166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$14166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$14154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$14137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$13819.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$13809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$13809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$13799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$13799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$13799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$13784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$13784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$13784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$13784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$13774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$13774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$13774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$13774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$13751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$13742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$13742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$13742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$13742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$13732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$12630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$12630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$12630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$12620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$12620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$12620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$12620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$12605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$12605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$12605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$12605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$12595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$12595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$12595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$12573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$12573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$12555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$12539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$12539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$11937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11923.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$11788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11788.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11696.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11663.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$11566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11415.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$11357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$11268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11251.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$133007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$133007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$11055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$11055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$10937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$10818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$10733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$10716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$10648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10604.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10487.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$10451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$10362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10177.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$10167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$10908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$9877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$9864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$9845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$9845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$9845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$9735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$9709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$132832$lut$auto$rtlil.cc:2582:Mux$3728[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$auto$rtlil.cc:2582:Mux$3728[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$10014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10031.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10985.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10122.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10126.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10155.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10200.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10257.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10295.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10376.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10456.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$10462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10467.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$10483.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10491.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10533.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11014.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10507.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10604.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10604.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10620.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10657.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10677.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$10716.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10742.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10758.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10776.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10785.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10856.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10847.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10972.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$10994.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11106.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$11128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11155.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11155.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11179.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11219.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11251.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11277.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11277.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11296.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11336.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11366.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11396.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11405.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11457.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11469.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11481.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11497.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11517.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$11606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11610.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11621.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11667.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11714.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$11804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11861.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11877.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$11886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11915.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11928.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$11971.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$12001.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12057.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12080.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12105.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12137.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12187.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12213.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12257.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12112.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$12315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12376.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$12400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12565.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$12580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$12595.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12649.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12675.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$12697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12705.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$auto$opt_dff.cc:219:make_patterns_logic$3526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$12960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$12988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$12995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13227.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$13234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$13255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$auto$fsm_map.cc:170:map_fsm$3315[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$13379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13515.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13616.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13667.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13702.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$13712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$13774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13814.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$13827.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$13890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$13922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14049.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$14127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$14137.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14176.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$14213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$14350.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14412.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$14442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14468.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14509.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$14745.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14792.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14928.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$14944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$15055.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$15075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15245.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$15461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$15555.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15572.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15681.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15720.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$15749.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$15756.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$15816.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$15909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$15999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16215.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$16227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$16227.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$16235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16269.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16301.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16308.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16341.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$16400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16433.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16449.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16516.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$16687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16754.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16949.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$16978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$16978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$17003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17277.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$17372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17377.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$auto$rtlil.cc:2582:Mux$3728[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$17435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17467.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17483.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17496.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$17520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17702.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$17719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17765.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$17781.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$17792.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$17821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17830.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$17851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$17870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17938.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$17998.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$auto$rtlil.cc:2582:Mux$3728[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$18217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18335.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18345.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$auto$rtlil.cc:2582:Mux$3728[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$18581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18765.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18891.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$18951.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$18991.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19073.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19086.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$19095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19189.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19225.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$19273.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$19404.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19561.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$auto$rtlil.cc:2582:Mux$3728[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$19728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19760.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19923.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$19963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$20040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20050.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20341.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$20405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20418.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$20454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20454.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$20542.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20568.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20755.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20785.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$20817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$20856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$20949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21015.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21051.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21077.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21144.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$21283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21578.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21591.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$21601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$21613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21625.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21760.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$21985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22085.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22283.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22457.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22492.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22508.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$22715.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$22884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22944.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22967.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$22996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$auto$rtlil.cc:2582:Mux$3728[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$23026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$23079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$23394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$23480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$23488.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$23505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$auto$rtlil.cc:2582:Mux$3728[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$23864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$23992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$24001.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24116.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$24172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$24213.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24245.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24273.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24341.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24371.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$auto$rtlil.cc:2582:Mux$3728[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$24544.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$24559.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$24601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$24613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$24738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24754.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24771.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24820.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24865.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$24888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$auto$rtlil.cc:2582:Mux$3728[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$9620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$10502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$9788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$9814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$9845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$aiger132831$9864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$9877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10150.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$10427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$aiger132831$9877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9913.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$9920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$9937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$9954.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$9767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$aiger132831$9902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$132832$lut$aiger132831$9998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$132832$lut$auto$fsm_map.cc:170:map_fsm$3315[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$auto$rtlil.cc:2582:Mux$3728[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$auto$rtlil.cc:2582:Mux$3728[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut$auto$rtlil.cc:2582:Mux$3728[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$auto$rtlil.cc:2582:Mux$3728[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.CSR_Unit.csr_write_data[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.CSR_Unit.csr_write_data[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132973.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[8].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[12].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$auto$rtlil.cc:2582:Mux$3728[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut$auto$rtlil.cc:2582:Mux$3728[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$132832$lut\SOC.Core.Pc.Input[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132856.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132858.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132869.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132875.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132880.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132907.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132923.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132834.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132955.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132961.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$133007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Removed 0 unused cells and 14274 unused wires. 22.45. Executing AUTONAME pass. Renamed 220228 objects in module top (200 iterations). <suppressed ~16487 debug messages> 22.46. Executing HIERARCHY pass (managing design hierarchy). 22.46.1. Analyzing design hierarchy.. Top module: \top 22.46.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 22.47. Printing statistics. === top === Number of wires: 7654 Number of wire bits: 23004 Number of public wires: 7654 Number of public wire bits: 23004 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 10208 $_TBUF_ 6 $scopeinfo 30 CCU2C 60 L6MUX21 439 LUT4 6500 PFUMX 1393 TRELLIS_DPR16X4 1076 TRELLIS_FF 704 22.48. Executing CHECK pass (checking for obvious problems). Checking module top... Found and reported 0 problems. 22.49. Executing JSON backend. Warnings: 21 unique messages, 22 total End of script. Logfile hash: c5e78d0549, CPU: user 11.39s system 0.12s, MEM: 270.93 MB peak Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) Time spent: 47% 1x abc9_exe (10 sec), 10% 11x techmap (2 sec), ... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (NextPNR) --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2028.812 ; gain = 404.715 ; free physical = 1416 ; free virtual = 25185 --------------------------------------------------------------------------------- [Pipeline] sh + /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained Info: constraining clock net 'clk' to 25.00 MHz Info: Logic utilisation before packing: Info: Total LUT4s: 13076/43848 29% Info: logic LUTs: 6500/43848 14% Info: carry LUTs: 120/43848 0% Info: RAM LUTs: 4304/ 5481 78% Info: RAMW LUTs: 2152/10962 19% Info: Total DFFs: 704/43848 1% Info: Packing IOs.. Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'. Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'. Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'. Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'. Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'. Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'. Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'. Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'. Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'. Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'. Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'. Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'. Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'. Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'. Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'. Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'. Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'. Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 229 FFs paired with LUTs. Info: Generating derived timing constraints... INFO: [Synth 8-11241] undeclared symbol 'pc_source', assumed default net type 'wire' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:142] WARNING: [Synth 8-11065] parameter 'SET_DIRECTION' becomes localparam in 'GPIOS' with formal parameter declaration list [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:19] WARNING: [Synth 8-11065] parameter 'READ' becomes localparam in 'GPIOS' with formal parameter declaration list [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:20] WARNING: [Synth 8-9400] empty statement in sequential block [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:54] Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: Checksum: 0x4613b3cc INFO: [Synth 8-6157] synthesizing module 'top' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1] INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1] Parameter CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1] WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:22] WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 3 connections declared, but only 2 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:22] INFO: [Synth 8-6157] synthesizing module 'Risco_5_SOC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1] Parameter CLOCK_FREQ bound to: 100000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter MEMORY_SIZE bound to: 2048 - type: integer Parameter MEMORY_FILE bound to: ../../software/memory/fpga_test_3.hex - type: string Parameter GPIO_WIDHT bound to: 8 - type: integer INFO: [Synth 8-6157] synthesizing module 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:1] Parameter BOOT_ADDRESS bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'PC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1] INFO: [Synth 8-6155] done synthesizing module 'PC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1] INFO: [Synth 8-6157] synthesizing module 'MUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1] INFO: [Synth 8-6155] done synthesizing module 'MUX' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1] INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1] INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1] INFO: [Synth 8-6157] synthesizing module 'Control_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:1] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:152] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:328] INFO: [Synth 8-6155] done synthesizing module 'Control_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:1] INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1] INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:33] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:10] INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1] INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1] INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1] INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1] INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1] INFO: [Synth 8-6157] synthesizing module 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:118] INFO: [Synth 8-6155] done synthesizing module 'CSR_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1] WARNING: [Synth 8-7071] port 'save_pc' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:228] WARNING: [Synth 8-7071] port 'interrupt_on_hold' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:228] WARNING: [Synth 8-7023] instance 'CSR_Unit' of module 'CSR_Unit' has 15 connections declared, but only 13 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:228] INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:1] WARNING: [Synth 8-7071] port 'halt' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32] WARNING: [Synth 8-7071] port 'interruption_request_external' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32] WARNING: [Synth 8-7071] port 'interruption_request_timer' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32] WARNING: [Synth 8-7071] port 'interruption_request_software' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32] WARNING: [Synth 8-7071] port 'interruption_request_fast' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32] WARNING: [Synth 8-7023] instance 'Core' of module 'Core' has 14 connections declared, but only 9 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32] INFO: [Synth 8-6157] synthesizing module 'Memory' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1] Parameter MEMORY_FILE bound to: ../../software/memory/fpga_test_3.hex - type: string Parameter MEMORY_SIZE bound to: 2048 - type: integer INFO: [Synth 8-3876] $readmem data file '../../software/memory/fpga_test_3.hex' is read successfully [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:35] INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1] INFO: [Synth 8-6157] synthesizing module 'BUS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1] INFO: [Synth 8-6155] done synthesizing module 'BUS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1] INFO: [Synth 8-6157] synthesizing module 'LEDs' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1] INFO: [Synth 8-6155] done synthesizing module 'LEDs' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1] INFO: [Synth 8-6157] synthesizing module 'UART' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1] Parameter CLOCK_FREQ bound to: 100000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer INFO: [Synth 8-6157] synthesizing module 'FIFO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1] Parameter DEPTH bound to: 8 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1] INFO: [Synth 8-6157] synthesizing module 'uart_tool_rx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 100000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tool_rx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10] INFO: [Synth 8-6157] synthesizing module 'uart_tool_tx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 100000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tool_tx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10] INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1] INFO: [Synth 8-6157] synthesizing module 'GPIOS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1] Parameter WIDHT bound to: 8 - type: integer INFO: [Synth 8-6157] synthesizing module 'GPIO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1] INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1] INFO: [Synth 8-6155] done synthesizing module 'GPIOS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1] INFO: [Synth 8-6155] done synthesizing module 'Risco_5_SOC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1] INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1] Info: Device utilisation: Info: TRELLIS_IO: 18/ 245 7% Info: DCCA: 1/ 56 1% Info: DP16KD: 0/ 108 0% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 704/43848 1% Info: TRELLIS_COMB: 13126/43848 29% Info: TRELLIS_RAMW: 1076/ 5481 19% WARNING: [Synth 8-3848] Net interrupt_on_hold in module/entity CSR_Unit does not have driver. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:20] WARNING: [Synth 8-6014] Unused sequential element buffer_full_reg was removed. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:52] WARNING: [Synth 8-6014] Unused sequential element tx_fifo_read_reg was removed. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:46] WARNING: [Synth 8-7129] Port address[31] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[7] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[6] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[5] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[4] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[3] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[2] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[1] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[16] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[15] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[14] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[13] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[12] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[11] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[10] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[9] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[8] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[31] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[30] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[29] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[28] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[27] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[26] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[25] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[24] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[23] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[22] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[21] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[20] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[19] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[18] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[17] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[16] in module UART is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2116.781 ; gain = 492.684 ; free physical = 1001 ; free virtual = 24771 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2134.594 ; gain = 510.496 ; free physical = 987 ; free virtual = 24757 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2134.594 ; gain = 510.496 ; free physical = 987 ; free virtual = 24757 --------------------------------------------------------------------------------- Info: Placed 18 cells based on constraints. Info: Creating initial analytic placement for 6237 cells, random placement wirelen = 570079. Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2134.594 ; gain = 0.000 ; free physical = 975 ; free virtual = 24745 Info: at initial placer iter 0, wirelen = 2865 Info: at initial placer iter 1, wirelen = 2252 Info: at initial placer iter 2, wirelen = 1718 Info: at initial placer iter 3, wirelen = 1684 Info: Running main analytical placer, max placement attempts per cell = 27844453. INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Info: at iteration #1, type ALL: wirelen solved = 1668, spread = 101886, legal = 102720; time = 0.40s Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2281.344 ; gain = 0.000 ; free physical = 953 ; free virtual = 24723 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2281.379 ; gain = 0.000 ; free physical = 953 ; free virtual = 24723 Info: at iteration #2, type ALL: wirelen solved = 7496, spread = 71010, legal = 72193; time = 0.46s Info: at iteration #3, type ALL: wirelen solved = 13000, spread = 66620, legal = 67656; time = 0.42s Info: at iteration #4, type ALL: wirelen solved = 19007, spread = 63531, legal = 64668; time = 0.58s Info: at iteration #5, type ALL: wirelen solved = 21184, spread = 59230, legal = 60767; time = 0.41s Info: at iteration #6, type ALL: wirelen solved = 24007, spread = 57386, legal = 58817; time = 0.40s Info: at iteration #7, type ALL: wirelen solved = 25389, spread = 54164, legal = 55815; time = 0.39s Info: at iteration #8, type ALL: wirelen solved = 27290, spread = 53364, legal = 54718; time = 0.40s Info: at iteration #9, type ALL: wirelen solved = 28822, spread = 52112, legal = 53538; time = 0.52s Info: at iteration #10, type ALL: wirelen solved = 29707, spread = 50985, legal = 52581; time = 0.37s Info: at iteration #11, type ALL: wirelen solved = 30125, spread = 50117, legal = 51663; time = 0.38s --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2281.379 ; gain = 657.281 ; free physical = 921 ; free virtual = 24694 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2281.379 ; gain = 657.281 ; free physical = 921 ; free virtual = 24694 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2281.379 ; gain = 657.281 ; free physical = 921 ; free virtual = 24694 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RESET_COUNTER | 00 | 01 IDLE | 01 | 10 INIT | 10 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FETCH | 0000000000000000000000000000000000000000000001 | 000000 DECODE | 0000000000000000000000000000000000000000000010 | 000001 MEMADR | 0000000000000000000000000000000000000000000100 | 000010 MEMREAD_UNALIGNED | 0000000000000000000000000000000000000000001000 | 010110 LOAD_FIRST_BLOCK | 0000000000000000000000000000000000000000010000 | 010000 SAVE_FIRST_BLOCK | 0000000000000000000000000000000000000000100000 | 010001 CALC_NEXT_ADDRESS | 0000000000000000000000000000000000000001000000 | 010010 READ_SECOND_BLOCK | 0000000000000000000000000000000000000010000000 | 010011 LOAD_SECOND_BLOCK | 0000000000000000000000000000000000000100000000 | 010100 MERGE_BLOCKS | 0000000000000000000000000000000000001000000000 | 010101 FILTER_ALU_WB | 0000000000000000000000000000000000010000000000 | 010111 MEMREAD | 0000000000000000000000000000000000100000000000 | 000011 MEMWB | 0000000000000000000000000000000001000000000000 | 000100 MEMWRITE_UNALIGNED | 0000000000000000000000000000000010000000000000 | 011000 GEN_FIRST_BLOCK_PART_1 | 0000000000000000000000000000000100000000000000 | 011001 GEN_FIRST_BLOCK_PART_2 | 0000000000000000000000000000001000000000000000 | 011010 GEN_SECOND_BLOCK_PART_1 | 0000000000000000000000000000010000000000000000 | 011011 GEN_SECOND_BLOCK_PART_2 | 0000000000000000000000000000100000000000000000 | 011100 MERGE_WRITE_BLOCKS | 0000000000000000000000000001000000000000000000 | 011101 SWAP_VALUE_DIRECTION | 0000000000000000000000000010000000000000000000 | 011110 CLEAR_VALUE_HALF_BYTE_ONE_BLOCK | 0000000000000000000000000100000000000000000000 | 100010 CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_2 | 0000000000000000000000001000000000000000000000 | 100011 CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_3 | 0000000000000000000000010000000000000000000000 | 100100 CLEAR_VALUE | 0000000000000000000000100000000000000000000000 | 011111 MERGE_WRITE_VALUE_1 | 0000000000000000000001000000000000000000000000 | 100000 WRITE_VALUE_1 | 0000000000000000000010000000000000000000000000 | 100001 CALC_SECOND_BLOCK_ADDRESS_TO_WRITE | 0000000000000000000100000000000000000000000000 | 100101 READ_SECOND_BLOCK_TO_WRITE | 0000000000000000001000000000000000000000000000 | 100110 LOAD_SECOND_BLOCK_TO_WRITE | 0000000000000000010000000000000000000000000000 | 100111 LOAD_SECOND_BLOCK_TO_WRITE_2 | 0000000000000000100000000000000000000000000000 | 101000 SWAP_VALUE_DIRECTION_2 | 0000000000000001000000000000000000000000000000 | 101001 CLEAR_VALUE_PART_2 | 0000000000000010000000000000000000000000000000 | 101010 CLEAR_VALUE_PART_2_1 | 0000000000000100000000000000000000000000000000 | 101011 MERGE_WRITE_VALUE_2 | 0000000000001000000000000000000000000000000000 | 101100 WRITE_VALUE_2 | 0000000000010000000000000000000000000000000000 | 101101 MEMWRITE | 0000000000100000000000000000000000000000000000 | 000101 EXECUTER | 0000000001000000000000000000000000000000000000 | 000110 EXECUTEI | 0000000010000000000000000000000000000000000000 | 001000 JAL | 0000000100000000000000000000000000000000000000 | 001001 BEQ | 0000001000000000000000000000000000000000000000 | 001010 AUIPC | 0000010000000000000000000000000000000000000000 | 001100 LUI | 0000100000000000000000000000000000000000000000 | 001101 JALR_PC | 0001000000000000000000000000000000000000000000 | 001110 JALR | 0010000000000000000000000000000000000000000000 | 001011 ALUWB | 0100000000000000000000000000000000000000000000 | 000111 EXECUTECSR | 1000000000000000000000000000000000000000000000 | 001111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit' Info: at iteration #12, type ALL: wirelen solved = 31234, spread = 50397, legal = 52010; time = 0.41s WARNING: [Synth 8-327] inferring latch for variable 'aluop_out_reg' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:12] --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_RECV | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_SEND | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2281.379 ; gain = 657.281 ; free physical = 864 ; free virtual = 24637 --------------------------------------------------------------------------------- Info: at iteration #13, type ALL: wirelen solved = 32325, spread = 48489, legal = 50206; time = 0.62s --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 3 Input 32 Bit Adders := 1 2 Input 11 Bit Adders := 2 2 Input 6 Bit Adders := 4 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 2 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 32 Bit XORs := 1 +---XORs : 2 Bit Wide XORs := 1 +---Registers : 33 Bit Registers := 1 32 Bit Registers := 48 16 Bit Registers := 2 11 Bit Registers := 2 8 Bit Registers := 8 6 Bit Registers := 1 4 Bit Registers := 2 1 Bit Registers := 18 +---RAMs : 16K Bit (512 X 32 bit) RAMs := 1 64 Bit (8 X 8 bit) RAMs := 2 +---Muxes : 46 Input 46 Bit Muxes := 1 2 Input 46 Bit Muxes := 17 11 Input 46 Bit Muxes := 1 3 Input 33 Bit Muxes := 1 2 Input 32 Bit Muxes := 21 8 Input 32 Bit Muxes := 1 4 Input 32 Bit Muxes := 10 6 Input 32 Bit Muxes := 1 2 Input 31 Bit Muxes := 1 2 Input 8 Bit Muxes := 3 5 Input 8 Bit Muxes := 1 3 Input 6 Bit Muxes := 1 2 Input 6 Bit Muxes := 4 2 Input 5 Bit Muxes := 1 46 Input 4 Bit Muxes := 1 9 Input 4 Bit Muxes := 1 10 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 1 5 Input 3 Bit Muxes := 1 2 Input 3 Bit Muxes := 3 4 Input 3 Bit Muxes := 2 46 Input 3 Bit Muxes := 3 10 Input 3 Bit Muxes := 1 3 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 14 46 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 4 3 Input 1 Bit Muxes := 6 2 Input 1 Bit Muxes := 65 46 Input 1 Bit Muxes := 12 4 Input 1 Bit Muxes := 3 8 Input 1 Bit Muxes := 7 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Info: at iteration #14, type ALL: wirelen solved = 32079, spread = 48768, legal = 50338; time = 0.36s [80%] Tech-Mapping Phase 3 completed [90%] Tech-Mapping Phase 4 completed WARN (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":226) WARN (NL0002) : The module "MUX" instantiated to "PCSourceMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":152) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29) [95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed [100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed GowinSynthesis finish Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed Processing netlist completed Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst" Physical Constraint parsed completed Running placement...... Info: at iteration #15, type ALL: wirelen solved = 32860, spread = 48839, legal = 50338; time = 0.36s --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met Info: at iteration #16, type ALL: wirelen solved = 33864, spread = 49642, legal = 51086; time = 0.40s INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template. Info: at iteration #17, type ALL: wirelen solved = 34870, spread = 48462, legal = 50067; time = 0.37s Info: at iteration #18, type ALL: wirelen solved = 34731, spread = 47436, legal = 48958; time = 0.53s Info: at iteration #19, type ALL: wirelen solved = 34815, spread = 47406, legal = 49136; time = 0.37s Info: at iteration #20, type ALL: wirelen solved = 34898, spread = 46880, legal = 48465; time = 0.37s Info: at iteration #21, type ALL: wirelen solved = 34803, spread = 46487, legal = 48051; time = 0.37s Info: at iteration #22, type ALL: wirelen solved = 34902, spread = 46174, legal = 47993; time = 0.40s [10%] Placement Phase 0 completed Info: at iteration #23, type ALL: wirelen solved = 35135, spread = 45696, legal = 47439; time = 0.51s Info: at iteration #24, type ALL: wirelen solved = 35198, spread = 45462, legal = 47321; time = 0.38s Info: at iteration #25, type ALL: wirelen solved = 35360, spread = 45512, legal = 47193; time = 0.37s Info: at iteration #26, type ALL: wirelen solved = 35640, spread = 45414, legal = 47282; time = 0.37s [20%] Placement Phase 1 completed Info: at iteration #27, type ALL: wirelen solved = 35692, spread = 45270, legal = 46965; time = 0.45s Info: at iteration #28, type ALL: wirelen solved = 35706, spread = 46115, legal = 47745; time = 0.48s Info: at iteration #29, type ALL: wirelen solved = 36346, spread = 45894, legal = 47610; time = 0.37s Info: at iteration #30, type ALL: wirelen solved = 36349, spread = 46727, legal = 48286; time = 0.36s Info: at iteration #31, type ALL: wirelen solved = 36890, spread = 46387, legal = 47843; time = 0.37s Info: at iteration #32, type ALL: wirelen solved = 37226, spread = 45981, legal = 47625; time = 0.43s Info: HeAP Placer Time: 20.65s Info: of which solving equations: 12.12s Info: of which spreading cells: 1.57s Info: of which strict legalisation: 0.47s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 9739, wirelen = 46965 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2281.379 ; gain = 657.281 ; free physical = 653 ; free virtual = 24434 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Preliminary Mapping Report (see note below) +------------+-----------------------------+-----------+----------------------+-----------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-----------------------------+-----------+----------------------+-----------------+ |top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 | |top | SOC/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |top | SOC/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | +------------+-----------------------------+-----------+----------------------+-----------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:34 ; elapsed = 00:00:34 . Memory (MB): peak = 2281.379 ; gain = 657.281 ; free physical = 650 ; free virtual = 24430 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Info: at iteration #5: temp = 0.000000, timing cost = 9648, wirelen = 42779 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:00:37 . Memory (MB): peak = 2281.379 ; gain = 657.281 ; free physical = 647 ; free virtual = 24428 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +------------+-----------------------------+-----------+----------------------+-----------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-----------------------------+-----------+----------------------+-----------------+ |top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 | |top | SOC/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |top | SOC/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 | +------------+-----------------------------+-----------+----------------------+-----------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- [30%] Placement Phase 2 completed --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2281.379 ; gain = 657.281 ; free physical = 605 ; free virtual = 24386 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2281.379 ; gain = 657.281 ; free physical = 593 ; free virtual = 24374 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2281.379 ; gain = 657.281 ; free physical = 593 ; free virtual = 24374 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2281.379 ; gain = 657.281 ; free physical = 591 ; free virtual = 24372 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2281.379 ; gain = 657.281 ; free physical = 588 ; free virtual = 24369 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2281.379 ; gain = 657.281 ; free physical = 586 ; free virtual = 24367 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2281.379 ; gain = 657.281 ; free physical = 585 ; free virtual = 24365 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFG | 2| |2 |CARRY4 | 23| |3 |LUT1 | 8| |4 |LUT2 | 162| |5 |LUT3 | 193| |6 |LUT4 | 186| |7 |LUT5 | 402| |8 |LUT6 | 1435| |9 |MUXF7 | 387| |10 |MUXF8 | 30| |11 |RAM256X1S | 64| |12 |RAM32M | 2| |13 |RAM32X1D | 4| |14 |FDRE | 1758| |15 |FDSE | 5| |16 |LD | 4| |17 |IBUF | 2| |18 |IOBUF | 8| |19 |OBUF | 9| +------+----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2281.379 ; gain = 657.281 ; free physical = 583 ; free virtual = 24364 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 38 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2281.379 ; gain = 510.496 ; free physical = 593 ; free virtual = 24373 Synthesis Optimization Complete : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2281.379 ; gain = 657.281 ; free physical = 593 ; free virtual = 24373 INFO: [Project 1-571] Translating synthesized netlist Info: at iteration #10: temp = 0.000000, timing cost = 10193, wirelen = 41294 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2281.379 ; gain = 0.000 ; free physical = 861 ; free virtual = 24641 INFO: [Netlist 29-17] Analyzing 522 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2345.375 ; gain = 0.000 ; free physical = 859 ; free virtual = 24639 INFO: [Project 1-111] Unisim Transformation Summary: A total of 82 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 8 instances LD => LDCE: 4 instances RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances Synth Design complete | Checksum: 2cad56c5 INFO: [Common 17-83] Releasing license: Synthesis 74 Infos, 119 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:54 ; elapsed = 00:00:51 . Memory (MB): peak = 2345.410 ; gain = 1028.320 ; free physical = 858 ; free virtual = 24638 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2021.757; main = 1747.860; forked = 423.194 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3218.984; main = 2345.379; forked = 969.652 # opt_design Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.79 . Memory (MB): peak = 2409.406 ; gain = 63.996 ; free physical = 853 ; free virtual = 24633 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 105e4cc7e Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2523.219 ; gain = 113.812 ; free physical = 790 ; free virtual = 24571 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 105e4cc7e Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 521 ; free virtual = 24302 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 105e4cc7e Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 521 ; free virtual = 24302 Phase 1 Initialization | Checksum: 105e4cc7e Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 521 ; free virtual = 24302 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 105e4cc7e Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 521 ; free virtual = 24302 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 105e4cc7e Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 521 ; free virtual = 24302 Phase 2 Timer Update And Timing Data Collection | Checksum: 105e4cc7e Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 521 ; free virtual = 24302 Phase 3 Retarget INFO: [Opt 31-1566] Pulled 2 inverters resulting in an inversion of 8 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: c751195a Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 521 ; free virtual = 24302 Retarget | Checksum: c751195a INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 2 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: c751195a Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.2 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 521 ; free virtual = 24302 Constant propagation | Checksum: c751195a INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep Phase 5 Sweep | Checksum: d05c018c Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2770.156 ; gain = 0.000 ; free physical = 521 ; free virtual = 24301 Sweep | Checksum: d05c018c INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 1 cells Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: d05c018c Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2802.172 ; gain = 32.016 ; free physical = 521 ; free virtual = 24301 BUFG optimization | Checksum: d05c018c INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: d05c018c Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2802.172 ; gain = 32.016 ; free physical = 521 ; free virtual = 24301 Shift Register Optimization | Checksum: d05c018c INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 126e560c2 Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.3 . Memory (MB): peak = 2802.172 ; gain = 32.016 ; free physical = 521 ; free virtual = 24301 Post Processing Netlist | Checksum: 126e560c2 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1dd117c22 Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2802.172 ; gain = 32.016 ; free physical = 521 ; free virtual = 24301 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2802.172 ; gain = 0.000 ; free physical = 521 ; free virtual = 24301 Phase 9.2 Verifying Netlist Connectivity | Checksum: 1dd117c22 Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2802.172 ; gain = 32.016 ; free physical = 521 ; free virtual = 24301 Phase 9 Finalization | Checksum: 1dd117c22 Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2802.172 ; gain = 32.016 ; free physical = 521 ; free virtual = 24301 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 2 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 8 | 1 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 1dd117c22 Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2802.172 ; gain = 32.016 ; free physical = 521 ; free virtual = 24301 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2802.172 ; gain = 0.000 ; free physical = 521 ; free virtual = 24301 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 1dd117c22 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2802.172 ; gain = 0.000 ; free physical = 521 ; free virtual = 24301 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 1dd117c22 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.172 ; gain = 0.000 ; free physical = 521 ; free virtual = 24301 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.172 ; gain = 0.000 ; free physical = 521 ; free virtual = 24301 Ending Netlist Obfuscation Task | Checksum: 1dd117c22 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.172 ; gain = 0.000 ; free physical = 521 ; free virtual = 24301 INFO: [Common 17-83] Releasing license: Implementation 19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2802.172 ; gain = 456.762 ; free physical = 521 ; free virtual = 24301 # place_design Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-83] Releasing license: Implementation INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2834.188 ; gain = 0.000 ; free physical = 518 ; free virtual = 24298 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 130b01abc Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2834.188 ; gain = 0.000 ; free physical = 518 ; free virtual = 24298 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2834.188 ; gain = 0.000 ; free physical = 518 ; free virtual = 24298 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Info: at iteration #15: temp = 0.000000, timing cost = 10728, wirelen = 40777 INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f76724fb Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2834.188 ; gain = 0.000 ; free physical = 524 ; free virtual = 24304 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: f91e9462 Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 523 ; free virtual = 24303 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: f91e9462 Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 523 ; free virtual = 24303 Phase 1 Placer Initialization | Checksum: f91e9462 Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 523 ; free virtual = 24303 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 153a46bcf Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 521 ; free virtual = 24302 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1d0eb1b7d Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 521 ; free virtual = 24302 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 1d0eb1b7d Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.215 ; gain = 7.027 ; free physical = 521 ; free virtual = 24302 Phase 2.4 Global Placement Core Info: at iteration #16: temp = 0.000000, timing cost = 10191, wirelen = 40716 Info: SA placement time 28.24s Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 35.01 MHz (PASS at 25.00 MHz) Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 12.95 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 8.60 ns Info: Slack histogram: Info: legend: * represents 163 endpoint(s) Info: + represents [1,163) endpoint(s) Info: [ 11440, 12830) |+ Info: [ 12830, 14220) |+ Info: [ 14220, 15610) |**+ Info: [ 15610, 17000) |*****+ Info: [ 17000, 18390) |*****+ Info: [ 18390, 19780) |*+ Info: [ 19780, 21170) |****+ Info: [ 21170, 22560) |*************+ Info: [ 22560, 23950) |***********+ Info: [ 23950, 25340) |****+ Info: [ 25340, 26730) |********************************+ Info: [ 26730, 28120) |************************************************************ Info: [ 28120, 29510) |********************+ Info: [ 29510, 30900) |+ Info: [ 30900, 32290) |*+ Info: [ 32290, 33680) |**+ Info: [ 33680, 35070) |*+ Info: [ 35070, 36460) |+ Info: [ 36460, 37850) |+ Info: [ 37850, 39240) |+ Info: Checksum: 0xdea8d9eb Phase 2.4.1 UpdateTiming Before Physical Synthesis Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1e0fe456a Time (s): cpu = 00:00:14 ; elapsed = 00:00:04 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 463 ; free virtual = 24244 Phase 2.4.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 71 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 27 nets or LUTs. Breaked 0 LUT, combined 27 existing LUTs and moved 0 existing LUT Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 509 ; free virtual = 24290 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 27 | 27 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 27 | 27 | 0 | 4 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.4.2 Physical Synthesis In Placer | Checksum: 17563c468 Time (s): cpu = 00:00:15 ; elapsed = 00:00:05 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 509 ; free virtual = 24290 Phase 2.4 Global Placement Core | Checksum: 220001dff Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 498 ; free virtual = 24279 Phase 2 Global Placement | Checksum: 220001dff Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 498 ; free virtual = 24279 Info: Routing 66433 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 20a403ec0 Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 495 ; free virtual = 24275 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 12ca45ff8 Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 506 ; free virtual = 24286 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 13b2d4308 Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 509 ; free virtual = 24289 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1796c96ac Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 507 ; free virtual = 24288 Phase 3.5 Small Shape Detail Placement Info: 1000 | 146 853 | 146 853 | 65760| 1.49 1.49| Info: 2000 | 217 1782 | 71 929 | 65168| 0.37 1.86| Info: 3000 | 318 2681 | 101 899 | 64986| 0.37 2.23| Phase 3.5 Small Shape Detail Placement | Checksum: 1798ffff3 Time (s): cpu = 00:00:20 ; elapsed = 00:00:07 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 509 ; free virtual = 24290 Phase 3.6 Re-assign LUT pins Info: 4000 | 398 3601 | 80 920 | 64468| 0.35 2.58| Phase 3.6 Re-assign LUT pins | Checksum: 1a8ef1000 Time (s): cpu = 00:00:21 ; elapsed = 00:00:07 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 509 ; free virtual = 24290 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 16a9fefa4 Time (s): cpu = 00:00:21 ; elapsed = 00:00:07 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 509 ; free virtual = 24290 Phase 3 Detail Placement | Checksum: 16a9fefa4 Time (s): cpu = 00:00:21 ; elapsed = 00:00:07 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 509 ; free virtual = 24290 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Info: 5000 | 494 4505 | 96 904 | 63668| 0.34 2.92| INFO: [Timing 38-35] Done setting XDC timing constraints. Info: 6000 | 603 5396 | 109 891 | 63006| 0.44 3.36| Phase 4.1.1 Post Placement Optimization Info: 7000 | 700 6299 | 97 903 | 62751| 0.38 3.74| Post Placement Optimization Initialization | Checksum: 1f138cc74 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.882 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 1a9e2d7ff Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 500 ; free virtual = 24281 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 1a9e2d7ff Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 494 ; free virtual = 24275 Phase 4.1.1.1 BUFG Insertion | Checksum: 1f138cc74 Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 491 ; free virtual = 24272 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=8.882. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1f2c40495 Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 509 ; free virtual = 24289 Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 508 ; free virtual = 24289 Phase 4.1 Post Commit Optimization | Checksum: 1f2c40495 Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 505 ; free virtual = 24285 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1f2c40495 Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 508 ; free virtual = 24289 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 2x2| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1f2c40495 Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 504 ; free virtual = 24285 Phase 4.3 Placer Reporting | Checksum: 1f2c40495 Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 502 ; free virtual = 24282 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 511 ; free virtual = 24292 Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 511 ; free virtual = 24292 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ca941ac3 Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 509 ; free virtual = 24289 Ending Placer Task | Checksum: d5518cc7 Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2849.219 ; gain = 15.031 ; free physical = 505 ; free virtual = 24286 29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:09 . Memory (MB): peak = 2849.219 ; gain = 47.047 ; free physical = 504 ; free virtual = 24285 # report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt Info: 8000 | 779 7220 | 79 921 | 62099| 0.37 4.11| # report_utilization -file digilent_nexys4ddr_utilization_place.rpt Info: 9000 | 886 8113 | 107 893 | 61645| 0.33 4.44| # report_io -file digilent_nexys4ddr_io.rpt report_io: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 510 ; free virtual = 24290 # report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt Info: 10000 | 991 9008 | 105 895 | 61072| 0.35 4.79| report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 510 ; free virtual = 24290 # report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt Info: 11000 | 1067 9932 | 76 924 | 60286| 0.34 5.13| # route_design Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads Info: 12000 | 1177 10822 | 110 890 | 59901| 0.38 5.52| Info: 13000 | 1285 11714 | 108 892 | 59654| 0.34 5.86| INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design Checksum: PlaceDB: 3910ec48 ConstDB: 0 ShapeSum: 9c40a07f RouteDB: 0 Info: 14000 | 1395 12604 | 110 890 | 59786| 0.43 6.29| Info: 15000 | 1463 13536 | 68 932 | 59019| 0.29 6.58| Info: 16000 | 1575 14424 | 112 888 | 58701| 0.31 6.89| Info: 17000 | 1670 15329 | 95 905 | 58139| 0.34 7.23| Info: 18000 | 1784 16215 | 114 886 | 57421| 0.35 7.57| Info: 19000 | 1879 17120 | 95 905 | 57188| 0.32 7.89| Info: 20000 | 1961 18038 | 82 918 | 56557| 0.33 8.23| [50%] Placement Phase 3 completed Running routing...... [60%] Routing Phase 0 completed Info: 21000 | 2046 18953 | 85 915 | 55718| 0.31 8.54| Info: 22000 | 2169 19830 | 123 877 | 55545| 0.37 8.90| Info: 23000 | 2252 20747 | 83 917 | 55355| 0.38 9.28| Info: 24000 | 2331 21668 | 79 921 | 55179| 0.37 9.66| Info: 25000 | 2436 22563 | 105 895 | 54629| 0.39 10.05| Info: 26000 | 2503 23496 | 67 933 | 54326| 0.32 10.37| Info: 27000 | 2557 24442 | 54 946 | 54025| 0.30 10.66| Info: 28000 | 2654 25345 | 97 903 | 53201| 0.33 10.99| Info: 29000 | 2742 26257 | 88 912 | 52481| 0.33 11.32| Info: 30000 | 2879 27120 | 137 863 | 53112| 0.38 11.71| Info: 31000 | 2967 28032 | 88 912 | 52538| 0.52 12.23| Info: 32000 | 3005 28994 | 38 962 | 51696| 0.48 12.71| Info: 33000 | 3116 29883 | 111 889 | 51256| 0.51 13.22| Info: 34000 | 3196 30803 | 80 920 | 50393| 0.38 13.60| Info: 35000 | 3282 31717 | 86 914 | 49718| 0.37 13.97| Info: 36000 | 3389 32610 | 107 893 | 49196| 0.34 14.31| Info: 37000 | 3528 33471 | 139 861 | 48595| 0.34 14.65| Info: 38000 | 3710 34289 | 182 818 | 48336| 0.40 15.06| Info: 39000 | 3838 35161 | 128 872 | 47497| 0.35 15.41| Info: 40000 | 3954 36045 | 116 884 | 47099| 0.41 15.82| Info: 41000 | 4056 36943 | 102 898 | 46346| 0.34 16.15| Info: 42000 | 4177 37822 | 121 879 | 45670| 0.35 16.51| Info: 43000 | 4271 38728 | 94 906 | 45278| 0.34 16.85| Info: 44000 | 4363 39636 | 92 908 | 46150| 0.35 17.20| Info: 45000 | 4433 40566 | 70 930 | 45876| 0.37 17.57| Info: 46000 | 4472 41527 | 39 961 | 44918| 0.36 17.93| [70%] Routing Phase 1 completed Info: 47000 | 4589 42410 | 117 883 | 45392| 0.41 18.34| Info: 48000 | 4651 43348 | 62 938 | 44569| 0.36 18.71| Info: 49000 | 4821 44178 | 170 830 | 43919| 0.37 19.08| Info: 50000 | 4948 45051 | 127 873 | 43341| 0.36 19.44| Info: 51000 | 5046 45953 | 98 902 | 43935| 0.37 19.81| Info: 52000 | 5073 46926 | 27 973 | 43135| 0.36 20.17| Info: 53000 | 5174 47825 | 101 899 | 42574| 0.38 20.55| Info: 54000 | 5286 48713 | 112 888 | 41882| 0.38 20.93| Info: 55000 | 5427 49572 | 141 859 | 41308| 0.38 21.31| Info: 56000 | 5541 50458 | 114 886 | 40753| 0.37 21.67| Info: 57000 | 5666 51333 | 125 875 | 39968| 0.36 22.03| Info: 58000 | 5787 52212 | 121 879 | 39425| 0.38 22.41| Info: 59000 | 5919 53080 | 132 868 | 38698| 0.34 22.75| Info: 60000 | 6104 53895 | 185 815 | 38197| 0.40 23.15| Info: 61000 | 6241 54758 | 137 863 | 37444| 0.36 23.51| Info: 62000 | 6344 55655 | 103 897 | 37089| 0.40 23.91| Info: 63000 | 6404 56595 | 60 940 | 36698| 0.34 24.25| Info: 64000 | 6539 57460 | 135 865 | 36328| 0.38 24.63| Info: 65000 | 6668 58331 | 129 871 | 35900| 0.40 25.03| Info: 66000 | 6804 59195 | 136 864 | 35662| 0.39 25.43| Info: 67000 | 6867 60132 | 63 937 | 35533| 0.45 25.88| Info: 68000 | 7019 60980 | 152 848 | 35348| 0.41 26.29| Info: 69000 | 7137 61862 | 118 882 | 35026| 0.43 26.72| Info: 70000 | 7275 62724 | 138 862 | 34341| 0.40 27.12| Info: 71000 | 7377 63622 | 102 898 | 34001| 0.37 27.49| Info: 72000 | 7565 64434 | 188 812 | 33365| 0.38 27.87| Info: 73000 | 7829 65170 | 264 736 | 33324| 0.45 28.32| Info: 74000 | 7986 66013 | 157 843 | 32623| 0.42 28.73| Info: 75000 | 8065 66934 | 79 921 | 33832| 0.44 29.18| Info: 76000 | 8081 67918 | 16 984 | 32861| 0.39 29.57| Info: 77000 | 8231 68768 | 150 850 | 32086| 0.38 29.96| [80%] Routing Phase 2 completed Info: 78000 | 8399 69600 | 168 832 | 31622| 0.40 30.36| Info: 79000 | 8591 70408 | 192 808 | 30875| 0.37 30.73| Info: 80000 | 8818 71181 | 227 773 | 30337| 0.40 31.14| Info: 81000 | 9066 71933 | 248 752 | 29767| 0.49 31.62| Info: 82000 | 9314 72685 | 248 752 | 29164| 0.45 32.07| Info: 83000 | 9597 73402 | 283 717 | 28929| 0.47 32.53| Info: 84000 | 9935 74064 | 338 662 | 28494| 0.45 32.99| Info: 85000 | 10220 74779 | 285 715 | 28397| 0.61 33.60| Info: 86000 | 10429 75570 | 209 791 | 29157| 0.51 34.11| Info: 87000 | 10556 76443 | 127 873 | 28532| 0.60 34.71| Info: 88000 | 10700 77299 | 144 856 | 29863| 0.51 35.22| Info: 89000 | 10776 78223 | 76 924 | 29288| 0.54 35.76| Info: 90000 | 10862 79137 | 86 914 | 28593| 0.57 36.33| Info: 91000 | 11085 79914 | 223 777 | 27952| 0.49 36.82| Info: 92000 | 11331 80668 | 246 754 | 28859| 0.49 37.31| Info: 93000 | 11401 81598 | 70 930 | 27975| 0.52 37.83| Post Restoration Checksum: NetGraph: 411f1306 | NumContArr: e34b1284 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 2a9bc1ac4 Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 422 ; free virtual = 24203 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 2a9bc1ac4 Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 422 ; free virtual = 24203 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 2a9bc1ac4 Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 422 ; free virtual = 24203 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 2d66eb66d Time (s): cpu = 00:00:38 ; elapsed = 00:00:29 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 388 ; free virtual = 24169 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797 | TNS=0.000 | WHS=0.008 | THS=0.000 | Router Utilization Summary Global Vertical Routing Utilization = 0.000391696 % Global Horizontal Routing Utilization = 0.000639386 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 3568 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 3564 Number of Partially Routed Nets = 4 Number of Node Overlaps = 2 Phase 2 Router Initialization | Checksum: 3338cb7c9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:30 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 385 ; free virtual = 24165 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 3338cb7c9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:30 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 385 ; free virtual = 24165 Phase 3.2 Initial Net Routing Phase 3.2 Initial Net Routing | Checksum: 1cbb2d3c9 Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 385 ; free virtual = 24166 Phase 3 Initial Routing | Checksum: 1cbb2d3c9 Time (s): cpu = 00:00:42 ; elapsed = 00:00:30 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 385 ; free virtual = 24166 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 493 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.540 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1fc6c14ca Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 378 ; free virtual = 24158 Phase 4 Rip-up And Reroute | Checksum: 1fc6c14ca Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 377 ; free virtual = 24158 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 1fc6c14ca Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 377 ; free virtual = 24158 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1fc6c14ca Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 376 ; free virtual = 24157 Phase 5 Delay and Skew Optimization | Checksum: 1fc6c14ca Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 376 ; free virtual = 24157 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 181650c03 Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 372 ; free virtual = 24153 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.636 | TNS=0.000 | WHS=0.364 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 181650c03 Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 372 ; free virtual = 24152 Phase 6 Post Hold Fix | Checksum: 181650c03 Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 371 ; free virtual = 24152 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.763764 % Global Horizontal Routing Utilization = 0.966823 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 181650c03 Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 377 ; free virtual = 24158 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 181650c03 Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 375 ; free virtual = 24156 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 21c8133ba Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 371 ; free virtual = 24152 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=8.636 | TNS=0.000 | WHS=0.364 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 21c8133ba Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 378 ; free virtual = 24159 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing Phase 11 Post-Route Event Processing | Checksum: 20b5d0693 Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 378 ; free virtual = 24159 Ending Routing Task | Checksum: 20b5d0693 Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 378 ; free virtual = 24159 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:48 ; elapsed = 00:00:33 . Memory (MB): peak = 2849.219 ; gain = 0.000 ; free physical = 378 ; free virtual = 24159 # report_timing_summary -no_header -no_detailed_paths INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs Info: 94000 | 11672 82327 | 271 729 | 27373| 0.54 38.38| Info: 95000 | 12058 82941 | 386 614 | 26933| 0.59 38.97| ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (2062) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (6725) 5. checking no_input_delay (9) 6. checking no_output_delay (17) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (2062) --------------------------- There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[36]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[37]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[39]/Q (HIGH) There are 2050 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH) 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (6725) --------------------------------------------------- There are 6725 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (9) ------------------------------ There are 9 input ports with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (17) -------------------------------- There are 17 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 8.661 0.000 0 1 0.380 0.000 0 1 4.500 0.000 0 2 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- sys_clk_pin {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- sys_clk_pin 8.661 0.000 0 1 0.380 0.000 0 1 4.500 0.000 0 2 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- # report_route_status -file digilent_nexys4ddr_route_status.rpt Info: 96000 | 12451 83548 | 393 607 | 26471| 0.51 39.48| # report_drc -file digilent_nexys4ddr_drc.rpt Command: report_drc -file digilent_nexys4ddr_drc.rpt INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'. Info: 97000 | 12844 84155 | 393 607 | 26173| 0.46 39.94| INFO: [DRC 23-27] Running DRC with 8 threads Info: 98000 | 13196 84803 | 352 648 | 25974| 0.59 40.54| INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt. report_drc completed successfully # report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs Info: 99000 | 13565 85434 | 369 631 | 25565| 0.56 41.09| # report_power -file digilent_nexys4ddr_power.rpt Command: report_power -file digilent_nexys4ddr_power.rpt Running Vector-less Activity Propagation... Info: 100000 | 13976 86023 | 411 589 | 25170| 0.56 41.65| Finished Running Vector-less Activity Propagation Info: 101000 | 14300 86699 | 324 676 | 24820| 0.55 42.20| WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully # write_bitstream -force "./build/out.bit" Command: write_bitstream -force ./build/out.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. Info: 102000 | 14523 87476 | 223 777 | 24833| 0.51 42.72| Info: 103000 | 14887 88112 | 364 636 | 24383| 0.44 43.16| Info: 104000 | 15344 88655 | 457 543 | 24090| 0.50 43.66| Info: 105000 | 15819 89180 | 475 525 | 23715| 0.45 44.11| Info: 106000 | 16304 89695 | 485 515 | 23368| 0.48 44.59| WARN (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew [90%] Routing Phase 3 completed Running timing analysis...... Info: 107000 | 16787 90212 | 483 517 | 23000| 0.46 45.05| Info: 108000 | 17229 90770 | 442 558 | 22645| 0.47 45.51| [95%] Timing analysis completed Placement and routing completed Bitstream generation in progress...... Info: 109000 | 17699 91300 | 470 530 | 22417| 0.52 46.03| Info: 110000 | 18129 91868 | 430 568 | 22011| 0.45 46.49| Info: 111000 | 18573 92423 | 444 555 | 21650| 0.46 46.94| Info: 112000 | 18983 93012 | 410 589 | 21390| 0.43 47.37| Info: 113000 | 19458 93529 | 475 517 | 21016| 0.45 47.82| Info: 114000 | 19733 94252 | 275 723 | 20935| 0.54 48.36| Info: 115000 | 20130 94836 | 397 584 | 20395| 0.40 48.76| Info: 116000 | 20208 95756 | 78 920 | 20433| 0.48 49.24| Info: 117000 | 20440 96480 | 232 724 | 19803| 0.34 49.58| Info: 118000 | 20710 97144 | 270 664 | 19163| 0.30 49.88| Info: 119000 | 21015 97759 | 305 615 | 18500| 0.29 50.17| Info: 120000 | 21391 98329 | 376 570 | 17929| 0.35 50.52| Info: 121000 | 21736 98905 | 345 576 | 17353| 0.35 50.87| Bitstream generation completed Running power analysis...... [100%] Power analysis completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed Fri May 3 02:07:16 2024 [Pipeline] } [Pipeline] // stage Info: 122000 | 22127 99460 | 391 555 | 16800| 0.37 51.24| [Pipeline] } Info: 123000 | 22541 99999 | 414 539 | 16355| 0.44 51.68| Info: 124000 | 22951 100521 | 410 522 | 15836| 0.40 52.08| Info: 125000 | 23430 100962 | 479 441 | 15406| 0.41 52.49| Info: 126000 | 23794 101530 | 364 568 | 15038| 0.48 52.97| Info: 127000 | 24237 102016 | 443 486 | 14524| 0.41 53.37| Info: 128000 | 24620 102560 | 383 544 | 13921| 0.36 53.73| Info: 129000 | 24823 103276 | 203 716 | 13137| 0.27 54.01| Info: 130000 | 24939 104077 | 116 801 | 12287| 0.25 54.25| Info: 131000 | 25055 104928 | 116 851 | 11408| 0.22 54.48| Info: 132000 | 25067 105908 | 12 980 | 10421| 0.16 54.63| INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. WARNING: [DRC PDRC-153] Gated clock check: Net SOC/Core/Control_Unit/FSM_onehot_state_reg[39]_1[0] is a gated clock net sourced by a combinational pin SOC/Core/Control_Unit/aluop_out_reg[3]_i_2/O, cell SOC/Core/Control_Unit/aluop_out_reg[3]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Info: 133000 | 25073 106898 | 6 990 | 9427| 0.15 54.78| Info: 134000 | 25080 107885 | 7 987 | 8434| 0.14 54.92| Info: 135000 | 25089 108875 | 9 990 | 7443| 0.14 55.06| Info: 136000 | 25090 109874 | 1 999 | 6444| 0.14 55.20| Info: 137000 | 25097 110867 | 7 993 | 5453| 0.14 55.34| Info: 138000 | 25102 111862 | 5 995 | 4458| 0.14 55.49| Info: 139000 | 25108 112856 | 6 994 | 3464| 0.15 55.63| Info: 140000 | 25113 113847 | 5 991 | 2470| 0.15 55.78| Info: 141000 | 25177 114757 | 64 910 | 1551| 0.23 56.01| Info: 142000 | 25346 115544 | 169 787 | 748| 0.33 56.35| Info: 142781 | 25370 115937 | 24 393 | 0| 0.26 56.61| Info: Routing complete. Info: Router1 time 56.61s Info: Checksum: 0xaf386bbc Loading site data... Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_2.Q Info: 1.2 1.7 Net SOC.Core.Control_Unit.state[3] (32,39) -> (30,42) Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z.C Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 2.0 Source SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_Z_D_LUT4_Z.F Info: 0.6 2.6 Net SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_Z_D[2] (30,42) -> (30,42) Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_Z_D_LUT4_D.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 2.8 Source SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_Z_D_LUT4_D.F Info: 0.9 3.7 Net SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_B_Z_LUT4_Z_D[3] (30,42) -> (32,40) Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z_1_B_LUT4_D_Z_LUT4_Z.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 3.9 Source SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z_1_B_LUT4_D_Z_LUT4_Z.F Info: 1.4 5.3 Net SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z_1_B_LUT4_D_Z[0] (32,40) -> (30,26) Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z_1_B_LUT4_D_Z_LUT4_B.B Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 5.6 Source SOC.Core.RegisterBank.registers.0.1_DO_2_LUT4_A_Z_LUT4_Z_C_LUT4_Z_1_D_PFUMX_C0_Z_LUT4_D_Z_PFUMX_C0_Z_LUT4_Z_1_B_LUT4_D_Z_LUT4_B.F Info: 2.0 7.6 Net SOC.Memory.memory.0.868_DO_LUT4_A_Z_LUT4_Z_C[2] (30,26) -> (20,16) Info: Sink SOC.Memory.address_LUT4_Z_2.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 7.8 Source SOC.Memory.address_LUT4_Z_2.F Info: 2.3 10.1 Net SOC.address[3] (20,16) -> (2,8) Info: Sink SOC.Memory.memory.0.681$DPRAM_COMB3.B Info: Defined in: Info: Risco-5/src/peripheral/soc.v:22.5-22.18 Info: 0.2 10.4 Source SOC.Memory.memory.0.681$DPRAM_COMB3.F Info: 0.6 11.0 Net SOC.Memory.memory.0.681_DO[1] (2,8) -> (2,8) Info: Sink SOC.Memory.memory.0.641_DO_LUT4_Z.B Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 11.2 Source SOC.Memory.memory.0.641_DO_LUT4_Z.F Info: 0.7 11.9 Net SOC.Memory.memory.0.641_DO[4] (2,8) -> (3,7) Info: Sink SOC.Memory.memory.0.649_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 12.2 Source SOC.Memory.memory.0.649_DO_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 0.6 12.8 Net SOC.Memory.memory.0.649_DO_LUT4_A_Z[3] (3,7) -> (4,7) Info: Sink SOC.Memory.memory.0.649_DO_LUT4_A_Z_LUT4_B.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 13.0 Source SOC.Memory.memory.0.649_DO_LUT4_A_Z_LUT4_B.F Info: 0.8 13.9 Net SOC.Memory.memory.0.753_DO_LUT4_A_Z_LUT4_B_Z[2] (4,7) -> (7,7) Info: Sink SOC.Memory.memory.0.753_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B.C Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.4 14.3 Source SOC.Memory.memory.0.753_DO_LUT4_A_Z_LUT4_B_Z_LUT4_B.OFX Info: 1.5 15.8 Net SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_C[4] (7,7) -> (9,18) Info: Sink SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 16.0 Source SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 0.0 16.0 Net SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D1 (9,18) -> (9,18) Info: Sink SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40 Info: 0.2 16.3 Source SOC.Memory.memory.0.260_DO_2_LUT4_A_Z_LUT4_A_Z_LUT4_Z_1_D_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 2.4 18.7 Net SOC.Core.read_data_LUT4_Z_10_D[2] (9,18) -> (30,28) Info: Sink SOC.Memory.memory.0.615_DO_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 19.0 Source SOC.Memory.memory.0.615_DO_LUT4_A_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 2.7 21.6 Net SOC.Core.read_data_L6MUX21_Z_2_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] (30,28) -> (54,16) Info: Sink SOC.Core.read_data_PFUMX_Z_3_BLUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 21.9 Source SOC.Core.read_data_PFUMX_Z_3_BLUT_LUT4_Z.OFX Info: 0.5 22.4 Net SOC.read_data[19] (54,16) -> (54,16) Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_12.M Info: Defined in: Info: Risco-5/src/peripheral/soc.v:21.34-21.43 Info: 0.0 22.4 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_12.M Info: 4.1 ns logic, 18.3 ns routing Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: curr total Info: 0.0 0.0 Source gpios[0]$tr_io.O Info: 2.9 2.9 Net gpios[0]$TRELLIS_IO_IN (0,44) -> (6,23) Info: Sink SOC.GPIOS.Gpios[0].direction_LUT4_C.B Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:7.16-7.21 Info: 0.2 3.2 Source SOC.GPIOS.Gpios[0].direction_LUT4_C.F Info: 1.3 4.5 Net SOC.GPIOS.Gpios[0].direction_LUT4_C_Z[2] (6,23) -> (6,16) Info: Sink SOC.GPIOS.Gpios[0].direction_LUT4_C_Z_LUT4_C.C Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 4.7 Source SOC.GPIOS.Gpios[0].direction_LUT4_C_Z_LUT4_C.F Info: 1.9 6.6 Net SOC.GPIOS.Gpios[0].direction_LUT4_C_Z_LUT4_C_Z[1] (6,16) -> (22,12) Info: Sink SOC.Core.read_data_LUT4_Z.B Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 6.9 Source SOC.Core.read_data_LUT4_Z.F Info: 1.9 8.7 Net SOC.read_data[0] (22,12) -> (31,21) Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_31.M Info: Defined in: Info: Risco-5/src/peripheral/soc.v:21.34-21.43 Info: 0.0 8.7 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_31.M Info: 0.7 ns logic, 8.0 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>': Info: curr total Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_27.Q Info: 2.9 3.4 Net SOC.Leds.data[4] (5,24) -> (6,54) Info: Sink led_LUT4_Z_3.D Info: Defined in: Info: Risco-5/src/peripheral/leds.v:15.12-15.16 Info: 0.2 3.7 Source led_LUT4_Z_3.F Info: 2.3 6.0 Net led[4]$TRELLIS_IO_OUT (6,54) -> (15,71) Info: Sink led[4]$tr_io.I Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:6.22-6.25 Info: 0.8 ns logic, 5.3 ns routing Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 44.71 MHz (PASS at 25.00 MHz) Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.74 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.02 ns Info: Slack histogram: Info: legend: * represents 202 endpoint(s) Info: + represents [1,202) endpoint(s) Info: [ 17634, 18706) |+ Info: [ 18706, 19778) |*+ Info: [ 19778, 20850) |****+ Info: [ 20850, 21922) |****+ Info: [ 21922, 22994) |+ Info: [ 22994, 24066) |*+ Info: [ 24066, 25138) |****+ Info: [ 25138, 26210) |************+ Info: [ 26210, 27282) |********+ Info: [ 27282, 28354) |**+ Info: [ 28354, 29426) |***************+ Info: [ 29426, 30498) |************************************************************ Info: [ 30498, 31570) |***************+ Info: [ 31570, 32642) |+ Info: [ 32642, 33714) |+ Info: [ 33714, 34786) |*+ Info: [ 34786, 35858) |**+ Info: [ 35858, 36930) |+ Info: [ 36930, 38002) |+ Info: [ 38002, 39074) |+ Loading route data... Processing options... Creating bitmap... Creating bitstream... Info: Program finished normally. [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (ECPPACK) Writing bitstream ./build/out.bit... [Pipeline] sh INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 3154.230 ; gain = 250.176 ; free physical = 770 ; free virtual = 24603 + /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit INFO: [Common 17-206] Exiting Vivado at Fri May 3 02:07:26 2024... [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Flash) [Pipeline] parallel [Pipeline] { (Branch: openFPGAloader ECP5) [Pipeline] { (Branch: openFPGAloader Tangnano 20k) [Pipeline] { (Branch: openFPGAloader Nexys 4 DDR) [Pipeline] stage [Pipeline] { (openFPGAloader ECP5) [Pipeline] stage [Pipeline] { (openFPGAloader Tangnano 20k) [Pipeline] stage [Pipeline] { (openFPGAloader Nexys 4 DDR) [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] lock Trying to acquire lock on [ecp5] Resource [ecp5] did not exist. Created. Lock acquired on [ecp5] [Pipeline] { [Pipeline] lock Trying to acquire lock on [tangnano20k] Resource [tangnano20k] did not exist. Created. Lock acquired on [tangnano20k] [Pipeline] { [Pipeline] lock Trying to acquire lock on [nexys4] Resource [nexys4] did not exist. Created. Lock acquired on [nexys4] [Pipeline] { [Pipeline] echo FPGA ECP5 Broqueada [Pipeline] sh [Pipeline] echo FPGA TangNano Broqueada + /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit empty Found 1 compatible device: 0x0d28 0x0204 0x3 DAPLink CMSIS-DAP Open file: DONE b3bdffff Parse file: DONE Enable configuration: DONE SRAM erase: DONE [Pipeline] sh [Pipeline] echo FPGA Nexys 4 Broqueada + echo gravando na tang nano gravando na tang nano [Pipeline] sh [Pipeline] } + cd Risco-5/fpga/nexys4_ddr + /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit empty Jtag frequency : requested 6.00MHz -> real 6.00MHz Open file DONE Parse file DONE load program Lock released on resource [tangnano20k] [Pipeline] // lock [Pipeline] } [Pipeline] // script Loading: [==== ] 8.00%[Pipeline] } Load SRAM: [========= ] 18.00%[Pipeline] // stage [Pipeline] } Loading: [======== ] 16.00% Load SRAM: [=================== ] 38.00% Loading: [============ ] 23.99% Load SRAM: [============================= ] 58.00% Loading: [================ ] 31.99% Load SRAM: [======================================= ] 78.00% Loading: [==================== ] 39.99% Load SRAM: [================================================= ] 98.00% Load SRAM: [===================================================] 100.00% Done [Pipeline] } Lock released on resource [nexys4] Loading: [======================== ] 47.99%[Pipeline] // lock [Pipeline] } [Pipeline] // script [Pipeline] } [Pipeline] // stage [Pipeline] } Loading: [============================ ] 55.98% Loading: [================================ ] 63.98% Loading: [==================================== ] 71.98% Loading: [======================================== ] 79.98% Loading: [============================================ ] 87.97% Loading: [================================================ ] 95.97% Loading: [==================================================] 100.00% Done Disable configuration: DONE [Pipeline] } Lock released on resource [ecp5] [Pipeline] // lock [Pipeline] } [Pipeline] // script [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Testes) [Pipeline] parallel [Pipeline] { (Branch: ECP5 - Testes) [Pipeline] { (Branch: TangNano - Testes) [Pipeline] { (Branch: Nexys 4 - Testes) [Pipeline] stage [Pipeline] { (ECP5 - Testes) [Pipeline] stage [Pipeline] { (TangNano - Testes) [Pipeline] stage [Pipeline] { (Nexys 4 - Testes) [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] echo Rodando teste na ECP5 [Pipeline] lock Trying to acquire lock on [ecp5] Resource [ecp5] did not exist. Created. Lock acquired on [ecp5] [Pipeline] { [Pipeline] echo Rodando teste na tang nano [Pipeline] lock Trying to acquire lock on [tangnano20k] Resource [tangnano20k] did not exist. Created. Lock acquired on [tangnano20k] [Pipeline] { [Pipeline] echo Rodando teste na Nexys 4 [Pipeline] lock Trying to acquire lock on [nexys4] Resource [nexys4] did not exist. Created. Lock acquired on [nexys4] [Pipeline] { [Pipeline] echo FPGA ECP5 Broqueada [Pipeline] sh [Pipeline] echo FPGA TangNano Broqueada + echo testando na ecp5 testando na ecp5 [Pipeline] sh [Pipeline] echo FPGA Nexys 4 Broqueada + echo testando na tang nano testando na tang nano [Pipeline] sh [Pipeline] } + echo testando na tang nano testando na tang nano Lock released on resource [ecp5] [Pipeline] } Lock released on resource [tangnano20k] [Pipeline] // lock [Pipeline] // lock [Pipeline] echo ECP5 liberada [Pipeline] } [Pipeline] echo TangNano liberada [Pipeline] } [Pipeline] } Lock released on resource [nexys4] [Pipeline] // script [Pipeline] // script [Pipeline] // lock [Pipeline] } [Pipeline] } [Pipeline] echo TangNano liberada [Pipeline] } [Pipeline] // stage [Pipeline] // stage [Pipeline] // script [Pipeline] } [Pipeline] } [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline Finished: SUCCESS