Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Risco_5
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -Rf Risco-5/ build/
[Pipeline] sh
+ git clone https://github.com/JN513/Risco-5
Cloning into 'Risco-5'...
[Pipeline] sh
+ cd Risco-5
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (IVerilog)
[Pipeline] sh
+ mkdir -p build
[Pipeline] sh
+ cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/csr_unit.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/fifo.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v
[Pipeline] sh
+ /eda/oss-cad-suite/bin/vvp build/soc_test.o
ERROR: Risco-5/src/peripheral/memory.v:35: $readmemh: Unable to open software/memory/generic.hex for reading.
VCD info: dumpfile build/soc.vcd opened for output.
Risco-5/tests/soc_test.v:34: $finish called at 3606 (1s)
[Pipeline] sh
+ rm -f Risco-5/software/memory/generic.hex
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Síntese)
[Pipeline] parallel
[Pipeline] { (Branch: OSS-Cad-Suite)
[Pipeline] { (Branch: Gowin)
[Pipeline] { (Branch: Vivado)
[Pipeline] stage
[Pipeline] { (OSS-Cad-Suite)
[Pipeline] stage
[Pipeline] { (Gowin)
[Pipeline] stage
[Pipeline] { (Vivado)
[Pipeline] stage
[Pipeline] { (Yosys)
[Pipeline] sh
[Pipeline] sh
+ rm -rf Risco-5/impl/pnr
+ cd Risco-5/fpga/nexys4_ddr
+ mkdir build
+ /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source run.tcl
[Pipeline] sh
[Pipeline] sh
+ mkdir -p Risco-5/impl/pnr
[Pipeline] sh
+ /eda/oss-cad-suite/bin/yosys -p                                          read_verilog Risco-5/fpga/ecp5/*.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)

-- Running command `                                         read_verilog Risco-5/fpga/ecp5/*.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     ' --

1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v
Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: Risco-5/debug/reset.v
Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v
Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation.
Generating RTLIL representation for module `\Alu'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v
Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation.
Generating RTLIL representation for module `\ALU_Control'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v
Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: Risco-5/src/core/core.v
Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation.
Generating RTLIL representation for module `\Core'.
Risco-5/src/core/core.v:142: Warning: Identifier `\pc_source' is implicitly declared.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: Risco-5/src/core/csr_unit.v
Parsing Verilog input from `Risco-5/src/core/csr_unit.v' to AST representation.
Generating RTLIL representation for module `\CSR_Unit'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v
Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation.
Generating RTLIL representation for module `\Immediate_Generator'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v
Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation.
Generating RTLIL representation for module `\MUX'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v
Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation.
Generating RTLIL representation for module `\PC'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v
Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation.
Generating RTLIL representation for module `\Registers'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v
Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation.
Generating RTLIL representation for module `\BUS'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/fifo.v
Parsing Verilog input from `Risco-5/src/peripheral/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v
Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9)
Generating RTLIL representation for module `\GPIO'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v
Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation.
Generating RTLIL representation for module `\GPIOS'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v
Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation.
Generating RTLIL representation for module `\LEDs'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v
Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v
Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation.
Generating RTLIL representation for module `\Risco_5_SOC'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v
Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_rx'.
Successfully finished Verilog frontend.

21. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_tx'.
Successfully finished Verilog frontend.

22. Executing SYNTH_ECP5 pass.

22.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

22.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

22.3. Executing HIERARCHY pass (managing design hierarchy).

22.3.1. Finding top of design hierarchy..
root of   0 design levels: uart_tool_tx        
root of   0 design levels: uart_tool_rx        
root of   1 design levels: UART                
root of   2 design levels: Risco_5_SOC         
root of   0 design levels: Memory              
root of   0 design levels: LEDs                
root of   1 design levels: GPIOS               
root of   0 design levels: GPIO                
root of   0 design levels: FIFO                
root of   0 design levels: BUS                 
root of   0 design levels: Registers           
root of   0 design levels: PC                  
root of   0 design levels: MUX                 
root of   0 design levels: Immediate_Generator 
root of   0 design levels: CSR_Unit            
root of   1 design levels: Core                
root of   0 design levels: Control_Unit        
root of   0 design levels: ALU_Control         
root of   0 design levels: Alu                 
root of   0 design levels: ResetBootSystem     
root of   3 design levels: top                 
Automatically selected top as design top module.

22.3.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     \ResetBootSystem
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \MEMORY_SIZE = 8192
Parameter \MEMORY_FILE = 312'001011100010111000101111001011100010111000101111011100110110111101100110011101000111011101100001011100100110010100101111011011010110010101101101011011110111001001111001001011110111010001100101011100110111010001100101010111110111010101100001011100100111010001011111011101000111100000101110011010000110010101111000
Parameter \GPIO_WIDHT = 6

22.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \MEMORY_SIZE = 8192
Parameter \MEMORY_FILE = 312'001011100010111000101111001011100010111000101111011100110110111101100110011101000111011101100001011100100110010100101111011011010110010101101101011011110111001001111001001011110111010001100101011100110111010001100101010111110111010101100001011100100111010001011111011101000111100000101110011010000110010101111000
Parameter \GPIO_WIDHT = 6
Generating RTLIL representation for module `$paramod$3165995eef18218159020b46b9263540bd7186c4\Risco_5_SOC'.
Parameter \CYCLES = 20

22.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \WIDHT = 5

22.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 5
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600

22.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Generating RTLIL representation for module `$paramod$6bda1990038484dedf11a31b91004b83302c1c9a\UART'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

22.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \BOOT_ADDRESS = 0

22.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'.
Parameter \BOOT_ADDRESS = 0
Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.
Risco-5/src/core/core.v:142: Warning: Identifier `\pc_source' is implicitly declared.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

22.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

22.3.12. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$3165995eef18218159020b46b9263540bd7186c4\Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \WIDHT = 6

22.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 6
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200

22.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Generating RTLIL representation for module `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART'.
Parameter \MEMORY_FILE = 312'001011100010111000101111001011100010111000101111011100110110111101100110011101000111011101100001011100100110010100101111011011010110010101101101011011110111001001111001001011110111010001100101011100110111010001100101010111110111010101100001011100100111010001011111011101000111100000101110011010000110010101111000
Parameter \MEMORY_SIZE = 8192

22.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = 312'001011100010111000101111001011100010111000101111011100110110111101100110011101000111011101100001011100100110010100101111011011010110010101101101011011110111001001111001001011110111010001100101011100110111010001100101010111110111010101100001011100100111010001011111011101000111100000101110011010000110010101111000
Parameter \MEMORY_SIZE = 8192
Generating RTLIL representation for module `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory'.
Parameter \BOOT_ADDRESS = 0
Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.

22.3.16. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$3165995eef18218159020b46b9263540bd7186c4\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

22.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

22.3.19. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$3165995eef18218159020b46b9263540bd7186c4\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100

22.3.20. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$3165995eef18218159020b46b9263540bd7186c4\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:         $paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Removing unused module `$paramod$6bda1990038484dedf11a31b91004b83302c1c9a\UART'.
Removing unused module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Removing unused module `\uart_tool_tx'.
Removing unused module `\uart_tool_rx'.
Removing unused module `\UART'.
Removing unused module `\Risco_5_SOC'.
Removing unused module `\Memory'.
Removing unused module `\GPIOS'.
Removing unused module `\FIFO'.
Removing unused module `\Core'.
Removing unused module `\ResetBootSystem'.
Removed 14 unused modules.

22.4. Executing PROC pass (convert processes to netlists).

22.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$545'.
Found and cleaned up 1 empty switch in `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:0$959'.
Removing empty process `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:0$959'.
Cleaned up 2 empty switches.

22.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$652 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$604 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$546 in module TRELLIS_DPR16X4.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/fifo.v:24$870 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:189$1052 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:178$1050 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:163$1042 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:152$1039 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:140$1033 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:125$1028 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:108$1023 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:89$1014 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:167$1001 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:156$999 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:141$991 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:124$977 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:109$971 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:92$966 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:244$755 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:59$957 in module $paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:47$920 in module $paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$266 in module LEDs.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:127$905 in module $paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.
Marked 5 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:61$897 in module $paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:31$895 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:24$170 in module Registers.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:15$159 in module PC.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:18$142 in module Immediate_Generator.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:189$132 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:180$128 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:143$126 in module CSR_Unit.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:104$124 in module CSR_Unit.
Marked 5 switch rules as full_case in process $proc$Risco-5/debug/reset.v:24$655 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:628$86 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:618$85 in module Control_Unit.
Marked 19 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:141$40 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:133$39 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:9$31 in module ALU_Control.
Marked 5 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:9$31 in module ALU_Control.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:26$11 in module Alu.
Removed a total of 1 dead cases.

22.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 14 redundant assignments.
Promoted 145 assignments to connections.

22.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:124$1054'.
  Set init value: \i = 0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:108$1007'.
  Set init value: \i = 0
Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$763'.
  Set init value: \instruction_register = 0
  Set init value: \memory_register = 0
  Set init value: \alu_out_register = 0
  Set init value: \register_data_1 = 0
  Set init value: \register_data_2 = 0
  Set init value: \pc_old = 0
  Set init value: \temp_address = 0
  Set init value: \temp_reg2 = 0
  Set init value: \temp_write_value = 0
Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$269'.
  Set init value: \data = 33'000000000000000000000000000000000
Found init rule in `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:0$912'.
  Set init value: \state = 3'000
  Set init value: \counter = 3'000
  Set init value: \read_data = 0
  Set init value: \response = 1'0
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$162'.
  Set init value: \Output = 0
Found init rule in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$141'.
  Set init value: \csr_mcause = 0
  Set init value: \csr_mepc = 0
  Set init value: \csr_mie_mfie = 16'0000000000000000
  Set init value: \csr_mie_meie = 1'0
  Set init value: \csr_mie_msie = 1'0
  Set init value: \csr_mie_mtie = 1'0
  Set init value: \csr_mip_mfip = 16'0000000000000000
  Set init value: \csr_mip_meip = 1'0
  Set init value: \csr_mip_mtip = 1'0
  Set init value: \csr_mip_msip = 1'0
  Set init value: \csr_mscratch = 0
  Set init value: \csr_mstatus_mie = 1'0
  Set init value: \csr_mstatus_mpie = 1'0
  Set init value: \csr_mtvec = 0
  Set init value: \csr_mtval = 0
  Set init value: \csr_write_data = 0
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$661'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000
Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$87'.
  Set init value: \state = 6'000000
  Set init value: \is_immediate = 1'0
  Set init value: \pc_write = 1'0
  Set init value: \ir_write = 1'0
  Set init value: \pc_source = 1'0
  Set init value: \reg_write = 1'0
  Set init value: \memory_read = 1'0
  Set init value: \memory_write = 1'0
  Set init value: \pc_write_cond = 1'0
  Set init value: \csr_write_enable = 1'0
  Set init value: \alu_input_selector = 1'0
  Set init value: \save_address = 1'0
  Set init value: \save_value = 1'0
  Set init value: \save_value_2 = 1'0
  Set init value: \save_write_value = 1'0
  Set init value: \control_memory_op = 1'0
  Set init value: \write_data_in = 1'0
  Set init value: \lorD = 2'00
  Set init value: \aluop = 2'00
  Set init value: \alu_src_a = 3'000
  Set init value: \alu_src_b = 3'000
  Set init value: \memory_to_reg = 3'000
  Set init value: \control_unit_memory_op = 3'010
  Set init value: \control_unit_aluop = 4'0000
  Set init value: \clear_hal_byte_one_block_option = 3'000
  Set init value: \clear_hal_byte_one_block_option_2 = 3'000
  Set init value: \nextstate = 6'000000

22.4.5. Executing PROC_ARST pass (detect async resets in processes).

22.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~114 debug messages>

22.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$652'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$604'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$603_EN[3:0]$610
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$603_DATA[3:0]$609
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$603_ADDR[3:0]$608
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$546'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$544_EN[3:0]$552
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$544_DATA[3:0]$551
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$544_ADDR[3:0]$550
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$545'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$870'.
     1/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_EN[7:0]$882
     2/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_DATA[7:0]$881
     3/8: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_ADDR[5:0]$880
     4/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_EN[7:0]$877
     5/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_DATA[7:0]$876
     6/8: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_ADDR[5:0]$875
     7/8: $0\write_ptr[5:0]
     8/8: $0\read_ptr[5:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:124$1054'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1052'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1050'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1042'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1039'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1033'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1028'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1023'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1014'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:108$1007'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$1001'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$999'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$991'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$977'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$971'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$966'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$763'.
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$755'.
     1/10: $0\alu_out_register[31:0]
     2/10: $0\register_data_2[31:0]
     3/10: $0\register_data_1[31:0]
     4/10: $0\memory_register[31:0]
     5/10: $0\temp_write_value[31:0]
     6/10: $0\temp_reg3[31:0]
     7/10: $0\temp_reg2[31:0]
     8/10: $0\temp_address[31:0]
     9/10: $0\pc_old[31:0]
    10/10: $0\instruction_register[31:0]
Creating decoders for process `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:59$957'.
     1/1: $1\read_data[31:0]
Creating decoders for process `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:47$920'.
     1/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$953
     2/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_DATA[31:0]$952
     3/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_ADDR[31:0]$951
     4/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$956
     5/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_DATA[31:0]$955
     6/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_ADDR[31:0]$954
     7/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$943
     8/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_DATA[31:0]$942
     9/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_ADDR[31:0]$941
    10/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$949
    11/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_DATA[31:0]$948
    12/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_ADDR[31:0]$947
    13/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$946
    14/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_DATA[31:0]$945
    15/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_ADDR[31:0]$944
    16/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$939
    17/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_DATA[31:0]$938
    18/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_ADDR[31:0]$937
    19/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$936
    20/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_DATA[31:0]$935
    21/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_ADDR[31:0]$934
    22/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$933
    23/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_DATA[31:0]$932
    24/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_ADDR[31:0]$931
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$269'.
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$266'.
     1/1: $0\data[32:0]
Creating decoders for process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:0$912'.
Creating decoders for process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:127$905'.
     1/5: $0\rx_fifo_write[0:0]
     2/5: $0\tx_fifo_read[0:0]
     3/5: $0\uart_tx_en[0:0]
     4/5: $0\rx_fifo_write_data[7:0]
     5/5: $0\uart_tx_data[7:0]
Creating decoders for process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:61$897'.
     1/8: $0\tx_fifo_write[0:0]
     2/8: $0\rx_fifo_read[0:0]
     3/8: $0\response[0:0]
     4/8: $0\write_data_buffer[31:0]
     5/8: $0\tx_fifo_write_data[7:0]
     6/8: $0\read_data[31:0]
     7/8: $0\counter[2:0]
     8/8: $0\state[2:0]
Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:31$895'.
     1/2: $0\gpio_value[5:0]
     2/2: $0\gpio_direction[5:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$188'.
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:24$170'.
     1/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$185
     2/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$165_DATA[31:0]$184
     3/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$165_ADDR[4:0]$183
     4/9: $2$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$186
     5/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$177
     6/9: $1$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$181
     7/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$180
     8/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$165_DATA[31:0]$179
     9/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$165_ADDR[4:0]$178
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$162'.
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:15$159'.
     1/1: $0\Output[31:0]
Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$142'.
     1/2: $2\immediate[31:0]
     2/2: $1\immediate[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$141'.
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:189$132'.
     1/1: $1\csr_data_out[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128'.
     1/1: $1\csr_write_data[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:143$126'.
     1/4: $0\csr_mip_msip[0:0]
     2/4: $0\csr_mip_mtip[0:0]
     3/4: $0\csr_mip_meip[0:0]
     4/4: $0\csr_mip_mfip[15:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'.
     1/11: $0\csr_mtval[31:0]
     2/11: $0\csr_mtvec[31:0]
     3/11: $0\csr_mstatus_mpie[0:0]
     4/11: $0\csr_mstatus_mie[0:0]
     5/11: $0\csr_mscratch[31:0]
     6/11: $0\csr_mie_mtie[0:0]
     7/11: $0\csr_mie_msie[0:0]
     8/11: $0\csr_mie_meie[0:0]
     9/11: $0\csr_mie_mfie[15:0]
    10/11: $0\csr_mepc[31:0]
    11/11: $0\csr_mcause[31:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$661'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$655'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$87'.
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86'.
     1/2: $0\clear_hal_byte_one_block_option_2[2:0]
     2/2: $0\clear_hal_byte_one_block_option[2:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:618$85'.
     1/1: $0\wb_filter[2:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
     1/22: $0\save_write_value[0:0]
     2/22: $0\write_data_in[0:0]
     3/22: $0\save_value_2[0:0]
     4/22: $0\save_value[0:0]
     5/22: $0\control_memory_op[0:0]
     6/22: $0\save_address[0:0]
     7/22: $0\control_unit_aluop[3:0]
     8/22: $0\alu_input_selector[0:0]
     9/22: $0\csr_write_enable[0:0]
    10/22: $0\is_immediate[0:0]
    11/22: $0\reg_write[0:0]
    12/22: $0\alu_src_a[2:0]
    13/22: $0\alu_src_b[2:0]
    14/22: $0\aluop[1:0]
    15/22: $0\pc_source[0:0]
    16/22: $0\memory_to_reg[2:0]
    17/22: $0\memory_write[0:0]
    18/22: $0\memory_read[0:0]
    19/22: $0\lorD[1:0]
    20/22: $0\ir_write[0:0]
    21/22: $0\pc_write[0:0]
    22/22: $0\pc_write_cond[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40'.
     1/19: $19\nextstate[5:0]
     2/19: $18\nextstate[5:0]
     3/19: $17\nextstate[5:0]
     4/19: $16\nextstate[5:0]
     5/19: $15\nextstate[5:0]
     6/19: $14\nextstate[5:0]
     7/19: $13\nextstate[5:0]
     8/19: $12\nextstate[5:0]
     9/19: $11\nextstate[5:0]
    10/19: $10\nextstate[5:0]
    11/19: $9\nextstate[5:0]
    12/19: $8\nextstate[5:0]
    13/19: $7\nextstate[5:0]
    14/19: $6\nextstate[5:0]
    15/19: $5\nextstate[5:0]
    16/19: $4\nextstate[5:0]
    17/19: $3\nextstate[5:0]
    18/19: $2\nextstate[5:0]
    19/19: $1\nextstate[5:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:133$39'.
     1/1: $0\state[5:0]
Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'.
     1/5: $5\aluop_out[3:0]
     2/5: $4\aluop_out[3:0]
     3/5: $3\aluop_out[3:0]
     4/5: $2\aluop_out[3:0]
     5/5: $1\aluop_out[3:0]
Creating decoders for process `\Alu.$proc$Risco-5/src/core/alu.v:26$11'.
     1/1: $1\ALU_out_S[31:0]

22.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1023'.
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$966'.
No latch inferred for signal `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.\read_data' from process `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:59$957'.
No latch inferred for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:17$163_EN' from process `\Registers.$proc$Risco-5/src/core/registers.v:0$188'.
No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$142'.
No latch inferred for signal `\CSR_Unit.\csr_mcause_code' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$141'.
No latch inferred for signal `\CSR_Unit.\csr_mcause_interrupt_flag' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$141'.
No latch inferred for signal `\CSR_Unit.\csr_data_out' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:189$132'.
No latch inferred for signal `\CSR_Unit.\csr_write_data' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128'.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [0]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [1]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [2]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [3]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [4]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [5]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [6]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [7]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [8]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [9]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [10]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [11]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [12]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [13]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [14]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [15]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [16]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [17]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [18]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [19]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [20]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [21]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [22]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [23]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [24]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [25]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [26]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [27]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [28]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [29]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [30]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
Removing init bit 1'0 for non-memory siginal `\CSR_Unit.\csr_write_data [31]` in process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128`.
No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86`.
No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option_2' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86`.
No latch inferred for signal `\Control_Unit.\wb_filter' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:618$85'.
No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\csr_write_enable` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\alu_input_selector' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_input_selector` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\save_address' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_address` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\save_value' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\save_value_2' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value_2` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\save_write_value' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_write_value` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\control_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_memory_op` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\write_data_in' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\write_data_in` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\control_unit_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
Removing init bit 1'1 for non-memory siginal `\Control_Unit.\control_unit_memory_op [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\control_unit_aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72`.
No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [4]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [5]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40`.
Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31': $auto$proc_dlatch.cc:433:proc_dlatch$3152
No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$Risco-5/src/core/alu.v:26$11'.

22.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$652'.
  created $dff cell `$procdff$3175' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$588_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$589_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$590_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$591_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$592_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$593_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$594_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$595_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$596_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$597_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$598_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$599_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$600_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$601_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$602_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$603_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$604'.
  created $dff cell `$procdff$3176' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$603_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$604'.
  created $dff cell `$procdff$3177' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$603_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$604'.
  created $dff cell `$procdff$3178' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$528_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$529_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$530_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$531_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$532_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$533_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$534_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$535_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$536_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$537_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$538_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$539_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$540_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$541_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$542_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$543_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$544_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$546'.
  created $dff cell `$procdff$3179' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$544_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$546'.
  created $dff cell `$procdff$3180' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$544_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$546'.
  created $dff cell `$procdff$3181' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$545'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$870'.
  created $dff cell `$procdff$3182' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$870'.
  created $dff cell `$procdff$3183' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$870'.
  created $dff cell `$procdff$3184' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$870'.
  created $dff cell `$procdff$3185' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$870'.
  created $dff cell `$procdff$3186' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1052'.
  created $dff cell `$procdff$3187' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1052'.
  created $dff cell `$procdff$3188' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1050'.
  created $dff cell `$procdff$3189' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1042'.
  created $dff cell `$procdff$3190' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1039'.
  created $dff cell `$procdff$3191' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1033'.
  created $dff cell `$procdff$3192' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1028'.
  created $dff cell `$procdff$3193' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1028'.
  created $dff cell `$procdff$3194' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1014'.
  created $dff cell `$procdff$3195' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$1001'.
  created $dff cell `$procdff$3196' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$999'.
  created $dff cell `$procdff$3197' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$991'.
  created $dff cell `$procdff$3198' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$977'.
  created $dff cell `$procdff$3199' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$971'.
  created $dff cell `$procdff$3200' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$971'.
  created $dff cell `$procdff$3201' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$755'.
  created $dff cell `$procdff$3202' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$755'.
  created $dff cell `$procdff$3203' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$755'.
  created $dff cell `$procdff$3204' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$755'.
  created $dff cell `$procdff$3205' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$755'.
  created $dff cell `$procdff$3206' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$755'.
  created $dff cell `$procdff$3207' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_address' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$755'.
  created $dff cell `$procdff$3208' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_reg2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$755'.
  created $dff cell `$procdff$3209' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_reg3' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$755'.
  created $dff cell `$procdff$3210' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_write_value' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$755'.
  created $dff cell `$procdff$3211' with positive edge clock.
Creating register for signal `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_ADDR' using process `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:47$920'.
  created $dff cell `$procdff$3212' with positive edge clock.
Creating register for signal `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_DATA' using process `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:47$920'.
  created $dff cell `$procdff$3213' with positive edge clock.
Creating register for signal `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN' using process `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:47$920'.
  created $dff cell `$procdff$3214' with positive edge clock.
Creating register for signal `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_ADDR' using process `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:47$920'.
  created $dff cell `$procdff$3215' with positive edge clock.
Creating register for signal `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_DATA' using process `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:47$920'.
  created $dff cell `$procdff$3216' with positive edge clock.
Creating register for signal `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN' using process `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:47$920'.
  created $dff cell `$procdff$3217' with positive edge clock.
Creating register for signal `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_ADDR' using process `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:47$920'.
  created $dff cell `$procdff$3218' with positive edge clock.
Creating register for signal `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_DATA' using process `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:47$920'.
  created $dff cell `$procdff$3219' with positive edge clock.
Creating register for signal `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN' using process `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:47$920'.
  created $dff cell `$procdff$3220' with positive edge clock.
Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$266'.
  created $dff cell `$procdff$3221' with positive edge clock.
Creating register for signal `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.\uart_tx_en' using process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:127$905'.
  created $dff cell `$procdff$3222' with positive edge clock.
Creating register for signal `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.\tx_fifo_read' using process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:127$905'.
  created $dff cell `$procdff$3223' with positive edge clock.
Creating register for signal `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.\rx_fifo_write' using process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:127$905'.
  created $dff cell `$procdff$3224' with positive edge clock.
Creating register for signal `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.\uart_tx_data' using process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:127$905'.
  created $dff cell `$procdff$3225' with positive edge clock.
Creating register for signal `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.\rx_fifo_write_data' using process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:127$905'.
  created $dff cell `$procdff$3226' with positive edge clock.
Creating register for signal `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.\state' using process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:61$897'.
  created $dff cell `$procdff$3227' with positive edge clock.
Creating register for signal `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.\counter' using process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:61$897'.
  created $dff cell `$procdff$3228' with positive edge clock.
Creating register for signal `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.\read_data' using process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:61$897'.
  created $dff cell `$procdff$3229' with positive edge clock.
Creating register for signal `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.\response' using process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:61$897'.
  created $dff cell `$procdff$3230' with positive edge clock.
Creating register for signal `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.\tx_fifo_write' using process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:61$897'.
  created $dff cell `$procdff$3231' with positive edge clock.
Creating register for signal `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.\rx_fifo_read' using process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:61$897'.
  created $dff cell `$procdff$3232' with positive edge clock.
Creating register for signal `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.\tx_fifo_write_data' using process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:61$897'.
  created $dff cell `$procdff$3233' with positive edge clock.
Creating register for signal `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.\write_data_buffer' using process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:61$897'.
  created $dff cell `$procdff$3234' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:31$895'.
  created $dff cell `$procdff$3235' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:31$895'.
  created $dff cell `$procdff$3236' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$170'.
  created $dff cell `$procdff$3237' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$165_ADDR' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$170'.
  created $dff cell `$procdff$3238' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$165_DATA' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$170'.
  created $dff cell `$procdff$3239' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$170'.
  created $dff cell `$procdff$3240' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$170'.
  created $dff cell `$procdff$3241' with positive edge clock.
Creating register for signal `\PC.\Output' using process `\PC.$proc$Risco-5/src/core/pc.v:15$159'.
  created $dff cell `$procdff$3242' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_mfip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:143$126'.
  created $dff cell `$procdff$3243' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_meip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:143$126'.
  created $dff cell `$procdff$3244' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_mtip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:143$126'.
  created $dff cell `$procdff$3245' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mip_msip' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:143$126'.
  created $dff cell `$procdff$3246' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mcause' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'.
  created $dff cell `$procdff$3247' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mepc' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'.
  created $dff cell `$procdff$3248' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_mfie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'.
  created $dff cell `$procdff$3249' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_meie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'.
  created $dff cell `$procdff$3250' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_msie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'.
  created $dff cell `$procdff$3251' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mie_mtie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'.
  created $dff cell `$procdff$3252' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mscratch' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'.
  created $dff cell `$procdff$3253' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mstatus_mie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'.
  created $dff cell `$procdff$3254' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mstatus_mpie' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'.
  created $dff cell `$procdff$3255' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mtvec' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'.
  created $dff cell `$procdff$3256' with positive edge clock.
Creating register for signal `\CSR_Unit.\csr_mtval' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'.
  created $dff cell `$procdff$3257' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$655'.
  created $dff cell `$procdff$3258' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$655'.
  created $dff cell `$procdff$3259' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$655'.
  created $dff cell `$procdff$3260' with positive edge clock.
Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:133$39'.
  created $dff cell `$procdff$3261' with positive edge clock.

22.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$653'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$652'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$652'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$627'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$604'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$570'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$546'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$545'.
Found and cleaned up 3 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$870'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$Risco-5/src/peripheral/fifo.v:24$870'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:124$1054'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1052'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1052'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1050'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1050'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1042'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1042'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1039'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1039'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1033'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1033'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1028'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1028'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1023'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1023'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1014'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1014'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:108$1007'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$1001'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$1001'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$999'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$999'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$991'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$991'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$977'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$977'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$971'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$971'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$966'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$966'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$763'.
Found and cleaned up 6 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$755'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$755'.
Found and cleaned up 1 empty switch in `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:59$957'.
Removing empty process `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:59$957'.
Found and cleaned up 3 empty switches in `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:47$920'.
Removing empty process `$paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.$proc$Risco-5/src/peripheral/memory.v:47$920'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$269'.
Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$266'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$266'.
Removing empty process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:0$912'.
Found and cleaned up 2 empty switches in `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:127$905'.
Removing empty process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:127$905'.
Found and cleaned up 8 empty switches in `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:61$897'.
Removing empty process `$paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.$proc$Risco-5/src/peripheral/uart.v:61$897'.
Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:31$895'.
Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:31$895'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$188'.
Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:24$170'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:24$170'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$162'.
Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:15$159'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:15$159'.
Found and cleaned up 2 empty switches in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$142'.
Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$142'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$141'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:189$132'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:189$132'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:180$128'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:143$126'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:143$126'.
Found and cleaned up 4 empty switches in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$124'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$661'.
Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$655'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$655'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$87'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:628$86'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:618$85'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:618$85'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:303$72'.
Found and cleaned up 19 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:141$40'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:133$39'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:133$39'.
Found and cleaned up 5 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'.
Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'.
Found and cleaned up 1 empty switch in `\Alu.$proc$Risco-5/src/core/alu.v:26$11'.
Removing empty process `Alu.$proc$Risco-5/src/core/alu.v:26$11'.
Cleaned up 114 empty switches.

22.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
<suppressed ~4 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
<suppressed ~10 debug messages>
Optimizing module $paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.
<suppressed ~5 debug messages>
Optimizing module LEDs.
<suppressed ~3 debug messages>
Optimizing module $paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.
<suppressed ~16 debug messages>
Optimizing module GPIO.
<suppressed ~3 debug messages>
Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
<suppressed ~4 debug messages>
Optimizing module BUS.
<suppressed ~4 debug messages>
Optimizing module Registers.
<suppressed ~2 debug messages>
Optimizing module PC.
<suppressed ~2 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module Immediate_Generator.
Optimizing module CSR_Unit.
<suppressed ~3 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~7 debug messages>
Optimizing module Control_Unit.
<suppressed ~26 debug messages>
Optimizing module ALU_Control.
<suppressed ~18 debug messages>
Optimizing module Alu.
<suppressed ~1 debug messages>
Optimizing module $paramod$3165995eef18218159020b46b9263540bd7186c4\Risco_5_SOC.
Optimizing module top.

22.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Deleting now unused module $paramod$341aa037cc9f2d333096c006c9583dd9a8ce958a\Memory.
Deleting now unused module LEDs.
Deleting now unused module $paramod$e7a32d66beee4a01468676cd84ffc560be3c380b\UART.
Deleting now unused module GPIO.
Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Deleting now unused module BUS.
Deleting now unused module Registers.
Deleting now unused module PC.
Deleting now unused module MUX.
Deleting now unused module Immediate_Generator.
Deleting now unused module CSR_Unit.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module Control_Unit.
Deleting now unused module ALU_Control.
Deleting now unused module Alu.
Deleting now unused module $paramod$3165995eef18218159020b46b9263540bd7186c4\Risco_5_SOC.
<suppressed ~30 debug messages>

22.6. Executing TRIBUF pass.

22.7. Executing DEMINOUT pass (demote inout ports to input or output).

22.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~47 debug messages>

22.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 82 unused cells and 880 unused wires.
<suppressed ~103 debug messages>

22.10. Executing CHECK pass (checking for obvious problems).
Checking module top...
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [15] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [14] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [13] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [12] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [11] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [10] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [9] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [8] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [7] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [6] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [5] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [4] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [3] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [2] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [1] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_fast [0] is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_external is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_timer is used but has no driver.
Warning: Wire top.\SOC.Core.CSR_Unit.interruption_request_software is used but has no driver.
Found and reported 19 problems.

22.11. Executing OPT pass (performing simple optimizations).

22.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~21 debug messages>

22.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~771 debug messages>
Removed a total of 257 cells.

22.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2432.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2445.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2461.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2463.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2478.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2496.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2517.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2542.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2569.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2599.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2632.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2677.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2724.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2772.
    dead port 1/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2822.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2824.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2874.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2876.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2925.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2984.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3035.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1777.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1728.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1734.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1740.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1746.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1437.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1439.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1446.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1448.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1455.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1457.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1464.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1466.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1473.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1475.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1482.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1484.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1490.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1496.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1502.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1508.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1514.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1520.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1526.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1532.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1538.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1082.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1088.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1094.
Removed 50 multiplexer ports.
<suppressed ~140 debug messages>

22.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2040: $auto$opt_reduce.cc:134:opt_pmux$3312
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2054: $auto$opt_reduce.cc:134:opt_pmux$3314
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2072: $auto$opt_reduce.cc:134:opt_pmux$3316
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2121: $auto$opt_reduce.cc:134:opt_pmux$3318
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2147: $auto$opt_reduce.cc:134:opt_pmux$3320
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2164: { $auto$opt_reduce.cc:134:opt_pmux$3324 $auto$opt_reduce.cc:134:opt_pmux$3322 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2192: $auto$opt_reduce.cc:134:opt_pmux$3326
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2212: $auto$opt_reduce.cc:134:opt_pmux$3328
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2215: $auto$opt_reduce.cc:134:opt_pmux$3330
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2222: { $flatten\SOC.\Core.\Control_Unit.$procmux$2075_CMP $auto$opt_reduce.cc:134:opt_pmux$3342 $auto$opt_reduce.cc:134:opt_pmux$3340 $auto$opt_reduce.cc:134:opt_pmux$3338 $auto$opt_reduce.cc:134:opt_pmux$3336 $auto$opt_reduce.cc:134:opt_pmux$3334 $auto$opt_reduce.cc:134:opt_pmux$3332 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3109: { $flatten\SOC.\Core.\ALU_Control.$procmux$3116_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3115_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3114_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3113_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3112_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3111_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3110_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2256: { $flatten\SOC.\Core.\Control_Unit.$procmux$2249_CMP $auto$opt_reduce.cc:134:opt_pmux$3356 $auto$opt_reduce.cc:134:opt_pmux$3354 $auto$opt_reduce.cc:134:opt_pmux$3352 $flatten\SOC.\Core.\Control_Unit.$procmux$2171_CMP $auto$opt_reduce.cc:134:opt_pmux$3350 $flatten\SOC.\Core.\Control_Unit.$procmux$2168_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2167_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2166_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2165_CMP $auto$opt_reduce.cc:134:opt_pmux$3348 $auto$opt_reduce.cc:134:opt_pmux$3346 $auto$opt_reduce.cc:134:opt_pmux$3344 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3132: { $flatten\SOC.\Core.\ALU_Control.$procmux$3134_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3133_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2291: { $auto$opt_reduce.cc:134:opt_pmux$3358 $flatten\SOC.\Core.\Control_Unit.$procmux$2227_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2298: $auto$opt_reduce.cc:134:opt_pmux$3360
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2302: { $flatten\SOC.\Core.\Control_Unit.$procmux$2220_CMP $auto$opt_reduce.cc:134:opt_pmux$3362 $flatten\SOC.\Core.\Control_Unit.$procmux$2208_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2318: $auto$opt_reduce.cc:134:opt_pmux$3364
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2340: $auto$opt_reduce.cc:134:opt_pmux$3366
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2358: $auto$opt_reduce.cc:134:opt_pmux$3368
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2417: $auto$opt_reduce.cc:134:opt_pmux$3370
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2973: { $auto$opt_reduce.cc:134:opt_pmux$3372 $flatten\SOC.\Core.\Control_Unit.$procmux$2981_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2980_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2979_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2978_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2977_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2976_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2975_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2974_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3038: { $flatten\SOC.\Core.\Control_Unit.$procmux$2285_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2254_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2150_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2345_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2127_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2321_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2226_CMP $auto$opt_reduce.cc:134:opt_pmux$3376 $flatten\SOC.\Core.\Control_Unit.$procmux$2178_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2219_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2149_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2126_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2177_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2249_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2125_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2109_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2076_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2075_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2173_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2244_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2074_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2171_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2170_CMP $auto$opt_reduce.cc:134:opt_pmux$3374 $flatten\SOC.\Core.\Control_Unit.$procmux$2042_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2056_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2148_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2123_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2168_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2167_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2073_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2166_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2165_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2041_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2055_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1780: { $flatten\SOC.\Core.\Control_Unit.$procmux$2978_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2979_CMP $auto$opt_reduce.cc:134:opt_pmux$3380 $flatten\SOC.\Core.\Control_Unit.$procmux$2980_CMP $auto$opt_reduce.cc:134:opt_pmux$3378 $flatten\SOC.\Core.\Control_Unit.$procmux$2974_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2982_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1725:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1743:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1749:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$164_EN[31:0]$171 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1434:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1434_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1434_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1434_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] $flatten\SOC.\Memory.$procmux$1434_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1461:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Memory.$procmux$1461_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Memory.$procmux$1461_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1461_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] $flatten\SOC.\Memory.$procmux$1461_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1488:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1488_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1488_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1488_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] $flatten\SOC.\Memory.$procmux$1488_Y [0] }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2018: { $flatten\SOC.\Core.\Control_Unit.$procmux$2015_CMP $auto$opt_reduce.cc:134:opt_pmux$3382 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1079:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1079_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1079_Y [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$procmux$1079_Y [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$procmux$1079_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1079_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1079_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1079_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1079_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1079_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1079_Y [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1752:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$186, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1743_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$166_EN[31:0]$175 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1755:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$185, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1725_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$165_EN[31:0]$174 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1506:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$956, B=0, Y=$flatten\SOC.\Memory.$procmux$1506_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1461_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1506_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1506_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] $flatten\SOC.\Memory.$procmux$1506_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1524:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$953, B=0, Y=$flatten\SOC.\Memory.$procmux$1524_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1434_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1524_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1524_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] $flatten\SOC.\Memory.$procmux$1524_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1559:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$943, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1488_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_EN[31:0]$923 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1097:
      Old ports: A=$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_EN[7:0]$882, B=8'00000000, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_EN[7:0]$873
      New ports: A=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1079_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_EN[7:0]$873 [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_EN[7:0]$873 [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_EN[7:0]$873 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_EN[7:0]$873 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_EN[7:0]$873 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_EN[7:0]$873 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_EN[7:0]$873 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_EN[7:0]$873 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_EN[7:0]$873 [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1541:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$949, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1506_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_EN[31:0]$929 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1550:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$946, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1524_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_EN[31:0]$926 [0] }
  Optimizing cells in module \top.
Performed a total of 39 changes.

22.11.5. Executing OPT_MERGE pass (detect identical cells).
+ cd Risco-5/fpga/tangnano20k/
+ /eda/gowin/IDE/bin/gw_sh run.tcl
*** GOWIN Tcl Command Line Console  *** 
current device: GW2AR-18C  GW2AR-LV18QN88C8/I7
add new file: "pinout.cst"
add new file: "top.sdc"
add new file: "main.v"
add new file: "../../debug/reset.v"
add new file: "../../src/core/alu_control.v"
add new file: "../../src/core/alu.v"
add new file: "../../src/core/control_unit.v"
add new file: "../../src/core/core.v"
add new file: "../../src/core/immediate_generator.v"
add new file: "../../src/core/mux.v"
add new file: "../../src/core/pc.v"
add new file: "../../src/core/registers.v"
add new file: "../../src/core/csr_unit.v"
add new file: "../../src/peripheral/bus.v"
add new file: "../../src/peripheral/gpio.v"
add new file: "../../src/peripheral/gpios.v"
add new file: "../../src/peripheral/leds.v"
add new file: "../../src/peripheral/memory.v"
add new file: "../../src/peripheral/soc.v"
add new file: "../../src/peripheral/uart_rx.v"
add new file: "../../src/peripheral/uart_tx.v"
add new file: "../../src/peripheral/uart.v"
add new file: "../../src/peripheral/fifo.v"
GowinSynthesis start
Running parser ...
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v'
Undeclared symbol 'pc_source', assumed default net type 'wire'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":142)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v'
WARN  (EX3801) : Parameter 'SET_DIRECTION' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":19)
WARN  (EX3801) : Parameter 'READ' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":20)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v'
WARN  (EX3012) : Empty statement in sequential block("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":54)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v'
WARN  (EX3073) : Port 'resetn_o' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":18)
Compiling module 'top'("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":1)
Compiling module 'ResetBootSystem'("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":1)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":37)
Compiling module 'Risco_5_SOC(CLOCK_FREQ=27000000,MEMORY_SIZE=2048,MEMORY_FILE="../../software/memory/fpga_test_3.hex")'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":1)
WARN  (EX3073) : Port 'interrupt_on_hold' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":242)
Compiling module 'Core(BOOT_ADDRESS=32'b00000000000000000000000000000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":1)
Compiling module 'PC'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v":1)
Compiling module 'MUX'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v":1)
Compiling module 'Registers'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v":1)
Compiling module 'Control_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":1)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":507)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":514)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":527)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":534)
Compiling module 'ALU_Control'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":1)
WARN  (EX2420) : Latch inferred for net 'aluop_out[3]'; We do not recommend the use of latches in FPGA designs, as they may lead to timing problems("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":60)
Compiling module 'Alu'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v":1)
Compiling module 'Immediate_Generator'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v":1)
Compiling module 'CSR_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":1)
WARN  (EX3780) : Using initial value of 'csr_mcause_code' since it is never assigned("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":100)
WARN  (EX2565) : Input 'save_pc' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":242)
Compiling module 'Memory(MEMORY_FILE="../../software/memory/fpga_test_3.hex",MEMORY_SIZE=2048)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":1)
Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":16)
Compiling module 'BUS'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v":1)
Compiling module 'LEDs'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":1)
WARN  (EX3791) : Expression size 33 truncated to fit in target size 32("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":21)
Compiling module 'UART(CLK_FREQ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v":1)
WARN  (EX3791) : Expression size 33 truncated to fit in target size 32("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v":91)
Compiling module 'FIFO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":1)
Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":15)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":35)
Compiling module 'uart_tool_rx(CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v":10)
Compiling module 'uart_tool_tx(CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v":10)
Finding identical cells in module `\top'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

22.11.6. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $flatten\SOC.\Uart.$procdff$3222 ($dff) from module top.

22.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 331 unused wires.
<suppressed ~1 debug messages>

22.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~12 debug messages>

22.11.9. Rerunning OPT passes. (Maybe there is more to do..)

22.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$890.
    dead port 2/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$890.
Removed 2 multiplexer ports.
<suppressed ~140 debug messages>

22.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Alu.$procmux$3137: { $flatten\SOC.\Core.\Alu.$procmux$3151_CMP $flatten\SOC.\Core.\Alu.$procmux$3150_CMP $flatten\SOC.\Core.\Alu.$procmux$3149_CMP $flatten\SOC.\Core.\Alu.$procmux$3148_CMP $auto$opt_reduce.cc:134:opt_pmux$3386 $flatten\SOC.\Core.\Alu.$procmux$3145_CMP $flatten\SOC.\Core.\Alu.$procmux$3144_CMP $flatten\SOC.\Core.\Alu.$procmux$3143_CMP $flatten\SOC.\Core.\Alu.$procmux$3142_CMP $flatten\SOC.\Core.\Alu.$procmux$3141_CMP $flatten\SOC.\Core.\Alu.$procmux$3140_CMP $auto$opt_reduce.cc:134:opt_pmux$3384 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2256: { $flatten\SOC.\Core.\Control_Unit.$procmux$2249_CMP $auto$opt_reduce.cc:134:opt_pmux$3356 $auto$opt_reduce.cc:134:opt_pmux$3354 $auto$opt_reduce.cc:134:opt_pmux$3352 $flatten\SOC.\Core.\Control_Unit.$procmux$2171_CMP $auto$opt_reduce.cc:134:opt_pmux$3350 $auto$opt_reduce.cc:134:opt_pmux$3390 $auto$opt_reduce.cc:134:opt_pmux$3388 $auto$opt_reduce.cc:134:opt_pmux$3348 $auto$opt_reduce.cc:134:opt_pmux$3346 $auto$opt_reduce.cc:134:opt_pmux$3344 }
    New ctrl vector for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$1378: { $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:146$993_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:114$975_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:131$985_Y }
  Optimizing cells in module \top.
Performed a total of 3 changes.

22.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.11.13. Executing OPT_DFF pass (perform DFF optimizations).

22.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 6 unused cells and 21 unused wires.
<suppressed ~11 debug messages>

22.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.11.16. Rerunning OPT passes. (Maybe there is more to do..)

22.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~138 debug messages>

22.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.11.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.11.20. Executing OPT_DFF pass (perform DFF optimizations).

22.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.11.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.11.23. Finished OPT passes. (There is nothing left to do.)

22.12. Executing FSM pass (extract and optimize FSM).

22.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Compiling module 'GPIOS(WIDHT=5)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":1)
Compiling module 'GPIO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v":1)
WARN  (EX2565) : Input 'halt' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_external' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_timer' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_software' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_fast[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_fast[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_fast[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_fast[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_fast[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_fast[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_fast[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_fast[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_fast[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_fast[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_fast[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_fast[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_fast[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_fast[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_fast[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
WARN  (EX2565) : Input 'interruption_request_fast[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":42)
NOTE  (EX0101) : Current top module is "top"
WARN  (EX0211) : The output port "interrupt_on_hold" of module "CSR_Unit" has no driver, assigning undriven bits to Z, simulation mismatch possible("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":20)
[5%] Running netlist conversion ...
WARN  (CV0016) : Input reset is unused("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":3)
Not marking top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.
Not marking top.SOC.Core.CSR_Unit.csr_mip_mfip as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Not marking top.SOC.Core.Control_Unit.state as FSM state register:
    Register has an initialization value.
Found FSM state register top.SOC.Uart.TX_FIFO.read_ptr.
Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state.
Found FSM state register top.SOC.Uart.i_uart_tx.fsm_state.
Not marking top.SOC.Uart.state as FSM state register:
    Register has an initialization value.

22.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\SOC.Uart.TX_FIFO.read_ptr' from module `\top'.
  found $dff cell for state register: $flatten\SOC.\Uart.\TX_FIFO.$procdff$3182
  root of input selection tree: $flatten\SOC.\Uart.\TX_FIFO.$0\read_ptr[5:0]
  found reset state: 6'000000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found state code: 6'000000
  fsm extraction failed: at least two states are required.
Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'.
  found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$3189
  root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1018_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1031_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1044_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1030_Y
  found state code: 3'000
  found ctrl input: \SOC.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \SOC.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1044_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:143$1035_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1031_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1030_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1018_Y
  ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o }
  ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1018_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1030_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1031_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:143$1035_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1044_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'0--0 ->      3'001 8'01010001
  transition:      3'000 4'1--0 ->      3'000 8'01010000
  transition:      3'000 4'---1 ->      3'000 8'01010000
  transition:      3'010 4'--00 ->      3'010 8'00100010
  transition:      3'010 4'--10 ->      3'011 8'00100011
  transition:      3'010 4'---1 ->      3'000 8'00100000
  transition:      3'001 4'-0-0 ->      3'001 8'00011001
  transition:      3'001 4'-1-0 ->      3'010 8'00011010
  transition:      3'001 4'---1 ->      3'000 8'00011000
  transition:      3'011 4'-0-0 ->      3'011 8'10010011
  transition:      3'011 4'-1-0 ->      3'000 8'10010000
  transition:      3'011 4'---1 ->      3'000 8'10010000
Extracting FSM `\SOC.Uart.i_uart_tx.fsm_state' from module `\top'.
  found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_tx.$procdff$3197
  root of input selection tree: $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:131$985_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:114$975_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:146$993_Y
  found state code: 3'000
  found ctrl input: \SOC.Uart.i_uart_tx.stop_done
  found state code: 3'011
  found ctrl input: \SOC.Uart.i_uart_tx.payload_done
  found state code: 3'010
  found ctrl input: \SOC.Uart.i_uart_tx.next_bit
  found state code: 3'001
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:146$993_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:131$985_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:127$980_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:127$979_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:114$975_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:112$973_Y
  ctrl inputs: { \SOC.Uart.i_uart_tx.next_bit \SOC.Uart.i_uart_tx.payload_done \SOC.Uart.i_uart_tx.stop_done \ResetBootSystem.reset_o }
  ctrl outputs: { $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:112$973_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:114$975_Y $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:127$979_Y $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:127$980_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:131$985_Y $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:146$993_Y $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] }
  transition:      3'000 4'---0 ->      3'000 9'101100000
  transition:      3'000 4'---1 ->      3'000 9'101100000
  transition:      3'010 4'-0-0 ->      3'010 9'010100010
  transition:      3'010 4'-1-0 ->      3'011 9'010100011
  transition:      3'010 4'---1 ->      3'000 9'010100000
  transition:      3'001 4'0--0 ->      3'001 9'001101001
  transition:      3'001 4'1--0 ->      3'010 9'001101010
  transition:      3'001 4'---1 ->      3'000 9'001101000
  transition:      3'011 4'--00 ->      3'011 9'001010011
  transition:      3'011 4'--10 ->      3'000 9'001010000
  transition:      3'011 4'---1 ->      3'000 9'001010000

22.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$3398' from module `\top'.
  Merging pattern 4'---0 and 4'---1 from group (0 0 9'101100000).
  Merging pattern 4'---1 and 4'---0 from group (0 0 9'101100000).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3391' from module `\top'.

22.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 15 unused cells and 15 unused wires.
<suppressed ~16 debug messages>

22.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3391' from module `\top'.
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].
Optimizing FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$3398' from module `\top'.
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_tx.$0\fsm_state[2:0] [2].

22.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3391' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---
Recoding FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$3398' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---

22.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3391' from module `top':
-------------------------------------

  Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$3391 (\SOC.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \ResetBootSystem.reset_o
    1: \SOC.Uart.i_uart_rx.payload_done
    2: \SOC.Uart.i_uart_rx.next_bit
    3: \SOC.Uart.i_uart_rx.rxd_reg

  Output signals:
    0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1044_Y
    1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:143$1035_Y
    2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1031_Y
    3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1030_Y
    4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1018_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'1--0   ->     0 5'01010
      1:     0 4'---1   ->     0 5'01010
      2:     0 4'0--0   ->     2 5'01010
      3:     1 4'---1   ->     0 5'00100
      4:     1 4'--00   ->     1 5'00100
      5:     1 4'--10   ->     3 5'00100
      6:     2 4'---1   ->     0 5'00011
      7:     2 4'-1-0   ->     1 5'00011
      8:     2 4'-0-0   ->     2 5'00011
      9:     3 4'-1-0   ->     0 5'10010
     10:     3 4'---1   ->     0 5'10010
     11:     3 4'-0-0   ->     3 5'10010

-------------------------------------

FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$3398' from module `top':
-------------------------------------

  Information on FSM $fsm$\SOC.Uart.i_uart_tx.fsm_state$3398 (\SOC.Uart.i_uart_tx.fsm_state):

  Number of input signals:    4
  Number of output signals:   6
  Number of state bits:       4

  Input signals:
    0: \ResetBootSystem.reset_o
    1: \SOC.Uart.i_uart_tx.stop_done
    2: \SOC.Uart.i_uart_tx.payload_done
    3: \SOC.Uart.i_uart_tx.next_bit

  Output signals:
    0: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:146$993_Y
    1: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:131$985_Y
    2: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:127$980_Y
    3: $flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:127$979_Y
    4: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:114$975_Y
    5: $flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:112$973_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'----   ->     0 6'101100
      1:     1 4'---1   ->     0 6'010100
      2:     1 4'-0-0   ->     1 6'010100
      3:     1 4'-1-0   ->     3 6'010100
      4:     2 4'---1   ->     0 6'001101
      5:     2 4'1--0   ->     1 6'001101
      6:     2 4'0--0   ->     2 6'001101
      7:     3 4'--10   ->     0 6'001010
      8:     3 4'---1   ->     0 6'001010
      9:     3 4'--00   ->     3 6'001010

-------------------------------------

22.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3391' from module `\top'.
Mapping FSM `$fsm$\SOC.Uart.i_uart_tx.fsm_state$3398' from module `\top'.

22.13. Executing OPT pass (performing simple optimizations).

22.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~9 debug messages>

22.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

22.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~136 debug messages>

22.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3201 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1354_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1345_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1336_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1327_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1318_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1300_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1309_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0], rval = 7'0000000).
Adding EN signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3201 ($dff) from module top (D = 1'0, Q = \SOC.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$3484 ($sdff) from module top (D = \SOC.Uart.i_uart_tx.data_to_send [7:1], Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3199 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1279_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3488 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1279_Y, Q = \SOC.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3198 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1268_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$3494 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$998_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3196 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1257_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$3498 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1257_Y, Q = \SOC.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3195 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1246_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3504 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3193 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$1223_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1214_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1205_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1196_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1187_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1178_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1160_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1169_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3506 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3192 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1142_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3510 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1038_Y, Q = \SOC.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3191 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1137_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3514 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3190 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1129_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$3516 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1049_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3188 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3187 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$3183 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1106_Y, Q = \SOC.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3522 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$885_Y, Q = \SOC.Uart.TX_FIFO.write_ptr).
Adding EN signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$3182 ($dff) from module top (D = 6'000000, Q = \SOC.Uart.TX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$3183 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1106_Y, Q = \SOC.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3525 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:31$885_Y, Q = \SOC.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$3182 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1111_Y, Q = \SOC.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3527 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$890_Y [5:0], Q = \SOC.Uart.RX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3232 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1608_Y, Q = \SOC.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3231 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1593_Y, Q = \SOC.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3230 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1619_Y, Q = \SOC.Uart.response, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3229 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1661_Y, Q = \SOC.Uart.read_data, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3544 ($sdff) from module top (D = { \SOC.Uart.read_data [23:0] \SOC.Uart.rx_fifo_read_data }, Q = \SOC.Uart.read_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3228 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1674_Y, Q = \SOC.Uart.counter, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$3550 ($sdff) from module top (D = $flatten\SOC.\Uart.$procmux$1674_Y, Q = \SOC.Uart.counter).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3227 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1688_Y, Q = \SOC.Uart.state, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$3564 ($sdff) from module top (D = $flatten\SOC.\Uart.$procmux$1688_Y, Q = \SOC.Uart.state).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3226 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1581_Y, Q = \SOC.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3572 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.uart_rx_data, Q = \SOC.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$3224 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1572_Y, Q = \SOC.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Leds.$procdff$3221 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$1567_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3575 ($sdff) from module top (D = { 1'0 \SOC.GPIOS.write_data [31] \SOC.Leds.write_data [30:6] \SOC.GPIOS.write_data [5:0] }, Q = \SOC.Leds.data).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$3236 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1711_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3577 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_value).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$3235 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1719_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3581 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_direction).
Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$3242 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$1763_Y, Q = \SOC.Core.Pc.Output, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3587 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.Output).
Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$3261 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 6'000000).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3257 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1827_Y, Q = \SOC.Core.CSR_Unit.csr_mtval, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3590 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mtval).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3256 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 1'0 \SOC.Core.CSR_Unit.csr_write_data [0] }, Q = \SOC.Core.CSR_Unit.csr_mtvec).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3255 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1853_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$3603 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mstatus_mpie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3254 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1868_Y, Q = \SOC.Core.CSR_Unit.csr_mstatus_mie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3609 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mstatus_mie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3253 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1882_Y, Q = \SOC.Core.CSR_Unit.csr_mscratch, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3615 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mscratch).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3252 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1898_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mtie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3621 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [7], Q = \SOC.Core.CSR_Unit.csr_mie_mtie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3251 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1914_Y, Q = \SOC.Core.CSR_Unit.csr_mie_msie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3627 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [3], Q = \SOC.Core.CSR_Unit.csr_mie_msie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3250 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1930_Y, Q = \SOC.Core.CSR_Unit.csr_mie_meie, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3633 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [11], Q = \SOC.Core.CSR_Unit.csr_mie_meie).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3249 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1946_Y, Q = \SOC.Core.CSR_Unit.csr_mie_mfie, rval = 16'0000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3639 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data [31:16], Q = \SOC.Core.CSR_Unit.csr_mie_mfie).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3248 ($dff) from module top (D = { \SOC.Core.CSR_Unit.csr_write_data [31:2] 2'00 }, Q = \SOC.Core.CSR_Unit.csr_mepc).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3247 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1966_Y, Q = \SOC.Core.CSR_Unit.csr_mcause, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3652 ($sdff) from module top (D = \SOC.Core.CSR_Unit.csr_write_data, Q = \SOC.Core.CSR_Unit.csr_mcause).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3246 ($dff) from module top (D = \SOC.Core.CSR_Unit.interruption_request_software, Q = \SOC.Core.CSR_Unit.csr_mip_msip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3245 ($dff) from module top (D = \SOC.Core.CSR_Unit.interruption_request_timer, Q = \SOC.Core.CSR_Unit.csr_mip_mtip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3244 ($dff) from module top (D = \SOC.Core.CSR_Unit.interruption_request_external, Q = \SOC.Core.CSR_Unit.csr_mip_meip, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3243 ($dff) from module top (D = \SOC.Core.CSR_Unit.interruption_request_fast, Q = \SOC.Core.CSR_Unit.csr_mip_mfip, rval = 16'0000000000000000).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3211 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1395_Y, Q = \SOC.Core.temp_write_value, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3662 ($sdff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.temp_write_value).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3210 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1400_Y, Q = \SOC.Core.temp_reg3, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3664 ($sdff) from module top (D = \SOC.Core.alu_out_register, Q = \SOC.Core.temp_reg3).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3209 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1405_Y, Q = \SOC.Core.temp_reg2, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3666 ($sdff) from module top (D = \SOC.Core.memory_register, Q = \SOC.Core.temp_reg2).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3208 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1410_Y, Q = \SOC.Core.temp_address, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3668 ($sdff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.temp_address).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3207 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1415_Y, Q = \SOC.Core.pc_old, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3670 ($sdff) from module top (D = \SOC.Core.Pc.Output, Q = \SOC.Core.pc_old).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3206 ($dff) from module top (D = \SOC.Core.register_data_2_out, Q = \SOC.Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3205 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3204 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3203 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$3202 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1420_Y, Q = \SOC.Core.instruction_register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3676 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register).
Adding EN signal on $flatten\ResetBootSystem.$procdff$3260 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$3259 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding EN signal on $flatten\ResetBootSystem.$procdff$3258 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3645 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3645 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3596 ($dffe) from module top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$3576 ($sdffe) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3524 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3524 ($dffe) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3524 ($dffe) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$3524 ($dffe) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$3524 ($dffe) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$3524 ($dffe) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3486 ($dffe) from module top.

22.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 157 unused cells and 161 unused wires.
<suppressed ~158 debug messages>

22.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~9 debug messages>

22.13.9. Rerunning OPT passes. (Maybe there is more to do..)

22.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~82 debug messages>

22.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$3512: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o }
  Optimizing cells in module \top.
Performed a total of 1 changes.

22.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~45 debug messages>
Removed a total of 15 cells.

22.13.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$3487 ($sdffe) from module top.

22.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 21 unused wires.
<suppressed ~3 debug messages>

22.13.15. Executing OPT_EXPR pass (perform const folding).
Running device independent optimization ...
Optimizing module top.

22.13.16. Rerunning OPT passes. (Maybe there is more to do..)

22.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~82 debug messages>

22.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.20. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$3704 ($sdffe) from module top.

22.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.13.23. Rerunning OPT passes. (Maybe there is more to do..)

22.13.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~82 debug messages>

22.13.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.27. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$3705 ($sdffe) from module top.

22.13.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.13.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.13.30. Rerunning OPT passes. (Maybe there is more to do..)

22.13.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~82 debug messages>

22.13.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.34. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$3706 ($sdffe) from module top.

22.13.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.13.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.13.37. Rerunning OPT passes. (Maybe there is more to do..)

22.13.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~82 debug messages>

22.13.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.40. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.41. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3707 ($sdffe) from module top.

22.13.42. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.13.43. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.13.44. Rerunning OPT passes. (Maybe there is more to do..)

22.13.45. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~82 debug messages>

22.13.46. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.47. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.48. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3708 ($sdffe) from module top.

22.13.49. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.13.50. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.13.51. Rerunning OPT passes. (Maybe there is more to do..)

22.13.52. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~82 debug messages>

22.13.53. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.54. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.55. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3709 ($sdffe) from module top.

22.13.56. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.13.57. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.13.58. Rerunning OPT passes. (Maybe there is more to do..)

22.13.59. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~82 debug messages>

22.13.60. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.13.61. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.13.62. Executing OPT_DFF pass (perform DFF optimizations).

22.13.63. Executing OPT_CLEAN pass (remove unused cells and wires).
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
Finding unused cells or wires in module \top..

22.13.64. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.13.65. Finished OPT passes. (There is nothing left to do.)

22.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$3266 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$3268 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$meminit$\registers$Risco-5/src/core/registers.v:17$187 (SOC.Core.RegisterBank.registers).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3263 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3264 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3265 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$958 (SOC.Memory.memory).
Removed top 21 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:24$918 (SOC.Memory.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$3262 (SOC.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:22$869 (SOC.Uart.RX_FIFO.memory).
Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$2003_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$659 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$658 ($add).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$658 ($add).
Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$657 ($lt).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$3689 ($ne).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$3684 ($ne).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:22$894 ($mux).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$ne$Risco-5/src/peripheral/uart.v:103$902 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$1598_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$1613_CMP0 ($eq).
Removed top 2 bits (of 3) from mux cell top.$flatten\SOC.\Uart.$procmux$1699 ($mux).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$883 ($eq).
Removed top 5 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:20$863 ($eq).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1103 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1091 ($mux).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$890 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$889 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:31$883 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:21$865 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:113$1027 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:112$1026 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:111$1025 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:110$1024 ($mux).
Removed top 2 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:103$1019 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:101$1017 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:129$983 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:97$970 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:96$969 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:95$968 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:88$963 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:86$961 ($eq).
Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$265 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Bus.$eq$Risco-5/src/peripheral/bus.v:53$194 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Memory.$procmux$1430_CMP0 ($eq).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1547 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1556 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1565 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\MemoryAddressMUX.$eq$Risco-5/src/core/mux.v:15$144 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$eq$Risco-5/src/core/mux.v:17$146 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$eq$Risco-5/src/core/mux.v:16$145 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$eq$Risco-5/src/core/mux.v:15$144 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$eq$Risco-5/src/core/mux.v:17$146 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$eq$Risco-5/src/core/mux.v:16$145 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$eq$Risco-5/src/core/mux.v:15$144 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:17$146 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:16$145 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:15$144 ($eq).
Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3033 ($mux).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2982_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2981_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2980_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2977_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2976_CMP0 ($eq).
Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2973 ($pmux).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2872 ($mux).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2819 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2770 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2722 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2675 ($mux).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2630 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2597 ($mux).
Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2567 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2540 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2494 ($mux).
Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2443 ($mux).
Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2345_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2321_CMP0 ($eq).
Removed top 5 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2254_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2249_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2244_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2230_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2228_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2227_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2226_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2224_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2223_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2220_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2219_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2218_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2217_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2214_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2213_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2208_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2178_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2177_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2173_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2172_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2150_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2149_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2127_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2126_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2125_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2109_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2076_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2075_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2074_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2018 ($pmux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2016_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2015_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:527$81 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:507$75 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:238$54 ($eq).
Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:166$41 ($eq).
Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:101$38 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3134_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3116_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3115_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3114_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3102 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3150_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3149_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3148_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3147_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3140_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:53$28 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:37$17 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1807_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1800_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1799_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1798_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1797_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1796_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1795_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1794_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1793_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1792_CMP0 ($eq).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1500 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1518 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1536 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1452 ($mux).
Removed top 21 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1479 ($mux).
Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$658_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:37$17_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:53$28_Y.
Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$10\nextstate[5:0].
Removed top 4 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$11\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$13\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$15\nextstate[5:0].
Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$18\nextstate[5:0].
Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0].
Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0].
Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$5\nextstate[5:0].
Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$6\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$7\nextstate[5:0].
Removed top 4 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$8\nextstate[5:0].
Removed top 4 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$9\nextstate[5:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:507$75_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:527$81_Y.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_ADDR[31:0]$921.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_ADDR[31:0]$924.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_ADDR[31:0]$927.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$913_ADDR[31:0]$941.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_ADDR[31:0]$944.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_ADDR[31:0]$947.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$914_ADDR[31:0]$951.
Removed top 21 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$915_ADDR[31:0]$954.
Removed top 1 bits (of 32) from wire top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:24$918_DATA.
Removed top 2 bits (of 3) from wire top.$flatten\SOC.\Uart.$procmux$1699_Y.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_ADDR[5:0]$871.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:30$859_ADDR[5:0]$880.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$889_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:35$890_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:110$1024_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:111$1025_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:112$1026_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:113$1027_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:95$968_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:96$969_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:97$970_Y.

22.15. Executing PEEPOPT pass (run peephole optimizers).

22.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 41 unused wires.
<suppressed ~1 debug messages>

22.17. Executing SHARE pass (SAT-based resource sharing).
Found 5 cells in module top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:24$918 ($memrd):
    Found 7 activation_patterns using ctrl signal { $flatten\SOC.\Memory.$procmux$1431_CMP $flatten\SOC.\Memory.$procmux$1430_CMP $flatten\SOC.\Memory.$procmux$1429_CMP $flatten\SOC.\Memory.$procmux$1428_CMP \SOC.Memory.option [1:0] \SOC.Memory.memory_write \SOC.Memory.memory_read $flatten\SOC.\Bus.$eq$Risco-5/src/peripheral/bus.v:48$190_Y }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\RegisterBank.$memrd$\registers$Risco-5/src/core/registers.v:22$169 ($memrd):
    Found 12 activation_patterns using ctrl signal { $auto$opt_reduce.cc:134:opt_pmux$3384 $auto$opt_reduce.cc:134:opt_pmux$3386 $flatten\SOC.\Core.\Alu.$procmux$3140_CMP $flatten\SOC.\Core.\Alu.$procmux$3141_CMP $flatten\SOC.\Core.\Alu.$procmux$3142_CMP $flatten\SOC.\Core.\Alu.$procmux$3143_CMP $flatten\SOC.\Core.\Alu.$procmux$3144_CMP $flatten\SOC.\Core.\Alu.$procmux$3145_CMP $flatten\SOC.\Core.\Alu.$procmux$3148_CMP $flatten\SOC.\Core.\Alu.$procmux$3149_CMP $flatten\SOC.\Core.\Alu.$procmux$3150_CMP $flatten\SOC.\Core.\Alu.$procmux$3151_CMP $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:14$143_Y $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:15$144_Y $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:16$145_Y $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:17$146_Y }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$sshr$Risco-5/src/core/alu.v:51$26 ($sshr):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3140_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:49$25 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3141_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:47$24 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3142_CMP.
    No candidates found.

22.18. Executing TECHMAP pass (map to technology primitives).

22.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

22.18.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~88 debug messages>

22.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.21. Executing TECHMAP pass (map to technology primitives).

22.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

22.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

22.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

22.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$658 ($add).
  creating $macc model for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$744 ($add).
  creating $macc model for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$743 ($sub).
  creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15 ($sub).
  creating $macc model for $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:105$904 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$862 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$884 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$889 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$884 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1038 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1049 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:132$987 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$998 ($add).
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$998.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:132$987.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1049.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1038.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$884.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$889.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$884.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$862.
  creating $alu model for $macc $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:105$904.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14.
  creating $alu model for $macc $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$743.
  creating $alu model for $macc $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$744.
  creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$658.
  creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$657 ($lt): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:53$27 ($ge): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:37$16 ($lt): merged with $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:53$27.
  creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$659 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$657.
  creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23 ($eq): merged with $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:53$27.
  creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$657, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$659: $auto$alumacc.cc:485:replace_alu$3753
  creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$658: $auto$alumacc.cc:485:replace_alu$3764
  creating $alu cell for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$744: $auto$alumacc.cc:485:replace_alu$3767
  creating $alu cell for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$743: $auto$alumacc.cc:485:replace_alu$3770
  creating $alu cell for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:53$27, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:37$16, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23: $auto$alumacc.cc:485:replace_alu$3773
  creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14: $auto$alumacc.cc:485:replace_alu$3786
  creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15: $auto$alumacc.cc:485:replace_alu$3789
  creating $alu cell for $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:105$904: $auto$alumacc.cc:485:replace_alu$3792
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$884: $auto$alumacc.cc:485:replace_alu$3795
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:20$862: $auto$alumacc.cc:485:replace_alu$3798
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$889: $auto$alumacc.cc:485:replace_alu$3801
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:31$884: $auto$alumacc.cc:485:replace_alu$3804
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1038: $auto$alumacc.cc:485:replace_alu$3807
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1049: $auto$alumacc.cc:485:replace_alu$3810
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:132$987: $auto$alumacc.cc:485:replace_alu$3813
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$998: $auto$alumacc.cc:485:replace_alu$3816
  created 16 $alu and 0 $macc cells.

22.23. Executing OPT pass (performing simple optimizations).

22.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

22.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~5 debug messages>
Removed a total of 1 cells.

22.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~82 debug messages>

22.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

22.23.6. Executing OPT_DFF pass (perform DFF optimizations).

22.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 12 unused wires.
<suppressed ~2 debug messages>

22.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.23.9. Rerunning OPT passes. (Maybe there is more to do..)

22.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~82 debug messages>

22.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.23.13. Executing OPT_DFF pass (perform DFF optimizations).

22.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.23.16. Finished OPT passes. (There is nothing left to do.)

22.24. Executing MEMORY pass.

22.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

22.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

22.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing top.SOC.Core.RegisterBank.registers write port 0.
  Analyzing top.SOC.Core.RegisterBank.registers write port 1.
  Analyzing top.SOC.Core.RegisterBank.registers write port 2.
  Analyzing top.SOC.Memory.memory write port 0.
  Analyzing top.SOC.Memory.memory write port 1.
  Analyzing top.SOC.Memory.memory write port 2.
  Analyzing top.SOC.Uart.RX_FIFO.memory write port 0.

22.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

22.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\SOC.Core.RegisterBank.registers'[0] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[1] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[2] in module `\top': merging output FF to cell.
    Write port 0: don't care on collision.
    Write port 1: non-transparent.
    Write port 2: non-transparent.
Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found.
Checking read port `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port address `\SOC.Core.RegisterBank.registers'[0] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Core.RegisterBank.registers'[1] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found.

22.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 34 unused wires.
<suppressed ~4 debug messages>

22.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
  Merging ports 0, 2 (address 5'00000).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Memory.memory by address:
  Merging ports 0, 1 (address \SOC.Memory.address [12:2]).
  Merging ports 0, 2 (address \SOC.Memory.address [12:2]).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers using sat-based resource sharing:
  Checking group clocked with posedge \clk, width 32: ports 0, 1.
  Common input cone for all EN signals: 13 cells.
  Size of unconstrained SAT problem: 103 variables, 281 clauses
  Merging port 1 into port 0.

22.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

22.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 8 unused cells and 8 unused wires.
<suppressed ~9 debug messages>

22.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

22.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory top.SOC.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_
Extracted data FF from read port 2 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[2]
mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory top.SOC.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of top.SOC.Uart.RX_FIFO.memory: $\SOC.Uart.RX_FIFO.memory$rdreg[0]
<suppressed ~637 debug messages>

22.27. Executing TECHMAP pass (map to technology primitives).

22.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

22.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

22.27.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$8b7e4372fcddb841ff2345ed5b5086c6f0ba0892\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$53415d03e61fda49ab201106a44aeb3bced8762c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$c19a5ea3503c20659e4914754a2828f314969675\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$b0c2857c1edc7c236c691d3923d11ce75ed95a82\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$5487b42ef7d30750413b215363b89156d25a7688\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$4d31dd18949332ef0eef2cd4d2c2caa4836a2455\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$e31cab081cdd1c94d0735cdaaf50d61c1512a237\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
Using template $paramod$673950984e2b9041065a4d811bde0639e1fc3630\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~1209 debug messages>

22.28. Executing OPT pass (performing simple optimizations).

22.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~97 debug messages>

22.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~15 debug messages>
Removed a total of 5 cells.

22.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$3678 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$1983_Y, Q = \ResetBootSystem.counter, rval = 6'000000).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3658 ($sdff) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3661 ($sdff) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3661 ($sdff) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3661 ($sdff) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$3661 ($sdff) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$3661 ($sdff) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$3661 ($sdff) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$3661 ($sdff) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$3661 ($sdff) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$3661 ($sdff) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$3661 ($sdff) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$3661 ($sdff) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$3661 ($sdff) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$3661 ($sdff) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$3661 ($sdff) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$3661 ($sdff) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$3661 ($sdff) from module top.

22.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 7587 unused wires.
<suppressed ~3 debug messages>

22.28.5. Rerunning OPT passes. (Removed registers in this run.)

22.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~17 debug messages>

22.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$6311 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$3710 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3545 ($sdffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3545 ($sdffe) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3545 ($sdffe) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$3545 ($sdffe) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$3545 ($sdffe) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$3545 ($sdffe) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$3545 ($sdffe) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$3545 ($sdffe) from module top.

22.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 18 unused wires.
<suppressed ~2 debug messages>

22.28.10. Rerunning OPT passes. (Removed registers in this run.)

22.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.28.13. Executing OPT_DFF pass (perform DFF optimizations).

22.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.28.15. Finished fast OPT passes.

22.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

22.30. Executing OPT pass (performing simple optimizations).

22.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$3886: $auto$rtlil.cc:2489:ReduceOr$3880 -> 1'1
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\PCSourceMUX.$ternary$Risco-5/src/core/mux.v:15$157.
Removed 1 multiplexer ports.
<suppressed ~51 debug messages>

22.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$3871:
      Old ports: A={ \SOC.Memory.buffer [31:16] \SOC.Leds.write_data [15:6] \SOC.GPIOS.write_data [5:0] }, B={ \SOC.GPIOS.write_data [31] \SOC.Leds.write_data [30:6] \SOC.GPIOS.write_data [5:0] }, Y=$auto$rtlil.cc:2582:Mux$3872
      New ports: A=\SOC.Memory.buffer [31:16], B={ \SOC.GPIOS.write_data [31] \SOC.Leds.write_data [30:16] }, Y=$auto$rtlil.cc:2582:Mux$3872 [31:16]
      New connections: $auto$rtlil.cc:2582:Mux$3872 [15:0] = { \SOC.Leds.write_data [15:6] \SOC.GPIOS.write_data [5:0] }
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$1992: { $flatten\ResetBootSystem.$procmux$1987_CMP $flatten\ResetBootSystem.$procmux$1986_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1995:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$1995_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$1995_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$1995_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3087:
      Old ports: A=4'1001, B=4'0011, Y=$flatten\SOC.\Core.\ALU_Control.$5\aluop_out[3:0]
      New ports: A=2'10, B=2'01, Y={ $flatten\SOC.\Core.\ALU_Control.$5\aluop_out[3:0] [3] $flatten\SOC.\Core.\ALU_Control.$5\aluop_out[3:0] [1] }
      New connections: { $flatten\SOC.\Core.\ALU_Control.$5\aluop_out[3:0] [2] $flatten\SOC.\Core.\ALU_Control.$5\aluop_out[3:0] [0] } = 2'01
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3102:
      Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$3711 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3711 [2]
      New connections: $auto$wreduce.cc:461:run$3711 [1:0] = 2'10
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1791: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1802_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1801_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1800_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1799_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1798_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1797_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1796_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1795_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1794_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1793_CMP }
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2164:
      Old ports: A=4'0000, B=8'10001001, Y=\SOC.Core.control_unit_aluop
      New ports: A=2'00, B=4'1011, Y={ \SOC.Core.control_unit_aluop [3] \SOC.Core.control_unit_aluop [0] }
      New connections: \SOC.Core.control_unit_aluop [2:1] = 2'00
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2358:
      Old ports: A=2'00, B=2'10, Y=\SOC.Core.lorD
      New ports: A=1'0, B=1'1, Y=\SOC.Core.lorD [1]
      New connections: \SOC.Core.lorD [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2430:
      Old ports: A=6'101101, B=6'000000, Y=$flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0]
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0]
      New connections: $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [5:1] = { $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] 1'0 $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2459:
      Old ports: A=6'000000, B=6'100101, Y=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0]
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0]
      New connections: $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [5:1] = { $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] 2'00 $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2494:
      Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$3718 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3718 [2]
      New connections: $auto$wreduce.cc:461:run$3718 [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2515:
      Old ports: A=6'011111, B=6'100010, Y=$flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0]
      New ports: A=2'01, B=2'10, Y={ $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [5] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] }
      New connections: $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [4:1] = { $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] 1'1 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2540:
      Old ports: A=3'110, B=3'011, Y=$auto$wreduce.cc:461:run$3717 [2:0]
      New ports: A=2'10, B=2'01, Y={ $auto$wreduce.cc:461:run$3717 [2] $auto$wreduce.cc:461:run$3717 [0] }
      New connections: $auto$wreduce.cc:461:run$3717 [1] = 1'1
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2597:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$3716 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3716 [2] $auto$wreduce.cc:461:run$3716 [0] }
      New connections: $auto$wreduce.cc:461:run$3716 [1] = $auto$wreduce.cc:461:run$3716 [0]
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2630:
      Old ports: A=5'00000, B=5'10010, Y=$auto$wreduce.cc:461:run$3715 [4:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3715 [1]
      New connections: { $auto$wreduce.cc:461:run$3715 [4:2] $auto$wreduce.cc:461:run$3715 [0] } = { $auto$wreduce.cc:461:run$3715 [1] 3'000 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2675:
      Old ports: A=3'101, B=3'000, Y=$auto$wreduce.cc:461:run$3726 [2:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3726 [0]
      New connections: $auto$wreduce.cc:461:run$3726 [2:1] = { $auto$wreduce.cc:461:run$3726 [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2722:
      Old ports: A=3'110, B=3'000, Y=$auto$wreduce.cc:461:run$3725 [2:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3725 [1]
      New connections: { $auto$wreduce.cc:461:run$3725 [2] $auto$wreduce.cc:461:run$3725 [0] } = { $auto$wreduce.cc:461:run$3725 [1] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2819:
      Old ports: A=5'00101, B=5'11000, Y=$auto$wreduce.cc:461:run$3723 [4:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3723 [3] $auto$wreduce.cc:461:run$3723 [0] }
      New connections: { $auto$wreduce.cc:461:run$3723 [4] $auto$wreduce.cc:461:run$3723 [2:1] } = { $auto$wreduce.cc:461:run$3723 [3] $auto$wreduce.cc:461:run$3723 [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2872:
      Old ports: A=5'00011, B=5'10110, Y=$auto$wreduce.cc:461:run$3722 [4:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3722 [2] $auto$wreduce.cc:461:run$3722 [0] }
      New connections: { $auto$wreduce.cc:461:run$3722 [4:3] $auto$wreduce.cc:461:run$3722 [1] } = { $auto$wreduce.cc:461:run$3722 [2] 2'01 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2923:
      Old ports: A={ 1'0 $auto$wreduce.cc:461:run$3723 [4:0] }, B={ 1'0 $auto$wreduce.cc:461:run$3722 [4:0] }, Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0]
      New ports: A=$auto$wreduce.cc:461:run$3723 [4:0], B=$auto$wreduce.cc:461:run$3722 [4:0], Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [4:0]
      New connections: $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [5] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:101$38:
      Old ports: A=2'11, B=2'01, Y=\SOC.Core.Control_Unit.second_block_write_src_b [1:0]
      New ports: A=1'1, B=1'0, Y=\SOC.Core.Control_Unit.second_block_write_src_b [1]
      New connections: \SOC.Core.Control_Unit.second_block_write_src_b [0] = 1'1
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1773:
      Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:20] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] 20'00000000000000000000 \SOC.Core.instruction_register [31:20] 27'000000000000000000000000000 \SOC.Core.instruction_register [24:20] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0]
      New ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:25] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] 1'0 \SOC.Core.instruction_register [31:25] 8'00000000 }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12:5]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [31:13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] \SOC.Core.instruction_register [24:20] }
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Memory.$procmux$1427:
      Old ports: A=\SOC.Memory.buffer, B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7:0] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:0] 24'000000000000000000000000 \SOC.Memory.buffer [7:0] 16'0000000000000000 \SOC.Memory.buffer [15:0] }, Y=\SOC.Bus.slave_0_read_data
      New ports: A=\SOC.Memory.buffer [31:8], B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:8] 40'0000000000000000000000000000000000000000 \SOC.Memory.buffer [15:8] }, Y=\SOC.Bus.slave_0_read_data [31:8]
      New connections: \SOC.Bus.slave_0_read_data [7:0] = \SOC.Memory.buffer [7:0]
    New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$1674: $auto$opt_reduce.cc:134:opt_pmux$6319
    New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$1688: { $flatten\SOC.\Uart.$procmux$1682_CMP $flatten\SOC.\Uart.$procmux$1694_CMP $auto$opt_reduce.cc:134:opt_pmux$6321 $flatten\SOC.\Uart.$procmux$1619_Y }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.$procmux$1702:
      Old ports: A={ 2'00 \SOC.Bus.slave_2_read }, B=3'101, Y=$flatten\SOC.\Uart.$procmux$1702_Y
      New ports: A={ 1'0 \SOC.Bus.slave_2_read }, B=2'11, Y={ $flatten\SOC.\Uart.$procmux$1702_Y [2] $flatten\SOC.\Uart.$procmux$1702_Y [0] }
      New connections: $flatten\SOC.\Uart.$procmux$1702_Y [1] = 1'0
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_rx.$procmux$1241:
      Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$3743 [0] 1'0 $auto$wreduce.cc:461:run$3744 [1:0] 2'01 \SOC.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$3746 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$3743 [0] $auto$wreduce.cc:461:run$3744 [1:0] 1'1 \SOC.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$3746 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:113$1027:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3746 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3746 [0]
      New connections: $auto$wreduce.cc:461:run$3746 [1] = $auto$wreduce.cc:461:run$3746 [0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$1378:
      Old ports: A=3'000, B={ 1'0 $auto$wreduce.cc:461:run$3747 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$3749 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ $auto$wreduce.cc:461:run$3747 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$3749 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:97$970:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3749 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3749 [0]
      New connections: $auto$wreduce.cc:461:run$3749 [1] = $auto$wreduce.cc:461:run$3749 [0]
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$3875:
      Old ports: A=$auto$rtlil.cc:2582:Mux$3872, B={ \SOC.Memory.buffer [31:8] \SOC.Leds.write_data [7:6] \SOC.GPIOS.write_data [5:0] }, Y=$auto$rtlil.cc:2582:Mux$3876
      New ports: A={ $auto$rtlil.cc:2582:Mux$3872 [31:16] \SOC.Leds.write_data [15:8] }, B=\SOC.Memory.buffer [31:8], Y=$auto$rtlil.cc:2582:Mux$3876 [31:8]
      New connections: $auto$rtlil.cc:2582:Mux$3876 [7:0] = { \SOC.Leds.write_data [7:6] \SOC.GPIOS.write_data [5:0] }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2001:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$1995_Y, Y=$flatten\ResetBootSystem.$procmux$2001_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$1995_Y [1], Y=$flatten\ResetBootSystem.$procmux$2001_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2001_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2476:
      Old ports: A=6'100001, B=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0], Y=$flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0]
      New ports: A=2'01, B={ $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] }, Y={ $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [2] $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [0] }
      New connections: { $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [5:3] $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [1] } = { $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [0] 3'000 }
  Optimizing cells in module \top.
Performed a total of 36 changes.

22.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

22.30.6. Executing OPT_DFF pass (perform DFF optimizations).

22.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 6 unused wires.
<suppressed ~2 debug messages>

22.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~8 debug messages>

22.30.9. Rerunning OPT passes. (Maybe there is more to do..)

22.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\MemoryAddressMUX.$ternary$Risco-5/src/core/mux.v:16$156.
Removed 1 multiplexer ports.
<suppressed ~53 debug messages>

22.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2923:
      Old ports: A={ $auto$wreduce.cc:461:run$3722 [4] $auto$wreduce.cc:461:run$3722 [4] $auto$wreduce.cc:461:run$3722 [0] 1'0 $auto$wreduce.cc:461:run$3722 [0] }, B={ $auto$wreduce.cc:461:run$3722 [4] 1'0 $auto$wreduce.cc:461:run$3722 [4] 1'1 $auto$wreduce.cc:461:run$3722 [0] }, Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [4:0]
      New ports: A={ $auto$wreduce.cc:461:run$3722 [4] $auto$wreduce.cc:461:run$3722 [0] 1'0 }, B={ 1'0 $auto$wreduce.cc:461:run$3722 [4] 1'1 }, Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [3:1]
      New connections: { $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [4] $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [0] } = { $auto$wreduce.cc:461:run$3722 [4] $auto$wreduce.cc:461:run$3722 [0] }
  Optimizing cells in module \top.
Performed a total of 1 changes.

22.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.30.13. Executing OPT_DFF pass (perform DFF optimizations).

22.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 6 unused wires.
<suppressed ~1 debug messages>

22.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.30.16. Rerunning OPT passes. (Maybe there is more to do..)

22.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~54 debug messages>

22.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.30.20. Executing OPT_DFF pass (perform DFF optimizations).

22.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.30.23. Finished OPT passes. (There is nothing left to do.)

22.31. Executing TECHMAP pass (map to technology primitives).

22.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

22.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

22.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $logic_not.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $reduce_bool.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu.
Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $bmux.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $or.
Using template $paramod$bf541dd3c0ba8228982b61e7bfbc350a2c253f4c\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $tribuf.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu.
Using template $paramod$97565c3687be688407d1272a293bd9d0ae6852dc\_90_pmux for cells of type $pmux.
Using template $paramod$19e9557905baa9d3741d0daa66e2ef076e9bab7d\_90_pmux for cells of type $pmux.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using template $paramod$2116a631f856d4d4902c2618dca73dafa3b8c9c0\_90_alu for cells of type $alu.
Using template $paramod$4d45682f6d5f8751d24fc75184ef72226da353f7\_90_pmux for cells of type $pmux.
Using template $paramod$382ee18765329ac2a4237df67c8ed074f3b7e946\_90_pmux for cells of type $pmux.
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
Using template $paramod$e25898cce02b4d043ab08e065e45db8cf66c901c\_90_pmux for cells of type $pmux.
Using template $paramod$a285b5a57fe61eabc57c91b8c412748ee1151a85\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $reduce_xor.
Using template $paramod$95ab7b964273918a033d1324366ecc612d202989\_90_pmux for cells of type $pmux.
Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\_90_pmux for cells of type $pmux.
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $dlatch.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$f5c0c5233796d8af9071458034942fe6bc61211e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$56955d0f36f77738c952d3505dc563df3ee11b94\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$ed6389a5938b09f91843a91d67becca5abedb1bd\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux.
Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux.
Using template $paramod$104d3d1e82b09b030a785dad8a5e608a6d4401f7\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using template $paramod$e4e871699ef984d49b67460a907fd39b385c5c53\_90_demux for cells of type $demux.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~4239 debug messages>

22.32. Executing OPT pass (performing simple optimizations).

22.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~8890 debug messages>

22.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3975 debug messages>
Removed a total of 1325 cells.

22.32.3. Executing OPT_DFF pass (perform DFF optimizations).

22.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).

****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

source run.tcl
# read_verilog "main.v"
Finding unused cells or wires in module \top..
Removed 318 unused cells and 3131 unused wires.
<suppressed ~323 debug messages>

22.32.5. Finished fast OPT passes.

22.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

22.35. Executing TECHMAP pass (map to technology primitives).

22.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

22.35.2. Continuing TECHMAP pass.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_.
No more expansions possible.
<suppressed ~826 debug messages>

22.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~18 debug messages>

22.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

22.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in top.

22.39. Executing ATTRMVCP pass (move or copy attributes).

22.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 4044 unused wires.
<suppressed ~1 debug messages>

22.41. Executing TECHMAP pass (map to technology primitives).

22.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

22.41.2. Continuing TECHMAP pass.

22.41.3. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping \$_DLATCH_N_.$ternary$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$31163 ($mux).
Mapping \$_DLATCH_N_.$logic_not$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$31162 ($logic_not).
<suppressed ~4 debug messages>

22.41.4. Executing OPT pass (performing simple optimizations).

22.41.4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.
<suppressed ~1 debug messages>

22.41.4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

22.41.4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.41.4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

22.41.4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

22.41.4.6. Executing OPT_DFF pass (perform DFF optimizations).

22.41.4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..
Removed 1 unused cells and 2 unused wires.
<suppressed ~2 debug messages>

22.41.4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

22.41.4.9. Rerunning OPT passes. (Maybe there is more to do..)

22.41.4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \$_DLATCH_N_..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.41.4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \$_DLATCH_N_.
Performed a total of 0 changes.

22.41.4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\$_DLATCH_N_'.
Removed a total of 0 cells.

22.41.4.13. Executing OPT_DFF pass (perform DFF optimizations).

22.41.4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \$_DLATCH_N_..

22.41.4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module \$_DLATCH_N_.

22.41.4.16. Finished OPT passes. (There is nothing left to do.)
Using template \$_DLATCH_N_ for cells of type $_DLATCH_N_.
No more expansions possible.
<suppressed ~4 debug messages>

22.42. Executing ABC9 pass.

22.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.3. Executing PROC pass (convert processes to netlists).

22.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31267'.
Cleaned up 1 empty switch.

22.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31268 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.3.4. Executing PROC_INIT pass (extract init attributes).

22.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31268'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31266_EN[3:0]$31274
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31266_DATA[3:0]$31272
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31266_ADDR[3:0]$31273
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31267'.

22.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31262_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31257_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31261_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31252_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31265_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31260_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31251_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31259_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31255_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31254_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31250_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31263_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31258_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31253_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31264_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31256_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31266_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31268'.
  created $dff cell `$procdff$31318' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31266_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31268'.
  created $dff cell `$procdff$31319' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31266_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31268'.
  created $dff cell `$procdff$31320' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31267'.
  created direct connection (no actual register cell created).

22.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31292'.
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31268'.
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31267'.
Cleaned up 1 empty switch.

22.42.3.12. Executing OPT_EXPR pass (perform const folding).

22.42.4. Executing PROC pass (convert processes to netlists).

22.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31338'.
Cleaned up 1 empty switch.

22.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31339 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.4.4. Executing PROC_INIT pass (extract init attributes).

22.42.4.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31339'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31337_EN[3:0]$31343
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31337_DATA[3:0]$31344
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31337_ADDR[3:0]$31345
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31338'.

22.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31335_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31330_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31334_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31325_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31329_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31333_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31324_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31332_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31327_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31323_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31322_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31321_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31336_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31331_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31326_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31328_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31337_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31339'.
  created $dff cell `$procdff$31389' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31337_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31339'.
  created $dff cell `$procdff$31390' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31337_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31339'.
  created $dff cell `$procdff$31391' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31338'.
  created direct connection (no actual register cell created).

22.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31363'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31339'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31338'.
Cleaned up 1 empty switch.

22.42.4.12. Executing OPT_EXPR pass (perform const folding).

22.42.5. Executing PROC pass (convert processes to netlists).

22.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31409'.
Cleaned up 1 empty switch.

22.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31410 in module $paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.5.4. Executing PROC_INIT pass (extract init attributes).

22.42.5.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
Creating decoders for process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31410'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31408_EN[3:0]$31415
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31408_DATA[3:0]$31414
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31408_ADDR[3:0]$31416
Creating decoders for process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31409'.

22.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.\i' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31399_EN' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31393_EN' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31404_EN' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31398_EN' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31392_EN' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31403_EN' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31402_EN' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31397_EN' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31407_EN' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31396_EN' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31406_EN' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31394_EN' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31395_EN' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31401_EN' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31400_EN' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31405_EN' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31408_DATA' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31410'.
  created $dff cell `$procdff$31460' with positive edge clock.
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31408_EN' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31410'.
  created $dff cell `$procdff$31461' with positive edge clock.
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31408_ADDR' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31410'.
  created $dff cell `$procdff$31462' with positive edge clock.
Creating register for signal `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.\muxwre' using process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31409'.
  created direct connection (no actual register cell created).

22.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31434'.
Found and cleaned up 1 empty switch in `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31410'.
Removing empty process `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31409'.
Cleaned up 1 empty switch.

22.42.5.12. Executing OPT_EXPR pass (perform const folding).

22.42.6. Executing PROC pass (convert processes to netlists).

22.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31480'.
Cleaned up 1 empty switch.

22.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31481 in module $paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.6.4. Executing PROC_INIT pass (extract init attributes).

22.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
Creating decoders for process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31481'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31479_EN[3:0]$31486
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31479_DATA[3:0]$31487
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31479_ADDR[3:0]$31485
Creating decoders for process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31480'.

22.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.\i' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31463_EN' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31469_EN' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31470_EN' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31465_EN' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31478_EN' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31473_EN' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31472_EN' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31467_EN' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31477_EN' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31466_EN' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31476_EN' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31475_EN' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31471_EN' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31474_EN' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31468_EN' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31464_EN' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31479_ADDR' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31481'.
  created $dff cell `$procdff$31531' with positive edge clock.
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31479_EN' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31481'.
  created $dff cell `$procdff$31532' with positive edge clock.
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31479_DATA' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31481'.
  created $dff cell `$procdff$31533' with positive edge clock.
Creating register for signal `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.\muxwre' using process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31480'.
  created direct connection (no actual register cell created).

22.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31505'.
Found and cleaned up 1 empty switch in `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31481'.
Removing empty process `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31480'.
Cleaned up 1 empty switch.

22.42.6.12. Executing OPT_EXPR pass (perform const folding).

22.42.7. Executing PROC pass (convert processes to netlists).

22.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31551'.
Cleaned up 1 empty switch.

22.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31552 in module $paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.7.4. Executing PROC_INIT pass (extract init attributes).

22.42.7.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
Creating decoders for process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31552'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31550_EN[3:0]$31556
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31550_DATA[3:0]$31557
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31550_ADDR[3:0]$31558
Creating decoders for process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31551'.

22.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.\i' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31534_EN' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31549_EN' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31548_EN' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31543_EN' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31542_EN' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31537_EN' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31547_EN' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31536_EN' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31546_EN' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31545_EN' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31541_EN' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31540_EN' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31539_EN' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31535_EN' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31544_EN' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31538_EN' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31550_EN' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31552'.
  created $dff cell `$procdff$31602' with positive edge clock.
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31550_DATA' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31552'.
  created $dff cell `$procdff$31603' with positive edge clock.
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31550_ADDR' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31552'.
  created $dff cell `$procdff$31604' with positive edge clock.
Creating register for signal `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.\muxwre' using process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31551'.
  created direct connection (no actual register cell created).

22.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31576'.
Found and cleaned up 1 empty switch in `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31552'.
Removing empty process `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31551'.
Cleaned up 1 empty switch.

22.42.7.12. Executing OPT_EXPR pass (perform const folding).

22.42.8. Executing PROC pass (convert processes to netlists).

22.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31622'.
Cleaned up 1 empty switch.

22.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31623 in module $paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.8.4. Executing PROC_INIT pass (extract init attributes).

22.42.8.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.8.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
Creating decoders for process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31623'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31621_EN[3:0]$31627
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31621_DATA[3:0]$31628
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31621_ADDR[3:0]$31629
Creating decoders for process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31622'.

22.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.\i' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31619_EN' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31618_EN' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31613_EN' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31612_EN' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31607_EN' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31617_EN' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31606_EN' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31616_EN' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31615_EN' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31611_EN' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31610_EN' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31609_EN' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31605_EN' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31620_EN' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31614_EN' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31608_EN' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31621_EN' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31623'.
  created $dff cell `$procdff$31673' with positive edge clock.
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31621_DATA' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31623'.
  created $dff cell `$procdff$31674' with positive edge clock.
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31621_ADDR' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31623'.
  created $dff cell `$procdff$31675' with positive edge clock.
Creating register for signal `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.\muxwre' using process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31622'.
  created direct connection (no actual register cell created).

22.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31647'.
Found and cleaned up 1 empty switch in `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31623'.
Removing empty process `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31622'.
Cleaned up 1 empty switch.

22.42.8.12. Executing OPT_EXPR pass (perform const folding).

22.42.9. Executing PROC pass (convert processes to netlists).

22.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31693'.
Cleaned up 1 empty switch.

22.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31694 in module $paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.9.4. Executing PROC_INIT pass (extract init attributes).

22.42.9.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.9.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
Creating decoders for process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31694'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31692_EN[3:0]$31698
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31692_DATA[3:0]$31699
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31692_ADDR[3:0]$31700
Creating decoders for process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31693'.

22.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.\i' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31689_EN' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31688_EN' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31683_EN' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31682_EN' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31677_EN' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31691_EN' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31687_EN' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31686_EN' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31685_EN' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31681_EN' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31680_EN' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31679_EN' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31690_EN' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31684_EN' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31678_EN' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31676_EN' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31692_EN' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31694'.
  created $dff cell `$procdff$31744' with positive edge clock.
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31692_DATA' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31694'.
  created $dff cell `$procdff$31745' with positive edge clock.
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31692_ADDR' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31694'.
  created $dff cell `$procdff$31746' with positive edge clock.
Creating register for signal `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.\muxwre' using process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31693'.
  created direct connection (no actual register cell created).

22.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31718'.
Found and cleaned up 1 empty switch in `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31694'.
Removing empty process `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31693'.
Cleaned up 1 empty switch.

22.42.9.12. Executing OPT_EXPR pass (perform const folding).

22.42.10. Executing PROC pass (convert processes to netlists).

22.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31764'.
Cleaned up 1 empty switch.

22.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31765 in module $paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.10.4. Executing PROC_INIT pass (extract init attributes).

22.42.10.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.10.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
Creating decoders for process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31765'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31763_EN[3:0]$31771
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31763_DATA[3:0]$31770
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31763_ADDR[3:0]$31769
Creating decoders for process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31764'.

22.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.\i' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31749_EN' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31750_EN' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31751_EN' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31755_EN' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31756_EN' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31757_EN' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31761_EN' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31762_EN' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31752_EN' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31753_EN' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31758_EN' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31759_EN' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31747_EN' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31760_EN' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31754_EN' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31748_EN' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31763_ADDR' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31765'.
  created $dff cell `$procdff$31815' with positive edge clock.
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31763_DATA' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31765'.
  created $dff cell `$procdff$31816' with positive edge clock.
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31763_EN' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31765'.
  created $dff cell `$procdff$31817' with positive edge clock.
Creating register for signal `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.\muxwre' using process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31764'.
  created direct connection (no actual register cell created).

22.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31789'.
Found and cleaned up 1 empty switch in `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31765'.
Removing empty process `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31764'.
Cleaned up 1 empty switch.

22.42.10.12. Executing OPT_EXPR pass (perform const folding).

22.42.11. Executing PROC pass (convert processes to netlists).

22.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31835'.
Cleaned up 1 empty switch.

22.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31836 in module $paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.11.4. Executing PROC_INIT pass (extract init attributes).

22.42.11.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.11.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
Creating decoders for process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31836'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31834_EN[3:0]$31842
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31834_DATA[3:0]$31841
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31834_ADDR[3:0]$31840
Creating decoders for process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31835'.

22.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.\i' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31818_EN' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31819_EN' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31820_EN' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31821_EN' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31825_EN' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31826_EN' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31827_EN' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31831_EN' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31832_EN' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31822_EN' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31833_EN' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31823_EN' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31828_EN' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31829_EN' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31830_EN' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31824_EN' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31834_ADDR' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31836'.
  created $dff cell `$procdff$31886' with positive edge clock.
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31834_DATA' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31836'.
  created $dff cell `$procdff$31887' with positive edge clock.
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31834_EN' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31836'.
  created $dff cell `$procdff$31888' with positive edge clock.
Creating register for signal `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.\muxwre' using process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31835'.
  created direct connection (no actual register cell created).

22.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31860'.
Found and cleaned up 1 empty switch in `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31836'.
Removing empty process `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31835'.
Cleaned up 1 empty switch.

22.42.11.12. Executing OPT_EXPR pass (perform const folding).

22.42.12. Executing PROC pass (convert processes to netlists).

22.42.12.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31906'.
Cleaned up 1 empty switch.

22.42.12.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31907 in module $paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

22.42.12.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

22.42.12.4. Executing PROC_INIT pass (extract init attributes).

22.42.12.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.12.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

22.42.12.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
Creating decoders for process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31907'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31905_EN[3:0]$31912
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31905_DATA[3:0]$31911
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31905_ADDR[3:0]$31913
Creating decoders for process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31906'.

22.42.12.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.12.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.\i' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31900_EN' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31894_EN' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31889_EN' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31890_EN' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31891_EN' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31895_EN' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31896_EN' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31897_EN' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31901_EN' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31902_EN' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31892_EN' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31903_EN' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31893_EN' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31898_EN' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31899_EN' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$31904_EN' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31905_DATA' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31907'.
  created $dff cell `$procdff$31957' with positive edge clock.
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31905_EN' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31907'.
  created $dff cell `$procdff$31958' with positive edge clock.
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$31905_ADDR' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31907'.
  created $dff cell `$procdff$31959' with positive edge clock.
Creating register for signal `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.\muxwre' using process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31906'.
  created direct connection (no actual register cell created).

22.42.12.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.12.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$31931'.
Found and cleaned up 1 empty switch in `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$31907'.
Removing empty process `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$31906'.
Cleaned up 1 empty switch.

22.42.12.12. Executing OPT_EXPR pass (perform const folding).

22.42.13. Executing SCC pass (detecting logic loops).
Found an SCC: $techmap$auto$ff.cc:266:slice$15755.$auto$simplemap.cc:267:simplemap_mux$31165
Found an SCC: $techmap$auto$ff.cc:266:slice$15754.$auto$simplemap.cc:267:simplemap_mux$31165
Found an SCC: $techmap$auto$ff.cc:266:slice$15753.$auto$simplemap.cc:267:simplemap_mux$31165
Found an SCC: $techmap$auto$ff.cc:266:slice$15752.$auto$simplemap.cc:267:simplemap_mux$31165
Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$30171 $auto$ff.cc:266:slice$12001 $auto$simplemap.cc:126:simplemap_reduce$12118 $auto$simplemap.cc:126:simplemap_reduce$12133 $auto$ff.cc:266:slice$12000 $auto$ff.cc:266:slice$11999 $auto$simplemap.cc:75:simplemap_bitop$23632 $auto$simplemap.cc:196:simplemap_lognot$12137 $auto$simplemap.cc:126:simplemap_reduce$12135 $auto$simplemap.cc:126:simplemap_reduce$12132 $auto$simplemap.cc:126:simplemap_reduce$23625 $auto$simplemap.cc:126:simplemap_reduce$23623 $auto$opt_expr.cc:613:replace_const_cells$30173 $auto$simplemap.cc:267:simplemap_mux$23636 $auto$simplemap.cc:126:simplemap_reduce$23629 $auto$simplemap.cc:126:simplemap_reduce$23627 $auto$simplemap.cc:75:simplemap_bitop$23634 $auto$opt_expr.cc:613:replace_const_cells$30147 $auto$simplemap.cc:225:simplemap_logbin$12107 $auto$simplemap.cc:196:simplemap_lognot$12122 $auto$simplemap.cc:126:simplemap_reduce$12120 $auto$simplemap.cc:126:simplemap_reduce$12117 $auto$opt_expr.cc:613:replace_const_cells$30395 $auto$ff.cc:266:slice$11998 $auto$simplemap.cc:126:simplemap_reduce$6584 $auto$simplemap.cc:126:simplemap_reduce$6582 $auto$simplemap.cc:225:simplemap_logbin$12084 $auto$simplemap.cc:196:simplemap_lognot$12094 $auto$simplemap.cc:126:simplemap_reduce$12092 $auto$opt_expr.cc:613:replace_const_cells$30169 $auto$simplemap.cc:267:simplemap_mux$23637
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$11266 $auto$simplemap.cc:38:simplemap_not$19122 $auto$alumacc.cc:485:replace_alu$3753.slice[0].ccu2c_i $auto$ff.cc:266:slice$11294 $auto$ff.cc:479:convert_ce_over_srst$30435 $auto$simplemap.cc:38:simplemap_not$19125 $auto$ff.cc:266:slice$11297 $auto$ff.cc:479:convert_ce_over_srst$30441 $auto$simplemap.cc:38:simplemap_not$23410 $auto$ff.cc:266:slice$11299 $auto$ff.cc:479:convert_ce_over_srst$30445 $auto$simplemap.cc:126:simplemap_reduce$11410 $auto$ff.cc:266:slice$11298 $auto$ff.cc:479:convert_ce_over_srst$30443 $auto$simplemap.cc:126:simplemap_reduce$11409 $auto$simplemap.cc:38:simplemap_not$11435 $auto$alumacc.cc:485:replace_alu$3753.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$3753.slice[2].ccu2c_i $auto$ff.cc:266:slice$11296 $auto$ff.cc:479:convert_ce_over_srst$30439 $auto$simplemap.cc:126:simplemap_reduce$11237 $auto$simplemap.cc:126:simplemap_reduce$11248 $auto$simplemap.cc:126:simplemap_reduce$11269 $auto$simplemap.cc:126:simplemap_reduce$11267 $auto$simplemap.cc:38:simplemap_not$11400 $auto$simplemap.cc:75:simplemap_bitop$11397 $auto$simplemap.cc:126:simplemap_reduce$11414 $auto$simplemap.cc:126:simplemap_reduce$11412 $auto$simplemap.cc:126:simplemap_reduce$11408 $auto$simplemap.cc:38:simplemap_not$19123 $auto$ff.cc:266:slice$11295 $auto$ff.cc:479:convert_ce_over_srst$30437 $auto$simplemap.cc:126:simplemap_reduce$11250
Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$30311 $auto$ff.cc:266:slice$11869 $auto$simplemap.cc:38:simplemap_not$23617 $auto$ff.cc:266:slice$11867 $auto$simplemap.cc:38:simplemap_not$23615 $auto$ff.cc:266:slice$11865 $auto$ff.cc:266:slice$11863 $auto$simplemap.cc:126:simplemap_reduce$11979 $auto$opt_expr.cc:613:replace_const_cells$30391 $auto$simplemap.cc:126:simplemap_reduce$11951 $auto$ff.cc:266:slice$11862 $auto$simplemap.cc:126:simplemap_reduce$11956 $auto$simplemap.cc:126:simplemap_reduce$11952 $auto$opt_expr.cc:613:replace_const_cells$30313 $auto$simplemap.cc:126:simplemap_reduce$11984 $auto$simplemap.cc:126:simplemap_reduce$11980 $auto$ff.cc:266:slice$11864 $auto$simplemap.cc:126:simplemap_reduce$11953 $auto$simplemap.cc:126:simplemap_reduce$11981 $auto$simplemap.cc:38:simplemap_not$23616 $auto$ff.cc:266:slice$11866 $auto$simplemap.cc:126:simplemap_reduce$11959 $auto$simplemap.cc:126:simplemap_reduce$11957 $auto$simplemap.cc:126:simplemap_reduce$11954 $auto$simplemap.cc:126:simplemap_reduce$11987 $auto$simplemap.cc:126:simplemap_reduce$11985 $auto$simplemap.cc:126:simplemap_reduce$11982 $auto$opt_expr.cc:613:replace_const_cells$30309 $auto$ff.cc:266:slice$11868 $auto$simplemap.cc:225:simplemap_logbin$11936 $auto$simplemap.cc:196:simplemap_lognot$11963 $auto$simplemap.cc:126:simplemap_reduce$11961 $auto$simplemap.cc:196:simplemap_lognot$11991 $auto$simplemap.cc:126:simplemap_reduce$11989 $auto$ff.cc:266:slice$11870 $auto$simplemap.cc:167:logic_reduce$11642 $auto$simplemap.cc:225:simplemap_logbin$11935
Found an SCC: $auto$ff.cc:266:slice$12010 $auto$opt_expr.cc:613:replace_const_cells$30167 $auto$ff.cc:266:slice$12009 $auto$simplemap.cc:126:simplemap_reduce$12155 $auto$opt_expr.cc:613:replace_const_cells$30165 $auto$ff.cc:266:slice$12008 $auto$ff.cc:266:slice$12007 $auto$simplemap.cc:126:simplemap_reduce$12158 $auto$simplemap.cc:126:simplemap_reduce$12154 $auto$opt_expr.cc:613:replace_const_cells$30163 $auto$ff.cc:266:slice$12006 $auto$opt_expr.cc:613:replace_const_cells$30161 $auto$ff.cc:266:slice$12005 $auto$simplemap.cc:126:simplemap_reduce$12153 $auto$ff.cc:266:slice$12004 $auto$ff.cc:266:slice$12003 $auto$simplemap.cc:126:simplemap_reduce$12160 $auto$simplemap.cc:126:simplemap_reduce$12157 $auto$simplemap.cc:126:simplemap_reduce$12152 $auto$simplemap.cc:38:simplemap_not$23972 $auto$ff.cc:266:slice$12002 $auto$simplemap.cc:167:logic_reduce$11402 $auto$simplemap.cc:196:simplemap_lognot$12164 $auto$simplemap.cc:126:simplemap_reduce$12162
Found 8 SCCs in module top.
Found 8 SCCs.

22.42.14. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.15. Executing PROC pass (convert processes to netlists).

22.42.15.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

22.42.15.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

22.42.15.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

22.42.15.4. Executing PROC_INIT pass (extract init attributes).

22.42.15.5. Executing PROC_ARST pass (detect async resets in processes).

22.42.15.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

22.42.15.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

22.42.15.8. Executing PROC_DLATCH pass (convert process syncs to latches).

22.42.15.9. Executing PROC_DFF pass (convert process syncs to FFs).

22.42.15.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

22.42.15.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

22.42.15.12. Executing OPT_EXPR pass (perform const folding).

22.42.16. Executing TECHMAP pass (map to technology primitives).

22.42.16.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

22.42.16.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~180 debug messages>

22.42.17. Executing OPT pass (performing simple optimizations).

22.42.17.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.
Optimizing module $paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.
Optimizing module $paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.
Optimizing module $paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.
Optimizing module $paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.
Optimizing module $paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.
Optimizing module $paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.
Optimizing module $paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.

22.42.17.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

22.42.17.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.42.17.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.
Performed a total of 0 changes.

22.42.17.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

22.42.17.6. Executing OPT_DFF pass (perform DFF optimizations).

22.42.17.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4..

22.42.17.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.
Optimizing module $paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.
Optimizing module $paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.
Optimizing module $paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.
Optimizing module $paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.
Optimizing module $paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.

22.42.17.9. Finished OPT passes. (There is nothing left to do.)

22.42.18. Executing TECHMAP pass (map to technology primitives).

22.42.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

22.42.18.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4 for cells of type $paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.
Using template $paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4 for cells of type $paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.
Using template $paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4 for cells of type $paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.
Using template $paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4 for cells of type $paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.
Using template $paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4 for cells of type $paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.
Using template $paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4 for cells of type $paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.
Using template $paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4 for cells of type $paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.
Using template $paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4 for cells of type $paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~1086 debug messages>

22.42.19. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

22.42.20. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

22.42.21. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.22. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

22.42.23. Executing TECHMAP pass (map to technology primitives).

22.42.23.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

22.42.23.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $and.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~219 debug messages>

22.42.24. Executing OPT pass (performing simple optimizations).

22.42.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~18 debug messages>

22.42.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

22.42.24.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.42.24.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.42.24.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.42.24.6. Executing OPT_DFF pass (perform DFF optimizations).

22.42.24.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

22.42.24.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.42.24.9. Rerunning OPT passes. (Maybe there is more to do..)

22.42.24.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

22.42.24.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

22.42.24.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

22.42.24.13. Executing OPT_DFF pass (perform DFF optimizations).

22.42.24.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

22.42.24.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

22.42.24.16. Finished OPT passes. (There is nothing left to do.)

22.42.25. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

22.42.26. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 7673 cells with 49247 new cells, skipped 4422 cells.
  replaced 3 cell types:
    1488 $_OR_
      86 $_XOR_
    6099 $_MUX_
  not replaced 27 cell types:
      30 $scopeinfo
     359 $_NOT_
    1094 $_AND_
       6 $_TBUF_
     711 TRELLIS_FF
    1042 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
      73 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
       1 $paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4
       1 $paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4
    1042 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
      24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4
      24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4
       1 $paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4
       1 $paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4
       1 $paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4
       1 $paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4
       1 $paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4
       1 $paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4_$abc9_byp
       1 $__ABC9_SCC_BREAKER

22.42.26.1. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.26.2. Executing ABC9_OPS pass (helper functions for ABC9).

22.42.26.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 21137 AND gates and 60796 wires from module `top' to a netlist network with 5024 inputs and 754 outputs.

22.42.26.4. Executing ABC9_EXE pass (technology mapping using ABC9).

22.42.26.5. Executing ABC9.
read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1317.090 ; gain = 0.023 ; free physical = 9538 ; free virtual = 28640
# read_verilog ../../debug/reset.v
# read_verilog ../../src/core/alu_control.v
# read_verilog ../../src/core/alu.v
# read_verilog ../../src/core/control_unit.v
# read_verilog ../../src/core/core.v
# read_verilog ../../src/core/immediate_generator.v
# read_verilog ../../src/core/mux.v
# read_verilog ../../src/core/pc.v
# read_verilog ../../src/core/registers.v
# read_verilog ../../src/core/csr_unit.v
# read_verilog ../../src/peripheral/bus.v
# read_verilog ../../src/peripheral/gpio.v
# read_verilog ../../src/peripheral/gpios.v
# read_verilog ../../src/peripheral/leds.v
# read_verilog ../../src/peripheral/memory.v
# read_verilog ../../src/peripheral/soc.v
# read_verilog ../../src/peripheral/uart_rx.v
# read_verilog ../../src/peripheral/uart_tx.v
# read_verilog ../../src/peripheral/uart.v
# read_verilog ../../src/peripheral/fifo.v
# read_xdc "digilent_nexys4_ddr.xdc"
# set_property PROCESSING_ORDER EARLY [get_files digilent_nexys4_ddr.xdc]
# synth_design -top "top" -part "xc7a100tcsg324-1"
Command: synth_design -top top -part xc7a100tcsg324-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   5024/    754  and =   19261  lev =   57 (4.75)  mem = 0.52 MB  box = 1147  bb = 1074
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   5024/    754  and =   24448  lev =   64 (4.31)  mem = 0.58 MB  ch = 2337  box = 1147  bb = 1074
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   60. Obj =  140. Set =  636. CutMin = no
ABC: Node =   24448.  Ch =  1683.  Total mem =    6.54 MB. Peak cut mem =    0.28 MB.
ABC: P:  Del = 7935.00.  Ar =   18962.0.  Edge =    24708.  Cut =   249728.  T =     0.06 sec
ABC: P:  Del = 7913.00.  Ar =   19483.0.  Edge =    24953.  Cut =   245866.  T =     0.07 sec
ABC: P:  Del = 7913.00.  Ar =   10165.0.  Edge =    22722.  Cut =   824012.  T =     0.20 sec
ABC: F:  Del = 7913.00.  Ar =    7763.0.  Edge =    20565.  Cut =   655534.  T =     0.18 sec
ABC: A:  Del = 7913.00.  Ar =    6745.0.  Edge =    19137.  Cut =   591149.  T =     0.27 sec
ABC: A:  Del = 7913.00.  Ar =    6611.0.  Edge =    19047.  Cut =   663551.  T =     0.30 sec
ABC: Total time =     1.09 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   5024/    754  and =   15470  lev =   51 (5.29)  mem = 0.48 MB  box = 1147  bb = 1074
ABC: Mapping (K=7)  :  lut =   4719  edge =   18910  lev =   16 (2.55)  levB =   28  mem = 0.24 MB
ABC: LUT = 4719 : 2=377 8.0 %  3=484 10.3 %  4=2900 61.5 %  5=753 16.0 %  6=96 2.0 %  7=109 2.3 %  Ave = 4.01
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 8.92 seconds, total: 8.92 seconds

22.42.26.6. Executing AIGER frontend.
<suppressed ~11568 debug messages>
Removed 20603 unused cells and 44662 unused wires.

22.42.26.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     4742
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:     1042
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:       73
ABC RESULTS:   $paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells:       24
ABC RESULTS:   $paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:           input signals:     1122
ABC RESULTS:          output signals:      124
Removing temp directory.

22.42.27. Executing TECHMAP pass (map to technology primitives).

22.42.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

22.42.27.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4 for cells of type $paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4.
Using template $paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4 for cells of type $paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4.
Using template $paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4 for cells of type $paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4.
Using template $paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4 for cells of type $paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4.
Using template $paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4 for cells of type $paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4.
Using template $paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4 for cells of type $paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4.
Using template $paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4 for cells of type $paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4.
Using template $paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4 for cells of type $paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001010 for cells of type $__ABC9_SCC_BREAKER.
Using template $paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$5c731b2a056f393e088f0032953d0a19e895af98\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$a0a5c207553f055956aaa26e51b3d694893d734d\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$f8437374bd105e0c86ce0e0a7670c672b32def86\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$ff7de821fd1e8e6caa4d413125d51e803515a4d8\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$ea2658816081785f02c1b6c25430c4c9a3816560\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$1c437089bb5c538491173e182c3e3402916f7e9d\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$3b66c05867c20deaa7ac6eb80b4158cde6cdae81\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$baebf483574bfbad6378a81a3e372f88364f01de\TRELLIS_DPR16X4_$abc9_byp.
No more expansions possible.
<suppressed ~2259 debug messages>
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 1105264
Removed 176 unused cells and 75506 unused wires.

22.43. Executing TECHMAP pass (map to technology primitives).

22.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

22.43.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$ccd3e15dc00d71b9284dff48e88ccef5be7362c8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$2844c7fef2a755a9af80c70990cd830291c4b71c\$lut for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut.
Using template $paramod$b035762d6265eb7c924c8c10d28889d1029384d1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
Using template $paramod$c8f2b00a2feb859040935d06cafa51f6c4e20e0d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut.
Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0\$lut for cells of type $lut.
Using template $paramod$4e45a60feb8bbe3cabd280417c9ffbefad6f6ef3\$lut for cells of type $lut.
Using template $paramod$8e1c82b304528085a78e4651c993ce9e1ef6b8a8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$d315acbf930db7c20b3f4ac2dad3b7982b1f437c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$b5a47d8cbfa131ec0581330a805a294b896377f4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011011 for cells of type $lut.
Using template $paramod$b54212ffe53be6d04a3c54f8fd1e79d56170af8e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut.
Using template $paramod$e8e38e13ba4ca36ee2f40f244789338dfa28acd1\$lut for cells of type $lut.
Using template $paramod$6a3d1b4c6389888034ca851571f0d03f46d1c4e9\$lut for cells of type $lut.
Using template $paramod$a8b7516c4ccadf4ab65906113028f2819d14ea8b\$lut for cells of type $lut.
Using template $paramod$a743caf801766df40bcc22d49baa12a0bdc2f7fe\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111101 for cells of type $lut.
Using template $paramod$774a669204184147b38453b69c15da44a7cf748f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$e2d4399e1e149b2bd3c04b32fc0d847bb8cdd6d6\$lut for cells of type $lut.
Using template $paramod$fbffc3e42b3faa1e0f4cad085b43900c06168af5\$lut for cells of type $lut.
Using template $paramod$1c9926eeb87db621086d9a82e994686a1d2e4a2b\$lut for cells of type $lut.
Using template $paramod$fbc305206fd1e383535be52fe61aee50a48c6397\$lut for cells of type $lut.
Using template $paramod$c78b629ab7f81eac7af8758481352cb811c66fac\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$d968e199ea396ec1669d272dadc967f3acfb80d5\$lut for cells of type $lut.
Using template $paramod$183ec76ed3429a430a8be24b57f3de734985f568\$lut for cells of type $lut.
Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut.
Using template $paramod$fffd8c8a2c16d3e719d9c28e2fe86b8433c3091c\$lut for cells of type $lut.
Using template $paramod$e273fa8cae278cec2f8890909f5331d722e1d2cc\$lut for cells of type $lut.
Using template $paramod$bd57e9718a938c253993cb582d13218a9bcdcc54\$lut for cells of type $lut.
Using template $paramod$fca14a1dc90f256210b24dfb42a9d98daf2b7e68\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$00637d70c3cdf03077bfcd9cc6ec5cac28c87d45\$lut for cells of type $lut.
Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc\$lut for cells of type $lut.
Using template $paramod$df54d578e56702ff6bf2a8f3257b6cfc59435f68\$lut for cells of type $lut.
Using template $paramod$853b4c6d2cbefecad1316f73097bd72762fc43dd\$lut for cells of type $lut.
Using template $paramod$ff540cdcb1a0e1f176a1c4dafcf1a33c5c4a026c\$lut for cells of type $lut.
Using template $paramod$5b4991ef8e215d9f18839630c2afa21273bf9421\$lut for cells of type $lut.
Using template $paramod$547ac4d3aa2d0cc2dd61462e70e48b5e3e336609\$lut for cells of type $lut.
Using template $paramod$468e8bd0c20446047d0d5956656a4bdfde36073f\$lut for cells of type $lut.
Using template $paramod$3ceaaffe10e9f5053ae0fa08a67977d5e6337e7a\$lut for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
Using template $paramod$d2ed484609b6b9eae8a69e216265a51e59f810ae\$lut for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut.
Using template $paramod$6ad88d74f0135f34d71ee5d3e40f304050043498\$lut for cells of type $lut.
Using template $paramod$b7712ad66490a50bf0f0eb1278d478652991d6c1\$lut for cells of type $lut.
Using template $paramod$a238bb199d4b53d4c976c9e68dafcfe86b19f40f\$lut for cells of type $lut.
Using template $paramod$b6d7b8802225d3fe3444a1b7fbd727be1d62f151\$lut for cells of type $lut.
Using template $paramod$02dce938b008608a8f0ca601bb5c1f6b094d99a4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$4d0440a90e55befc55639569976d9facbb4a73c8\$lut for cells of type $lut.
Using template $paramod$9d6f10107f18c4024325f1d95de2e1922b695700\$lut for cells of type $lut.
Using template $paramod$73d9bdcd8cfe64710d3bac0728468506f2302ae3\$lut for cells of type $lut.
Using template $paramod$60f14f86984aa1917b846e5bfccd508e60b6049d\$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod$b137f1af03021d8e43ba5925f93bf7dbd3b27f3f\$lut for cells of type $lut.
Using template $paramod$751deec16797ad636614056fbec0999890f52913\$lut for cells of type $lut.
Using template $paramod$9f37a8bc96eb243b0046a932d032199006c99597\$lut for cells of type $lut.
Using template $paramod$942376ab850c06b9fdc78db2f8e7c3790c5011dd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$4e549bd83d017aa5bcca14a32d293e8afc3c4e05\$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$bce98cbc4c7663d9534fcdf870483176065e0cfd\$lut for cells of type $lut.
Using template $paramod$40125d98d5dd1c96fe1b8cf5dfc7d17c8a5c0470\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod$f5c118b1371bfc24986fe89a9f3e936c05edfbc3\$lut for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod$12d55b60f0f4993cdeef74f2f65f385722841c5f\$lut for cells of type $lut.
Using template $paramod$63114da772fb28945ba24699e32f1e30ca7142f4\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod$f85e321f2b86ef38fb19961b529f607b1b7a7821\$lut for cells of type $lut.
Using template $paramod$38400b76de2b00d7d5f8f09de118b82fd1b8be0a\$lut for cells of type $lut.
Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut.
Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut.
Using template $paramod$ad20fca3806784b4dd796f318b5f4e40828faf1e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$eb453e5c4284f97a8ffea70cb552841f9d2d6223\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101110 for cells of type $lut.
Using template $paramod$04d31c7c8aa4030e47dda8fff46f3040fcaf6fb1\$lut for cells of type $lut.
Using template $paramod$8fde361db764d5449ce4ce79a2c3fddf3d066835\$lut for cells of type $lut.
Using template $paramod$71d09d8354f5555fb54ab0bd4f3934a22c793990\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod$525425bfbe66d72ee88210d059d9a74f55ab8de8\$lut for cells of type $lut.
Using template $paramod$c43faee8d0b10c9386bf360b026af1afaa4197ce\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod$a5d5c745abad930299600272e8260a256cf53240\$lut for cells of type $lut.
Using template $paramod$cdedaeac136b0ddce26b73f942df5f4bec7d331c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$d3949f71f49fbc586e9767c35be678f9222e5866\$lut for cells of type $lut.
Using template $paramod$c0a4d9417755c1bd5ec9a311325000b8535d91ad\$lut for cells of type $lut.
Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa\$lut for cells of type $lut.
Using template $paramod$d3555d73c80f344ad155fd99dc6031e9a5df0a0e\$lut for cells of type $lut.
Using template $paramod$56d36648044d0bf0f892c2050a60c21ad090a3b1\$lut for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$8cac60f778d22518f85ff7609bd7e8781e91c16a\$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod$99a730676ae1842a22fdc62de11e7b85bdd11948\$lut for cells of type $lut.
Using template $paramod$70a934594406e8042bf2854c778fef542ef3ea5f\$lut for cells of type $lut.
Using template $paramod$44587907eb547902863ad65ee925d87164ab0cc4\$lut for cells of type $lut.
Using template $paramod$1f0d7e71f8fbcd9eac17bf5f4c1739e2f5a96cef\$lut for cells of type $lut.
Using template $paramod$5a2475f0ff8adfa6c48e46c1977dad3962daa33d\$lut for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod$8e2df60c6f844bb7122d00d18b4cc43e25eb4771\$lut for cells of type $lut.
Using template $paramod$2cd3e47a3853d83cfc6314213b691149112be3f0\$lut for cells of type $lut.
Using template $paramod$99a2a175d178a040bb1ffceb53184fb0f59423c6\$lut for cells of type $lut.
Using template $paramod$82d0a748bb4682cb8247d0526164208604e3778f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$b5c075da76f8fda4d6b19864023f74d16b7a396f\$lut for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
Using template $paramod$e484b1e0bd351ba5af34f5fd66a8e850cc5b8335\$lut for cells of type $lut.
Using template $paramod$8ac469b08ec304beefad090d643d1150a22311b3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod$160dd3fc13278bc3e9da8aa3a8b9af0ec5ca7e3b\$lut for cells of type $lut.
Using template $paramod$3c26f9ba8de51ae29a045f5aac83e1a22b1bb6f8\$lut for cells of type $lut.
Using template $paramod$dc8eb389b2fc3ec6a78d93ff9b548b7fd27b6950\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod$c20bb0ec9b7ffe048b440bc5b52865dca055e17d\$lut for cells of type $lut.
Using template $paramod$6e2b27a23561eba4d5d7a3612a01502854865858\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000111 for cells of type $lut.
Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut.
Using template $paramod$5810dc7df8ed24e679f53cf772dc7896a80666ec\$lut for cells of type $lut.
Using template $paramod$b2a4860cd839ff40d9dca4c3f237b2b534267028\$lut for cells of type $lut.
Using template $paramod$40779edd19227ce424efbc27bdb6a265d707da07\$lut for cells of type $lut.
Using template $paramod$01f4da2c0597603af76393d85a0bd280d860ce94\$lut for cells of type $lut.
Using template $paramod$7088e7e0937795cc8690a7d351156ede5489ace4\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$b45308ffeb4031bc5d55ef31b149afd94d3d7565\$lut for cells of type $lut.
Using template $paramod$65b95acb0049321eb44e2abe78fa768563e28257\$lut for cells of type $lut.
Using template $paramod$a499f32dff9f508f991dc2a1a6029889c8ff7f44\$lut for cells of type $lut.
Using template $paramod$bf2b86015a3f3344148f0badf38715701d4ac82a\$lut for cells of type $lut.
Using template $paramod$c22a370b0ac036786339c000f458c7a0a658e959\$lut for cells of type $lut.
Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut.
Using template $paramod$7eded28cf8cfe7a69014ba3ea568d667a5cb22d7\$lut for cells of type $lut.
Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut.
Using template $paramod$855b2c1d6931bc7ac39a5e8ecd8eb6e90ffc6baf\$lut for cells of type $lut.
Using template $paramod$8f57cd70abb82f54e0913f9a888c1eabb8bdef77\$lut for cells of type $lut.
Using template $paramod$78f5590b0462181d8749c9e6ed8a771b22dfb9ed\$lut for cells of type $lut.
Using template $paramod$f71bdbecf3a181fba36172fd8e7c491f36b1710d\$lut for cells of type $lut.
Using template $paramod$211c23e0dd3ef96aacd349fd2692766b2c495d83\$lut for cells of type $lut.
Using template $paramod$a7dad16c080c08c1647c7e1b9706a59a123d8bcd\$lut for cells of type $lut.
Using template $paramod$4504ecd5e67168fc3e20dff863a25c6da00af1ae\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$8921e608da57eb3483e6390a11938d2bd4d7314d\$lut for cells of type $lut.
Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e\$lut for cells of type $lut.
Using template $paramod$f52ac008435695f9b4157529669c6afa0327a863\$lut for cells of type $lut.
Using template $paramod$b9aa10638f8a6853e58a1987af7ebe46418cf502\$lut for cells of type $lut.
Using template $paramod$88617b825e7dd42cf332aa6987a1a3ddd108645d\$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$dad5b5b4f38c15cf8cf974a553cb73b5f43351be\$lut for cells of type $lut.
Using template $paramod$1ec3fb8fd1fa98216cb96b4422de32c4ba5f6c9c\$lut for cells of type $lut.
Using template $paramod$325e90edf97670f9dea57833ae1f51a5e8bcddea\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$9616fecedc1a6ce839b990a3156875e06908d6fa\$lut for cells of type $lut.
Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut.
Using template $paramod$d72cf91b35e890dddab14d1c7614248d16c97851\$lut for cells of type $lut.
Using template $paramod$d7a755ba2a0ea6c040238233a3d32f809b665959\$lut for cells of type $lut.
Using template $paramod$6c2255d628bb6d516c6ca9b30be6165c517de877\$lut for cells of type $lut.
Using template $paramod$ca0f677caa0bfae62a111b310b30c32db00b073a\$lut for cells of type $lut.
Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod$7e9df0afb32b76fe5fce0691b8752aca650057fa\$lut for cells of type $lut.
Using template $paramod$7048a04c957e98cf6b49be41c97d98bd337bf42f\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$e13d7fd7924338d91319fab7ac7b50907df26077\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut.
Using template $paramod$28f1f052daece0ac14809cddfcdfaa5151170630\$lut for cells of type $lut.
Using template $paramod$20235ca863361fbc253329cfc7eeea38c77404dc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod$43987c9cc87683fa7a6ecfc84dddb93414b52f9f\$lut for cells of type $lut.
Using template $paramod$4e79aa6839e287ee36e65fa83c13a532a028e9cd\$lut for cells of type $lut.
Using template $paramod$530e84e711d00ee94a04273b459e87c8d074784e\$lut for cells of type $lut.
Using template $paramod$7ed3d685a887e531dc8f4f21b9907d4766cf861f\$lut for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut.
Using template $paramod$1bf62ab10e48d71d6497bccacf5c70420c470fe9\$lut for cells of type $lut.
Using template $paramod$27dd7ea71d2126c74d85758e5a06b7f432d9242f\$lut for cells of type $lut.
Using template $paramod$6a9b42dd2737c91073e6a695b8ac858c4a8587d7\$lut for cells of type $lut.
Using template $paramod$8fd8efe0a495790cc9ddc97266933ea8a8cd7b45\$lut for cells of type $lut.
Using template $paramod$a197ef6f3b51d411ae3e5b42b5d77a606c4fb11a\$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod$32abbd1d449a67fb913b4733374e345d4c17175b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut.
Using template $paramod$22a17f102d8eb29f9e3f67afc5da9acc7c1e8867\$lut for cells of type $lut.
Using template $paramod$adc0b354bb960519a616db7423a6274fc380540e\$lut for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9\$lut for cells of type $lut.
Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d\$lut for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$6b7c9c56fc2a32a479d463d5f3b0d3f4673b67f1\$lut for cells of type $lut.
Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut.
Using template $paramod$6c51c1ba6c39f0c09b896d52432b366f116bd3c1\$lut for cells of type $lut.
Using template $paramod$bc1342afe293ee3056f1a0aaf81d9379dd048f93\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod$a467e3aee4b54a60cdec89714694957109e0405d\$lut for cells of type $lut.
Using template $paramod$e50929688d8319f8cd7bdd627065cd59d2e91fe4\$lut for cells of type $lut.
Using template $paramod$f921ab2c451d17e196d1dcad0b6d434881387fe3\$lut for cells of type $lut.
Using template $paramod$3fe6dd1a7a210428d5eebf0497b15782d1883a1c\$lut for cells of type $lut.
Using template $paramod$4fc6efaec5bd8994232500ce8f8be9cb357522d5\$lut for cells of type $lut.
Using template $paramod$fe1497207981e9e4f2f9556fad9970ec052e0a6d\$lut for cells of type $lut.
Using template $paramod$4b9b235bc4444ff899bef0c648e4109b26737f1a\$lut for cells of type $lut.
Using template $paramod$d68c955eab3e0ff857c6b60afe14ca397531beeb\$lut for cells of type $lut.
Using template $paramod$65608fa8414ca06f61126549fed316db1f6a4001\$lut for cells of type $lut.
Using template $paramod$f58f6342089d5f3741f49aff5afd6b381f3580ad\$lut for cells of type $lut.
Using template $paramod$47d363ae7b1a0e81207e02fe31af85b6bf36a2ac\$lut for cells of type $lut.
Using template $paramod$994d90e9e38bc4b3e41611c486bc42235dc97a88\$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
Using template $paramod$f2ffc9085000a0a9f052860f5ccb192550bf9aac\$lut for cells of type $lut.
Using template $paramod$5f767ed93dc5f60ee6253a19a32124874cb3810b\$lut for cells of type $lut.
Using template $paramod$6ae4b1e60c63ce9d50fe39399e50e2c0b298fef6\$lut for cells of type $lut.
Using template $paramod$15300569a8540f724c838cc8fb82cadd28c6445c\$lut for cells of type $lut.
Using template $paramod$7fbf9189133d4e370bfdef679f97ebc3fe0bafc3\$lut for cells of type $lut.
Using template $paramod$fa498f4ac811b5775c322b5582cff0d60ae230fc\$lut for cells of type $lut.
Using template $paramod$501e7e2dece807610b8069d140490ad4174b95a8\$lut for cells of type $lut.
Using template $paramod$a96c1b98643fd4029e7967e2dfdaed9f89b3206a\$lut for cells of type $lut.
Using template $paramod$dbf03f9eccb786ee607033e5b90c8420b122b313\$lut for cells of type $lut.
Using template $paramod$1a5a5af284e7741a4ed67d1292de91133d294c45\$lut for cells of type $lut.
Using template $paramod$35a75b6c1db87c052e13420f6e0df2626a52563b\$lut for cells of type $lut.
Using template $paramod$17fd36fab32bce162e5828682c2ba9fa7f9e273b\$lut for cells of type $lut.
Using template $paramod$21b051a1cf30565bddf1900c93a9b5e3135164a7\$lut for cells of type $lut.
Using template $paramod$21cf622a43652f7c2a2017f61c6a7d790323ce81\$lut for cells of type $lut.
Using template $paramod$6842b8b2a2a38d0fdb35de972b4ce1a464745b17\$lut for cells of type $lut.
Using template $paramod$1c35ff100221cf8df22783e59f5bd73bebf52503\$lut for cells of type $lut.
Using template $paramod$39b0d201a18bed5573a88835da3f39d40814d360\$lut for cells of type $lut.
Using template $paramod$75f001c2559d212d7f58a5b0a49f25624079d3ef\$lut for cells of type $lut.
Using template $paramod$13a79e008061312bbb4dd073f52bfcaecdaec07e\$lut for cells of type $lut.
Using template $paramod$9e7ec91b849e13d89526d4ce612349c0ca02923f\$lut for cells of type $lut.
Using template $paramod$afbb78ea2f898aa3cffa65de18f43b6b53d33ce1\$lut for cells of type $lut.
Using template $paramod$24f6bdbbc069cd3533a52f9c978362f343606a3f\$lut for cells of type $lut.
Using template $paramod$6b0fab1a5cdff684c789ff9c684d828e9b3724f7\$lut for cells of type $lut.
Using template $paramod$7cc1afc04a241da704913bc694e960a54ab8d7c6\$lut for cells of type $lut.
Using template $paramod$0edfe63d061bc717a1cd20d382f48b999bc3f27e\$lut for cells of type $lut.
Using template $paramod$a4feb7db8ce913743fc9979ff52d0c0d3ddae42f\$lut for cells of type $lut.
Using template $paramod$ebc32c2b992f8f00823342df5b8919dde94039a4\$lut for cells of type $lut.
Using template $paramod$fd7504563cde7d0333763cdd2a2bdf0dd0f519f5\$lut for cells of type $lut.
Using template $paramod$8408d7073feb8760bb451cec38155c5b0a91b73a\$lut for cells of type $lut.
Using template $paramod$fa12881e7c42da0c7fbd5910905796353751089f\$lut for cells of type $lut.
Using template $paramod$1489258aa56881caf389bc7722fe917dcf727df5\$lut for cells of type $lut.
Using template $paramod$f2173573d28df9e83416399b4aad8587656b198d\$lut for cells of type $lut.
Using template $paramod$ee5811a7c38f0719efe60f55170bda2acb58de2d\$lut for cells of type $lut.
Using template $paramod$d69fe5a3baeb3d745316fb203ab6bce0137446f5\$lut for cells of type $lut.
Using template $paramod$65e3cdffdbf5846733d136d6f12c36d5e13059c0\$lut for cells of type $lut.
Using template $paramod$fc54c3b3f3a688950d83b23a46c092569e4d1a4b\$lut for cells of type $lut.
Using template $paramod$9774287ee4bec7df1d0882830b1d28be77035739\$lut for cells of type $lut.
Using template $paramod$74e271e0476258c722e7fb10146fa20b8213228e\$lut for cells of type $lut.
Using template $paramod$4fa501cd0a07ec410036c870d96552048a629fd8\$lut for cells of type $lut.
Using template $paramod$6e74b06c5e082601a502a24c75f68b262adc561a\$lut for cells of type $lut.
Using template $paramod$84c5cfa8d7481774250caab0fcdd6d249a376a31\$lut for cells of type $lut.
Using template $paramod$54d424703c2fa972b619e205ee8b656e8dd47aff\$lut for cells of type $lut.
Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut.
Using template $paramod$e726932ef2104723d3173538a786627dc6bd00fc\$lut for cells of type $lut.
Using template $paramod$31085587500b160f3135709c707a07fdaca2d782\$lut for cells of type $lut.
Using template $paramod$f8b88fc957e49237bbde64233bd6772697408b68\$lut for cells of type $lut.
Using template $paramod$571895341b084d34c7674b4aaa647bcb4272d4c8\$lut for cells of type $lut.
Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut.
Using template $paramod$1f313f85ef575d13bac75382f04905a8c8be8f57\$lut for cells of type $lut.
Using template $paramod$448a15eb147ad7fc5ed2723fb6e90b076130bdf5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut.
Using template $paramod$35369ee2661bc6f22afa7fd33e082ebba93672ba\$lut for cells of type $lut.
Using template $paramod$4bf0340e251e6b71bc0d5237b346c714f1b8119e\$lut for cells of type $lut.
Using template $paramod$947a8e6f964f60e61a6869420b73b897b1f59f72\$lut for cells of type $lut.
Using template $paramod$7a0b348a7069d0c8f44afe945e212fcf3f3fd64c\$lut for cells of type $lut.
Using template $paramod$bf9847da478bb5fab013976cf5972c1f68938e75\$lut for cells of type $lut.
Using template $paramod$5c36433ce316d37fc714374c2687fa8a8cfa4401\$lut for cells of type $lut.
Using template $paramod$cf3f07fca30d3bb92c126c2e66613fb12c81ecaf\$lut for cells of type $lut.
Using template $paramod$f3df070764dae7ee77696534c08d6a2230a5382e\$lut for cells of type $lut.
Using template $paramod$2fc44403459b9c93ee79bcfa44dba4c147e1879c\$lut for cells of type $lut.
Using template $paramod$436f5b2a701f46b4f2c40432561ff700e1d0a2c0\$lut for cells of type $lut.
Using template $paramod$3f50c381f8e2dabe626c4b8244ce12715a21947b\$lut for cells of type $lut.
Using template $paramod$bdaf823c2b63b6abd253588435447f6d6dafd586\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut.
Using template $paramod$f61116fd244ee1f33e42c48ae129f92ee4ad28c8\$lut for cells of type $lut.
Using template $paramod$1e06da73d21c5736c1f943dd00fdcd4f80e36a2b\$lut for cells of type $lut.
Using template $paramod$d3101fffd1f543464a1471e231ea9e2bf342bad2\$lut for cells of type $lut.
Using template $paramod$db8d333bf66c0cdffe51960a4478272318cfbbaa\$lut for cells of type $lut.
Using template $paramod$c7b9ca2bf4242027cbf3d93fb05d3ccf8bfa3ff5\$lut for cells of type $lut.
Using template $paramod$b687dc07959af1fa40c448af298b5a8ef545da15\$lut for cells of type $lut.
Using template $paramod$f8f99e76d5eb42e4b0e5c3930bfa733030a45152\$lut for cells of type $lut.
Using template $paramod$24d195be68262e2b33f7c7f3ad21db2492be63ab\$lut for cells of type $lut.
Using template $paramod$14e18645d824a8e19665cb1b607087f81c0aa7b8\$lut for cells of type $lut.
Using template $paramod$5943312c2c9cc7002289f2d8a6de3ad15d3abbbf\$lut for cells of type $lut.
Using template $paramod$44653b150d5dba87f6cfb645dbff19555846d07b\$lut for cells of type $lut.
Using template $paramod$c4b144c076fc8daef9adb1c0838b188761e724bf\$lut for cells of type $lut.
Using template $paramod$2c3263ad1f10bf72ee6bbe18ed92fa5b6fc0712d\$lut for cells of type $lut.
Using template $paramod$885f4f7b242e0fcdfa371c8315554e9e8009ac8a\$lut for cells of type $lut.
Using template $paramod$55ca65da18487716ba545b1f9028508a119502b7\$lut for cells of type $lut.
Using template $paramod$6878f41bb48730ac65519506065fb579fc81027b\$lut for cells of type $lut.
Using template $paramod$64f775137f221003d6afef9b19fcf173652d9e6f\$lut for cells of type $lut.
Using template $paramod$43115cb697633548f9d11f44030fd8960185c3fc\$lut for cells of type $lut.
Using template $paramod$59601b4481617ef8784cc027d3c1241388c1c653\$lut for cells of type $lut.
Using template $paramod$3666188b96545248717c2ff7edce939f185fe6fd\$lut for cells of type $lut.
Using template $paramod$3b56205e0e57b3ea26d80fc7983017f83663129e\$lut for cells of type $lut.
Using template $paramod$6db128b57b176816471de0fd56661f7869eabcda\$lut for cells of type $lut.
Using template $paramod$c39b4ae3eed03ff4e0ef2a41844cc5ea3df00d09\$lut for cells of type $lut.
Using template $paramod$47edca613d9eb90e2795930f85867b0fade1106c\$lut for cells of type $lut.
Using template $paramod$381f164d59d1439a7e1e734610279d64c0da26bc\$lut for cells of type $lut.
Using template $paramod$1f575543d734f2d93dfcc8f91b30fb001334bb95\$lut for cells of type $lut.
Using template $paramod$adbb1dde6c987d24ce9039960a9f4e56a141c78d\$lut for cells of type $lut.
Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut.
Using template $paramod$128dd8c3ee41826b47901135f5d1d2853eb4fc46\$lut for cells of type $lut.
Using template $paramod$8f7210088a40da1859d27e900c288fd298d68bed\$lut for cells of type $lut.
Using template $paramod$2b0ce5b4bf178304118bffafd0cdbbec119b2f06\$lut for cells of type $lut.
Using template $paramod$8224c7cc969c7f7c729b95d57505eb7e317a4c58\$lut for cells of type $lut.
Using template $paramod$4cbfd08c43b7b566f8cacf146cdf1778e05f2146\$lut for cells of type $lut.
Using template $paramod$d637970ae6c46c1cba9f112484c464e534062158\$lut for cells of type $lut.
Using template $paramod$86516aee9076e81c690d9a97e194d6fd980be209\$lut for cells of type $lut.
Using template $paramod$7c22c0ff54eda33ab84fbc96f0339fee737d6b53\$lut for cells of type $lut.
Using template $paramod$2d6e782f20859d415206dee57a123977b65030e7\$lut for cells of type $lut.
Using template $paramod$1a3391880fc221cac0bcdde8051516d949194afc\$lut for cells of type $lut.
Using template $paramod$2d70e360329f2b83357618532825d0cf30a325f3\$lut for cells of type $lut.
Using template $paramod$9506ecf18c91672f3dae4008b6ad1f2863e8019f\$lut for cells of type $lut.
Using template $paramod$a6b2d4693fada6bebbe4480262641915d709d280\$lut for cells of type $lut.
Using template $paramod$9891217114ca63a6e9d48073351d843bb1d46faf\$lut for cells of type $lut.
Using template $paramod$719af4422c761e97bd80aaf9c487328fb461a794\$lut for cells of type $lut.
Using template $paramod$f03663c7f91be924d1e9df8220b895406b3f6489\$lut for cells of type $lut.
Using template $paramod$441303b76529b811f79601ae0eb6114c8c594cf6\$lut for cells of type $lut.
Using template $paramod$88d97b94a8e28d24f419d85f01311dd687ffbae1\$lut for cells of type $lut.
Using template $paramod$159d5d4cd736439a67ba8663ad5ab3d228971a8c\$lut for cells of type $lut.
Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514\$lut for cells of type $lut.
Using template $paramod$1dbc005c3ca46176ed5f71d3318762a2498d170f\$lut for cells of type $lut.
Using template $paramod$63c21a63caf7b85f1f888b02cf745b7d3944fb57\$lut for cells of type $lut.
Using template $paramod$cadf4d3900415ee5abcf02466089b05ee4925e73\$lut for cells of type $lut.
Using template $paramod$e7066900dd6943dd139cd3eda5e7eb3dcecb65f5\$lut for cells of type $lut.
Using template $paramod$da216d5db97812160cff47a7b1c65cd43181b2a8\$lut for cells of type $lut.
Using template $paramod$92b7f4fb4479656d40c1b7f466e9301a278108f9\$lut for cells of type $lut.
Using template $paramod$0e3a63073d9266614119b800b7973fa7b8c05e77\$lut for cells of type $lut.
Using template $paramod$6e424bd4a747f8421ac946af3d9bb3a47fd0b233\$lut for cells of type $lut.
Using template $paramod$37863fb1d4b5c54888fbc168d735eadc19f59fdc\$lut for cells of type $lut.
Using template $paramod$7bfa38089a0fb52216c55d64f8d2619ea5368d83\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut.
Using template $paramod$fb4ed309581bcd972f41afa8566ae8b9812c7f6c\$lut for cells of type $lut.
Using template $paramod$d6793064271224d82c97f89efa9c3f48c828279c\$lut for cells of type $lut.
Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut.
Using template $paramod$2ca5a8bf2a853a223fe0e0148e443d1b7e1e37b1\$lut for cells of type $lut.
Using template $paramod$53dd41daf9072d93a218e1188603796824515446\$lut for cells of type $lut.
Using template $paramod$0b41d7b6b9b2f46cddf0447103dfc5ad7dac33c8\$lut for cells of type $lut.
Using template $paramod$9585e87f489b89062dd3699fe9bdc43c492c02ad\$lut for cells of type $lut.
Using template $paramod$034da822afc198aa8f2acdee5006c43f0decb366\$lut for cells of type $lut.
Using template $paramod$886869b4c3ad4aa68b8e73073150184c057126a4\$lut for cells of type $lut.
Using template $paramod$8d08395e9a4e4cded27c9198dd6b7fb30a5dc6be\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$318e655f028abd6c26dfa0bd6ca4aae49ecd6bb2\$lut for cells of type $lut.
Using template $paramod$c63efa97e6cbc8132d15a22fbd0c7fc96068748a\$lut for cells of type $lut.
Using template $paramod$41b25c02685725ef8ad91ddeb097a869680781c4\$lut for cells of type $lut.
Using template $paramod$0331e7d31e2e97fc44400612e0a14e91e731b8a5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$9dd298ae76fb41ac94779a83c068607fbc09ce4f\$lut for cells of type $lut.
Using template $paramod$57400e123f0147f905d2ec980ae5b64230fc0a43\$lut for cells of type $lut.
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut.
Using template $paramod$1d0525724ac068b5dfb483a798d6d5f207b20d29\$lut for cells of type $lut.
Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707\$lut for cells of type $lut.
Using template $paramod$c24ed72ebb67e9ead6029e42e909ef7fc0abbb11\$lut for cells of type $lut.
Using template $paramod$abaf3d04c136502e97aa54b58bddbaeb3679a345\$lut for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$7b733f5b3466ec911060896fccc5c2626cbe3d64\$lut for cells of type $lut.
Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0\$lut for cells of type $lut.
Using template $paramod$9225a1e7171a31391d3103e59bac04fd4b7aa6c1\$lut for cells of type $lut.
Using template $paramod$de66710b4dfaed0c5cf83567ae8fcc82bbfa7728\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut.
Using template $paramod$7187575eba6b1b57c39e107c781a1d13e510a61d\$lut for cells of type $lut.
Using template $paramod$413d040dcd860cd74ca61a70644516a95d328ae7\$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod$6f6a7fb6482d3745a696e7ec281190b5f0109710\$lut for cells of type $lut.
Using template $paramod$fd6231c731505a9abfb7933d219ef11ad30f2c89\$lut for cells of type $lut.
Using template $paramod$7cef2c8af49f0e0719fb9a5ed02b1ac5d9028931\$lut for cells of type $lut.
Using template $paramod$150b198f7b6a79bb68022b4897e0b9e764b4ab9c\$lut for cells of type $lut.
Using template $paramod$cba7d4f63aea5e4b3faf052f9f9805e0c6d202cb\$lut for cells of type $lut.
Using template $paramod$92c3899764cd8074859d6a5a5b733cffe8a391b3\$lut for cells of type $lut.
Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut.
Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut.
Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542\$lut for cells of type $lut.
Using template $paramod$3db826965e677cc72a454d5e910d68e35d246aa3\$lut for cells of type $lut.
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$559093dfe5eebcaa0a5cc38a19142c025c6333c4\$lut for cells of type $lut.
Using template $paramod$8be603794459732f9a374f76041b510fc63b115b\$lut for cells of type $lut.
Using template $paramod$f546bd96bcec6e3bf1b78bdea64b0f5bbbaff6df\$lut for cells of type $lut.
Using template $paramod$f626b575273537b3090dbe5d04b27b283ec9a192\$lut for cells of type $lut.
Using template $paramod$7491e7206ae8c682d288373efe06a43b67c277cf\$lut for cells of type $lut.
Using template $paramod$83c1b6108170249166239e09804c5f4542556524\$lut for cells of type $lut.
Using template $paramod$f4c6fe0020190952fcd7d4a4d5f3ec5a8512a50b\$lut for cells of type $lut.
Using template $paramod$5f99aa1a31b4f0c356281a67e16706e1e689d29f\$lut for cells of type $lut.
Using template $paramod$98da953dac84989c1dec711ba4d909885d65c4dd\$lut for cells of type $lut.
Using template $paramod$f91324047f1b25655cac9c7893f566ed6d1799eb\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$608ec71714e59b284981fc95a842d59ca59e1670\$lut for cells of type $lut.
Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111011 for cells of type $lut.
Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut.
Using template $paramod$1578333f1a5078051b84dbcbad362e8087bf5284\$lut for cells of type $lut.
Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut.
Using template $paramod$f7a897257decedfb6cc642e53d65fef7fc0df390\$lut for cells of type $lut.
Using template $paramod$57cf7fbf84518d9e7604ec42b59ba9511e1f3caf\$lut for cells of type $lut.
Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut.
Using template $paramod$1632c1c0242796acfc963a05742c4acd2f475c4e\$lut for cells of type $lut.
Using template $paramod$651e836885d95717c36e69441422c3fe04ee5f4d\$lut for cells of type $lut.
Using template $paramod$965ebc19d8bda21d2aaa1dee7a7b1e0348b073dc\$lut for cells of type $lut.
Using template $paramod$30d3e44b2de0ce3e28cf704dc9e8bf83df47c673\$lut for cells of type $lut.
Using template $paramod$44c0fe996e6f3f4ba8bae2e194245aa82c30fa47\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010111 for cells of type $lut.
Using template $paramod$74c0f3179b5cebe485563ea55e9b637e7ee5c0c3\$lut for cells of type $lut.
Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut.
Using template $paramod$f405ee362848dd1a47c58160f854302f6ecf95ff\$lut for cells of type $lut.
Using template $paramod$8e3e9a427b2bc0e7d837447fde19028feb6ec6fc\$lut for cells of type $lut.
Using template $paramod$d9922e15eb5da1acc26e937540cc16b16c2ad42c\$lut for cells of type $lut.
Using template $paramod$6daa1f38743ddf86b54e83cbcf8003e7e7d78aa1\$lut for cells of type $lut.
Using template $paramod$adce9c89515a4e83641fc3471eb3c01ec7b082ff\$lut for cells of type $lut.
Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut.
Using template $paramod$f258f431a7c2fc52205873e71cd6683fdc689824\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut.
Using template $paramod$cfa9b4e81fcdacc04b992595156c2eac04dcd644\$lut for cells of type $lut.
Using template $paramod$4d256fbdc9e64053bf8437c1c851d487119b6909\$lut for cells of type $lut.
Using template $paramod$5877b7c16fde3cb88ae4b2db269772e62817d645\$lut for cells of type $lut.
Using template $paramod$03a9885a61e46980831d2c64059eb66aa27bbfee\$lut for cells of type $lut.
Using template $paramod$7855bb4a9085da42c58c827ab70bdd4df7d24dda\$lut for cells of type $lut.
Using template $paramod$9e9140c7caddc86f7208e1c68a8d2895acc25739\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$769bdbbde83614df0f4ab5f54e777ded51bb10ce\$lut for cells of type $lut.
Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a\$lut for cells of type $lut.
Using template $paramod$849d013d096d73269ca4beb768f8e399745d37f2\$lut for cells of type $lut.
Using template $paramod$0328e568d609989242dcb98a1c5328d4372a6e9c\$lut for cells of type $lut.
Using template $paramod$bd4a031e59cf3a9faebffe4e5c7a833433ff28ed\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110011 for cells of type $lut.
Using template $paramod$3e63470ea7a06b3eefdfb990254dd83d20fa13a7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$21f957a7073b1ba634cad0df400394ca323de2fc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut.
Using template $paramod$cb728a9f792d450de2d7ebf35c268e7caeb195a3\$lut for cells of type $lut.
Using template $paramod$899a7d400185b4f778bea81a50f62c95a0b19d77\$lut for cells of type $lut.
Using template $paramod$39fecdaa624309b39c1f847c4e14205177fabf73\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut.
Using template $paramod$c96d7c7fd8b1109d21099b4dbaf38cd6304e051b\$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$850f48dac4014f6ce06187aa7664648cd494a38b\$lut for cells of type $lut.
Using template $paramod$048d747237dc7c0c9b3ac38b28fd102440b9c369\$lut for cells of type $lut.
Using template $paramod$d25c5ed7cce01a2a4804202e877356eeec4db6a1\$lut for cells of type $lut.
Using template $paramod$d2a1a3b18350dd0754abc41ae3ec8d880a85d26a\$lut for cells of type $lut.
Using template $paramod$5637f6366c0fa622e75f886ee59706323e5fe6fc\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~11250 debug messages>

22.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132103.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132046.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132049.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132053.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132073.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132077.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132089.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut\SOC.Core.Pc.load.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$14456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132129.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132130.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$14435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$14435.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$14428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$14352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$14352.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$14330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$14267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14260.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$14254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$14254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$14254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$14210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$14183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$14085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$14085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$14052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$14052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13982.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13972.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13926.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13674.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13526.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13517.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13484.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13406.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13262.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13172.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13034.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12992.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$12964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$12964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$12901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$12896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$12896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$12848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$12848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$12848.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$12839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$12832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$12825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$12825.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$12816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$12816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$12804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$12804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$12748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$12748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$12739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11907.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$11877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$11877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$11870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$11870.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$11852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$11724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11715.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11715.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11715.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11715.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11715.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11715.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$11598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11394.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$11329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$11329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11313.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11287.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11227.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11168.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11088.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11025.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10913.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10869.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10859.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10830.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10817.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10788.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10770.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10609.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10490.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10422.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10336.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10296.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10275.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10197.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10179.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$9922.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$9627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10155.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$9960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10001.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11428.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$11480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9656.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$11156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$10453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$10936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$9977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$9945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11341.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10967.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10402.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10402.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11335.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$9843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$9799.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$9837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$9785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$9908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$9740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$9740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$9820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10960.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10001.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10029.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10118.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$9882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10100.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10262.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10402.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10453.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$10472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11119.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10556.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10627.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10644.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10687.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10754.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11079.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10847.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$10900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10913.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10936.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$10944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10982.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10982.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$11025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11050.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132176.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$11088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10366.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11185.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132196.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11227.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132150.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$11296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$11341.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11399.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11432.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11448.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11473.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11498.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11518.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11529.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11537.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11564.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11574.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11580.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11672.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11680.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11687.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11698.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11715.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11734.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$11742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11748.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11753.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11907.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11907.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11941.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$11965.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12439.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12683.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$12696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12730.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12839.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$12852.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$12861.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$12964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$12996.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13011.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13048.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13148.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13153.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13375.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$13554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13646.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13740.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13763.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13795.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13854.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$13887.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13921.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$13986.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$13994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14056.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14089.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$14152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14210.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14237.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14267.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$14279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14377.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$14401.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut\SOC.Core.Pc.load.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$132022$lut$aiger132021$14476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14721.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$14994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15029.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15097.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$15286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15353.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15369.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15376.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15421.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15523.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15575.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15718.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15785.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15845.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15882.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$15987.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16089.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16440.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16457.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16541.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$16680.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16736.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16807.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16915.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$16943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$16978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$17039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$17242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17303.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$17339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17365.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17492.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17520.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$17577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17720.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17754.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$17969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$18016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$18293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$18341.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18375.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18765.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$18881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19060.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19067.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$19202.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$19319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19335.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19640.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19708.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19843.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$19984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20019.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20348.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20485.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20879.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$20887.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$20968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$20984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$21204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$21283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21467.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21495.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21541.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21545.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21757.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21861.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$21990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22000.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22073.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22089.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22151.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22227.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22409.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$22477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22509.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$22611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22627.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22807.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$22832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22962.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22972.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$22979.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23143.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$23278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23379.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23481.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23627.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23710.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23861.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$23985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24082.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24089.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24317.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24369.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$24539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$24553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$24623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24722.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$24873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$11377.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$9627.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$10379.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$10230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$9759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$9803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$aiger132021$9825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$9843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$9849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$9868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9882.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$9939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$9945.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$9960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$9977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$132022$lut$aiger132021$9985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$132022$lut$aiger132021$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$auto$fsm_map.cc:170:map_fsm$3406[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$auto$fsm_map.cc:170:map_fsm$3406[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$auto$fsm_map.cc:170:map_fsm$3449[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$132022$lut$auto$opt_dff.cc:219:make_patterns_logic$3685.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut$flatten\SOC.\Uart.$procmux$1688.Y[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$132022$lut$flatten\SOC.\Uart.$procmux$1688.Y[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132091.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$132022$lut\SOC.Core.Pc.load.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132030.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132034.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132039.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132064.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132067.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$132022$lut$auto$fsm_map.cc:170:map_fsm$3406[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132133.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132138.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132140.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132142.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132151.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132168.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132182.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132183.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132189.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132199.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$132200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Removed 0 unused cells and 14432 unused wires.

22.45. Executing AUTONAME pass.
Renamed 344560 objects in module top (287 iterations).
<suppressed ~16571 debug messages>

22.46. Executing HIERARCHY pass (managing design hierarchy).

22.46.1. Analyzing design hierarchy..
Top module:  \top

22.46.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

22.47. Printing statistics.

=== top ===

   Number of wires:               7704
   Number of wire bits:          23542
   Number of public wires:        7704
   Number of public wire bits:   23542
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              10245
     $_TBUF_                         6
     $scopeinfo                     30
     CCU2C                          73
     L6MUX21                       423
     LUT4                         6547
     PFUMX                        1381
     TRELLIS_DPR16X4              1074
     TRELLIS_FF                    711

22.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

22.49. Executing JSON backend.

Warnings: 21 unique messages, 22 total
End of script. Logfile hash: 344935e9aa, CPU: user 12.77s system 0.11s, MEM: 261.16 MB peak
Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)
Time spent: 41% 1x abc9_exe (8 sec), 11% 11x techmap (2 sec), ...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (NextPNR)
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2028.812 ; gain = 404.715 ; free physical = 8449 ; free virtual = 27561
---------------------------------------------------------------------------------
[Pipeline] sh
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:     13137/43848    29%
Info:         logic LUTs:   6547/43848    14%
Info:         carry LUTs:    146/43848     0%
Info:           RAM LUTs:   4296/ 5481    78%
Info:          RAMW LUTs:   2148/10962    19%

Info:      Total DFFs:       711/43848     1%

Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     249 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x989a6359
INFO: [Synth 8-11241] undeclared symbol 'pc_source', assumed default net type 'wire' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:142]
WARNING: [Synth 8-11065] parameter 'SET_DIRECTION' becomes localparam in 'GPIOS' with formal parameter declaration list [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:19]
WARNING: [Synth 8-11065] parameter 'READ' becomes localparam in 'GPIOS' with formal parameter declaration list [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:20]
WARNING: [Synth 8-9400] empty statement in sequential block [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:54]
INFO: [Synth 8-6157] synthesizing module 'top' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1]
	Parameter CYCLES bound to: 20 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1]
WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:22]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 3 connections declared, but only 2 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:22]
INFO: [Synth 8-6157] synthesizing module 'Risco_5_SOC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
	Parameter CLOCK_FREQ bound to: 100000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter MEMORY_SIZE bound to: 2048 - type: integer 
	Parameter MEMORY_FILE bound to: ../../software/memory/fpga_test_3.hex - type: string 
	Parameter GPIO_WIDHT bound to: 8 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:1]
	Parameter BOOT_ADDRESS bound to: 0 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'PC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'PC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6157] synthesizing module 'MUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1]
INFO: [Synth 8-6155] done synthesizing module 'MUX' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1]
INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1]
INFO: [Synth 8-6157] synthesizing module 'Control_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:1]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:152]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:328]
INFO: [Synth 8-6155] done synthesizing module 'Control_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:1]
INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:33]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:10]
INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6157] synthesizing module 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:118]
INFO: [Synth 8-6155] done synthesizing module 'CSR_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
WARNING: [Synth 8-7071] port 'save_pc' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:228]
WARNING: [Synth 8-7071] port 'interrupt_on_hold' of module 'CSR_Unit' is unconnected for instance 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:228]
WARNING: [Synth 8-7023] instance 'CSR_Unit' of module 'CSR_Unit' has 15 connections declared, but only 13 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:228]
INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:1]
WARNING: [Synth 8-7071] port 'halt' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32]
WARNING: [Synth 8-7071] port 'interruption_request_external' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32]
WARNING: [Synth 8-7071] port 'interruption_request_timer' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32]
WARNING: [Synth 8-7071] port 'interruption_request_software' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32]
WARNING: [Synth 8-7071] port 'interruption_request_fast' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32]
WARNING: [Synth 8-7023] instance 'Core' of module 'Core' has 14 connections declared, but only 9 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:32]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
	Parameter MEMORY_FILE bound to: ../../software/memory/fpga_test_3.hex - type: string 
	Parameter MEMORY_SIZE bound to: 2048 - type: integer 
INFO: [Synth 8-3876] $readmem data file '../../software/memory/fpga_test_3.hex' is read successfully [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:35]
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
INFO: [Synth 8-6157] synthesizing module 'BUS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6155] done synthesizing module 'BUS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6157] synthesizing module 'LEDs' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6155] done synthesizing module 'LEDs' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
	Parameter CLK_FREQ bound to: 100000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
	Parameter DEPTH bound to: 8 - type: integer 
	Parameter WIDTH bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_rx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 100000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_rx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_tx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 100000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_tx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'GPIOS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
	Parameter WIDHT bound to: 8 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'GPIO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIOS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Risco_5_SOC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]

Info: Device utilisation:
Info: 	          TRELLIS_IO:    18/  245     7%
Info: 	                DCCA:     1/   56     1%
Info: 	              DP16KD:     0/  108     0%
Info: 	          MULT18X18D:     0/   72     0%
Info: 	              ALU54B:     0/   36     0%
Info: 	             EHXPLLL:     0/    4     0%
Info: 	             EXTREFB:     0/    2     0%
Info: 	                DCUA:     0/    2     0%
Info: 	           PCSCLKDIV:     0/    2     0%
Info: 	             IOLOGIC:     0/  160     0%
Info: 	            SIOLOGIC:     0/   85     0%
Info: 	                 GSR:     0/    1     0%
Info: 	               JTAGG:     0/    1     0%
Info: 	                OSCG:     0/    1     0%
Info: 	               SEDGA:     0/    1     0%
Info: 	                 DTR:     0/    1     0%
Info: 	             USRMCLK:     0/    1     0%
Info: 	             CLKDIVF:     0/    4     0%
Info: 	           ECLKSYNCB:     0/   10     0%
Info: 	             DLLDELD:     0/    8     0%
Info: 	              DDRDLL:     0/    4     0%
Info: 	             DQSBUFM:     0/   10     0%
Info: 	     TRELLIS_ECLKBUF:     0/    8     0%
Info: 	        ECLKBRIDGECS:     0/    2     0%
Info: 	                DCSC:     0/    2     0%
Info: 	          TRELLIS_FF:   711/43848     1%
Info: 	        TRELLIS_COMB: 13187/43848    30%
Info: 	        TRELLIS_RAMW:  1074/ 5481    19%

WARNING: [Synth 8-3848] Net interrupt_on_hold in module/entity CSR_Unit does not have driver. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:20]
WARNING: [Synth 8-6014] Unused sequential element tx_fifo_read_reg was removed.  [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:129]
WARNING: [Synth 8-7129] Port address[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[4] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[3] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[2] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[4] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[3] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[2] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module LEDs is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2116.781 ; gain = 492.684 ; free physical = 8288 ; free virtual = 27401
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2134.594 ; gain = 510.496 ; free physical = 8278 ; free virtual = 27391
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2134.594 ; gain = 510.496 ; free physical = 8278 ; free virtual = 27391
---------------------------------------------------------------------------------
Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 6297 cells, random placement wirelen = 570023.
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2134.594 ; gain = 0.000 ; free physical = 8268 ; free virtual = 27381
Info:     at initial placer iter 0, wirelen = 2341
Info:     at initial placer iter 1, wirelen = 1746
Info:     at initial placer iter 2, wirelen = 1797
Info:     at initial placer iter 3, wirelen = 1808
Info: Running main analytical placer, max placement attempts per cell = 28091260.
Info:     at iteration #1, type ALL: wirelen solved = 1789, spread = 88043, legal = 88716; time = 0.41s
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2282.344 ; gain = 0.000 ; free physical = 8244 ; free virtual = 27357
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2282.379 ; gain = 0.000 ; free physical = 8245 ; free virtual = 27358
Info:     at iteration #2, type ALL: wirelen solved = 8222, spread = 72686, legal = 73858; time = 0.63s
Info:     at iteration #3, type ALL: wirelen solved = 16150, spread = 70977, legal = 71634; time = 0.42s
Info:     at iteration #4, type ALL: wirelen solved = 19803, spread = 60080, legal = 61549; time = 0.41s
Info:     at iteration #5, type ALL: wirelen solved = 20583, spread = 59574, legal = 60646; time = 0.40s
Info:     at iteration #6, type ALL: wirelen solved = 24140, spread = 54259, legal = 55540; time = 0.47s
Info:     at iteration #7, type ALL: wirelen solved = 25335, spread = 51563, legal = 52796; time = 0.49s
Info:     at iteration #8, type ALL: wirelen solved = 26213, spread = 51180, legal = 52489; time = 0.39s
Info:     at iteration #9, type ALL: wirelen solved = 28638, spread = 50299, legal = 51833; time = 0.38s
Info:     at iteration #10, type ALL: wirelen solved = 28380, spread = 49374, legal = 50909; time = 0.37s
Info:     at iteration #11, type ALL: wirelen solved = 28483, spread = 49705, legal = 51066; time = 0.55s
Info:     at iteration #12, type ALL: wirelen solved = 29181, spread = 50623, legal = 51701; time = 0.42s
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2282.379 ; gain = 658.281 ; free physical = 8210 ; free virtual = 27325
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2282.379 ; gain = 658.281 ; free physical = 8208 ; free virtual = 27324
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2282.379 ; gain = 658.281 ; free physical = 8212 ; free virtual = 27327
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'UART'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
           RESET_COUNTER |                               00 |                               01
                    IDLE |                               01 |                               10
                    INIT |                               10 |                               00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                   FETCH | 0000000000000000000000000000000000000000000001 |                           000000
                  DECODE | 0000000000000000000000000000000000000000000010 |                           000001
                  MEMADR | 0000000000000000000000000000000000000000000100 |                           000010
       MEMREAD_UNALIGNED | 0000000000000000000000000000000000000000001000 |                           010110
        LOAD_FIRST_BLOCK | 0000000000000000000000000000000000000000010000 |                           010000
        SAVE_FIRST_BLOCK | 0000000000000000000000000000000000000000100000 |                           010001
       CALC_NEXT_ADDRESS | 0000000000000000000000000000000000000001000000 |                           010010
       READ_SECOND_BLOCK | 0000000000000000000000000000000000000010000000 |                           010011
       LOAD_SECOND_BLOCK | 0000000000000000000000000000000000000100000000 |                           010100
            MERGE_BLOCKS | 0000000000000000000000000000000000001000000000 |                           010101
           FILTER_ALU_WB | 0000000000000000000000000000000000010000000000 |                           010111
                 MEMREAD | 0000000000000000000000000000000000100000000000 |                           000011
                   MEMWB | 0000000000000000000000000000000001000000000000 |                           000100
      MEMWRITE_UNALIGNED | 0000000000000000000000000000000010000000000000 |                           011000
  GEN_FIRST_BLOCK_PART_1 | 0000000000000000000000000000000100000000000000 |                           011001
  GEN_FIRST_BLOCK_PART_2 | 0000000000000000000000000000001000000000000000 |                           011010
 GEN_SECOND_BLOCK_PART_1 | 0000000000000000000000000000010000000000000000 |                           011011
 GEN_SECOND_BLOCK_PART_2 | 0000000000000000000000000000100000000000000000 |                           011100
      MERGE_WRITE_BLOCKS | 0000000000000000000000000001000000000000000000 |                           011101
    SWAP_VALUE_DIRECTION | 0000000000000000000000000010000000000000000000 |                           011110
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK | 0000000000000000000000000100000000000000000000 |                           100010
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_2 | 0000000000000000000000001000000000000000000000 |                           100011
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_3 | 0000000000000000000000010000000000000000000000 |                           100100
             CLEAR_VALUE | 0000000000000000000000100000000000000000000000 |                           011111
     MERGE_WRITE_VALUE_1 | 0000000000000000000001000000000000000000000000 |                           100000
           WRITE_VALUE_1 | 0000000000000000000010000000000000000000000000 |                           100001
CALC_SECOND_BLOCK_ADDRESS_TO_WRITE | 0000000000000000000100000000000000000000000000 |                           100101
READ_SECOND_BLOCK_TO_WRITE | 0000000000000000001000000000000000000000000000 |                           100110
LOAD_SECOND_BLOCK_TO_WRITE | 0000000000000000010000000000000000000000000000 |                           100111
LOAD_SECOND_BLOCK_TO_WRITE_2 | 0000000000000000100000000000000000000000000000 |                           101000
  SWAP_VALUE_DIRECTION_2 | 0000000000000001000000000000000000000000000000 |                           101001
      CLEAR_VALUE_PART_2 | 0000000000000010000000000000000000000000000000 |                           101010
    CLEAR_VALUE_PART_2_1 | 0000000000000100000000000000000000000000000000 |                           101011
     MERGE_WRITE_VALUE_2 | 0000000000001000000000000000000000000000000000 |                           101100
           WRITE_VALUE_2 | 0000000000010000000000000000000000000000000000 |                           101101
                MEMWRITE | 0000000000100000000000000000000000000000000000 |                           000101
                EXECUTER | 0000000001000000000000000000000000000000000000 |                           000110
                EXECUTEI | 0000000010000000000000000000000000000000000000 |                           001000
                     JAL | 0000000100000000000000000000000000000000000000 |                           001001
                     BEQ | 0000001000000000000000000000000000000000000000 |                           001010
                   AUIPC | 0000010000000000000000000000000000000000000000 |                           001100
                     LUI | 0000100000000000000000000000000000000000000000 |                           001101
                 JALR_PC | 0001000000000000000000000000000000000000000000 |                           001110
                    JALR | 0010000000000000000000000000000000000000000000 |                           001011
                   ALUWB | 0100000000000000000000000000000000000000000000 |                           000111
              EXECUTECSR | 1000000000000000000000000000000000000000000000 |                           001111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
WARNING: [Synth 8-327] inferring latch for variable 'aluop_out_reg' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:12]
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_RECV |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_SEND |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                              000 |                              000
       COPY_WRITE_BUFFER |                              001 |                              101
                   WRITE |                              010 |                              010
                    READ |                              011 |                              001
                      WB |                              100 |                              100
                  FINISH |                              101 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2282.379 ; gain = 658.281 ; free physical = 8161 ; free virtual = 27278
---------------------------------------------------------------------------------
Info:     at iteration #13, type ALL: wirelen solved = 30428, spread = 48609, legal = 50095; time = 0.45s
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input   32 Bit       Adders := 1     
	   3 Input   32 Bit       Adders := 1     
	   2 Input   11 Bit       Adders := 2     
	   2 Input    6 Bit       Adders := 4     
	   2 Input    5 Bit       Adders := 1     
	   2 Input    4 Bit       Adders := 2     
	   2 Input    3 Bit       Adders := 2     
	   2 Input    2 Bit       Adders := 1     
+---XORs : 
	   2 Input     32 Bit         XORs := 1     
+---XORs : 
	                2 Bit    Wide XORs := 1     
+---Registers : 
	               33 Bit    Registers := 1     
	               32 Bit    Registers := 50    
	               16 Bit    Registers := 2     
	               11 Bit    Registers := 2     
	                8 Bit    Registers := 8     
	                6 Bit    Registers := 1     
	                4 Bit    Registers := 2     
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 19    
+---RAMs : 
	              16K Bit	(512 X 32 bit)          RAMs := 1     
	               64 Bit	(8 X 8 bit)          RAMs := 2     
+---Muxes : 
	  46 Input   46 Bit        Muxes := 1     
	   2 Input   46 Bit        Muxes := 17    
	  11 Input   46 Bit        Muxes := 1     
	   3 Input   33 Bit        Muxes := 1     
	   2 Input   32 Bit        Muxes := 21    
	   8 Input   32 Bit        Muxes := 1     
	   4 Input   32 Bit        Muxes := 10    
	   6 Input   32 Bit        Muxes := 2     
	   2 Input   31 Bit        Muxes := 1     
	   2 Input    8 Bit        Muxes := 3     
	   3 Input    6 Bit        Muxes := 1     
	   2 Input    6 Bit        Muxes := 4     
	   2 Input    5 Bit        Muxes := 1     
	  46 Input    4 Bit        Muxes := 1     
	   9 Input    4 Bit        Muxes := 1     
	  10 Input    4 Bit        Muxes := 1     
	   2 Input    4 Bit        Muxes := 1     
	   5 Input    3 Bit        Muxes := 1     
	   2 Input    3 Bit        Muxes := 5     
	   4 Input    3 Bit        Muxes := 2     
	  46 Input    3 Bit        Muxes := 3     
	  10 Input    3 Bit        Muxes := 1     
	   6 Input    3 Bit        Muxes := 2     
	   3 Input    2 Bit        Muxes := 1     
	   2 Input    2 Bit        Muxes := 14    
	  46 Input    2 Bit        Muxes := 2     
	   4 Input    2 Bit        Muxes := 4     
	   3 Input    1 Bit        Muxes := 6     
	   2 Input    1 Bit        Muxes := 65    
	  46 Input    1 Bit        Muxes := 12    
	   4 Input    1 Bit        Muxes := 3     
	   8 Input    1 Bit        Muxes := 7     
	   6 Input    1 Bit        Muxes := 8     
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
Info:     at iteration #14, type ALL: wirelen solved = 30280, spread = 48217, legal = 49887; time = 0.36s
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN  (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":226)
WARN  (NL0002) : The module "MUX" instantiated to "PCSourceMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":152)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
WARN  (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29)
[95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
[100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg"
Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Processing netlist completed
Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst"
Physical Constraint parsed completed
Running placement......
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
Info:     at iteration #15, type ALL: wirelen solved = 30629, spread = 50016, legal = 51141; time = 0.44s
WARNING: [Synth 8-6014] Unused sequential element SOC/Uart/TX_FIFO/memory_reg was removed. 
Info:     at iteration #16, type ALL: wirelen solved = 31960, spread = 49928, legal = 51146; time = 0.53s
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template. 
Info:     at iteration #17, type ALL: wirelen solved = 32775, spread = 49137, legal = 50442; time = 0.37s
Info:     at iteration #18, type ALL: wirelen solved = 32636, spread = 48769, legal = 50016; time = 0.37s
Info:     at iteration #19, type ALL: wirelen solved = 32785, spread = 48112, legal = 49511; time = 0.37s
Info:     at iteration #20, type ALL: wirelen solved = 32493, spread = 48790, legal = 50079; time = 0.46s
WARNING: [Synth 8-3332] Sequential element (SOC/Uart/i_uart_tx/FSM_sequential_fsm_state_reg[1]) is unused and will be removed from module top.
WARNING: [Synth 8-3332] Sequential element (SOC/Uart/i_uart_tx/FSM_sequential_fsm_state_reg[0]) is unused and will be removed from module top.
Info:     at iteration #21, type ALL: wirelen solved = 33652, spread = 48176, legal = 49487; time = 0.46s
Info:     at iteration #22, type ALL: wirelen solved = 33158, spread = 47098, legal = 48745; time = 0.38s
Info:     at iteration #23, type ALL: wirelen solved = 33345, spread = 46845, legal = 48411; time = 0.38s
[10%] Placement Phase 0 completed
Info:     at iteration #24, type ALL: wirelen solved = 33201, spread = 46604, legal = 48212; time = 0.38s
[20%] Placement Phase 1 completed
Info:     at iteration #25, type ALL: wirelen solved = 33458, spread = 46220, legal = 47907; time = 0.53s
Info:     at iteration #26, type ALL: wirelen solved = 33283, spread = 46395, legal = 48107; time = 0.38s
Info:     at iteration #27, type ALL: wirelen solved = 33346, spread = 47126, legal = 48613; time = 0.38s
Info:     at iteration #28, type ALL: wirelen solved = 33907, spread = 48110, legal = 49353; time = 0.38s
Info:     at iteration #29, type ALL: wirelen solved = 35076, spread = 47932, legal = 49439; time = 0.39s
Info:     at iteration #30, type ALL: wirelen solved = 35320, spread = 46608, legal = 48161; time = 0.54s
Info: HeAP Placer Time: 19.64s
Info:   of which solving equations: 11.58s
Info:   of which spreading cells: 1.52s
Info:   of which strict legalisation: 0.42s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 18686, wirelen = 47907
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 2282.379 ; gain = 658.281 ; free physical = 7949 ; free virtual = 27073
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object                  | Inference | Size (Depth x Width) | Primitives      | 
+------------+-----------------------------+-----------+----------------------+-----------------+
|top         | SOC/Memory/memory_reg       | Implied   | 512 x 32             | RAM256X1S x 64  | 
|top         | SOC/Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
+------------+-----------------------------+-----------+----------------------+-----------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Info:   at iteration #5: temp = 0.000000, timing cost = 11314, wirelen = 42540
[30%] Placement Phase 2 completed
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2282.379 ; gain = 658.281 ; free physical = 7934 ; free virtual = 27058
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2282.379 ; gain = 658.281 ; free physical = 7884 ; free virtual = 27008
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object                  | Inference | Size (Depth x Width) | Primitives      | 
+------------+-----------------------------+-----------+----------------------+-----------------+
|top         | SOC/Memory/memory_reg       | Implied   | 512 x 32             | RAM256X1S x 64  | 
|top         | SOC/Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2      | 
+------------+-----------------------------+-----------+----------------------+-----------------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2282.379 ; gain = 658.281 ; free physical = 7886 ; free virtual = 27009
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
Info:   at iteration #10: temp = 0.000000, timing cost = 8162, wirelen = 41218
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2282.379 ; gain = 658.281 ; free physical = 7878 ; free virtual = 27002
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2282.379 ; gain = 658.281 ; free physical = 7878 ; free virtual = 27002
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2282.379 ; gain = 658.281 ; free physical = 7874 ; free virtual = 26998
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2282.379 ; gain = 658.281 ; free physical = 7874 ; free virtual = 26998
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2282.379 ; gain = 658.281 ; free physical = 7878 ; free virtual = 27001
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2282.379 ; gain = 658.281 ; free physical = 7878 ; free virtual = 27001
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+----------+------+
|      |Cell      |Count |
+------+----------+------+
|1     |BUFG      |     2|
|2     |CARRY4    |    23|
|3     |LUT1      |     9|
|4     |LUT2      |   161|
|5     |LUT3      |   178|
|6     |LUT4      |   176|
|7     |LUT5      |   392|
|8     |LUT6      |  1463|
|9     |MUXF7     |   387|
|10    |MUXF8     |    30|
|11    |RAM256X1S |    64|
|12    |RAM32M    |     1|
|13    |RAM32X1D  |     2|
|14    |FDRE      |  1761|
|15    |FDSE      |     4|
|16    |LD        |     4|
|17    |IBUF      |     2|
|18    |IOBUF     |     8|
|19    |OBUF      |     9|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2282.379 ; gain = 658.281 ; free physical = 7877 ; free virtual = 27001
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 41 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2282.379 ; gain = 510.496 ; free physical = 7876 ; free virtual = 27000
Synthesis Optimization Complete : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2282.379 ; gain = 658.281 ; free physical = 7876 ; free virtual = 27000
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2282.379 ; gain = 0.000 ; free physical = 8155 ; free virtual = 27279
INFO: [Netlist 29-17] Analyzing 519 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2346.375 ; gain = 0.000 ; free physical = 8154 ; free virtual = 27278
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 79 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 8 instances
  LD => LDCE: 4 instances
  RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 1 instance 
  RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances

Synth Design complete | Checksum: f413153f
INFO: [Common 17-83] Releasing license: Synthesis
76 Infos, 121 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:55 ; elapsed = 00:00:52 . Memory (MB): peak = 2346.410 ; gain = 1029.320 ; free physical = 8154 ; free virtual = 27277
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2022.361; main = 1748.177; forked = 422.294
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3219.988; main = 2346.379; forked = 969.656
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.74 . Memory (MB): peak = 2410.406 ; gain = 63.996 ; free physical = 8143 ; free virtual = 27267

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1aa1442d4

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2521.219 ; gain = 110.812 ; free physical = 8083 ; free virtual = 27207
Info:   at iteration #15: temp = 0.000000, timing cost = 7531, wirelen = 40517

Starting Logic Optimization Task

Phase 1 Initialization

Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 1aa1442d4

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2767.156 ; gain = 0.000 ; free physical = 7814 ; free virtual = 26938

Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1aa1442d4

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2767.156 ; gain = 0.000 ; free physical = 7814 ; free virtual = 26938
Phase 1 Initialization | Checksum: 1aa1442d4

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2767.156 ; gain = 0.000 ; free physical = 7814 ; free virtual = 26938

Phase 2 Timer Update And Timing Data Collection

Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 1aa1442d4

Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2767.156 ; gain = 0.000 ; free physical = 7814 ; free virtual = 26938

Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 1aa1442d4

Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2767.156 ; gain = 0.000 ; free physical = 7814 ; free virtual = 26938
Phase 2 Timer Update And Timing Data Collection | Checksum: 1aa1442d4

Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2767.156 ; gain = 0.000 ; free physical = 7814 ; free virtual = 26938

Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 2 inverters resulting in an inversion of 8 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 179e11ec2

Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2767.156 ; gain = 0.000 ; free physical = 7814 ; free virtual = 26938
Retarget | Checksum: 179e11ec2
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 2 cells

Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 179e11ec2

Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2767.156 ; gain = 0.000 ; free physical = 7814 ; free virtual = 26938
Constant propagation | Checksum: 179e11ec2
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 5 Sweep
Phase 5 Sweep | Checksum: 21f58c90c

Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2767.156 ; gain = 0.000 ; free physical = 7813 ; free virtual = 26937
Sweep | Checksum: 21f58c90c
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 1 cells

Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 21f58c90c

Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2799.172 ; gain = 32.016 ; free physical = 7813 ; free virtual = 26937
BUFG optimization | Checksum: 21f58c90c
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 21f58c90c

Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2799.172 ; gain = 32.016 ; free physical = 7813 ; free virtual = 26937
Shift Register Optimization | Checksum: 21f58c90c
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 1bd902ca7

Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2799.172 ; gain = 32.016 ; free physical = 7813 ; free virtual = 26937
Post Processing Netlist | Checksum: 1bd902ca7
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells

Phase 9 Finalization

Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: c921fb92

Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2799.172 ; gain = 32.016 ; free physical = 7813 ; free virtual = 26937

Phase 9.2 Verifying Netlist Connectivity

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.172 ; gain = 0.000 ; free physical = 7813 ; free virtual = 26937
Phase 9.2 Verifying Netlist Connectivity | Checksum: c921fb92

Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2799.172 ; gain = 32.016 ; free physical = 7813 ; free virtual = 26937
Phase 9 Finalization | Checksum: c921fb92

Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2799.172 ; gain = 32.016 ; free physical = 7813 ; free virtual = 26937
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |               2  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               8  |               1  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------


Ending Logic Optimization Task | Checksum: c921fb92

Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2799.172 ; gain = 32.016 ; free physical = 7813 ; free virtual = 26937
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.172 ; gain = 0.000 ; free physical = 7813 ; free virtual = 26937

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: c921fb92

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.172 ; gain = 0.000 ; free physical = 7813 ; free virtual = 26937

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: c921fb92

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.172 ; gain = 0.000 ; free physical = 7813 ; free virtual = 26937

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.172 ; gain = 0.000 ; free physical = 7813 ; free virtual = 26937
Ending Netlist Obfuscation Task | Checksum: c921fb92

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.172 ; gain = 0.000 ; free physical = 7813 ; free virtual = 26937
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2799.172 ; gain = 452.762 ; free physical = 7813 ; free virtual = 26937
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2831.188 ; gain = 0.000 ; free physical = 7806 ; free virtual = 26930
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3625481

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2831.188 ; gain = 0.000 ; free physical = 7806 ; free virtual = 26930
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2831.188 ; gain = 0.000 ; free physical = 7806 ; free virtual = 26930

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 16a0c4d26

Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.93 . Memory (MB): peak = 2831.188 ; gain = 0.000 ; free physical = 7803 ; free virtual = 26927

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 22808c54f

Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7802 ; free virtual = 26926

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 22808c54f

Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7802 ; free virtual = 26926
Phase 1 Placer Initialization | Checksum: 22808c54f

Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7802 ; free virtual = 26926

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 2316fa4ab

Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7800 ; free virtual = 26924

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1aa7f67b1

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7800 ; free virtual = 26924

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1aa7f67b1

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7800 ; free virtual = 26924

Phase 2.4 Global Placement Core

Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 255a34eb8

Time (s): cpu = 00:00:14 ; elapsed = 00:00:04 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7787 ; free virtual = 26911

Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 56 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 25 nets or LUTs. Breaked 0 LUT, combined 25 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7787 ; free virtual = 26911

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            0  |             25  |                    25  |           0  |           1  |  00:00:00  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            0  |             25  |                    25  |           0  |           4  |  00:00:00  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.2 Physical Synthesis In Placer | Checksum: 25c9e873a

Time (s): cpu = 00:00:15 ; elapsed = 00:00:05 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7787 ; free virtual = 26911
Phase 2.4 Global Placement Core | Checksum: 1702b09f7

Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7786 ; free virtual = 26910
Phase 2 Global Placement | Checksum: 1702b09f7

Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7786 ; free virtual = 26910

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1c940d9ed

Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7783 ; free virtual = 26907

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1ac62de57

Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7789 ; free virtual = 26913

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: c2f5bead

Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7788 ; free virtual = 26912

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1a852a6a7

Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7788 ; free virtual = 26912

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 124e186e7

Time (s): cpu = 00:00:21 ; elapsed = 00:00:07 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7788 ; free virtual = 26912

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 10a4d031a

Time (s): cpu = 00:00:21 ; elapsed = 00:00:07 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7788 ; free virtual = 26912

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: f4f1aae0

Time (s): cpu = 00:00:21 ; elapsed = 00:00:08 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7788 ; free virtual = 26912
Phase 3 Detail Placement | Checksum: f4f1aae0

Time (s): cpu = 00:00:21 ; elapsed = 00:00:08 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7788 ; free virtual = 26912

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Info:   at iteration #20: temp = 0.000000, timing cost = 8846, wirelen = 40359

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1052eaf76

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.882 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: e77ddca1

Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7785 ; free virtual = 26909
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
[50%] Placement Phase 3 completed
Running routing......
Ending Physical Synthesis Task | Checksum: e77ddca1

Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7786 ; free virtual = 26910
Phase 4.1.1.1 BUFG Insertion | Checksum: 1052eaf76

Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7783 ; free virtual = 26907

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.882. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 10743d751

Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7786 ; free virtual = 26910

Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7786 ; free virtual = 26910
Phase 4.1 Post Commit Optimization | Checksum: 10743d751

Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7786 ; free virtual = 26910

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 10743d751

Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7785 ; free virtual = 26909

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                2x2|
|___________|___________________|___________________|
|      South|                1x1|                1x1|
|___________|___________________|___________________|
|       East|                1x1|                1x1|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 10743d751

Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7785 ; free virtual = 26909
Phase 4.3 Placer Reporting | Checksum: 10743d751

Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7782 ; free virtual = 26906

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7785 ; free virtual = 26909

Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7785 ; free virtual = 26909
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1126e65b4

Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7785 ; free virtual = 26909
Ending Placer Task | Checksum: dce8c3f3

Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 2838.215 ; gain = 7.027 ; free physical = 7785 ; free virtual = 26909
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:09 . Memory (MB): peak = 2838.215 ; gain = 39.043 ; free physical = 7784 ; free virtual = 26908
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
report_io: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7785 ; free virtual = 26909
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7784 ; free virtual = 26908
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
[60%] Routing Phase 0 completed
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs

Phase 1 Build RT Design
Checksum: PlaceDB: aa8f18d ConstDB: 0 ShapeSum: d23fd266 RouteDB: 0
Info:   at iteration #25: temp = 0.000000, timing cost = 7307, wirelen = 40282
[70%] Routing Phase 1 completed
Info:   at iteration #29: temp = 0.000000, timing cost = 8779, wirelen = 40261 
Info: SA placement time 50.25s

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 31.23 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 10.23 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 9.56 ns

Info: Slack histogram:
Info:  legend: * represents 141 endpoint(s)
Info:          + represents [1,141) endpoint(s)
Info: [  7979,   9543) |+
Info: [  9543,  11107) |+
Info: [ 11107,  12671) |+
Info: [ 12671,  14235) |+
Info: [ 14235,  15799) |*+
Info: [ 15799,  17363) |**********+
Info: [ 17363,  18927) |*********+
Info: [ 18927,  20491) |************+
Info: [ 20491,  22055) |*********+
Info: [ 22055,  23619) |*******+
Info: [ 23619,  25183) |*********+
Info: [ 25183,  26747) |*********************************************+
Info: [ 26747,  28311) |************************************************************ 
Info: [ 28311,  29875) |****************+
Info: [ 29875,  31439) |***+
Info: [ 31439,  33003) |*+
Info: [ 33003,  34567) |**+
Info: [ 34567,  36131) |***+
Info: [ 36131,  37695) |*+
Info: [ 37695,  39259) |*+
Info: Checksum: 0xc8e37b8c
Info: Routing globals...
Info:     routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0

Info: Routing..
Info: Setting up routing queue.
Info: Routing 67307 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |      133        866 |  133   866 |     66674|       1.27       1.27|
Info:       2000 |      340       1659 |  207   793 |     66162|       0.36       1.63|
Info:       3000 |      457       2542 |  117   883 |     65512|       0.37       2.00|
Info:       4000 |      569       3430 |  112   888 |     65409|       0.34       2.35|
Info:       5000 |      669       4330 |  100   900 |     64912|       0.31       2.65|
Info:       6000 |      776       5223 |  107   893 |     64517|       0.34       2.99|
Info:       7000 |      899       6100 |  123   877 |     63897|       0.33       3.33|
Info:       8000 |     1015       6984 |  116   884 |     63433|       0.32       3.65|
Info:       9000 |     1090       7909 |   75   925 |     63199|       0.33       3.98|
Info:      10000 |     1193       8806 |  103   897 |     62756|       0.34       4.32|
Info:      11000 |     1328       9671 |  135   865 |     62135|       0.29       4.61|
Info:      12000 |     1435      10564 |  107   893 |     61387|       0.29       4.91|
Info:      13000 |     1524      11475 |   89   911 |     61161|       0.31       5.22|
Info:      14000 |     1571      12428 |   47   953 |     61413|       0.33       5.55|
Info:      15000 |     1657      13342 |   86   914 |     60773|       0.32       5.87|
Info:      16000 |     1818      14181 |  161   839 |     60350|       0.33       6.20|
Info:      17000 |     1994      15005 |  176   824 |     60032|       0.35       6.55|
Info:      18000 |     2183      15816 |  189   811 |     59588|       0.34       6.89|
Info:      19000 |     2295      16704 |  112   888 |     59139|       0.32       7.22|
[80%] Routing Phase 2 completed
Info:      20000 |     2510      17489 |  215   785 |     58721|       0.31       7.53|
Info:      21000 |     2600      18399 |   90   910 |     59194|       0.40       7.93|
Info:      22000 |     2664      19335 |   64   936 |     58322|       0.28       8.21|
Info:      23000 |     2792      20207 |  128   872 |     57923|       0.30       8.51|
Info:      24000 |     2912      21087 |  120   880 |     57916|       0.39       8.90|
Info:      25000 |     2993      22006 |   81   919 |     57318|       0.35       9.25|
Info:      26000 |     3122      22877 |  129   871 |     56731|       0.31       9.56|
Info:      27000 |     3221      23778 |   99   901 |     57352|       0.36       9.91|
Info:      28000 |     3235      24764 |   14   986 |     57178|       0.33      10.24|
Info:      29000 |     3268      25731 |   33   967 |     56385|       0.30      10.54|
Info:      30000 |     3461      26538 |  193   807 |     55780|       0.33      10.87|
Info:      31000 |     3571      27428 |  110   890 |     55070|       0.33      11.20|
Info:      32000 |     3760      28239 |  189   811 |     54503|       0.32      11.52|
Info:      33000 |     3922      29077 |  162   838 |     54089|       0.34      11.86|
Info:      34000 |     4081      29918 |  159   841 |     53429|       0.33      12.19|
Info:      35000 |     4171      30828 |   90   910 |     53050|       0.31      12.49|
Info:      36000 |     4313      31686 |  142   858 |     52302|       0.31      12.81|
Info:      37000 |     4464      32535 |  151   849 |     51698|       0.30      13.10|
Info:      38000 |     4604      33395 |  140   860 |     51186|       0.28      13.39|
Info:      39000 |     4765      34234 |  161   839 |     50513|       0.33      13.72|
Info:      40000 |     4974      35025 |  209   791 |     49962|       0.43      14.14|
Info:      41000 |     5135      35864 |  161   839 |     49298|       0.44      14.58|
Info:      42000 |     5325      36674 |  190   810 |     48598|       0.38      14.96|
Info:      43000 |     5483      37516 |  158   842 |     48045|       0.46      15.42|
Info:      44000 |     5620      38379 |  137   863 |     47265|       0.30      15.72|
Info:      45000 |     5792      39207 |  172   828 |     46623|       0.47      16.19|
Info:      46000 |     5939      40060 |  147   853 |     45860|       0.41      16.60|
Info:      47000 |     6101      40898 |  162   838 |     45479|       0.46      17.06|
Info:      48000 |     6198      41801 |   97   903 |     45205|       0.52      17.59|
Post Restoration Checksum: NetGraph: c2a814c7 | NumContArr: 80586d11 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2c8527712

Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7709 ; free virtual = 26834

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2c8527712

Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7709 ; free virtual = 26833

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2c8527712

Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7708 ; free virtual = 26833
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 1a1d7cbfe

Time (s): cpu = 00:00:39 ; elapsed = 00:00:30 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7673 ; free virtual = 26797
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797  | TNS=0.000  | WHS=0.008  | THS=0.000  |


Router Utilization Summary
  Global Vertical Routing Utilization    = 0.00047874 %
  Global Horizontal Routing Utilization  = 0.000213129 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 3568
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 3564
  Number of Partially Routed Nets     = 4
  Number of Node Overlaps             = 4

Phase 2 Router Initialization | Checksum: 16a15a7da

Time (s): cpu = 00:00:40 ; elapsed = 00:00:30 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7673 ; free virtual = 26797

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 16a15a7da

Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7673 ; free virtual = 26797

Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 2cdbc1088

Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7673 ; free virtual = 26797
Phase 3 Initial Routing | Checksum: 2cdbc1088

Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7673 ; free virtual = 26797

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 516
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.540  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Info:      49000 |     6354      42645 |  156   844 |     44400|       0.39      17.98|
Phase 4.1 Global Iteration 0 | Checksum: 1d071b908

Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7666 ; free virtual = 26790
Phase 4 Rip-up And Reroute | Checksum: 1d071b908

Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7666 ; free virtual = 26790

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 1d071b908

Time (s): cpu = 00:00:45 ; elapsed = 00:00:32 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7666 ; free virtual = 26790

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1d071b908

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7666 ; free virtual = 26790
Phase 5 Delay and Skew Optimization | Checksum: 1d071b908

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7666 ; free virtual = 26790

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 174a87ea6

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7666 ; free virtual = 26790
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.636  | TNS=0.000  | WHS=0.364  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 174a87ea6

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7666 ; free virtual = 26790
Phase 6 Post Hold Fix | Checksum: 174a87ea6

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7666 ; free virtual = 26790

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.762328 %
  Global Horizontal Routing Utilization  = 0.930804 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 174a87ea6

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7666 ; free virtual = 26790

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 174a87ea6

Time (s): cpu = 00:00:46 ; elapsed = 00:00:32 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7666 ; free virtual = 26790

Phase 9 Depositing Routes
Info:      50000 |     6542      43457 |  188   812 |     43702|       0.43      18.41|
Phase 9 Depositing Routes | Checksum: 2139001e9

Time (s): cpu = 00:00:47 ; elapsed = 00:00:33 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7666 ; free virtual = 26790

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.636  | TNS=0.000  | WHS=0.364  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 2139001e9

Time (s): cpu = 00:00:47 ; elapsed = 00:00:33 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7666 ; free virtual = 26790
INFO: [Route 35-16] Router Completed Successfully

Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 1dccc16cb

Time (s): cpu = 00:00:47 ; elapsed = 00:00:33 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7666 ; free virtual = 26790
Info:      51000 |     6704      44295 |  162   838 |     43149|       0.38      18.79|
Ending Routing Task | Checksum: 1dccc16cb

Time (s): cpu = 00:00:47 ; elapsed = 00:00:33 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7666 ; free virtual = 26790

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:33 . Memory (MB): peak = 2838.215 ; gain = 0.000 ; free physical = 7666 ; free virtual = 26790
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Info:      52000 |     6937      45062 |  233   767 |     42609|       0.51      19.29|
Info:      53000 |     7107      45892 |  170   830 |     41886|       0.42      19.71|
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (2052)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (6683)
5. checking no_input_delay (9)
6. checking no_output_delay (16)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (2052)
---------------------------
 There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[36]/Q (HIGH)

 There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[37]/Q (HIGH)

 There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[39]/Q (HIGH)

 There are 2040 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (6683)
---------------------------------------------------
 There are 6683 pins that are not constrained for maximum delay. (HIGH)

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (9)
------------------------------
 There are 9 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (16)
--------------------------------
 There are 16 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      8.661        0.000                      0                    1        0.380        0.000                      0                    1        4.500        0.000                       0                     2  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock        Waveform(ns)       Period(ns)      Frequency(MHz)
-----        ------------       ----------      --------------
sys_clk_pin  {0.000 5.000}      10.000          100.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
sys_clk_pin         8.661        0.000                      0                    1        0.380        0.000                      0                    1        4.500        0.000                       0                     2  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
Info:      54000 |     7276      46723 |  169   831 |     41245|       0.44      20.15|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
Info:      55000 |     7491      47508 |  215   785 |     40738|       0.39      20.55|
INFO: [DRC 23-27] Running DRC with 8 threads
Info:      56000 |     7680      48319 |  189   811 |     40202|       0.43      20.97|
Info:      57000 |     7862      49137 |  182   818 |     39483|       0.37      21.34|
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...
Info:      58000 |     8084      49915 |  222   778 |     38961|       0.44      21.79|
WARN  (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew

Finished Running Vector-less Activity Propagation
Info:      59000 |     8313      50686 |  229   771 |     38372|       0.44      22.23|
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Info:      60000 |     8503      51496 |  190   810 |     37781|       0.44      22.67|
[90%] Routing Phase 3 completed
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
Info:      61000 |     8684      52315 |  181   819 |     37323|       0.42      23.09|
Running timing analysis......
Info:      62000 |     8844      53155 |  160   840 |     36991|       0.40      23.49|
Info:      63000 |     9006      53993 |  162   838 |     36463|       0.36      23.85|
Info:      64000 |     9236      54763 |  230   770 |     36293|       0.36      24.21|
Info:      65000 |     9421      55578 |  185   815 |     35721|       0.36      24.58|
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Info:      66000 |     9625      56374 |  204   796 |     35113|       0.38      24.96|
Info:      67000 |     9833      57166 |  208   792 |     34420|       0.36      25.31|
Info:      68000 |     9988      58011 |  155   845 |     34622|       0.58      25.89|
Info:      69000 |    10061      58938 |   73   927 |     34358|       0.36      26.25|
Info:      70000 |    10219      59780 |  158   842 |     33890|       0.33      26.58|
Info:      71000 |    10419      60580 |  200   800 |     33233|       0.36      26.94|
Info:      72000 |    10655      61344 |  236   764 |     32782|       0.39      27.32|
Info:      73000 |    10965      62034 |  310   690 |     32210|       0.37      27.69|
Info:      74000 |    11294      62705 |  329   671 |     31717|       0.38      28.08|
Info:      75000 |    11625      63374 |  331   669 |     31162|       0.41      28.48|
Info:      76000 |    11896      64103 |  271   729 |     30653|       0.44      28.92|
Info:      77000 |    12176      64823 |  280   720 |     30375|       0.44      29.36|
Info:      78000 |    12467      65532 |  291   709 |     29827|       0.41      29.77|
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Sun May 26 02:07:16 2024

[Pipeline] }
Info:      79000 |    12907      66092 |  440   560 |     29393|       0.45      30.22|
[Pipeline] // stage
[Pipeline] }
Info:      80000 |    13193      66806 |  286   714 |     29054|       0.40      30.62|
Info:      81000 |    13469      67530 |  276   724 |     28768|       0.40      31.01|
Info:      82000 |    13811      68188 |  342   658 |     28406|       0.41      31.42|
Info:      83000 |    14099      68900 |  288   712 |     27929|       0.42      31.84|
Info:      84000 |    14421      69578 |  322   678 |     27442|       0.42      32.26|
Info:      85000 |    14873      70126 |  452   548 |     26992|       0.41      32.66|
Info:      86000 |    15379      70620 |  506   494 |     26565|       0.38      33.04|
Info:      87000 |    15826      71173 |  447   553 |     26122|       0.43      33.47|
Info:      88000 |    16258      71741 |  432   568 |     25656|       0.46      33.93|
Info:      89000 |    16565      72434 |  307   693 |     25351|       0.45      34.38|
Info:      90000 |    16949      73050 |  384   616 |     24956|       0.43      34.81|
Info:      91000 |    17351      73648 |  402   598 |     24577|       0.45      35.26|
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
WARNING: [DRC PDRC-153] Gated clock check: Net SOC/Core/Control_Unit/FSM_onehot_state_reg[39]_1[0] is a gated clock net sourced by a combinational pin SOC/Core/Control_Unit/aluop_out_reg[3]_i_2/O, cell SOC/Core/Control_Unit/aluop_out_reg[3]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Info:      92000 |    17752      74247 |  401   599 |     24156|       0.43      35.69|
Info:      93000 |    18143      74856 |  391   609 |     23825|       0.42      36.11|
Info:      94000 |    18598      75401 |  455   545 |     23463|       0.46      36.57|
Info:      95000 |    18987      75972 |  389   571 |     23137|       0.52      37.10|
Info:      96000 |    19364      76548 |  377   576 |     22716|       0.41      37.51|
Loading site data...
Info:      97000 |    19759      77095 |  395   547 |     22266|       0.50      38.01|
Info:      98000 |    20144      77648 |  385   553 |     21727|       0.47      38.48|
Info:      99000 |    20487      78246 |  343   598 |     21313|       0.46      38.94|
Loading route data...
Processing options...
Creating bitmap...
Info:     100000 |    20853      78818 |  366   572 |     20889|       0.66      39.60|
Info:     101000 |    21257      79344 |  404   526 |     20366|       0.43      40.03|
Info:     102000 |    21668      79890 |  411   546 |     19975|       0.44      40.47|
Info:     103000 |    22143      80363 |  475   473 |     19528|       0.40      40.87|
Creating bitstream...
Info:     104000 |    22462      81018 |  319   655 |     19241|       0.44      41.31|
Writing bitstream ./build/out.bit...
Info:     105000 |    22855      81576 |  393   558 |     18812|       0.41      41.72|
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 3154.340 ; gain = 247.207 ; free physical = 7648 ; free virtual = 26786
INFO: [Common 17-206] Exiting Vivado at Sun May 26 02:07:28 2024...
[Pipeline] }
Info:     106000 |    23227      82143 |  372   567 |     18316|       0.39      42.11|
[Pipeline] // stage
[Pipeline] }
Info:     107000 |    23560      82704 |  333   561 |     17747|       0.38      42.49|
Info:     108000 |    23887      83304 |  327   600 |     17150|       0.33      42.82|
Info:     109000 |    24152      83991 |  265   687 |     16455|       0.26      43.08|
Info:     110000 |    24442      84652 |  290   661 |     15783|       0.29      43.37|
Info:     111000 |    24756      85277 |  314   625 |     15147|       0.31      43.68|
Info:     112000 |    25133      85855 |  377   578 |     14559|       0.35      44.02|
Info:     113000 |    25560      86384 |  427   529 |     14154|       0.41      44.43|
Info:     114000 |    26045      86865 |  485   481 |     13764|       0.41      44.84|
Info:     115000 |    26477      87398 |  432   533 |     13219|       0.40      45.24|
Info:     116000 |    26725      88130 |  248   732 |     12563|       0.33      45.57|
Info:     117000 |    26764      89087 |   39   957 |     11604|       0.17      45.74|
Info:     118000 |    26804      90047 |   40   960 |     10647|       0.16      45.90|
Info:     119000 |    26826      91025 |   22   978 |      9677|       0.15      46.05|
Info:     120000 |    26855      91996 |   29   971 |      8722|       0.15      46.20|
Info:     121000 |    26868      92983 |   13   987 |      7773|       0.15      46.36|
Info:     122000 |    26872      93979 |    4   996 |      6778|       0.14      46.49|
Info:     123000 |    26875      94976 |    3   997 |      5781|       0.14      46.63|
Info:     124000 |    26882      95969 |    7   993 |      4788|       0.14      46.77|
Info:     125000 |    26888      96963 |    6   994 |      3813|       0.15      46.91|
Info:     126000 |    26905      97944 |   17   981 |      2831|       0.15      47.06|
Info:     127000 |    26946      98901 |   41   957 |      1881|       0.19      47.25|
Info:     128000 |    27069      99744 |  123   843 |      1088|       0.30      47.56|
Info:     129000 |    27155     100507 |   86   763 |       225|       0.35      47.91|
Info:     129227 |    27158     100594 |    3    87 |         0|       0.18      48.09|
Info: Routing complete.
Info: Router1 time 48.09s
Info: Checksum: 0xc7d17d27

Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_3.Q
Info:  1.4  1.9    Net SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_1_C_LUT4_Z_D[1] (14,17) -> (16,5)
Info:                Sink SOC.Uart.response_LUT4_B_Z_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  2.1  Source SOC.Uart.response_LUT4_B_Z_LUT4_Z.F
Info:  1.2  3.3    Net SOC.Uart.response_LUT4_B_Z[2] (16,5) -> (15,6)
Info:                Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_B_LUT4_D_C_LUT4_Z_D_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  3.5  Source SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_B_LUT4_D_C_LUT4_Z_D_LUT4_Z.F
Info:  0.4  4.0    Net SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_B_LUT4_C_Z_LUT4_Z_A_LUT4_B_Z_LUT4_D_Z_LUT4_Z_C[1] (15,6) -> (15,6)
Info:                Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_B_LUT4_D_C_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  4.2  Source SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_B_LUT4_D_C_LUT4_Z.F
Info:  1.0  5.2    Net SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_B[2] (15,6) -> (18,15)
Info:                Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_B_LUT4_D_C_LUT4_D.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  5.5  Source SOC.Core.Control_Unit.nextstate_LUT4_Z_1_B_LUT4_Z_B_LUT4_D_C_LUT4_D.F
Info:  1.9  7.4    Net SOC.Core.Alu.ALU_out_S_LUT4_Z_1_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_SD_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_C0[1] (18,15) -> (32,6)
Info:                Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_D_Z_CCU2C_S0_B1_PFUMX_Z_ALUT_LUT4_Z.B
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  7.7  Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_D_Z_CCU2C_S0_B1_PFUMX_Z_ALUT_LUT4_Z.F
Info:  0.0  7.7    Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_D_Z_CCU2C_S0_B1_PFUMX_Z_ALUT (32,6) -> (32,6)
Info:                Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_D_Z_CCU2C_S0_B1_PFUMX_Z_BLUT_LUT4_Z.F1
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info:  0.2  7.8  Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_D_Z_CCU2C_S0_B1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  2.0  9.8    Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_D_Z_CCU2C_S0_A1[1] (32,6) -> (29,18)
Info:                Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_Z_2_D_LUT4_Z.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 10.0  Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_Z_2_D_LUT4_Z.F
Info:  1.0 11.0    Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_Z_2_D[2] (29,18) -> (23,19)
Info:                Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_Z_2.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 11.3  Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_Z_2.F
Info:  0.7 12.0    Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z[2] (23,19) -> (22,20)
Info:                Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_PFUMX_Z_1_ALUT_LUT4_Z.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 12.2  Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_PFUMX_Z_1_ALUT_LUT4_Z.F
Info:  0.0 12.2    Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_PFUMX_Z_1_ALUT (22,20) -> (22,20)
Info:                Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_PFUMX_Z_1_BLUT_LUT4_Z.F1
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info:  0.2 12.4  Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_PFUMX_Z_1_BLUT_LUT4_Z.OFX
Info:  0.8 13.2    Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_D_1_Z[6] (22,20) -> (21,18)
Info:                Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_LUT4_B.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 13.4  Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_LUT4_B.OFX
Info:  0.0 13.4    Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_PFUMX_C0_Z (21,18) -> (21,18)
Info:                Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_LUT4_A.FXB
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info:  0.2 13.7  Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_LUT4_Z_A_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_2_D_LUT4_Z_C_LUT4_C_1_Z_LUT4_A.OFX
Info:  1.0 14.7    Net SOC.Core.RegisterBank.registers.0.0_DO_1_LUT4_A_Z_PFUMX_C0_Z_LUT4_Z_D_LUT4_D_Z_LUT4_D_Z[4] (21,18) -> (19,14)
Info:                Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_6_C0_LUT4_Z_1_C_LUT4_Z_D_LUT4_C_1_Z_PFUMX_Z_3_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 14.9  Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_6_C0_LUT4_Z_1_C_LUT4_Z_D_LUT4_C_1_Z_PFUMX_Z_3_BLUT_LUT4_Z.OFX
Info:  1.3 16.3    Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_6_C0_LUT4_Z_1_C_LUT4_Z_D_LUT4_C_1_Z[6] (19,14) -> (14,9)
Info:                Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 16.5  Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  0.9 17.5    Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_1_D_LUT4_D_Z_LUT4_Z_D_LUT4_A_Z[5] (14,9) -> (17,7)
Info:                Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_5_C0_LUT4_Z_1_D_LUT4_Z_D_LUT4_D_Z_PFUMX_Z_C0_LUT4_Z_D_CCU2C_S1_COUT_CCU2C_CIN_S0_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 17.7  Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_5_C0_LUT4_Z_1_D_LUT4_Z_D_LUT4_D_Z_PFUMX_Z_C0_LUT4_Z_D_CCU2C_S1_COUT_CCU2C_CIN_S0_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  1.3 19.0    Net SOC.Core.Alu.ALU_out_S_PFUMX_Z_5_C0_LUT4_Z_1_D_LUT4_Z_D_LUT4_D_Z_PFUMX_Z_C0_LUT4_Z_D_CCU2C_S1_COUT_CCU2C_CIN_S0_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_B_Z[6] (17,7) -> (30,9)
Info:                Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 19.3  Source SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  1.0 20.2    Net SOC.Core.Alu.ALU_out_S_LUT4_Z_5_B_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z[3] (30,9) -> (30,15)
Info:                Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 20.5  Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F
Info:  0.0 20.5    Net SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT (30,15) -> (30,15)
Info:                Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.30-141.32
Info:  0.2 20.7  Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.0 20.7    Net SOC.Core.Pc.load_L6MUX21_Z_D1 (30,15) -> (30,15)
Info:                Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info:  0.2 20.9  Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  1.9 22.8    Net SOC.Core.Pc.load (30,15) -> (16,6)
Info:                Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_30.CE
Info:                Defined in:
Info:                  Risco-5/src/core/pc.v:5.16-5.20
Info:  0.0 22.8  Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_30.CE
Info: 4.9 ns logic, 17.9 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source gpios[0]$tr_io.O
Info:  2.8  2.8    Net gpios[0]$TRELLIS_IO_IN (0,44) -> (13,23)
Info:                Sink SOC.GPIOS.Gpios[0].direction_LUT4_B.A
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:7.16-7.21
Info:  0.2  3.0  Source SOC.GPIOS.Gpios[0].direction_LUT4_B.F
Info:  2.5  5.6    Net SOC.GPIOS.Gpios[0].direction_LUT4_B_Z[1] (13,23) -> (36,20)
Info:                Sink SOC.Core.read_data_LUT4_Z.B
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  5.8  Source SOC.Core.read_data_LUT4_Z.F
Info:  1.7  7.5    Net SOC.read_data[0] (36,20) -> (25,25)
Info:                Sink SOC.Core.instruction_register_TRELLIS_FF_Q_31.M
Info:                Defined in:
Info:                  Risco-5/src/peripheral/soc.v:21.34-21.43
Info:  0.0  7.5  Setup SOC.Core.instruction_register_TRELLIS_FF_Q_31.M
Info: 0.5 ns logic, 7.0 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source SOC.GPIOS.Gpios[2].direction_TRELLIS_FF_Q.Q
Info:  3.8  4.4    Net SOC.Core.read_data_LUT4_Z_2_D[1] (19,20) -> (81,20)
Info:                Sink SOC.GPIOS.Gpios[2].direction_LUT4_D.D
Info:                Defined in:
Info:                  Risco-5/src/peripheral/gpios.v:16.19-16.33
Info:  0.2  4.6  Source SOC.GPIOS.Gpios[2].direction_LUT4_D.F
Info:  0.7  5.3    Net gpios_$_TBUF__Y_3_E (81,20) -> (82,21)
Info:                Sink gpios[2]$tr_io$invert_T.A
Info:  0.2  5.6  Source gpios[2]$tr_io$invert_T.F
Info:  1.3  6.8    Net gpios[2]$tr_io$invert_T$conn$Z (82,21) -> (90,23)
Info:                Sink gpios[2]$tr_io.T
Info: 1.0 ns logic, 5.8 ns routing

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 43.83 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.48 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 6.84 ns

Info: Slack histogram:
Info:  legend: * represents 137 endpoint(s)
Info:          + represents [1,137) endpoint(s)
Info: [ 17186,  18280) |+
Info: [ 18280,  19374) |+
Info: [ 19374,  20468) |****+
Info: [ 20468,  21562) |**********+
Info: [ 21562,  22656) |**+
Info: [ 22656,  23750) |***+
Info: [ 23750,  24844) |*********+
Info: [ 24844,  25938) |*************+
Info: [ 25938,  27032) |*******+
Info: [ 27032,  28126) |*****+
Info: [ 28126,  29220) |*************+
Info: [ 29220,  30314) |************************************************************ 
Info: [ 30314,  31408) |****************************************************+
Info: [ 31408,  32502) |********+
Info: [ 32502,  33596) |*+
Info: [ 33596,  34690) |*+
Info: [ 34690,  35784) |*+
Info: [ 35784,  36878) |**+
Info: [ 36878,  37972) |*+
Info: [ 37972,  39066) |*+

Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
	0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] sh
[Pipeline] }
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz   -> real 6.00MHz  
Parse file DONE
Erase SRAM Load SRAM Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] }

Loading: [====                                              ] 7.99%[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }

Load SRAM: [======                                            ] 10.28%
Loading: [========                                          ] 15.99%
Load SRAM: [===========                                       ] 20.56%
Loading: [============                                      ] 23.98%
Loading: [================                                  ] 31.97%
Load SRAM: [================                                  ] 30.83%
Load SRAM: [=====================                             ] 41.11%
Loading: [====================                              ] 39.97%
Loading: [========================                          ] 47.96%
Load SRAM: [==========================                        ] 51.39%
Loading: [============================                      ] 55.95%
Load SRAM: [===============================                   ] 61.67%
Loading: [================================                  ] 63.95%
Load SRAM: [====================================              ] 71.94%
Loading: [====================================              ] 71.94%
Load SRAM: [==========================================        ] 82.22%
Loading: [========================================          ] 79.93%
Load SRAM: [===============================================   ] 92.50%
Loading: [============================================      ] 87.92%
Load SRAM: [==================================================] 100.00%
Done
DONE
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // lock
[Pipeline] }

Loading: [================================================  ] 95.92%[Pipeline] // script

Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
Rodando teste na Nexys 4
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
+ echo testando na ecp5
testando na ecp5
FPGA TangNano Broqueada
[Pipeline] sh
[Pipeline] echo
+ echo testando na tang nano
testando na tang nano
FPGA Nexys 4 Broqueada
[Pipeline] sh
+ echo testando na tang nano
testando na tang nano
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // lock
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // lock
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // script
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS