![[Jenkins]](/jenkins/static/b6fe011e/images/svgs/logo.svg){kind=logo}
Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/lib/jenkins/workspace/Risco_5 [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -Rf Risco-5/ build/ [Pipeline] sh + git clone https://github.com/JN513/Risco-5 Cloning into 'Risco-5'... [Pipeline] sh + cd Risco-5 [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (IVerilog) [Pipeline] sh + mkdir -p build [Pipeline] sh + cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/csr_unit.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/fifo.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v [Pipeline] sh + /eda/oss-cad-suite/bin/vvp build/soc_test.o ERROR: Risco-5/src/peripheral/memory.v:35: $readmemh: Unable to open software/memory/generic.hex for reading. VCD info: dumpfile build/soc.vcd opened for output. Risco-5/tests/soc_test.v:42: $finish called at 3606 (1s) [Pipeline] sh + rm -f Risco-5/software/memory/generic.hex [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Síntese) [Pipeline] parallel [Pipeline] { (Branch: OSS-Cad-Suite) [Pipeline] { (Branch: Gowin) [Pipeline] { (Branch: Vivado) [Pipeline] stage [Pipeline] { (OSS-Cad-Suite) [Pipeline] stage [Pipeline] { (Gowin) [Pipeline] stage [Pipeline] { (Vivado) [Pipeline] stage [Pipeline] { (Yosys) [Pipeline] sh [Pipeline] sh + rm -rf Risco-5/impl/pnr + cd Risco-5/fpga/nexys4_ddr + mkdir build + /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source run.tcl [Pipeline] sh [Pipeline] sh + mkdir -p Risco-5/impl/pnr + /eda/oss-cad-suite/bin/yosys -p read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 [Pipeline] sh + cd Risco-5/fpga/tangnano20k/ + /eda/gowin/IDE/bin/gw_sh run.tcl /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf <claire@yosyshq.com> | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) -- Running command ` read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 ' -- 1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation. Generating RTLIL representation for module `\top'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: Risco-5/debug/reset.v Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation. Generating RTLIL representation for module `\ResetBootSystem'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation. Generating RTLIL representation for module `\Alu'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation. Generating RTLIL representation for module `\ALU_Control'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation. Generating RTLIL representation for module `\Control_Unit'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: Risco-5/src/core/core.v Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation. Generating RTLIL representation for module `\Core'. Risco-5/src/core/core.v:142: Warning: Identifier `\pc_source' is implicitly declared. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: Risco-5/src/core/csr_unit.v Parsing Verilog input from `Risco-5/src/core/csr_unit.v' to AST representation. Generating RTLIL representation for module `\CSR_Unit'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation. Generating RTLIL representation for module `\Immediate_Generator'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation. Generating RTLIL representation for module `\MUX'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation. Generating RTLIL representation for module `\PC'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation. Generating RTLIL representation for module `\Registers'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation. Generating RTLIL representation for module `\BUS'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/fifo.v Parsing Verilog input from `Risco-5/src/peripheral/fifo.v' to AST representation. Generating RTLIL representation for module `\FIFO'. Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation. Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9) Generating RTLIL representation for module `\GPIO'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation. Generating RTLIL representation for module `\GPIOS'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation. Generating RTLIL representation for module `\LEDs'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation. Generating RTLIL representation for module `\Memory'. Successfully finished Verilog frontend. 18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation. Generating RTLIL representation for module `\Risco_5_SOC'. Successfully finished Verilog frontend. 19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation. Generating RTLIL representation for module `\UART'. Successfully finished Verilog frontend. 20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_tool_rx'. Successfully finished Verilog frontend. 21. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tool_tx'. Successfully finished Verilog frontend. 22. Executing SYNTH_ECP5 pass. 22.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\DP16KD'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 22.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCUA'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Successfully finished Verilog frontend. 22.3. Executing HIERARCHY pass (managing design hierarchy). 22.3.1. Finding top of design hierarchy.. root of 0 design levels: uart_tool_tx root of 0 design levels: uart_tool_rx root of 1 design levels: UART root of 2 design levels: Risco_5_SOC root of 0 design levels: Memory root of 0 design levels: LEDs root of 1 design levels: GPIOS root of 0 design levels: GPIO root of 0 design levels: FIFO root of 0 design levels: BUS root of 0 design levels: Registers root of 0 design levels: PC root of 0 design levels: MUX root of 0 design levels: Immediate_Generator root of 0 design levels: CSR_Unit root of 1 design levels: Core root of 0 design levels: Control_Unit root of 0 design levels: ALU_Control root of 0 design levels: Alu root of 0 design levels: ResetBootSystem root of 3 design levels: top Automatically selected top as design top module. 22.3.2. Analyzing design hierarchy.. Top module: \top Used module: \Risco_5_SOC Used module: \GPIOS Used module: \GPIO Used module: \UART Used module: \uart_tool_tx Used module: \uart_tool_rx Used module: \FIFO Used module: \LEDs Used module: \BUS Used module: \Memory Used module: \Core Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: \ResetBootSystem Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \MEMORY_SIZE = 2048 Parameter \MEMORY_FILE = 328'0010111000101110001011110010111000101110001011110111001101101111011001100111010001110111011000010111001001100101001011110110110101100101011011010110111101110010011110010010111101110100011001010111001101110100011001010101111101110101011000010111001001110100010111110110011001110000011001110110000100101110011010000110010101111000 Parameter \GPIO_WIDHT = 6 Parameter \UART_BUFFER_SIZE = 16 22.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'. Parameter \CLOCK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \MEMORY_SIZE = 2048 Parameter \MEMORY_FILE = 328'0010111000101110001011110010111000101110001011110111001101101111011001100111010001110111011000010111001001100101001011110110110101100101011011010110111101110010011110010010111101110100011001010111001101110100011001010101111101110101011000010111001001110100010111110110011001110000011001110110000100101110011010000110010101111000 Parameter \GPIO_WIDHT = 6 Parameter \UART_BUFFER_SIZE = 16 Generating RTLIL representation for module `$paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC'. Parameter \CYCLES = 20 22.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'. Parameter \CYCLES = 20 Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'. Parameter \WIDHT = 5 22.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'. Parameter \WIDHT = 5 Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \BUFFER_SIZE = 8 22.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \BUFFER_SIZE = 8 Generating RTLIL representation for module `$paramod$65634474087d1ba2b03796f9a45556e4bd507a57\UART'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 22.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \BOOT_ADDRESS = 0 22.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'. Parameter \BOOT_ADDRESS = 0 Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'. Risco-5/src/core/core.v:142: Warning: Identifier `\pc_source' is implicitly declared. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 22.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 22.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 22.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 22.3.12. Analyzing design hierarchy.. Top module: \top Used module: $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC Used module: \GPIOS Used module: \GPIO Used module: \UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \LEDs Used module: \BUS Used module: \Memory Used module: \Core Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Parameter \WIDHT = 6 22.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'. Parameter \WIDHT = 6 Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \BUFFER_SIZE = 16 22.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \BUFFER_SIZE = 16 Generating RTLIL representation for module `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART'. Parameter \MEMORY_FILE = 328'0010111000101110001011110010111000101110001011110111001101101111011001100111010001110111011000010111001001100101001011110110110101100101011011010110111101110010011110010010111101110100011001010111001101110100011001010101111101110101011000010111001001110100010111110110011001110000011001110110000100101110011010000110010101111000 Parameter \MEMORY_SIZE = 2048 22.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = 328'0010111000101110001011110010111000101110001011110111001101101111011001100111010001110111011000010111001001100101001011110110110101100101011011010110111101110010011110010010111101110100011001010111001101110100011001010101111101110101011000010111001001110100010111110110011001110000011001110110000100101110011010000110010101111000 Parameter \MEMORY_SIZE = 2048 Generating RTLIL representation for module `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory'. Parameter \BOOT_ADDRESS = 0 Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'. 22.3.16. Analyzing design hierarchy.. Top module: \top Used module: $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART Used module: \uart_tool_tx Used module: \uart_tool_rx Used module: \FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 22.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 22.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx'. Parameter \DEPTH = 16 Parameter \WIDTH = 8 22.3.19. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'. Parameter \DEPTH = 16 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO'. Parameter \DEPTH = 16 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO'. 22.3.20. Analyzing design hierarchy.. Top module: \top Used module: $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx Used module: $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 22.3.21. Analyzing design hierarchy.. Top module: \top Used module: $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC Used module: $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110 Used module: \GPIO Used module: $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx Used module: $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO Used module: \LEDs Used module: \BUS Used module: $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory Used module: $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000 Used module: \CSR_Unit Used module: \Immediate_Generator Used module: \Alu Used module: \ALU_Control Used module: \Control_Unit Used module: \Registers Used module: \MUX Used module: \PC Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Removing unused module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'. Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'. Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Removing unused module `$paramod$65634474087d1ba2b03796f9a45556e4bd507a57\UART'. Removing unused module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'. Removing unused module `\uart_tool_tx'. Removing unused module `\uart_tool_rx'. Removing unused module `\UART'. Removing unused module `\Risco_5_SOC'. Removing unused module `\Memory'. Removing unused module `\GPIOS'. Removing unused module `\FIFO'. Removing unused module `\Core'. Removing unused module `\ResetBootSystem'. Removed 15 unused modules. 22.4. Executing PROC pass (convert processes to netlists). 22.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$533'. Found and cleaned up 1 empty switch in `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:0$950'. Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:128$122'. Cleaned up 3 empty switches. 22.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$640 in module TRELLIS_FF. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$592 in module DPR16X4C. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$534 in module TRELLIS_DPR16X4. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/fifo.v:28$1048 in module $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:189$1043 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:178$1041 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:163$1033 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:152$1030 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:140$1024 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:125$1019 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:108$1014 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:89$1005 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:167$992 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:156$990 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:141$982 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:124$968 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:109$962 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:92$957 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:244$746 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:59$948 in module $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory. Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:47$911 in module $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$250 in module LEDs. Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:158$892 in module $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART. Marked 7 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:64$884 in module $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART. Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:31$882 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:24$156 in module Registers. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:15$145 in module PC. Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:18$128 in module Immediate_Generator. Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:128$122 in module CSR_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:104$120 in module CSR_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:76$119 in module CSR_Unit. Marked 5 switch rules as full_case in process $proc$Risco-5/debug/reset.v:24$643 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:636$86 in module Control_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:626$85 in module Control_Unit. Marked 19 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:142$40 in module Control_Unit. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:134$39 in module Control_Unit. Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:9$31 in module ALU_Control. Marked 5 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:9$31 in module ALU_Control. Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:26$11 in module Alu. Removed a total of 1 dead cases. 22.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 12 redundant assignments. Promoted 137 assignments to connections. 22.4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. Set init value: \Q = 1'0 Found init rule in `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:0$1075'. Set init value: \counter = 6'000000 Set init value: \read_ptr = 6'000000 Set init value: \write_ptr = 6'000000 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:124$1045'. Set init value: \i = 0 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:108$998'. Set init value: \i = 0 Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$752'. Set init value: \instruction_register = 0 Set init value: \memory_register = 0 Set init value: \alu_out_register = 0 Set init value: \register_data_1 = 0 Set init value: \register_data_2 = 0 Set init value: \pc_old = 0 Set init value: \temp_address = 0 Set init value: \temp_reg2 = 0 Set init value: \temp_write_value = 0 Found init rule in `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:0$950'. Set init value: \memory_response = 1'0 Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$253'. Set init value: \data = 33'000000000000000000000000000000000 Found init rule in `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:0$902'. Set init value: \state = 4'0000 Set init value: \counter = 3'000 Set init value: \read_data = 0 Set init value: \response = 1'0 Set init value: \uart_tx_en = 1'0 Set init value: \tx_fifo_read = 1'0 Set init value: \tx_fifo_write = 1'0 Set init value: \rx_fifo_read = 1'0 Set init value: \rx_fifo_write = 1'0 Set init value: \uart_tx_data = 8'00000000 Set init value: \tx_fifo_write_data = 8'00000000 Set init value: \rx_fifo_write_data = 8'00000000 Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$148'. Set init value: \Output = 0 Found init rule in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$127'. Set init value: \mepc = 0 Set init value: \mscratch = 0 Set init value: \mcause = 0 Set init value: \mtval = 0 Set init value: \mtvec = 0 Set init value: \mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000 Set init value: \minstret = 64'0000000000000000000000000000000000000000000000000000000000000000 Set init value: \utime = 64'0000000000000000000000000000000000000000000000000000000000000000 Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$649'. Set init value: \reset_o = 1'0 Set init value: \state = 2'01 Set init value: \counter = 6'000000 Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$87'. Set init value: \state = 6'000000 Set init value: \is_immediate = 1'0 Set init value: \pc_write = 1'0 Set init value: \ir_write = 1'0 Set init value: \pc_source = 1'0 Set init value: \reg_write = 1'0 Set init value: \memory_read = 1'0 Set init value: \memory_write = 1'0 Set init value: \pc_write_cond = 1'0 Set init value: \csr_write_enable = 1'0 Set init value: \alu_input_selector = 1'0 Set init value: \save_address = 1'0 Set init value: \save_value = 1'0 Set init value: \save_value_2 = 1'0 Set init value: \save_write_value = 1'0 Set init value: \control_memory_op = 1'0 Set init value: \write_data_in = 1'0 Set init value: \lorD = 2'00 Set init value: \aluop = 2'00 Set init value: \alu_src_a = 3'000 Set init value: \alu_src_b = 3'000 Set init value: \memory_to_reg = 3'000 Set init value: \control_unit_memory_op = 3'010 Set init value: \control_unit_aluop = 4'0000 Set init value: \clear_hal_byte_one_block_option = 3'000 Set init value: \clear_hal_byte_one_block_option_2 = 3'000 Set init value: \nextstate = 6'000000 22.4.5. Executing PROC_ARST pass (detect async resets in processes). 22.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~118 debug messages> 22.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$640'. 1/1: $0\Q[0:0] Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$592'. 1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$591_EN[3:0]$598 2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$591_DATA[3:0]$597 3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$591_ADDR[3:0]$596 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$534'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$532_EN[3:0]$540 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$532_DATA[3:0]$539 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$532_ADDR[3:0]$538 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$533'. Creating decoders for process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:0$1075'. Creating decoders for process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1048'. 1/9: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1060 2/9: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_DATA[7:0]$1059 3/9: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_ADDR[5:0]$1058 4/9: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1055 5/9: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_DATA[7:0]$1054 6/9: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_ADDR[5:0]$1053 7/9: $0\write_ptr[5:0] 8/9: $0\read_ptr[5:0] 9/9: $0\counter[5:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:124$1045'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1043'. 1/2: $0\rxd_reg_0[0:0] 2/2: $0\rxd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1041'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1033'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1030'. 1/1: $0\bit_sample[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1024'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1019'. 1/11: $3\i[31:0] 2/11: $0\recieved_data[7:0] [1] 3/11: $0\recieved_data[7:0] [0] 4/11: $0\recieved_data[7:0] [2] 5/11: $0\recieved_data[7:0] [3] 6/11: $0\recieved_data[7:0] [4] 7/11: $0\recieved_data[7:0] [5] 8/11: $0\recieved_data[7:0] [6] 9/11: $0\recieved_data[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1014'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1005'. 1/1: $0\uart_rx_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:108$998'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$992'. 1/1: $0\txd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$990'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$982'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$968'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$962'. 1/11: $3\i[31:0] 2/11: $0\data_to_send[7:0] [1] 3/11: $0\data_to_send[7:0] [0] 4/11: $0\data_to_send[7:0] [2] 5/11: $0\data_to_send[7:0] [3] 6/11: $0\data_to_send[7:0] [4] 7/11: $0\data_to_send[7:0] [5] 8/11: $0\data_to_send[7:0] [6] 9/11: $0\data_to_send[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$957'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$752'. Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$746'. 1/10: $0\alu_out_register[31:0] 2/10: $0\register_data_2[31:0] 3/10: $0\register_data_1[31:0] 4/10: $0\memory_register[31:0] 5/10: $0\temp_write_value[31:0] 6/10: $0\temp_reg3[31:0] 7/10: $0\temp_reg2[31:0] 8/10: $0\temp_address[31:0] 9/10: $0\pc_old[31:0] 10/10: $0\instruction_register[31:0] Creating decoders for process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:0$950'. Creating decoders for process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:59$948'. 1/1: $1\read_data[31:0] Creating decoders for process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$911'. 1/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$944 2/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_DATA[31:0]$943 3/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_ADDR[31:0]$942 4/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$947 5/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_DATA[31:0]$946 6/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_ADDR[31:0]$945 7/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$934 8/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_DATA[31:0]$933 9/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_ADDR[31:0]$932 10/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$940 11/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_DATA[31:0]$939 12/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_ADDR[31:0]$938 13/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$937 14/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_DATA[31:0]$936 15/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_ADDR[31:0]$935 16/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$930 17/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_DATA[31:0]$929 18/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_ADDR[31:0]$928 19/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$927 20/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_DATA[31:0]$926 21/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_ADDR[31:0]$925 22/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$924 23/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_DATA[31:0]$923 24/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_ADDR[31:0]$922 Creating decoders for process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:39$909'. 1/1: $0\memory_response[0:0] Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$253'. Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$250'. 1/1: $0\data[32:0] Creating decoders for process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:0$902'. Creating decoders for process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$892'. 1/5: $0\rx_fifo_write[0:0] 2/5: $0\tx_fifo_read[0:0] 3/5: $0\uart_tx_en[0:0] 4/5: $0\rx_fifo_write_data[7:0] 5/5: $0\uart_tx_data[7:0] Creating decoders for process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$884'. 1/8: $0\tx_fifo_write[0:0] 2/8: $0\rx_fifo_read[0:0] 3/8: $0\response[0:0] 4/8: $0\write_data_buffer[31:0] 5/8: $0\tx_fifo_write_data[7:0] 6/8: $0\read_data[31:0] 7/8: $0\counter[2:0] 8/8: $0\state[3:0] Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:31$882'. 1/2: $0\gpio_value[5:0] 2/2: $0\gpio_direction[5:0] Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$174'. Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:24$156'. 1/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$171 2/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$151_DATA[31:0]$170 3/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$151_ADDR[4:0]$169 4/9: $2$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$172 5/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$163 6/9: $1$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$167 7/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$166 8/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$151_DATA[31:0]$165 9/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$151_ADDR[4:0]$164 Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$148'. Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:15$145'. 1/1: $0\Output[31:0] Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$128'. 1/2: $2\immediate[31:0] 2/2: $1\immediate[31:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$127'. Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:128$122'. 1/1: $0\minstret[63:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. 1/7: $0\mcycle[63:0] 2/7: $0\utime[63:0] 3/7: $0\mtvec[31:0] 4/7: $0\mtval[31:0] 5/7: $0\mcause[31:0] 6/7: $0\mscratch[31:0] 7/7: $0\mepc[31:0] Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:76$119'. 1/1: $0\csr_data_out[31:0] Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$649'. Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$643'. 1/3: $0\counter[5:0] 2/3: $0\state[1:0] 3/3: $0\reset_o[0:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$87'. Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:636$86'. 1/2: $0\clear_hal_byte_one_block_option_2[2:0] 2/2: $0\clear_hal_byte_one_block_option[2:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:626$85'. 1/1: $0\wb_filter[2:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. 1/22: $0\save_write_value[0:0] 2/22: $0\write_data_in[0:0] 3/22: $0\save_value_2[0:0] 4/22: $0\save_value[0:0] 5/22: $0\control_memory_op[0:0] 6/22: $0\save_address[0:0] 7/22: $0\control_unit_aluop[3:0] 8/22: $0\alu_input_selector[0:0] 9/22: $0\csr_write_enable[0:0] 10/22: $0\is_immediate[0:0] 11/22: $0\reg_write[0:0] 12/22: $0\alu_src_a[2:0] 13/22: $0\alu_src_b[2:0] 14/22: $0\aluop[1:0] 15/22: $0\pc_source[0:0] 16/22: $0\memory_to_reg[2:0] 17/22: $0\memory_write[0:0] 18/22: $0\memory_read[0:0] 19/22: $0\lorD[1:0] 20/22: $0\ir_write[0:0] 21/22: $0\pc_write[0:0] 22/22: $0\pc_write_cond[0:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:142$40'. 1/19: $19\nextstate[5:0] 2/19: $18\nextstate[5:0] 3/19: $17\nextstate[5:0] 4/19: $16\nextstate[5:0] 5/19: $15\nextstate[5:0] 6/19: $14\nextstate[5:0] 7/19: $13\nextstate[5:0] 8/19: $12\nextstate[5:0] 9/19: $11\nextstate[5:0] 10/19: $10\nextstate[5:0] 11/19: $9\nextstate[5:0] 12/19: $8\nextstate[5:0] 13/19: $7\nextstate[5:0] 14/19: $6\nextstate[5:0] 15/19: $5\nextstate[5:0] 16/19: $4\nextstate[5:0] 17/19: $3\nextstate[5:0] 18/19: $2\nextstate[5:0] 19/19: $1\nextstate[5:0] Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:134$39'. 1/1: $0\state[5:0] Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'. 1/5: $5\aluop_out[3:0] 2/5: $4\aluop_out[3:0] 3/5: $3\aluop_out[3:0] 4/5: $2\aluop_out[3:0] 5/5: $1\aluop_out[3:0] Creating decoders for process `\Alu.$proc$Risco-5/src/core/alu.v:26$11'. 1/1: $1\ALU_out_S[31:0] 22.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1014'. No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$957'. No latch inferred for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.\read_data' from process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:59$948'. No latch inferred for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:17$149_EN' from process `\Registers.$proc$Risco-5/src/core/registers.v:0$174'. No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$128'. No latch inferred for signal `\CSR_Unit.\csr_data_out' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:76$119'. No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:636$86'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:636$86`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:636$86`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:636$86`. No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option_2' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:636$86'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:636$86`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:636$86`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:636$86`. No latch inferred for signal `\Control_Unit.\wb_filter' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:626$85'. No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\csr_write_enable` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\alu_input_selector' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_input_selector` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\save_address' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_address` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\save_value' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\save_value_2' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value_2` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\save_write_value' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_write_value` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\control_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_memory_op` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\write_data_in' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\write_data_in` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\control_unit_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. Removing init bit 1'1 for non-memory siginal `\Control_Unit.\control_unit_memory_op [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\control_unit_aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72`. No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:142$40'. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:142$40`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:142$40`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:142$40`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:142$40`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [4]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:142$40`. Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [5]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:142$40`. Latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31': $auto$proc_dlatch.cc:433:proc_dlatch$3127 No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$Risco-5/src/core/alu.v:26$11'. 22.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$640'. created $dff cell `$procdff$3150' with positive edge clock. Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$576_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$577_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$578_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$579_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$580_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$581_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$582_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$583_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$584_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$585_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$586_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$587_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$588_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$589_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$590_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$591_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$592'. created $dff cell `$procdff$3151' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$591_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$592'. created $dff cell `$procdff$3152' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$591_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$592'. created $dff cell `$procdff$3153' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$516_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$517_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$518_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$519_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$520_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$521_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$522_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$523_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$524_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$525_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$526_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$527_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$528_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$529_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$530_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$531_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$532_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$534'. created $dff cell `$procdff$3154' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$532_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$534'. created $dff cell `$procdff$3155' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$532_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$534'. created $dff cell `$procdff$3156' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$533'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.\counter' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1048'. created $dff cell `$procdff$3157' with positive edge clock. Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.\read_ptr' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1048'. created $dff cell `$procdff$3158' with positive edge clock. Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.\write_ptr' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1048'. created $dff cell `$procdff$3159' with positive edge clock. Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_ADDR' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1048'. created $dff cell `$procdff$3160' with positive edge clock. Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_DATA' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1048'. created $dff cell `$procdff$3161' with positive edge clock. Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1048'. created $dff cell `$procdff$3162' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1043'. created $dff cell `$procdff$3163' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1043'. created $dff cell `$procdff$3164' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1041'. created $dff cell `$procdff$3165' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1033'. created $dff cell `$procdff$3166' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1030'. created $dff cell `$procdff$3167' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1024'. created $dff cell `$procdff$3168' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1019'. created $dff cell `$procdff$3169' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1019'. created $dff cell `$procdff$3170' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1005'. created $dff cell `$procdff$3171' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$992'. created $dff cell `$procdff$3172' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$990'. created $dff cell `$procdff$3173' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$982'. created $dff cell `$procdff$3174' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$968'. created $dff cell `$procdff$3175' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$962'. created $dff cell `$procdff$3176' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$962'. created $dff cell `$procdff$3177' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$746'. created $dff cell `$procdff$3178' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$746'. created $dff cell `$procdff$3179' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$746'. created $dff cell `$procdff$3180' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$746'. created $dff cell `$procdff$3181' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$746'. created $dff cell `$procdff$3182' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$746'. created $dff cell `$procdff$3183' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_address' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$746'. created $dff cell `$procdff$3184' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_reg2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$746'. created $dff cell `$procdff$3185' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_reg3' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$746'. created $dff cell `$procdff$3186' with positive edge clock. Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_write_value' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$746'. created $dff cell `$procdff$3187' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_ADDR' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$911'. created $dff cell `$procdff$3188' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_DATA' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$911'. created $dff cell `$procdff$3189' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$911'. created $dff cell `$procdff$3190' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_ADDR' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$911'. created $dff cell `$procdff$3191' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_DATA' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$911'. created $dff cell `$procdff$3192' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$911'. created $dff cell `$procdff$3193' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_ADDR' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$911'. created $dff cell `$procdff$3194' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_DATA' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$911'. created $dff cell `$procdff$3195' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$911'. created $dff cell `$procdff$3196' with positive edge clock. Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.\memory_response' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:39$909'. created $dff cell `$procdff$3197' with positive edge clock. Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$250'. created $dff cell `$procdff$3198' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\uart_tx_en' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$892'. created $dff cell `$procdff$3199' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\tx_fifo_read' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$892'. created $dff cell `$procdff$3200' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\rx_fifo_write' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$892'. created $dff cell `$procdff$3201' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\uart_tx_data' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$892'. created $dff cell `$procdff$3202' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\rx_fifo_write_data' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$892'. created $dff cell `$procdff$3203' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\state' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$884'. created $dff cell `$procdff$3204' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\counter' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$884'. created $dff cell `$procdff$3205' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\read_data' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$884'. created $dff cell `$procdff$3206' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\response' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$884'. created $dff cell `$procdff$3207' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\tx_fifo_write' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$884'. created $dff cell `$procdff$3208' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\rx_fifo_read' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$884'. created $dff cell `$procdff$3209' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\tx_fifo_write_data' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$884'. created $dff cell `$procdff$3210' with positive edge clock. Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\write_data_buffer' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$884'. created $dff cell `$procdff$3211' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:31$882'. created $dff cell `$procdff$3212' with positive edge clock. Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:31$882'. created $dff cell `$procdff$3213' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$156'. created $dff cell `$procdff$3214' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$151_ADDR' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$156'. created $dff cell `$procdff$3215' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$151_DATA' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$156'. created $dff cell `$procdff$3216' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$156'. created $dff cell `$procdff$3217' with positive edge clock. Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$156'. created $dff cell `$procdff$3218' with positive edge clock. Creating register for signal `\PC.\Output' using process `\PC.$proc$Risco-5/src/core/pc.v:15$145'. created $dff cell `$procdff$3219' with positive edge clock. Creating register for signal `\CSR_Unit.\minstret' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:128$122'. created $dff cell `$procdff$3220' with positive edge clock. Creating register for signal `\CSR_Unit.\mepc' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. created $dff cell `$procdff$3221' with positive edge clock. Creating register for signal `\CSR_Unit.\mscratch' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. created $dff cell `$procdff$3222' with positive edge clock. Creating register for signal `\CSR_Unit.\mcause' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. created $dff cell `$procdff$3223' with positive edge clock. Creating register for signal `\CSR_Unit.\mtval' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. created $dff cell `$procdff$3224' with positive edge clock. Creating register for signal `\CSR_Unit.\mtvec' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. created $dff cell `$procdff$3225' with positive edge clock. Creating register for signal `\CSR_Unit.\mcycle' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. created $dff cell `$procdff$3226' with positive edge clock. Creating register for signal `\CSR_Unit.\utime' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. created $dff cell `$procdff$3227' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$643'. created $dff cell `$procdff$3228' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$643'. created $dff cell `$procdff$3229' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$643'. created $dff cell `$procdff$3230' with positive edge clock. Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:134$39'. created $dff cell `$procdff$3231' with positive edge clock. 22.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$641'. Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$640'. Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$640'. Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$615'. Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$592'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$558'. Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$534'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$533'. Removing empty process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:0$1075'. Found and cleaned up 3 empty switches in `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1048'. Removing empty process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1048'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:124$1045'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1043'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1043'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1041'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1041'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1033'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1033'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1030'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1030'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1024'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1024'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1019'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1019'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1014'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1014'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1005'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1005'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:108$998'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$992'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$992'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$990'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$990'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$982'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$982'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$968'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$968'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$962'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$962'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$957'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$957'. Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$752'. Found and cleaned up 6 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$746'. Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:244$746'. Removing empty process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:0$950'. Found and cleaned up 1 empty switch in `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:59$948'. Removing empty process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:59$948'. Found and cleaned up 3 empty switches in `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$911'. Removing empty process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$911'. Found and cleaned up 1 empty switch in `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:39$909'. Removing empty process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:39$909'. Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$253'. Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$250'. Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$250'. Removing empty process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:0$902'. Found and cleaned up 3 empty switches in `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$892'. Removing empty process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$892'. Found and cleaned up 9 empty switches in `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$884'. Removing empty process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$884'. Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:31$882'. Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:31$882'. Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$174'. Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:24$156'. Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:24$156'. Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$148'. Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:15$145'. Removing empty process `PC.$proc$Risco-5/src/core/pc.v:15$145'. Found and cleaned up 2 empty switches in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$128'. Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$128'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$127'. Found and cleaned up 4 empty switches in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:128$122'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:128$122'. Found and cleaned up 3 empty switches in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'. Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:76$119'. Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:76$119'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$649'. Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$643'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$643'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$87'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:636$86'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:636$86'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:626$85'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:626$85'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:307$72'. Found and cleaned up 19 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:142$40'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:142$40'. Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:134$39'. Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:134$39'. Found and cleaned up 5 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'. Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'. Found and cleaned up 1 empty switch in `\Alu.$proc$Risco-5/src/core/alu.v:26$11'. Removing empty process `Alu.$proc$Risco-5/src/core/alu.v:26$11'. Cleaned up 118 empty switches. 22.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO. <suppressed ~4 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. <suppressed ~21 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. <suppressed ~19 debug messages> Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. <suppressed ~9 debug messages> Optimizing module $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory. <suppressed ~5 debug messages> Optimizing module LEDs. <suppressed ~3 debug messages> Optimizing module $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART. <suppressed ~17 debug messages> Optimizing module GPIO. <suppressed ~1 debug messages> Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. <suppressed ~4 debug messages> Optimizing module BUS. <suppressed ~4 debug messages> Optimizing module Registers. <suppressed ~2 debug messages> Optimizing module PC. <suppressed ~2 debug messages> Optimizing module MUX. <suppressed ~1 debug messages> Optimizing module Immediate_Generator. Optimizing module CSR_Unit. <suppressed ~1 debug messages> Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. <suppressed ~7 debug messages> Optimizing module Control_Unit. <suppressed ~23 debug messages> Optimizing module ALU_Control. <suppressed ~18 debug messages> Optimizing module Alu. <suppressed ~1 debug messages> Optimizing module $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC. Optimizing module top. 22.5. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx. Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000. Deleting now unused module $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory. Deleting now unused module LEDs. Deleting now unused module $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART. Deleting now unused module GPIO. Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110. Deleting now unused module BUS. Deleting now unused module Registers. Deleting now unused module PC. Deleting now unused module MUX. Deleting now unused module Immediate_Generator. Deleting now unused module CSR_Unit. Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Deleting now unused module Control_Unit. Deleting now unused module ALU_Control. Deleting now unused module Alu. Deleting now unused module $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC. <suppressed ~30 debug messages> 22.6. Executing TRIBUF pass. 22.7. Executing DEMINOUT pass (demote inout ports to input or output). 22.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~47 debug messages> 22.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 52 unused cells and 817 unused wires. <suppressed ~71 debug messages> 22.10. Executing CHECK pass (checking for obvious problems). Checking module top... Found and reported 0 problems. 22.11. Executing OPT pass (performing simple optimizations). 22.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~21 debug messages> 22.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~798 debug messages> Removed a total of 266 cells. 22.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2405. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2418. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2434. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2436. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2451. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2469. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2490. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2515. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2542. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2572. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2605. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2650. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2697. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2745. dead port 1/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2795. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2797. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2847. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2849. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2898. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$2957. dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3009. dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$1852. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1803. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1809. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1815. dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$1821. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1469. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1471. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1478. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1480. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1487. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1489. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1496. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1498. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1505. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1507. dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1514. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1516. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1522. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1528. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1534. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1540. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1546. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1552. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1558. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1564. dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1570. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1103. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1109. dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$1115. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1103. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1109. dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$1115. Removed 53 multiplexer ports. <suppressed ~140 debug messages> 22.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2187: $auto$opt_reduce.cc:134:opt_pmux$3282 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2194: { $flatten\SOC.\Core.\Control_Unit.$procmux$2047_CMP $auto$opt_reduce.cc:134:opt_pmux$3294 $auto$opt_reduce.cc:134:opt_pmux$3292 $auto$opt_reduce.cc:134:opt_pmux$3290 $auto$opt_reduce.cc:134:opt_pmux$3288 $auto$opt_reduce.cc:134:opt_pmux$3286 $auto$opt_reduce.cc:134:opt_pmux$3284 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2228: { $flatten\SOC.\Core.\Control_Unit.$procmux$2221_CMP $auto$opt_reduce.cc:134:opt_pmux$3308 $auto$opt_reduce.cc:134:opt_pmux$3306 $auto$opt_reduce.cc:134:opt_pmux$3304 $flatten\SOC.\Core.\Control_Unit.$procmux$2143_CMP $auto$opt_reduce.cc:134:opt_pmux$3302 $flatten\SOC.\Core.\Control_Unit.$procmux$2140_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2139_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2138_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2137_CMP $auto$opt_reduce.cc:134:opt_pmux$3300 $auto$opt_reduce.cc:134:opt_pmux$3298 $auto$opt_reduce.cc:134:opt_pmux$3296 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3084: { $flatten\SOC.\Core.\ALU_Control.$procmux$3091_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3090_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3089_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3088_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3087_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3086_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3085_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3107: { $flatten\SOC.\Core.\ALU_Control.$procmux$3109_CMP $flatten\SOC.\Core.\ALU_Control.$procmux$3108_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2263: { $auto$opt_reduce.cc:134:opt_pmux$3310 $flatten\SOC.\Core.\Control_Unit.$procmux$2199_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2270: $auto$opt_reduce.cc:134:opt_pmux$3312 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2274: { $flatten\SOC.\Core.\Control_Unit.$procmux$2192_CMP $auto$opt_reduce.cc:134:opt_pmux$3314 $flatten\SOC.\Core.\Control_Unit.$procmux$2180_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2290: $auto$opt_reduce.cc:134:opt_pmux$3316 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2312: $auto$opt_reduce.cc:134:opt_pmux$3318 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2331: $auto$opt_reduce.cc:134:opt_pmux$3320 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2390: $auto$opt_reduce.cc:134:opt_pmux$3322 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2044: $auto$opt_reduce.cc:134:opt_pmux$3324 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2093: $auto$opt_reduce.cc:134:opt_pmux$3326 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2119: $auto$opt_reduce.cc:134:opt_pmux$3328 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2946: { $auto$opt_reduce.cc:134:opt_pmux$3330 $flatten\SOC.\Core.\Control_Unit.$procmux$2954_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2953_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2952_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2951_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2950_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2949_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2948_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2947_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2136: { $auto$opt_reduce.cc:134:opt_pmux$3334 $auto$opt_reduce.cc:134:opt_pmux$3332 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3012: { $flatten\SOC.\Core.\Control_Unit.$procmux$2319_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2257_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2226_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2122_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2317_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2099_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2293_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2198_CMP $auto$opt_reduce.cc:134:opt_pmux$3338 $flatten\SOC.\Core.\Control_Unit.$procmux$2150_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2191_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2121_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2098_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2149_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2221_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2097_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2081_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2048_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2047_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2145_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2216_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2046_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2143_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2142_CMP $auto$opt_reduce.cc:134:opt_pmux$3336 $flatten\SOC.\Core.\Control_Unit.$procmux$2014_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2028_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2120_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2095_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2140_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2139_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2045_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2138_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2137_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2013_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2027_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1855: { $flatten\SOC.\Core.\Control_Unit.$procmux$2951_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2952_CMP $auto$opt_reduce.cc:134:opt_pmux$3342 $flatten\SOC.\Core.\Control_Unit.$procmux$2953_CMP $auto$opt_reduce.cc:134:opt_pmux$3340 $flatten\SOC.\Core.\Control_Unit.$procmux$2947_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2955_CMP } New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1927: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1944_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1941_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1939_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1938_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1937_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1882_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1909_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1920_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1899_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1890_CMP $auto$opt_reduce.cc:134:opt_pmux$3350 $auto$opt_reduce.cc:134:opt_pmux$3348 $auto$opt_reduce.cc:134:opt_pmux$3346 $auto$opt_reduce.cc:134:opt_pmux$3344 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1800: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1818: Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1824: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$150_EN[31:0]$157 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1466: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1466_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1466_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1466_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] $flatten\SOC.\Memory.$procmux$1466_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1493: Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Memory.$procmux$1493_Y New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Memory.$procmux$1493_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1493_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] $flatten\SOC.\Memory.$procmux$1493_Y [0] } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2164: $auto$opt_reduce.cc:134:opt_pmux$3352 Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1520: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1520_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1520_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1520_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] $flatten\SOC.\Memory.$procmux$1520_Y [0] } New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$1752: { $flatten\SOC.\Uart.$procmux$1746_CMP $flatten\SOC.\Uart.$procmux$1663_CMP $flatten\SOC.\Uart.$procmux$1688_CMP $flatten\SOC.\Uart.$procmux$1644_CMP $auto$opt_reduce.cc:134:opt_pmux$3354 $flatten\SOC.\Uart.$procmux$1670_CMP } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1100: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1100_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1100_Y [0] New connections: $flatten\SOC.\Uart.\RX_FIFO.$procmux$1100_Y [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$procmux$1100_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1100_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1100_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1100_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1100_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1100_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$1100_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1100: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1100_Y New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1100_Y [0] New connections: $flatten\SOC.\Uart.\TX_FIFO.$procmux$1100_Y [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$procmux$1100_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1100_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1100_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1100_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1100_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1100_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$1100_Y [0] } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2184: $auto$opt_reduce.cc:134:opt_pmux$3356 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$1990: { $flatten\SOC.\Core.\Control_Unit.$procmux$1987_CMP $auto$opt_reduce.cc:134:opt_pmux$3358 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2012: $auto$opt_reduce.cc:134:opt_pmux$3360 New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2026: $auto$opt_reduce.cc:134:opt_pmux$3362 Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1827: Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$172, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1818_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$152_EN[31:0]$161 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$1830: Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$171, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$1800_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$151_EN[31:0]$160 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1538: Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$947, B=0, Y=$flatten\SOC.\Memory.$procmux$1538_Y New ports: A=$flatten\SOC.\Memory.$procmux$1493_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1538_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1538_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] $flatten\SOC.\Memory.$procmux$1538_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1556: Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$944, B=0, Y=$flatten\SOC.\Memory.$procmux$1556_Y New ports: A=$flatten\SOC.\Memory.$procmux$1466_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1556_Y [0] New connections: $flatten\SOC.\Memory.$procmux$1556_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] $flatten\SOC.\Memory.$procmux$1556_Y [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1591: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$934, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1520_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_EN[31:0]$914 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$1118: Old ports: A=$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1060, B=8'00000000, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 New ports: A=$flatten\SOC.\Uart.\RX_FIFO.$procmux$1100_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [0] New connections: $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$1118: Old ports: A=$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1060, B=8'00000000, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 New ports: A=$flatten\SOC.\Uart.\TX_FIFO.$procmux$1100_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [0] New connections: $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_EN[7:0]$1051 [0] } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1573: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$940, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1538_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_EN[31:0]$920 [0] } Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1582: Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$937, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1556_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_EN[31:0]$917 [0] } Optimizing cells in module \top. Performed a total of 43 changes. 22.11.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~24 debug messages> Removed a total of 8 cells. 22.11.6. Executing OPT_DFF pass (perform DFF optimizations). 22.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 347 unused wires. <suppressed ~1 debug messages> 22.11.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.11.9. Rerunning OPT passes. (Maybe there is more to do..) 22.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~139 debug messages> 22.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New ctrl vector for $pmux cell $flatten\SOC.\Core.\Alu.$procmux$3112: { $flatten\SOC.\Core.\Alu.$procmux$3126_CMP $flatten\SOC.\Core.\Alu.$procmux$3125_CMP $flatten\SOC.\Core.\Alu.$procmux$3124_CMP $flatten\SOC.\Core.\Alu.$procmux$3123_CMP $auto$opt_reduce.cc:134:opt_pmux$3366 $flatten\SOC.\Core.\Alu.$procmux$3120_CMP $flatten\SOC.\Core.\Alu.$procmux$3119_CMP $flatten\SOC.\Core.\Alu.$procmux$3118_CMP $flatten\SOC.\Core.\Alu.$procmux$3117_CMP $flatten\SOC.\Core.\Alu.$procmux$3116_CMP $flatten\SOC.\Core.\Alu.$procmux$3115_CMP $auto$opt_reduce.cc:134:opt_pmux$3364 } New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2228: { $flatten\SOC.\Core.\Control_Unit.$procmux$2221_CMP $auto$opt_reduce.cc:134:opt_pmux$3308 $auto$opt_reduce.cc:134:opt_pmux$3306 $auto$opt_reduce.cc:134:opt_pmux$3304 $flatten\SOC.\Core.\Control_Unit.$procmux$2143_CMP $auto$opt_reduce.cc:134:opt_pmux$3302 $auto$opt_reduce.cc:134:opt_pmux$3370 $auto$opt_reduce.cc:134:opt_pmux$3368 $auto$opt_reduce.cc:134:opt_pmux$3300 $auto$opt_reduce.cc:134:opt_pmux$3298 $auto$opt_reduce.cc:134:opt_pmux$3296 } New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$1752: { $flatten\SOC.\Uart.$procmux$1746_CMP $flatten\SOC.\Uart.$procmux$1688_CMP $auto$opt_reduce.cc:134:opt_pmux$3372 $auto$opt_reduce.cc:134:opt_pmux$3354 $flatten\SOC.\Uart.$procmux$1670_CMP } Optimizing cells in module \top. Performed a total of 3 changes. 22.11.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.11.13. Executing OPT_DFF pass (perform DFF optimizations). 22.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.11.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.11.16. Rerunning OPT passes. (Maybe there is more to do..) 22.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~139 debug messages> 22.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.11.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.11.20. Executing OPT_DFF pass (perform DFF optimizations). 22.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.11.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.11.23. Finished OPT passes. (There is nothing left to do.) 22.12. Executing FSM pass (extract and optimize FSM). 22.12.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking top.ResetBootSystem.state as FSM state register: Register has an initialization value. Circuit seems to be self-resetting. Not marking top.SOC.Core.CSR_Unit.utime as FSM state register: Users of register don't seem to benefit from recoding. Register has an initialization value. Not marking top.SOC.Core.Control_Unit.state as FSM state register: Register has an initialization value. Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state. Not marking top.SOC.Uart.i_uart_tx.fsm_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking top.SOC.Uart.state as FSM state register: Register has an initialization value. 22.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'. found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$3165 root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1009_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1022_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1035_Y found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1021_Y found state code: 3'000 found ctrl input: \SOC.Uart.i_uart_rx.next_bit found state code: 3'011 found ctrl input: \SOC.Uart.i_uart_rx.payload_done found state code: 3'010 found state code: 3'001 found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1035_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:143$1026_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1022_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1021_Y found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1009_Y ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o } ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1009_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1021_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1022_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:143$1026_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1035_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] } transition: 3'000 4'0--0 -> 3'001 8'01010001 transition: 3'000 4'1--0 -> 3'000 8'01010000 transition: 3'000 4'---1 -> 3'000 8'01010000 transition: 3'010 4'--00 -> 3'010 8'00100010 transition: 3'010 4'--10 -> 3'011 8'00100011 transition: 3'010 4'---1 -> 3'000 8'00100000 transition: 3'001 4'-0-0 -> 3'001 8'00011001 transition: 3'001 4'-1-0 -> 3'010 8'00011010 transition: 3'001 4'---1 -> 3'000 8'00011000 transition: 3'011 4'-0-0 -> 3'011 8'10010011 transition: 3'011 4'-1-0 -> 3'000 8'10010000 transition: 3'011 4'---1 -> 3'000 8'10010000 22.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3373' from module `\top'. 22.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 7 unused cells and 7 unused wires. <suppressed ~8 debug messages> 22.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3373' from module `\top'. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2]. 22.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3373' from module `\top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ---1 010 -> --1- 001 -> -1-- 011 -> 1--- 22.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3373' from module `top': ------------------------------------- Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$3373 (\SOC.Uart.i_uart_rx.fsm_state): Number of input signals: 4 Number of output signals: 5 Number of state bits: 4 Input signals: 0: \ResetBootSystem.reset_o 1: \SOC.Uart.i_uart_rx.payload_done 2: \SOC.Uart.i_uart_rx.next_bit 3: \SOC.Uart.i_uart_rx.rxd_reg Output signals: 0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1035_Y 1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:143$1026_Y 2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1022_Y 3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1021_Y 4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1009_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'1--0 -> 0 5'01010 1: 0 4'---1 -> 0 5'01010 2: 0 4'0--0 -> 2 5'01010 3: 1 4'---1 -> 0 5'00100 4: 1 4'--00 -> 1 5'00100 5: 1 4'--10 -> 3 5'00100 6: 2 4'---1 -> 0 5'00011 7: 2 4'-1-0 -> 1 5'00011 8: 2 4'-0-0 -> 2 5'00011 9: 3 4'-1-0 -> 0 5'10010 10: 3 4'---1 -> 0 5'10010 11: 3 4'-0-0 -> 3 5'10010 ------------------------------------- 22.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$3373' from module `\top'. 22.13. Executing OPT pass (performing simple optimizations). 22.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5 debug messages> 22.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 22.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~138 debug messages> 22.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.13.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3177 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1395_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1389_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1380_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1371_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1362_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1353_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1335_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1344_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3423 ($sdff) from module top (D = \SOC.Uart.uart_tx_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]). Adding EN signal on $auto$ff.cc:266:slice$3423 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1389_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1380_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1371_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1362_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1353_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1335_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1344_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3175 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1311_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$3428 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1311_Y, Q = \SOC.Uart.i_uart_tx.bit_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3174 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1300_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$3434 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$989_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3173 ($dff) from module top (D = \SOC.Uart.i_uart_tx.n_fsm_state, Q = \SOC.Uart.i_uart_tx.fsm_state, rval = 3'000). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$3172 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1289_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$3439 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1289_Y, Q = \SOC.Uart.i_uart_tx.txd_reg). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3171 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1278_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3445 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3169 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$1255_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1246_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1237_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1228_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1219_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1210_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1192_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1201_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3447 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3168 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1174_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$3451 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1029_Y, Q = \SOC.Uart.i_uart_rx.bit_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3167 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1169_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$3455 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3166 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1161_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$3457 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1040_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3164 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1). Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$3163 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1). Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$3159 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1127_Y, Q = \SOC.Uart.TX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3463 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:37$1064_Y, Q = \SOC.Uart.TX_FIFO.write_ptr). Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$3158 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1135_Y, Q = \SOC.Uart.TX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3465 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1070_Y [5:0], Q = \SOC.Uart.TX_FIFO.read_ptr). Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$3157 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1143_Y, Q = \SOC.Uart.TX_FIFO.counter, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3471 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$1143_Y, Q = \SOC.Uart.TX_FIFO.counter). Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$3159 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1127_Y, Q = \SOC.Uart.RX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3475 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:37$1064_Y, Q = \SOC.Uart.RX_FIFO.write_ptr). Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$3158 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1135_Y, Q = \SOC.Uart.RX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3477 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1070_Y [5:0], Q = \SOC.Uart.RX_FIFO.read_ptr). Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$3157 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1143_Y, Q = \SOC.Uart.RX_FIFO.counter, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3483 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$1143_Y, Q = \SOC.Uart.RX_FIFO.counter). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3211 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1686_Y, Q = \SOC.Uart.write_data_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3487 ($sdff) from module top (D = $flatten\SOC.\Uart.$procmux$1686_Y, Q = \SOC.Uart.write_data_buffer). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3210 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1704_Y, Q = \SOC.Uart.tx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3497 ($sdff) from module top (D = \SOC.Uart.write_data_buffer [7:0], Q = \SOC.Uart.tx_fifo_write_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3209 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1658_Y, Q = \SOC.Uart.rx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3208 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1639_Y, Q = \SOC.Uart.tx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3207 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1669_Y, Q = \SOC.Uart.response, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3206 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1712_Y, Q = \SOC.Uart.read_data, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3518 ($sdff) from module top (D = $flatten\SOC.\Uart.$procmux$1712_Y, Q = \SOC.Uart.read_data). Adding EN signal on $flatten\SOC.\Uart.$procdff$3205 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1738_Y, Q = \SOC.Uart.counter). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3204 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1752_Y, Q = \SOC.Uart.state, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$3543 ($sdff) from module top (D = $flatten\SOC.\Uart.$procmux$1752_Y, Q = \SOC.Uart.state). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3203 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1621_Y, Q = \SOC.Uart.rx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3547 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.uart_rx_data, Q = \SOC.Uart.rx_fifo_write_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3202 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1626_Y, Q = \SOC.Uart.uart_tx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$3549 ($sdff) from module top (D = \SOC.Uart.tx_fifo_read_data, Q = \SOC.Uart.uart_tx_data). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3201 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1606_Y, Q = \SOC.Uart.rx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\SOC.\Uart.$procdff$3199 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$1611_Y, Q = \SOC.Uart.uart_tx_en, rval = 1'0). Adding SRST signal on $flatten\SOC.\Leds.$procdff$3198 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$1601_Y, Q = \SOC.Leds.data, rval = 33'000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$3553 ($sdff) from module top (D = { 1'0 \SOC.Leds.write_data [31:6] \SOC.GPIOS.write_data [5:0] }, Q = \SOC.Leds.data). Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$3213 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1786_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3555 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_value). Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$3212 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$1794_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$3559 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_direction). Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$3219 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$1838_Y, Q = \SOC.Core.Pc.Output, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3565 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.Output). Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$3231 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 6'000000). Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3227 ($dff) from module top (D = 64'0000000000000000000000000000000000000000000000000000000000000000, Q = \SOC.Core.CSR_Unit.utime). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3226 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:114$121_Y, Q = \SOC.Core.CSR_Unit.mcycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3225 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1883_Y, Q = \SOC.Core.CSR_Unit.mtvec, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3570 ($sdff) from module top (D = \SOC.Core.register_data_1, Q = \SOC.Core.CSR_Unit.mtvec). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3224 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1891_Y, Q = \SOC.Core.CSR_Unit.mtval, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3574 ($sdff) from module top (D = \SOC.Core.register_data_1, Q = \SOC.Core.CSR_Unit.mtval). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3223 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1900_Y, Q = \SOC.Core.CSR_Unit.mcause, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3578 ($sdff) from module top (D = \SOC.Core.register_data_1, Q = \SOC.Core.CSR_Unit.mcause). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3222 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1910_Y, Q = \SOC.Core.CSR_Unit.mscratch, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3582 ($sdff) from module top (D = \SOC.Core.register_data_1, Q = \SOC.Core.CSR_Unit.mscratch). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3221 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1921_Y, Q = \SOC.Core.CSR_Unit.mepc, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3586 ($sdff) from module top (D = { \SOC.Core.register_data_1 [31:2] 2'00 }, Q = \SOC.Core.CSR_Unit.mepc). Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$3220 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1870_Y, Q = \SOC.Core.CSR_Unit.minstret, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$3590 ($sdff) from module top (D = \SOC.Core.register_data_1, Q = \SOC.Core.CSR_Unit.minstret [63:32]). Adding EN signal on $auto$ff.cc:266:slice$3590 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$1868_Y [31:0], Q = \SOC.Core.CSR_Unit.minstret [31:0]). Adding SRST signal on $flatten\SOC.\Core.$procdff$3187 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1427_Y, Q = \SOC.Core.temp_write_value, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3603 ($sdff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.temp_write_value). Adding SRST signal on $flatten\SOC.\Core.$procdff$3186 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1432_Y, Q = \SOC.Core.temp_reg3, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3605 ($sdff) from module top (D = \SOC.Core.alu_out_register, Q = \SOC.Core.temp_reg3). Adding SRST signal on $flatten\SOC.\Core.$procdff$3185 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1437_Y, Q = \SOC.Core.temp_reg2, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3607 ($sdff) from module top (D = \SOC.Core.memory_register, Q = \SOC.Core.temp_reg2). Adding SRST signal on $flatten\SOC.\Core.$procdff$3184 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1442_Y, Q = \SOC.Core.temp_address, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3609 ($sdff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.temp_address). Adding SRST signal on $flatten\SOC.\Core.$procdff$3183 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1447_Y, Q = \SOC.Core.pc_old, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3611 ($sdff) from module top (D = \SOC.Core.Pc.Output, Q = \SOC.Core.pc_old). Adding SRST signal on $flatten\SOC.\Core.$procdff$3182 ($dff) from module top (D = \SOC.Core.register_data_2_out, Q = \SOC.Core.register_data_2, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$3181 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$3180 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$3179 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0). Adding SRST signal on $flatten\SOC.\Core.$procdff$3178 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$1452_Y, Q = \SOC.Core.instruction_register, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$3617 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register). Adding EN signal on $flatten\ResetBootSystem.$procdff$3230 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter). Adding EN signal on $flatten\ResetBootSystem.$procdff$3229 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state). Adding EN signal on $flatten\ResetBootSystem.$procdff$3228 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o). Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3587 ($sdffe) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3587 ($sdffe) from module top. Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 33 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 34 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 35 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 36 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 37 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 38 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 39 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 40 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 41 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 42 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 43 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 44 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 45 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 46 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 47 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 48 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 49 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 50 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 51 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 52 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 53 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 54 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 55 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 56 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 57 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 58 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 59 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 60 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 61 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 62 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 63 on $auto$ff.cc:266:slice$3568 ($dffe) from module top. Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$3554 ($sdffe) from module top. 22.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 133 unused cells and 129 unused wires. <suppressed ~134 debug messages> 22.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~11 debug messages> 22.13.9. Rerunning OPT passes. (Maybe there is more to do..) 22.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~98 debug messages> 22.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$3453: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o } New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$1927: { $flatten\SOC.\Core.\CSR_Unit.$procmux$1939_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1938_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1937_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1882_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1909_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1920_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1899_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$1890_CMP $auto$opt_reduce.cc:134:opt_pmux$3350 $auto$opt_reduce.cc:134:opt_pmux$3348 $auto$opt_reduce.cc:134:opt_pmux$3346 $auto$opt_reduce.cc:134:opt_pmux$3344 } Optimizing cells in module \top. Performed a total of 2 changes. 22.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~18 debug messages> Removed a total of 6 cells. 22.13.13. Executing OPT_DFF pass (perform DFF optimizations). 22.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 3 unused cells and 9 unused wires. <suppressed ~4 debug messages> 22.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.13.16. Rerunning OPT passes. (Maybe there is more to do..) 22.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~98 debug messages> 22.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.13.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.13.20. Executing OPT_DFF pass (perform DFF optimizations). 22.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.13.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.13.23. Finished OPT passes. (There is nothing left to do.) 22.14. Executing WREDUCE pass (reducing word size of cells). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$3236 (SOC.Core.RegisterBank.registers). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$3238 (SOC.Core.RegisterBank.registers). Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$meminit$\registers$Risco-5/src/core/registers.v:17$173 (SOC.Core.RegisterBank.registers). Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3233 (SOC.Memory.memory). Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3234 (SOC.Memory.memory). Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3235 (SOC.Memory.memory). Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$949 (SOC.Memory.memory). Removed top 23 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:24$907 (SOC.Memory.memory). Removed top 2 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$3232 (SOC.Uart.RX_FIFO.memory). Removed top 2 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:20$1047 (SOC.Uart.RX_FIFO.memory). Removed top 2 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$3232 (SOC.Uart.TX_FIFO.memory). Removed top 2 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\TX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:20$1047 (SOC.Uart.TX_FIFO.memory). Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$1975_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$647 ($eq). Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$646 ($add). Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$646 ($add). Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$645 ($lt). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$3630 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$3625 ($ne). Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$3600 ($ne). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:22$881 ($mux). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$ne$Risco-5/src/peripheral/uart.v:113$889 ($ne). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$1644_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$1663_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$1670_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$1688_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$1715_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$1716_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$1771_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$1772_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$1773_CMP0 ($eq). Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1124 ($mux). Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$1112 ($mux). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:45$1071 ($eq). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1070 ($mux). Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1069 ($add). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:40$1068 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:37$1062 ($eq). Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1124 ($mux). Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$1112 ($mux). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:45$1071 ($eq). Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1070 ($mux). Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1069 ($add). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:40$1068 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:37$1062 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:113$1018 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:112$1017 ($mux). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:111$1016 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:110$1015 ($mux). Removed top 2 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:103$1010 ($eq). Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:101$1008 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:146$984 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:131$976 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:129$974 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:127$971 ($ne). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:127$970 ($ne). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:114$966 ($eq). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:97$961 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:96$960 ($mux). Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:95$959 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:94$958 ($mux). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:88$954 ($eq). Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:86$952 ($eq). Removed top 1 bits (of 33) from mux cell top.$flatten\SOC.\Leds.$ternary$Risco-5/src/peripheral/leds.v:21$249 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Bus.$eq$Risco-5/src/peripheral/bus.v:53$180 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Memory.$procmux$1462_CMP0 ($eq). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1579 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1588 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1597 ($mux). Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:114$121 ($add). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\MemoryAddressMUX.$eq$Risco-5/src/core/mux.v:15$130 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$eq$Risco-5/src/core/mux.v:17$132 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$eq$Risco-5/src/core/mux.v:16$131 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$eq$Risco-5/src/core/mux.v:15$130 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$eq$Risco-5/src/core/mux.v:17$132 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$eq$Risco-5/src/core/mux.v:16$131 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$eq$Risco-5/src/core/mux.v:15$130 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:17$132 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:16$131 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:15$130 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2955_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2954_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2953_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2950_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2949_CMP0 ($eq). Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2946 ($pmux). Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2845 ($mux). Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2792 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2743 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2695 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2648 ($mux). Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2603 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2570 ($mux). Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2540 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2513 ($mux). Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2467 ($mux). Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2416 ($mux). Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2317_CMP0 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2293_CMP0 ($eq). Removed top 5 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2226_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2221_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2216_CMP0 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2202_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2200_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2199_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2198_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2196_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2195_CMP0 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2192_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2191_CMP0 ($eq). Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2190_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2189_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2186_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2185_CMP0 ($eq). Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2180_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2150_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2149_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2145_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2144_CMP0 ($eq). Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2122_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2121_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2099_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2098_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2097_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2081_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2048_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2047_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2046_CMP0 ($eq). Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1990 ($pmux). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1988_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$1987_CMP0 ($eq). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:535$81 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:515$75 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:242$54 ($eq). Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:170$41 ($eq). Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:102$38 ($mux). Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3109_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3091_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3090_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3089_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$3077 ($mux). Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3125_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3124_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3123_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3122_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$3115_CMP0 ($eq). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:53$28 ($mux). Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:37$17 ($mux). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1937_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1920_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1909_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1899_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1890_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1882_CMP0 ($eq). Removed top 32 bits (of 64) from mux cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1868 ($mux). Removed cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1865 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1532 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1550 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1568 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1484 ($mux). Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1511 ($mux). Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$646_Y. Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$4\aluop_out[3:0]. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:37$17_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:53$28_Y. Removed top 32 bits (of 64) from wire top.$flatten\SOC.\Core.\CSR_Unit.$procmux$1868_Y. Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$10\nextstate[5:0]. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$11\nextstate[5:0]. Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$12\nextstate[5:0]. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$13\nextstate[5:0]. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$15\nextstate[5:0]. Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$18\nextstate[5:0]. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0]. Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$5\nextstate[5:0]. Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$6\nextstate[5:0]. Removed top 4 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$7\nextstate[5:0]. Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$8\nextstate[5:0]. Removed top 4 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$9\nextstate[5:0]. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:515$75_Y. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_ADDR[31:0]$912. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_ADDR[31:0]$915. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_ADDR[31:0]$918. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$903_ADDR[31:0]$932. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_ADDR[31:0]$935. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_ADDR[31:0]$938. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$904_ADDR[31:0]$942. Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$905_ADDR[31:0]$945. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_ADDR[5:0]$1049. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_ADDR[5:0]$1058. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1069_Y. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1070_Y. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_ADDR[5:0]$1049. Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1046_ADDR[5:0]$1058. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1069_Y. Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1070_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:110$1015_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:111$1016_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:112$1017_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:113$1018_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:94$958_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:95$959_Y. Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:96$960_Y. Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:97$961_Y. 22.15. Executing PEEPOPT pass (run peephole optimizers). 22.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 45 unused wires. <suppressed ~1 debug messages> 22.17. Executing SHARE pass (SAT-based resource sharing). Found 6 cells in module top that may be considered for resource sharing. Analyzing resource sharing options for $flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:20$1047 ($memrd): Found 1 activation_patterns using ctrl signal { \SOC.Uart.RX_FIFO.empty $flatten\SOC.\Uart.$procmux$1663_CMP $flatten\SOC.\Uart.$ne$Risco-5/src/peripheral/uart.v:113$889_Y }. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:24$907 ($memrd): Found 7 activation_patterns using ctrl signal { $flatten\SOC.\Memory.$procmux$1463_CMP $flatten\SOC.\Memory.$procmux$1462_CMP $flatten\SOC.\Memory.$procmux$1461_CMP $flatten\SOC.\Memory.$procmux$1460_CMP \SOC.Memory.option [1:0] \SOC.Memory.memory_write \SOC.Memory.memory_read $flatten\SOC.\Bus.$eq$Risco-5/src/peripheral/bus.v:48$176_Y }. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\RegisterBank.$memrd$\registers$Risco-5/src/core/registers.v:22$155 ($memrd): Found 12 activation_patterns using ctrl signal { $flatten\SOC.\Core.\Alu.$procmux$3115_CMP $flatten\SOC.\Core.\Alu.$procmux$3116_CMP $flatten\SOC.\Core.\Alu.$procmux$3117_CMP $flatten\SOC.\Core.\Alu.$procmux$3118_CMP $flatten\SOC.\Core.\Alu.$procmux$3119_CMP $flatten\SOC.\Core.\Alu.$procmux$3120_CMP $flatten\SOC.\Core.\Alu.$procmux$3123_CMP $flatten\SOC.\Core.\Alu.$procmux$3124_CMP $flatten\SOC.\Core.\Alu.$procmux$3125_CMP $flatten\SOC.\Core.\Alu.$procmux$3126_CMP $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:14$129_Y $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:15$130_Y $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:16$131_Y $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:17$132_Y $auto$opt_reduce.cc:134:opt_pmux$3366 $auto$opt_reduce.cc:134:opt_pmux$3364 }. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$sshr$Risco-5/src/core/alu.v:51$26 ($sshr): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3115_CMP. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:49$25 ($shr): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3116_CMP. No candidates found. Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:47$24 ($shl): Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$3117_CMP. No candidates found. 22.18. Executing TECHMAP pass (map to technology primitives). 22.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 22.18.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~88 debug messages> 22.19. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.20. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.21. Executing TECHMAP pass (map to technology primitives). 22.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 22.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation. Generating RTLIL representation for module `\$__MUL18X18'. Successfully finished Verilog frontend. 22.21.3. Continuing TECHMAP pass. No more expansions possible. <suppressed ~5 debug messages> 22.22. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module top: creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$646 ($add). creating $macc model for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$735 ($add). creating $macc model for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$734 ($sub). creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14 ($add). creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15 ($sub). creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:114$121 ($add). creating $macc model for $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:115$891 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1061 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1063 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1069 ($add). creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1067 ($sub). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1061 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1063 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1069 ($add). creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1067 ($sub). creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1029 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1040 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:132$978 ($add). creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$989 ($add). creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$989. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:132$978. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1040. creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1029. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1067. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1069. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1063. creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1061. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1067. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1069. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1063. creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1061. creating $alu model for $macc $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:115$891. creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:114$121. creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15. creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14. creating $alu model for $macc $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$734. creating $alu model for $macc $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$735. creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$646. creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$645 ($lt): new $alu creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:53$27 ($ge): new $alu creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:37$16 ($lt): merged with $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:53$27. creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$647 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$645. creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23 ($eq): merged with $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:53$27. creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$645, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$647: $auto$alumacc.cc:485:replace_alu$3690 creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$646: $auto$alumacc.cc:485:replace_alu$3701 creating $alu cell for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:137$735: $auto$alumacc.cc:485:replace_alu$3704 creating $alu cell for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:135$734: $auto$alumacc.cc:485:replace_alu$3707 creating $alu cell for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:53$27, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:37$16, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23: $auto$alumacc.cc:485:replace_alu$3710 creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14: $auto$alumacc.cc:485:replace_alu$3723 creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15: $auto$alumacc.cc:485:replace_alu$3726 creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:114$121: $auto$alumacc.cc:485:replace_alu$3729 creating $alu cell for $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:115$891: $auto$alumacc.cc:485:replace_alu$3732 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1061: $auto$alumacc.cc:485:replace_alu$3735 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1063: $auto$alumacc.cc:485:replace_alu$3738 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1069: $auto$alumacc.cc:485:replace_alu$3741 creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1067: $auto$alumacc.cc:485:replace_alu$3744 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1061: $auto$alumacc.cc:485:replace_alu$3747 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1063: $auto$alumacc.cc:485:replace_alu$3750 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1069: $auto$alumacc.cc:485:replace_alu$3753 creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1067: $auto$alumacc.cc:485:replace_alu$3756 creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1029: $auto$alumacc.cc:485:replace_alu$3759 creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1040: $auto$alumacc.cc:485:replace_alu$3762 creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:132$978: $auto$alumacc.cc:485:replace_alu$3765 creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$989: $auto$alumacc.cc:485:replace_alu$3768 created 21 $alu and 0 $macc cells. 22.23. Executing OPT pass (performing simple optimizations). 22.23.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~3 debug messages> 22.23.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~98 debug messages> 22.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.23.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 22.23.6. Executing OPT_DFF pass (perform DFF optimizations). 22.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 8 unused wires. <suppressed ~2 debug messages> 22.23.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.23.9. Rerunning OPT passes. (Maybe there is more to do..) 22.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~98 debug messages> 22.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.23.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.23.13. Executing OPT_DFF pass (perform DFF optimizations). 22.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.23.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.23.16. Finished OPT passes. (There is nothing left to do.) 22.24. Executing MEMORY pass. 22.24.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 22.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 22.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing top.SOC.Core.RegisterBank.registers write port 0. Analyzing top.SOC.Core.RegisterBank.registers write port 1. Analyzing top.SOC.Core.RegisterBank.registers write port 2. Analyzing top.SOC.Memory.memory write port 0. Analyzing top.SOC.Memory.memory write port 1. Analyzing top.SOC.Memory.memory write port 2. Analyzing top.SOC.Uart.RX_FIFO.memory write port 0. Analyzing top.SOC.Uart.TX_FIFO.memory write port 0. 22.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 22.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\SOC.Core.RegisterBank.registers'[0] in module `\top': no output FF found. Checking read port `\SOC.Core.RegisterBank.registers'[1] in module `\top': no output FF found. Checking read port `\SOC.Core.RegisterBank.registers'[2] in module `\top': merging output FF to cell. Write port 0: don't care on collision. Write port 1: non-transparent. Write port 2: non-transparent. Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found. Checking read port `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': no output FF found. Checking read port `\SOC.Uart.TX_FIFO.memory'[0] in module `\top': merging output FF to cell. Write port 0: non-transparent. Checking read port address `\SOC.Core.RegisterBank.registers'[0] in module `\top': address FF has fully-defined init value, not supported. Checking read port address `\SOC.Core.RegisterBank.registers'[1] in module `\top': address FF has fully-defined init value, not supported. Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found. Checking read port address `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': address FF has fully-defined init value, not supported. 22.24.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 44 unused wires. <suppressed ~7 debug messages> 22.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating read ports of memory top.SOC.Core.RegisterBank.registers by address: Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address: Merging ports 0, 2 (address 5'00000). Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address: Consolidating write ports of memory top.SOC.Memory.memory by address: Merging ports 0, 1 (address { \SOC.Memory.address [10:3] \SOC.GPIOS.address [2] }). Merging ports 0, 2 (address { \SOC.Memory.address [10:3] \SOC.GPIOS.address [2] }). Consolidating write ports of memory top.SOC.Core.RegisterBank.registers using sat-based resource sharing: Checking group clocked with posedge \clk, width 32: ports 0, 1. Common input cone for all EN signals: 13 cells. Size of unconstrained SAT problem: 103 variables, 281 clauses Merging port 1 into port 0. 22.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 22.24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 8 unused cells and 8 unused wires. <suppressed ~9 debug messages> 22.24.10. Executing MEMORY_COLLECT pass (generating $mem cells). 22.25. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.26. Executing MEMORY_LIBMAP pass (mapping memories to cells). mapping memory top.SOC.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_ Extracted data FF from read port 2 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[2] mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_ mapping memory top.SOC.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_ mapping memory top.SOC.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of top.SOC.Uart.TX_FIFO.memory: $\SOC.Uart.TX_FIFO.memory$rdreg[0] <suppressed ~705 debug messages> 22.27. Executing TECHMAP pass (map to technology primitives). 22.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation. Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 22.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ECP5_DP16KD_'. Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'. Successfully finished Verilog frontend. 22.27.3. Continuing TECHMAP pass. Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$4e27082c5debfe2224cd4cfb46d57ecd26c2e614\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$293d72fa1e0ef78bf22001caecec6073cc652851\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$37d30a593e04dcef256e10d58b011be7c79b1d1f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$394227e87be903825446790353e91eb2c5e10934\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$02769dd26fe80f975fe33f4663ba95c7f0fadfe5\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$898e3b9b58dbd39d9c6ca83e9bea083cb54c924d\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$e36787c87f120885851706179ae5031aec78e0c5\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. Using template $paramod$f9f95b558f368450632c01b302c670921c7d458c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. No more expansions possible. <suppressed ~443 debug messages> 22.28. Executing OPT pass (performing simple optimizations). 22.28.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~93 debug messages> 22.28.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~9 debug messages> Removed a total of 3 cells. 22.28.3. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$3619 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$1955_Y, Q = \ResetBootSystem.counter, rval = 6'000000). 22.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 2246 unused wires. <suppressed ~3 debug messages> 22.28.5. Rerunning OPT passes. (Removed registers in this run.) 22.28.6. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.28.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.28.8. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$4637 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$3644 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000). 22.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 1 unused cells and 1 unused wires. <suppressed ~2 debug messages> 22.28.10. Rerunning OPT passes. (Removed registers in this run.) 22.28.11. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.28.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.28.13. Executing OPT_DFF pass (perform DFF optimizations). 22.28.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.28.15. Finished fast OPT passes. 22.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 22.30. Executing OPT pass (performing simple optimizations). 22.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$3840: $auto$rtlil.cc:2489:ReduceOr$3834 -> 1'1 Analyzing evaluation results. dead port 2/2 on $mux $flatten\SOC.\Core.\PCSourceMUX.$ternary$Risco-5/src/core/mux.v:15$143. Removed 1 multiplexer ports. <suppressed ~62 debug messages> 22.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$3825: Old ports: A={ \SOC.Memory.buffer [31:16] \SOC.Leds.write_data [15:6] \SOC.GPIOS.write_data [5:0] }, B={ \SOC.Leds.write_data [31:6] \SOC.GPIOS.write_data [5:0] }, Y=$auto$rtlil.cc:2582:Mux$3826 New ports: A=\SOC.Memory.buffer [31:16], B=\SOC.Leds.write_data [31:16], Y=$auto$rtlil.cc:2582:Mux$3826 [31:16] New connections: $auto$rtlil.cc:2582:Mux$3826 [15:0] = { \SOC.Leds.write_data [15:6] \SOC.GPIOS.write_data [5:0] } New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$1964: { $flatten\ResetBootSystem.$procmux$1959_CMP $flatten\ResetBootSystem.$procmux$1958_CMP } Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1967: Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$1967_Y New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$1967_Y [1] New connections: $flatten\ResetBootSystem.$procmux$1967_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3062: Old ports: A=4'1001, B=4'0011, Y=$flatten\SOC.\Core.\ALU_Control.$5\aluop_out[3:0] New ports: A=2'10, B=2'01, Y={ $flatten\SOC.\Core.\ALU_Control.$5\aluop_out[3:0] [3] $flatten\SOC.\Core.\ALU_Control.$5\aluop_out[3:0] [1] } New connections: { $flatten\SOC.\Core.\ALU_Control.$5\aluop_out[3:0] [2] $flatten\SOC.\Core.\ALU_Control.$5\aluop_out[3:0] [0] } = 2'01 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$3077: Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$3645 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3645 [2] New connections: $auto$wreduce.cc:461:run$3645 [1:0] = 2'10 Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2136: Old ports: A=4'0000, B=8'10001001, Y=\SOC.Core.control_unit_aluop New ports: A=2'00, B=4'1011, Y={ \SOC.Core.control_unit_aluop [3] \SOC.Core.control_unit_aluop [0] } New connections: \SOC.Core.control_unit_aluop [2:1] = 2'00 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2331: Old ports: A=2'00, B=2'10, Y=\SOC.Core.lorD New ports: A=1'0, B=1'1, Y=\SOC.Core.lorD [1] New connections: \SOC.Core.lorD [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2403: Old ports: A=6'101101, B=6'000000, Y=$flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] New connections: $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [5:1] = { $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] 1'0 $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0] [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2432: Old ports: A=6'000000, B=6'100101, Y=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] New connections: $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [5:1] = { $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] 2'00 $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2467: Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$3654 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3654 [2] New connections: $auto$wreduce.cc:461:run$3654 [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2488: Old ports: A=6'011111, B=6'100010, Y=$flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] New ports: A=2'01, B=2'10, Y={ $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [5] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] } New connections: $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [4:1] = { $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0] [0] 1'1 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2513: Old ports: A=3'110, B=3'011, Y=$auto$wreduce.cc:461:run$3653 [2:0] New ports: A=2'10, B=2'01, Y={ $auto$wreduce.cc:461:run$3653 [2] $auto$wreduce.cc:461:run$3653 [0] } New connections: $auto$wreduce.cc:461:run$3653 [1] = 1'1 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2570: Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$3651 [2:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3651 [2] $auto$wreduce.cc:461:run$3651 [0] } New connections: $auto$wreduce.cc:461:run$3651 [1] = $auto$wreduce.cc:461:run$3651 [0] Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2603: Old ports: A=5'00000, B=5'10010, Y=$auto$wreduce.cc:461:run$3650 [4:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3650 [1] New connections: { $auto$wreduce.cc:461:run$3650 [4:2] $auto$wreduce.cc:461:run$3650 [0] } = { $auto$wreduce.cc:461:run$3650 [1] 3'000 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2648: Old ports: A=3'101, B=3'000, Y=$auto$wreduce.cc:461:run$3661 [2:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3661 [0] New connections: $auto$wreduce.cc:461:run$3661 [2:1] = { $auto$wreduce.cc:461:run$3661 [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2695: Old ports: A=3'110, B=3'000, Y=$auto$wreduce.cc:461:run$3660 [2:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3660 [1] New connections: { $auto$wreduce.cc:461:run$3660 [2] $auto$wreduce.cc:461:run$3660 [0] } = { $auto$wreduce.cc:461:run$3660 [1] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2792: Old ports: A=5'00101, B=5'11000, Y=$auto$wreduce.cc:461:run$3658 [4:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3658 [3] $auto$wreduce.cc:461:run$3658 [0] } New connections: { $auto$wreduce.cc:461:run$3658 [4] $auto$wreduce.cc:461:run$3658 [2:1] } = { $auto$wreduce.cc:461:run$3658 [3] $auto$wreduce.cc:461:run$3658 [0] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2845: Old ports: A=5'00011, B=5'10110, Y=$auto$wreduce.cc:461:run$3657 [4:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3657 [2] $auto$wreduce.cc:461:run$3657 [0] } New connections: { $auto$wreduce.cc:461:run$3657 [4:3] $auto$wreduce.cc:461:run$3657 [1] } = { $auto$wreduce.cc:461:run$3657 [2] 2'01 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2896: Old ports: A={ 1'0 $auto$wreduce.cc:461:run$3658 [4:0] }, B={ 1'0 $auto$wreduce.cc:461:run$3657 [4:0] }, Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] New ports: A=$auto$wreduce.cc:461:run$3658 [4:0], B=$auto$wreduce.cc:461:run$3657 [4:0], Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [4:0] New connections: $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [5] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3007: Old ports: A=6'000000, B=6'101110, Y=$flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] New connections: { $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [5:2] $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [0] } = { $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] 1'0 $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] 1'0 } Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:102$38: Old ports: A=2'11, B=2'01, Y=\SOC.Core.Control_Unit.second_block_write_src_b [1:0] New ports: A=1'1, B=1'0, Y=\SOC.Core.Control_Unit.second_block_write_src_b [1] New connections: \SOC.Core.Control_Unit.second_block_write_src_b [0] = 1'1 Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$1848: Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:20] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] 20'00000000000000000000 \SOC.Core.instruction_register [31:20] 27'000000000000000000000000000 \SOC.Core.instruction_register [24:20] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] New ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:25] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] 1'0 \SOC.Core.instruction_register [31:25] 8'00000000 }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12:5] New connections: { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [31:13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] \SOC.Core.instruction_register [24:20] } Consolidated identical input bits for $pmux cell $flatten\SOC.\Memory.$procmux$1459: Old ports: A=\SOC.Memory.buffer, B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7:0] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:0] 24'000000000000000000000000 \SOC.Memory.buffer [7:0] 16'0000000000000000 \SOC.Memory.buffer [15:0] }, Y=\SOC.Bus.slave_0_read_data New ports: A=\SOC.Memory.buffer [31:8], B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:8] 40'0000000000000000000000000000000000000000 \SOC.Memory.buffer [15:8] }, Y=\SOC.Bus.slave_0_read_data [31:8] New connections: \SOC.Bus.slave_0_read_data [7:0] = \SOC.Memory.buffer [7:0] New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$1738: $auto$opt_reduce.cc:134:opt_pmux$4644 New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$1752: { $flatten\SOC.\Uart.$procmux$1746_CMP $flatten\SOC.\Uart.$procmux$1688_CMP $auto$opt_reduce.cc:134:opt_pmux$4646 $flatten\SOC.\Uart.$procmux$1669_Y } Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.$procmux$1769: Old ports: A=4'0001, B=16'0110011110001001, Y=$flatten\SOC.\Uart.$procmux$1769_Y New ports: A=3'001, B=12'010011100101, Y={ $flatten\SOC.\Uart.$procmux$1769_Y [3] $flatten\SOC.\Uart.$procmux$1769_Y [1:0] } New connections: $flatten\SOC.\Uart.$procmux$1769_Y [2] = $flatten\SOC.\Uart.$procmux$1769_Y [1] Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_rx.$procmux$1273: Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$3679 [0] 1'0 $auto$wreduce.cc:461:run$3680 [1:0] 2'01 \SOC.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$3682 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$3679 [0] $auto$wreduce.cc:461:run$3680 [1:0] 1'1 \SOC.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$3682 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state [1:0] New connections: \SOC.Uart.i_uart_rx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:113$1018: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3682 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3682 [0] New connections: $auto$wreduce.cc:461:run$3682 [1] = $auto$wreduce.cc:461:run$3682 [0] Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$1410: Old ports: A=3'000, B={ 2'00 \SOC.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$3684 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$3686 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state New ports: A=2'00, B={ 1'0 \SOC.Uart.uart_tx_en $auto$wreduce.cc:461:run$3684 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$3686 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0] New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:97$961: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3686 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3686 [0] New connections: $auto$wreduce.cc:461:run$3686 [1] = $auto$wreduce.cc:461:run$3686 [0] New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$4645: { $flatten\SOC.\Uart.$procmux$1716_CMP $flatten\SOC.\Uart.$procmux$1715_CMP $flatten\SOC.\Uart.$procmux$1714_CMP $flatten\SOC.\Uart.$procmux$1713_CMP $flatten\SOC.\Uart.$procmux$1663_CMP $flatten\SOC.\Uart.$procmux$1644_CMP } Optimizing cells in module \top. Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$3829: Old ports: A=$auto$rtlil.cc:2582:Mux$3826, B={ \SOC.Memory.buffer [31:8] \SOC.Leds.write_data [7:6] \SOC.GPIOS.write_data [5:0] }, Y=$auto$rtlil.cc:2582:Mux$3830 New ports: A={ $auto$rtlil.cc:2582:Mux$3826 [31:16] \SOC.Leds.write_data [15:8] }, B=\SOC.Memory.buffer [31:8], Y=$auto$rtlil.cc:2582:Mux$3830 [31:8] New connections: $auto$rtlil.cc:2582:Mux$3830 [7:0] = { \SOC.Leds.write_data [7:6] \SOC.GPIOS.write_data [5:0] } Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$1973: Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$1967_Y, Y=$flatten\ResetBootSystem.$procmux$1973_Y New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$1967_Y [1], Y=$flatten\ResetBootSystem.$procmux$1973_Y [1] New connections: $flatten\ResetBootSystem.$procmux$1973_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2449: Old ports: A=6'100001, B=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0], Y=$flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] New ports: A=2'01, B={ $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] }, Y={ $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [2] $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [0] } New connections: { $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [5:3] $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [1] } = { $flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0] [0] 3'000 } Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.$procmux$1774: Old ports: A=4'0000, B=$flatten\SOC.\Uart.$procmux$1769_Y, Y=$flatten\SOC.\Uart.$procmux$1774_Y New ports: A=3'000, B={ $flatten\SOC.\Uart.$procmux$1769_Y [3] $flatten\SOC.\Uart.$procmux$1769_Y [1:0] }, Y={ $flatten\SOC.\Uart.$procmux$1774_Y [3] $flatten\SOC.\Uart.$procmux$1774_Y [1:0] } New connections: $flatten\SOC.\Uart.$procmux$1774_Y [2] = $flatten\SOC.\Uart.$procmux$1774_Y [1] Optimizing cells in module \top. Performed a total of 38 changes. 22.30.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~12 debug messages> Removed a total of 4 cells. 22.30.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$3528 ($dffe) from module top (D = $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:115$891_Y, Q = \SOC.Uart.counter, rval = 3'000). 22.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 2 unused cells and 7 unused wires. <suppressed ~3 debug messages> 22.30.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~8 debug messages> 22.30.9. Rerunning OPT passes. (Maybe there is more to do..) 22.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $flatten\SOC.\Core.\MemoryAddressMUX.$ternary$Risco-5/src/core/mux.v:16$142. Removed 1 multiplexer ports. <suppressed ~63 debug messages> 22.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2896: Old ports: A={ $auto$wreduce.cc:461:run$3657 [4] $auto$wreduce.cc:461:run$3657 [4] $auto$wreduce.cc:461:run$3657 [0] 1'0 $auto$wreduce.cc:461:run$3657 [0] }, B={ $auto$wreduce.cc:461:run$3657 [4] 1'0 $auto$wreduce.cc:461:run$3657 [4] 1'1 $auto$wreduce.cc:461:run$3657 [0] }, Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [4:0] New ports: A={ $auto$wreduce.cc:461:run$3657 [4] $auto$wreduce.cc:461:run$3657 [0] 1'0 }, B={ 1'0 $auto$wreduce.cc:461:run$3657 [4] 1'1 }, Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [3:1] New connections: { $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [4] $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [0] } = { $auto$wreduce.cc:461:run$3657 [4] $auto$wreduce.cc:461:run$3657 [0] } Optimizing cells in module \top. Performed a total of 1 changes. 22.30.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.30.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3438 ($sdff) from module top. 22.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 6 unused wires. <suppressed ~1 debug messages> 22.30.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~2 debug messages> 22.30.16. Rerunning OPT passes. (Maybe there is more to do..) 22.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~64 debug messages> 22.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.30.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.30.20. Executing OPT_DFF pass (perform DFF optimizations). 22.30.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.30.22. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.30.23. Finished OPT passes. (There is nothing left to do.) 22.31. Executing TECHMAP pass (map to technology primitives). 22.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 22.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ecp5_alu'. Successfully finished Verilog frontend. 22.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $sdffce. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $dffe. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $eq. Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $reduce_bool. Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu. Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $or. Using template $paramod$2407ada40cc3dda6c6015be2b49b748cddb5a800\_90_demux for cells of type $demux. Using extmapper simplemap for cells of type $bmux. Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $dff. Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $tribuf. Using extmapper simplemap for cells of type $logic_and. Using template $paramod$b098bc6f249c0ac91c4d6e19d54b23c285914115\_90_pmux for cells of type $pmux. Using template $paramod$20d3ee62d72123142eb855d7ddafd835e31ba009\_90_pmux for cells of type $pmux. Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $sdff. Using template $paramod$a04dd9d4d8b430140c4ff94b50470fb380fda2a0\_80_ecp5_alu for cells of type $alu. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $logic_or. Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu. Using template $paramod$19e9557905baa9d3741d0daa66e2ef076e9bab7d\_90_pmux for cells of type $pmux. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. Using template $paramod$2116a631f856d4d4902c2618dca73dafa3b8c9c0\_90_alu for cells of type $alu. Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. Using template $paramod$4d45682f6d5f8751d24fc75184ef72226da353f7\_90_pmux for cells of type $pmux. Using template $paramod$e13ed4cc4d636b3e93547ec233231d1aa3a8ac92\_90_pmux for cells of type $pmux. Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux. Using template $paramod$e25898cce02b4d043ab08e065e45db8cf66c901c\_90_pmux for cells of type $pmux. Using template $paramod$a285b5a57fe61eabc57c91b8c412748ee1151a85\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $reduce_xor. Using template $paramod$95ab7b964273918a033d1324366ecc612d202989\_90_pmux for cells of type $pmux. Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\_90_pmux for cells of type $pmux. Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $dlatch. Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$f5c0c5233796d8af9071458034942fe6bc61211e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr. Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$56955d0f36f77738c952d3505dc563df3ee11b94\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr. Using template $paramod$constmap:b9a86d073741c2a0f7bb241e73c2dd11747f3288$paramod$dce7c1188cb25d2520d170426d59301c3b73f9e7\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using template $paramod$ed6389a5938b09f91843a91d67becca5abedb1bd\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $xor. Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu. Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux. Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux. Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux. No more expansions possible. <suppressed ~4177 debug messages> 22.32. Executing OPT pass (performing simple optimizations). 22.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~5872 debug messages> 22.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~4374 debug messages> Removed a total of 1458 cells. 22.32.3. Executing OPT_DFF pass (perform DFF optimizations). 22.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 434 unused cells and 3307 unused wires. <suppressed ~435 debug messages> 22.32.5. Finished fast OPT passes. 22.33. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 22.35. Executing TECHMAP pass (map to technology primitives). 22.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 22.35.2. Continuing TECHMAP pass. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_. Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_. Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_. No more expansions possible. <suppressed ~1009 debug messages> 22.36. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~21 debug messages> 22.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 22.38. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in top. 22.39. Executing ATTRMVCP pass (move or copy attributes). 22.40. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 5144 unused wires. <suppressed ~1 debug messages> 22.41. Executing TECHMAP pass (map to technology primitives). 22.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 22.41.2. Continuing TECHMAP pass. 22.41.3. Executing SIMPLEMAP pass (map simple cells to gate primitives). Mapping \$_DLATCH_N_.$ternary$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$23752 ($mux). Mapping \$_DLATCH_N_.$logic_not$/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v:4$23751 ($logic_not). <suppressed ~4 debug messages> 22.41.4. Executing OPT pass (performing simple optimizations). 22.41.4.1. Executing OPT_EXPR pass (perform const folding). Optimizing module \$_DLATCH_N_. <suppressed ~1 debug messages> 22.41.4.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\$_DLATCH_N_'. Removed a total of 0 cells. 22.41.4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \$_DLATCH_N_.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 22.41.4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \$_DLATCH_N_. Performed a total of 0 changes. 22.41.4.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\$_DLATCH_N_'. Removed a total of 0 cells. 22.41.4.6. Executing OPT_DFF pass (perform DFF optimizations). 22.41.4.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \$_DLATCH_N_.. Removed 1 unused cells and 2 unused wires. <suppressed ~2 debug messages> 22.41.4.8. Executing OPT_EXPR pass (perform const folding). Optimizing module \$_DLATCH_N_. 22.41.4.9. Rerunning OPT passes. (Maybe there is more to do..) 22.41.4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \$_DLATCH_N_.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 22.41.4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \$_DLATCH_N_. Performed a total of 0 changes. 22.41.4.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\$_DLATCH_N_'. Removed a total of 0 cells. 22.41.4.13. Executing OPT_DFF pass (perform DFF optimizations). 22.41.4.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \$_DLATCH_N_.. 22.41.4.15. Executing OPT_EXPR pass (perform const folding). Optimizing module \$_DLATCH_N_. 22.41.4.16. Finished OPT passes. (There is nothing left to do.) Using template \$_DLATCH_N_ for cells of type $_DLATCH_N_. No more expansions possible. <suppressed ~4 debug messages> 22.42. Executing ABC9 pass. 22.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.3. Executing PROC pass (convert processes to netlists). 22.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23856'. Cleaned up 1 empty switch. 22.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23857 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.3.4. Executing PROC_INIT pass (extract init attributes). 22.42.3.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23857'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23855_EN[3:0]$23862 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23855_DATA[3:0]$23861 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23855_ADDR[3:0]$23863 Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23856'. 22.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23841_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23848_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23846_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23850_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23854_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23845_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23853_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23840_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23849_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23844_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23839_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23852_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23847_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23842_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23851_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23843_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. created direct connection (no actual register cell created). Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23855_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23857'. created $dff cell `$procdff$23907' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23855_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23857'. created $dff cell `$procdff$23908' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23855_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23857'. created $dff cell `$procdff$23909' with positive edge clock. Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23856'. created direct connection (no actual register cell created). 22.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23881'. Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23857'. Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23856'. Cleaned up 1 empty switch. 22.42.3.12. Executing OPT_EXPR pass (perform const folding). 22.42.4. Executing PROC pass (convert processes to netlists). 22.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23927'. Cleaned up 1 empty switch. 22.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23928 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.4.4. Executing PROC_INIT pass (extract init attributes). 22.42.4.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23928'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23926_EN[3:0]$23934 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23926_DATA[3:0]$23932 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23926_ADDR[3:0]$23933 Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23927'. 22.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23910_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23925_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23920_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23915_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23912_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23916_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23917_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23913_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23921_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23922_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23918_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23911_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23914_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23919_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23923_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23924_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23926_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23928'. created $dff cell `$procdff$23978' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23926_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23928'. created $dff cell `$procdff$23979' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23926_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23928'. created $dff cell `$procdff$23980' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23927'. created direct connection (no actual register cell created). 22.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$23952'. Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23928'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23927'. Cleaned up 1 empty switch. 22.42.4.12. Executing OPT_EXPR pass (perform const folding). 22.42.5. Executing PROC pass (convert processes to netlists). 22.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23998'. Cleaned up 1 empty switch. 22.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23999 in module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.5.4. Executing PROC_INIT pass (extract init attributes). 22.42.5.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.5.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. Creating decoders for process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23999'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23997_EN[3:0]$24003 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23997_DATA[3:0]$24004 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23997_ADDR[3:0]$24005 Creating decoders for process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23998'. 22.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.\i' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23996_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23995_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23990_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23989_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23984_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23994_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23983_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23993_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23992_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23988_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23987_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23986_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23982_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23991_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23985_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$23981_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. created direct connection (no actual register cell created). Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23997_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23999'. created $dff cell `$procdff$24049' with positive edge clock. Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23997_DATA' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23999'. created $dff cell `$procdff$24050' with positive edge clock. Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$23997_ADDR' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23999'. created $dff cell `$procdff$24051' with positive edge clock. Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23998'. created direct connection (no actual register cell created). 22.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24023'. Found and cleaned up 1 empty switch in `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$23999'. Removing empty process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$23998'. Cleaned up 1 empty switch. 22.42.5.12. Executing OPT_EXPR pass (perform const folding). 22.42.6. Executing PROC pass (convert processes to netlists). 22.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24069'. Cleaned up 1 empty switch. 22.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24070 in module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.6.4. Executing PROC_INIT pass (extract init attributes). 22.42.6.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.6.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. Creating decoders for process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24070'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24068_EN[3:0]$24076 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24068_DATA[3:0]$24075 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24068_ADDR[3:0]$24074 Creating decoders for process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24069'. 22.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.\i' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24052_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24056_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24057_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24058_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24062_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24063_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24053_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24064_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24059_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24067_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24061_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24055_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24054_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24065_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24060_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24066_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. created direct connection (no actual register cell created). Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24068_ADDR' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24070'. created $dff cell `$procdff$24120' with positive edge clock. Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24068_DATA' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24070'. created $dff cell `$procdff$24121' with positive edge clock. Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24068_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24070'. created $dff cell `$procdff$24122' with positive edge clock. Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.\muxwre' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24069'. created direct connection (no actual register cell created). 22.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24094'. Found and cleaned up 1 empty switch in `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24070'. Removing empty process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24069'. Cleaned up 1 empty switch. 22.42.6.12. Executing OPT_EXPR pass (perform const folding). 22.42.7. Executing PROC pass (convert processes to netlists). 22.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24140'. Cleaned up 1 empty switch. 22.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24141 in module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.7.4. Executing PROC_INIT pass (extract init attributes). 22.42.7.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.7.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. Creating decoders for process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24141'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24139_EN[3:0]$24146 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24139_DATA[3:0]$24145 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24139_ADDR[3:0]$24147 Creating decoders for process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24140'. 22.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.\i' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24136_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24130_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24135_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24133_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24126_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24127_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24132_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24138_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24124_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24129_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24134_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24137_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24131_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24125_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24123_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24128_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. created direct connection (no actual register cell created). Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24139_DATA' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24141'. created $dff cell `$procdff$24191' with positive edge clock. Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24139_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24141'. created $dff cell `$procdff$24192' with positive edge clock. Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24139_ADDR' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24141'. created $dff cell `$procdff$24193' with positive edge clock. Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.\muxwre' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24140'. created direct connection (no actual register cell created). 22.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24165'. Found and cleaned up 1 empty switch in `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24141'. Removing empty process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24140'. Cleaned up 1 empty switch. 22.42.7.12. Executing OPT_EXPR pass (perform const folding). 22.42.8. Executing PROC pass (convert processes to netlists). 22.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24211'. Cleaned up 1 empty switch. 22.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24212 in module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.8.4. Executing PROC_INIT pass (extract init attributes). 22.42.8.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.8.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. Creating decoders for process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24212'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24210_EN[3:0]$24217 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24210_DATA[3:0]$24216 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24210_ADDR[3:0]$24218 Creating decoders for process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24211'. 22.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24203_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.\i' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24196_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24197_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24202_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24198_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24199_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24209_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24194_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24206_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24208_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24204_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24207_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24201_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24195_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24205_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24200_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. created direct connection (no actual register cell created). Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24210_DATA' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24212'. created $dff cell `$procdff$24262' with positive edge clock. Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24210_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24212'. created $dff cell `$procdff$24263' with positive edge clock. Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24210_ADDR' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24212'. created $dff cell `$procdff$24264' with positive edge clock. Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.\muxwre' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24211'. created direct connection (no actual register cell created). 22.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24236'. Found and cleaned up 1 empty switch in `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24212'. Removing empty process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24211'. Cleaned up 1 empty switch. 22.42.8.12. Executing OPT_EXPR pass (perform const folding). 22.42.9. Executing PROC pass (convert processes to netlists). 22.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24282'. Cleaned up 1 empty switch. 22.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24283 in module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.9.4. Executing PROC_INIT pass (extract init attributes). 22.42.9.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.9.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. Creating decoders for process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24283'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24281_EN[3:0]$24289 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24281_DATA[3:0]$24288 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24281_ADDR[3:0]$24287 Creating decoders for process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24282'. 22.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.\i' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24267_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24266_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24268_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24272_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24273_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24274_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24278_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24280_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24279_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24269_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24275_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24270_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24276_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24265_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24277_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24271_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. created direct connection (no actual register cell created). Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24281_ADDR' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24283'. created $dff cell `$procdff$24333' with positive edge clock. Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24281_DATA' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24283'. created $dff cell `$procdff$24334' with positive edge clock. Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24281_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24283'. created $dff cell `$procdff$24335' with positive edge clock. Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24282'. created direct connection (no actual register cell created). 22.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24307'. Found and cleaned up 1 empty switch in `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24283'. Removing empty process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24282'. Cleaned up 1 empty switch. 22.42.9.12. Executing OPT_EXPR pass (perform const folding). 22.42.10. Executing PROC pass (convert processes to netlists). 22.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24353'. Cleaned up 1 empty switch. 22.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24354 in module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.10.4. Executing PROC_INIT pass (extract init attributes). 22.42.10.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.10.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. Creating decoders for process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24354'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24352_EN[3:0]$24358 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24352_DATA[3:0]$24360 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24352_ADDR[3:0]$24359 Creating decoders for process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24353'. 22.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.\i' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24336_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24337_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24338_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24343_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24344_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24348_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24349_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24339_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24350_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24340_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24345_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24351_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24347_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24341_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24342_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24346_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. created direct connection (no actual register cell created). Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24352_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24354'. created $dff cell `$procdff$24404' with positive edge clock. Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24352_ADDR' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24354'. created $dff cell `$procdff$24405' with positive edge clock. Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24352_DATA' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24354'. created $dff cell `$procdff$24406' with positive edge clock. Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.\muxwre' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24353'. created direct connection (no actual register cell created). 22.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24378'. Found and cleaned up 1 empty switch in `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24354'. Removing empty process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24353'. Cleaned up 1 empty switch. 22.42.10.12. Executing OPT_EXPR pass (perform const folding). 22.42.11. Executing PROC pass (convert processes to netlists). 22.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24424'. Cleaned up 1 empty switch. 22.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24425 in module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.11.4. Executing PROC_INIT pass (extract init attributes). 22.42.11.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.11.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. Creating decoders for process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24425'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24423_EN[3:0]$24430 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24423_DATA[3:0]$24429 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24423_ADDR[3:0]$24431 Creating decoders for process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24424'. 22.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.\i' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24407_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24408_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24412_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24413_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24419_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24409_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24420_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24410_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24415_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24422_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24418_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24416_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24417_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24411_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24421_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24414_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24423_DATA' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24425'. created $dff cell `$procdff$24475' with positive edge clock. Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24423_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24425'. created $dff cell `$procdff$24476' with positive edge clock. Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24423_ADDR' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24425'. created $dff cell `$procdff$24477' with positive edge clock. Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.\muxwre' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24424'. created direct connection (no actual register cell created). 22.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24449'. Found and cleaned up 1 empty switch in `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24425'. Removing empty process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24424'. Cleaned up 1 empty switch. 22.42.11.12. Executing OPT_EXPR pass (perform const folding). 22.42.12. Executing PROC pass (convert processes to netlists). 22.42.12.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24495'. Cleaned up 1 empty switch. 22.42.12.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24496 in module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 22.42.12.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 22.42.12.4. Executing PROC_INIT pass (extract init attributes). 22.42.12.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.12.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 22.42.12.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. Creating decoders for process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24496'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24494_EN[3:0]$24502 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24494_DATA[3:0]$24501 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24494_ADDR[3:0]$24500 Creating decoders for process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24495'. 22.42.12.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.12.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.\i' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24480_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24488_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24483_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24482_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24486_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24491_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24489_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24485_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24493_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24487_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24481_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24490_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24479_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24478_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24484_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$24492_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. created direct connection (no actual register cell created). Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24494_ADDR' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24496'. created $dff cell `$procdff$24546' with positive edge clock. Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24494_DATA' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24496'. created $dff cell `$procdff$24547' with positive edge clock. Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$24494_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24496'. created $dff cell `$procdff$24548' with positive edge clock. Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24495'. created direct connection (no actual register cell created). 22.42.12.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.12.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$24520'. Found and cleaned up 1 empty switch in `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$24496'. Removing empty process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$24495'. Cleaned up 1 empty switch. 22.42.12.12. Executing OPT_EXPR pass (perform const folding). 22.42.13. Executing SCC pass (detecting logic loops). Found an SCC: $techmap$auto$ff.cc:266:slice$11164.$auto$simplemap.cc:267:simplemap_mux$23754 Found an SCC: $techmap$auto$ff.cc:266:slice$11163.$auto$simplemap.cc:267:simplemap_mux$23754 Found an SCC: $techmap$auto$ff.cc:266:slice$11162.$auto$simplemap.cc:267:simplemap_mux$23754 Found an SCC: $techmap$auto$ff.cc:266:slice$11161.$auto$simplemap.cc:267:simplemap_mux$23754 Found an SCC: $auto$simplemap.cc:38:simplemap_not$17907 $auto$ff.cc:266:slice$4741 $auto$ff.cc:479:convert_ce_over_srst$22843 $auto$simplemap.cc:126:simplemap_reduce$6451 $auto$simplemap.cc:38:simplemap_not$17905 $auto$ff.cc:266:slice$4739 $auto$ff.cc:479:convert_ce_over_srst$22839 $auto$simplemap.cc:126:simplemap_reduce$6452 $auto$ff.cc:266:slice$4740 $auto$ff.cc:479:convert_ce_over_srst$22841 $auto$opt_expr.cc:613:replace_const_cells$22805 $auto$ff.cc:266:slice$4736 $auto$ff.cc:479:convert_ce_over_srst$22833 $auto$simplemap.cc:126:simplemap_reduce$6224 $auto$simplemap.cc:126:simplemap_reduce$6456 $auto$simplemap.cc:126:simplemap_reduce$6454 $auto$simplemap.cc:126:simplemap_reduce$6450 $auto$simplemap.cc:38:simplemap_not$17903 $auto$alumacc.cc:485:replace_alu$3690.slice[0].ccu2c_i $auto$ff.cc:266:slice$4737 $auto$ff.cc:479:convert_ce_over_srst$22835 $auto$simplemap.cc:126:simplemap_reduce$6195 $auto$simplemap.cc:75:simplemap_bitop$6440 $auto$simplemap.cc:38:simplemap_not$6477 $auto$alumacc.cc:485:replace_alu$3690.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$3690.slice[2].ccu2c_i $auto$ff.cc:266:slice$4738 $auto$ff.cc:479:convert_ce_over_srst$22837 $auto$simplemap.cc:126:simplemap_reduce$6208 $auto$simplemap.cc:126:simplemap_reduce$6206 $auto$simplemap.cc:126:simplemap_reduce$6227 $auto$simplemap.cc:126:simplemap_reduce$6225 $auto$simplemap.cc:38:simplemap_not$6438 Found an SCC: $auto$simplemap.cc:38:simplemap_not$17741 $auto$ff.cc:266:slice$7380 $auto$simplemap.cc:126:simplemap_reduce$7516 $auto$simplemap.cc:126:simplemap_reduce$7501 $auto$ff.cc:266:slice$7381 $auto$opt_expr.cc:613:replace_const_cells$22703 $auto$ff.cc:266:slice$7383 $auto$simplemap.cc:75:simplemap_bitop$16547 $auto$simplemap.cc:196:simplemap_lognot$7521 $auto$simplemap.cc:126:simplemap_reduce$7519 $auto$simplemap.cc:126:simplemap_reduce$7517 $auto$simplemap.cc:126:simplemap_reduce$16554 $auto$opt_expr.cc:613:replace_const_cells$22721 $auto$simplemap.cc:267:simplemap_mux$16544 $auto$simplemap.cc:126:simplemap_reduce$16562 $auto$simplemap.cc:126:simplemap_reduce$16559 $auto$simplemap.cc:75:simplemap_bitop$16545 $auto$simplemap.cc:267:simplemap_mux$7486 $auto$simplemap.cc:225:simplemap_logbin$7489 $auto$simplemap.cc:196:simplemap_lognot$7506 $auto$simplemap.cc:126:simplemap_reduce$7504 $auto$simplemap.cc:126:simplemap_reduce$7502 $auto$ff.cc:266:slice$7382 $auto$simplemap.cc:126:simplemap_reduce$6414 $auto$simplemap.cc:126:simplemap_reduce$6412 $auto$simplemap.cc:225:simplemap_logbin$7443 $auto$simplemap.cc:196:simplemap_lognot$7453 $auto$simplemap.cc:126:simplemap_reduce$7451 $auto$opt_expr.cc:613:replace_const_cells$22723 $auto$simplemap.cc:267:simplemap_mux$16543 $auto$simplemap.cc:126:simplemap_reduce$16557 Found an SCC: $auto$ff.cc:266:slice$7384 $auto$ff.cc:266:slice$7386 $auto$ff.cc:266:slice$7389 $auto$ff.cc:266:slice$7392 $auto$ff.cc:266:slice$7385 $auto$simplemap.cc:38:simplemap_not$16494 $auto$ff.cc:266:slice$7390 $auto$simplemap.cc:126:simplemap_reduce$7539 $auto$opt_expr.cc:613:replace_const_cells$22693 $auto$ff.cc:266:slice$7391 $auto$simplemap.cc:126:simplemap_reduce$7542 $auto$simplemap.cc:126:simplemap_reduce$7538 $auto$simplemap.cc:38:simplemap_not$16492 $auto$ff.cc:266:slice$7388 $auto$simplemap.cc:126:simplemap_reduce$7537 $auto$simplemap.cc:38:simplemap_not$16491 $auto$ff.cc:266:slice$7387 $auto$simplemap.cc:126:simplemap_reduce$6408 $auto$simplemap.cc:196:simplemap_lognot$7548 $auto$simplemap.cc:126:simplemap_reduce$7546 $auto$simplemap.cc:126:simplemap_reduce$7544 $auto$simplemap.cc:126:simplemap_reduce$7541 $auto$simplemap.cc:126:simplemap_reduce$7536 $auto$simplemap.cc:38:simplemap_not$16488 Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$22739 $auto$ff.cc:266:slice$7215 $auto$ff.cc:266:slice$7223 $auto$opt_expr.cc:613:replace_const_cells$22731 $auto$ff.cc:266:slice$7222 $auto$simplemap.cc:38:simplemap_not$17695 $auto$ff.cc:266:slice$7219 $auto$simplemap.cc:126:simplemap_reduce$7362 $auto$simplemap.cc:126:simplemap_reduce$7335 $auto$simplemap.cc:38:simplemap_not$17696 $auto$ff.cc:266:slice$7220 $auto$simplemap.cc:126:simplemap_reduce$7366 $auto$simplemap.cc:126:simplemap_reduce$7363 $auto$simplemap.cc:126:simplemap_reduce$7339 $auto$simplemap.cc:126:simplemap_reduce$7336 $auto$simplemap.cc:38:simplemap_not$17697 $auto$ff.cc:266:slice$7221 $auto$simplemap.cc:126:simplemap_reduce$7360 $auto$simplemap.cc:126:simplemap_reduce$7333 $auto$ff.cc:266:slice$7216 $auto$opt_expr.cc:613:replace_const_cells$22747 $auto$ff.cc:266:slice$7217 $auto$simplemap.cc:196:simplemap_lognot$7372 $auto$simplemap.cc:126:simplemap_reduce$7370 $auto$simplemap.cc:126:simplemap_reduce$7368 $auto$simplemap.cc:126:simplemap_reduce$7365 $auto$simplemap.cc:126:simplemap_reduce$7361 $auto$simplemap.cc:126:simplemap_reduce$7338 $auto$simplemap.cc:126:simplemap_reduce$7334 $auto$opt_expr.cc:613:replace_const_cells$22737 $auto$ff.cc:266:slice$7218 $auto$simplemap.cc:167:logic_reduce$6419 $auto$simplemap.cc:225:simplemap_logbin$7317 $auto$simplemap.cc:225:simplemap_logbin$7318 $auto$simplemap.cc:196:simplemap_lognot$7345 $auto$simplemap.cc:126:simplemap_reduce$7343 $auto$simplemap.cc:126:simplemap_reduce$7341 Found an SCC: $auto$ff.cc:266:slice$9833 $auto$dfflegalize.cc:941:flip_pol$22851 $auto$ff.cc:485:convert_ce_over_srst$22849 $auto$simplemap.cc:126:simplemap_reduce$6547 $auto$opt_expr.cc:613:replace_const_cells$22319 $auto$ff.cc:266:slice$9832 $auto$dfflegalize.cc:941:flip_pol$22847 $auto$ff.cc:485:convert_ce_over_srst$22845 $auto$simplemap.cc:126:simplemap_reduce$6372 $auto$simplemap.cc:126:simplemap_reduce$6335 $auto$simplemap.cc:126:simplemap_reduce$6333 $auto$opt_expr.cc:613:replace_const_cells$22761 $auto$simplemap.cc:126:simplemap_reduce$6381 $auto$simplemap.cc:126:simplemap_reduce$6307 $auto$simplemap.cc:126:simplemap_reduce$6304 $auto$simplemap.cc:126:simplemap_reduce$6342 $auto$simplemap.cc:126:simplemap_reduce$6549 $auto$ff.cc:266:slice$9834 $auto$dfflegalize.cc:941:flip_pol$22855 $auto$ff.cc:485:convert_ce_over_srst$22853 $auto$simplemap.cc:126:simplemap_reduce$6309 $auto$simplemap.cc:126:simplemap_reduce$6305 $auto$simplemap.cc:126:simplemap_reduce$6374 Found 9 SCCs in module top. Found 9 SCCs. 22.42.14. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.15. Executing PROC pass (convert processes to netlists). 22.42.15.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 22.42.15.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 22.42.15.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 22.42.15.4. Executing PROC_INIT pass (extract init attributes). 22.42.15.5. Executing PROC_ARST pass (detect async resets in processes). 22.42.15.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 22.42.15.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 22.42.15.8. Executing PROC_DLATCH pass (convert process syncs to latches). 22.42.15.9. Executing PROC_DFF pass (convert process syncs to FFs). 22.42.15.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 22.42.15.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 22.42.15.12. Executing OPT_EXPR pass (perform const folding). 22.42.16. Executing TECHMAP pass (map to technology primitives). 22.42.16.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 22.42.16.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~180 debug messages> 22.42.17. Executing OPT pass (performing simple optimizations). 22.42.17.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4. Optimizing module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4. Optimizing module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4. Optimizing module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4. Optimizing module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4. Optimizing module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4. Optimizing module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4. Optimizing module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4. 22.42.17.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4'. Removed a total of 0 cells. 22.42.17.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 22.42.17.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing cells in module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4. Optimizing cells in module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4. Optimizing cells in module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4. Optimizing cells in module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4. Optimizing cells in module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4. Optimizing cells in module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4. Optimizing cells in module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4. Optimizing cells in module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4. Performed a total of 0 changes. 22.42.17.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4'. Finding identical cells in module `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4'. Removed a total of 0 cells. 22.42.17.6. Executing OPT_DFF pass (perform DFF optimizations). 22.42.17.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.. Finding unused cells or wires in module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.. 22.42.17.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4. Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Optimizing module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4. Optimizing module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4. Optimizing module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4. Optimizing module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4. Optimizing module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4. Optimizing module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4. Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Optimizing module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4. 22.42.17.9. Finished OPT passes. (There is nothing left to do.) 22.42.18. Executing TECHMAP pass (map to technology primitives). 22.42.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 22.42.18.2. Continuing TECHMAP pass. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Using template $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4 for cells of type $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4. Using template $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4 for cells of type $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4. Using template $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4 for cells of type $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4. Using template $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4 for cells of type $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4. Using template $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4 for cells of type $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4. Using template $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4 for cells of type $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4. Using template $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4 for cells of type $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4. Using template $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4 for cells of type $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. No more expansions possible. <suppressed ~320 debug messages> 22.42.19. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 22.42.20. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 22.42.21. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.22. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 22.42.23. Executing TECHMAP pass (map to technology primitives). 22.42.23.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 22.42.23.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $not. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using extmapper simplemap for cells of type $mux. No more expansions possible. <suppressed ~219 debug messages> 22.42.24. Executing OPT pass (performing simple optimizations). 22.42.24.1. Executing OPT_EXPR pass (perform const folding). Optimizing module top. <suppressed ~18 debug messages> 22.42.24.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 22.42.24.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 22.42.24.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.42.24.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.42.24.6. Executing OPT_DFF pass (perform DFF optimizations). 22.42.24.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. Removed 0 unused cells and 55 unused wires. <suppressed ~1 debug messages> 22.42.24.8. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.42.24.9. Rerunning OPT passes. (Maybe there is more to do..) 22.42.24.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 22.42.24.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \top. Performed a total of 0 changes. 22.42.24.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\top'. Removed a total of 0 cells. 22.42.24.13. Executing OPT_DFF pass (perform DFF optimizations). 22.42.24.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \top.. 22.42.24.15. Executing OPT_EXPR pass (perform const folding). Optimizing module top. 22.42.24.16. Finished OPT passes. (There is nothing left to do.) 22.42.25. Executing AIGMAP pass (map logic to AIG). Module top: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 2 $_OR_ 2 $_XOR_ 14 $_MUX_ not replaced 3 cell types: 31 $specify2 4 $_NOT_ 4 $_AND_ 22.42.26. Executing AIGMAP pass (map logic to AIG). Module top: replaced 4604 cells with 27518 new cells, skipped 2992 cells. replaced 4 cell types: 1566 $_OR_ 74 $_XOR_ 3 $_ORNOT_ 2961 $_MUX_ not replaced 27 cell types: 30 $scopeinfo 354 $_NOT_ 971 $_AND_ 6 $_TBUF_ 894 TRELLIS_FF 1 $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4 1 $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4 1 $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4 1 $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4 1 $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4 120 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 1 $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4 276 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4 276 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4_$abc9_byp 1 $__ABC9_SCC_BREAKER 1 $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4_$abc9_byp 1 $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4 22.42.26.1. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.26.2. Executing ABC9_OPS pass (helper functions for ABC9). 22.42.26.3. Executing XAIGER backend. <suppressed ~11 debug messages> Extracted 11645 AND gates and 33119 wires from module `top' to a netlist network with 2144 inputs and 827 outputs. 22.42.26.4. Executing ABC9_EXE pass (technology mapping using ABC9). 22.42.26.5. Executing ABC9. *** GOWIN Tcl Command Line Console *** current device: GW2AR-18C GW2AR-LV18QN88C8/I7 add new file: "pinout.cst" add new file: "top.sdc" add new file: "main.v" add new file: "../../debug/reset.v" add new file: "../../src/core/alu_control.v" add new file: "../../src/core/alu.v" add new file: "../../src/core/control_unit.v" add new file: "../../src/core/core.v" add new file: "../../src/core/immediate_generator.v" add new file: "../../src/core/mux.v" add new file: "../../src/core/pc.v" add new file: "../../src/core/registers.v" add new file: "../../src/core/csr_unit.v" add new file: "../../src/peripheral/bus.v" add new file: "../../src/peripheral/gpio.v" add new file: "../../src/peripheral/gpios.v" add new file: "../../src/peripheral/leds.v" add new file: "../../src/peripheral/memory.v" add new file: "../../src/peripheral/soc.v" add new file: "../../src/peripheral/uart_rx.v" add new file: "../../src/peripheral/uart_tx.v" add new file: "../../src/peripheral/uart.v" add new file: "../../src/peripheral/fifo.v" GowinSynthesis start Running parser ... Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v' Undeclared symbol 'pc_source', assumed default net type 'wire'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":142) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v' WARN (EX3801) : Parameter 'SET_DIRECTION' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":19) WARN (EX3801) : Parameter 'READ' becomes localparam in 'GPIOS' with formal parameter declaration list("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":20) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v' WARN (EX3012) : Empty statement in sequential block("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":54) Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v' Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v' WARN (EX3073) : Port 'resetn_o' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":18) Compiling module 'top'("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":1) Compiling module 'ResetBootSystem'("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":1) WARN (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":37) Compiling module 'Risco_5_SOC(CLOCK_FREQ=27000000,BIT_RATE=115200,MEMORY_SIZE=2048,MEMORY_FILE="../../software/memory/teste_uart_fpga.hex",UART_BUFFER_SIZE=16)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":1) Compiling module 'Core(BOOT_ADDRESS=32'b00000000000000000000000000000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":1) Compiling module 'PC'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v":1) Compiling module 'MUX'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v":1) Compiling module 'Registers'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v":1) Compiling module 'Control_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":1) WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":515) WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":522) WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":535) WARN (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":542) Compiling module 'ALU_Control'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":1) WARN (EX2420) : Latch inferred for net 'aluop_out[3]'; We do not recommend the use of latches in FPGA designs, as they may lead to timing problems("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":60) Compiling module 'Alu'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v":1) Compiling module 'Immediate_Generator'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v":1) Compiling module 'CSR_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":1) Compiling module 'Memory(MEMORY_FILE="../../software/memory/teste_uart_fpga.hex",MEMORY_SIZE=2048)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":1) Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":16) Compiling module 'BUS'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v":1) Compiling module 'LEDs'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":1) WARN (EX3791) : Expression size 33 truncated to fit in target size 32("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":21) Compiling module 'UART(CLK_FREQ=27000000,BIT_RATE=115200,BUFFER_SIZE=16)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v":1) WARN (EX3791) : Expression size 33 truncated to fit in target size 32("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v":101) Compiling module 'FIFO(DEPTH=16)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":1) Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":16) WARN (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":40) Compiling module 'uart_tool_rx(BIT_RATE=115200,CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v":10) Compiling module 'uart_tool_tx(BIT_RATE=115200,CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v":10) Compiling module 'GPIOS(WIDHT=5)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":1) Compiling module 'GPIO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v":1) WARN (EX2565) : Input 'halt' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_external' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_timer' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_software' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) WARN (EX2565) : Input 'interruption_request_fast[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43) NOTE (EX0101) : Current top module is "top" [5%] Running netlist conversion ... WARN (CV0016) : Input reset is unused("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":3) Running device independent optimization ... [10%] Optimizing Phase 0 completed [15%] Optimizing Phase 1 completed [25%] Optimizing Phase 2 completed Running inference ... [30%] Inferring Phase 0 completed [40%] Inferring Phase 1 completed [50%] Inferring Phase 2 completed [55%] Inferring Phase 3 completed Running technical mapping ... [60%] Tech-Mapping Phase 0 completed [65%] Tech-Mapping Phase 1 completed Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_lut <abc-temp-dir>/input.lut ABC: + read_box <abc-temp-dir>/input.box ABC: + &read <abc-temp-dir>/input.xaig ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 2144/ 827 and = 9907 lev = 57 (4.85) mem = 0.24 MB box = 428 bb = 308 ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 2144/ 827 and = 12437 lev = 64 (4.19) mem = 0.27 MB ch = 1339 box = 428 bb = 308 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 60. Obj = 140. Set = 636. CutMin = no ABC: Node = 12437. Ch = 1224. Total mem = 3.06 MB. Peak cut mem = 0.25 MB. ABC: P: Del = 7611.00. Ar = 14822.0. Edge = 16143. Cut = 163030. T = 0.04 sec ABC: P: Del = 7524.00. Ar = 15392.0. Edge = 16296. Cut = 157488. T = 0.04 sec ABC: P: Del = 7524.00. Ar = 6428.0. Edge = 12175. Cut = 427530. T = 0.10 sec ABC: F: Del = 7524.00. Ar = 4373.0. Edge = 10860. Cut = 375937. T = 0.09 sec ABC: A: Del = 7524.00. Ar = 4005.0. Edge = 10124. Cut = 326405. T = 0.12 sec ABC: A: Del = 7524.00. Ar = 3936.0. Edge = 10048. Cut = 355283. T = 0.13 sec ABC: Total time = 0.56 sec ABC: + &write -n <abc-temp-dir>/output.aig ABC: + &mfs ABC: + &ps -l ABC: <abc-temp-dir>/input : i/o = 2144/ 827 and = 8612 lev = 46 (4.31) mem = 0.22 MB box = 428 bb = 308 ABC: Mapping (K=7) : lut = 2595 edge = 9915 lev = 15 (2.41) levB = 32 mem = 0.12 MB ABC: LUT = 2595 : 2=298 11.5 % 3=608 23.4 % 4=1207 46.5 % 5=323 12.4 % 6=61 2.4 % 7=98 3.8 % Ave = 3.82 ABC: + &write -n <abc-temp-dir>/output.aig ABC: + time ABC: elapse: 8.35 seconds, total: 8.35 seconds 22.42.26.6. Executing AIGER frontend. <suppressed ~5954 debug messages> Removed 12323 unused cells and 21954 unused wires. 22.42.26.7. Executing ABC9_OPS pass (helper functions for ABC9). [75%] Tech-Mapping Phase 2 completed ABC RESULTS: $lut cells: 2624 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 120 ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 276 ABC RESULTS: $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells: 24 ABC RESULTS: $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4_$abc9_byp cells: 1 ABC RESULTS: input signals: 355 ABC RESULTS: output signals: 156 Removing temp directory. 22.42.27. Executing TECHMAP pass (map to technology primitives). 22.42.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 22.42.27.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4. Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4 for cells of type $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4. Using template $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000001011 for cells of type $__ABC9_SCC_BREAKER. Using template $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4 for cells of type $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4. Using template $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4 for cells of type $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4. Using template $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4 for cells of type $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4. Using template $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4 for cells of type $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4. Using template $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4 for cells of type $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4. Using template $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4 for cells of type $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4. Using template $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4 for cells of type $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4. Using template $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4_$abc9_byp. No more expansions possible. <suppressed ~774 debug messages> Removed 176 unused cells and 38291 unused wires. 22.43. Executing TECHMAP pass (map to technology primitives). 22.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 22.43.2. Continuing TECHMAP pass. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut. Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d\$lut for cells of type $lut. Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9\$lut for cells of type $lut. Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut. Using template $paramod$8fd8efe0a495790cc9ddc97266933ea8a8cd7b45\$lut for cells of type $lut. Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$059968be1ef12c596bb5d360a749040b6777bf4a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut. Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut. Using template $paramod$a197ef6f3b51d411ae3e5b42b5d77a606c4fb11a\$lut for cells of type $lut. Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut. Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. Using template $paramod$ccd3e15dc00d71b9284dff48e88ccef5be7362c8\$lut for cells of type $lut. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut. Using template $paramod$fb7bbfbe62f17d1abd6f8eaee546f5a966c46c29\$lut for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut. Using template $paramod$c8f2b00a2feb859040935d06cafa51f6c4e20e0d\$lut for cells of type $lut. Using template $paramod$9e1833a186966f2db3a6f246584a6f2d0abc1c40\$lut for cells of type $lut. Using template $paramod$5c3294d2efb88caf0474e72690e5c12ab871a3e8\$lut for cells of type $lut. Using template $paramod$df5c8730c0a53792c3f54c2192a2221c27162fb5\$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. Using template $paramod$3ddf1fe05cbbe1f70624cf84f3f82ca21c580b71\$lut for cells of type $lut. Using template $paramod$f397fc18133e056a9632f6a971b24996a57ad731\$lut for cells of type $lut. Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut. Using template $paramod$63114da772fb28945ba24699e32f1e30ca7142f4\$lut for cells of type $lut. Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod$f626b575273537b3090dbe5d04b27b283ec9a192\$lut for cells of type $lut. Using template $paramod$7491e7206ae8c682d288373efe06a43b67c277cf\$lut for cells of type $lut. Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut. Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut. Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011011 for cells of type $lut. Using template $paramod$4313d6a4df5be8d101d4989de89eeec5b7d9f7b3\$lut for cells of type $lut. Using template $paramod$a8b7516c4ccadf4ab65906113028f2819d14ea8b\$lut for cells of type $lut. Using template $paramod$75f6f0be508fd5e89f0b6f7cde2eae58888fb999\$lut for cells of type $lut. Using template $paramod$7927bcf0ebf9ad32c99c221ff948f324620c5795\$lut for cells of type $lut. Using template $paramod$e51b772fb31a0b1176ce6f7773dfe6e4e6384542\$lut for cells of type $lut. Using template $paramod$b37e021cada4da54ba4e35fdc50fbef18e4fff4e\$lut for cells of type $lut. Using template $paramod$206bcac7886fff6cc176ab966e5905c0892feaa0\$lut for cells of type $lut. Using template $paramod$e4ac2572f95de96a2a88c1fe38073cd9481b8eaa\$lut for cells of type $lut. Using template $paramod$de5074a80e0a92a065a2ccd0d26c618282111f8c\$lut for cells of type $lut. Using template $paramod$dc41a956c02896bb314b3585a99557a5e53688a4\$lut for cells of type $lut. Using template $paramod$774a669204184147b38453b69c15da44a7cf748f\$lut for cells of type $lut. Using template $paramod$e1fedc9e31e603b185870ecaa2d9ae21c31830e1\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$bce98cbc4c7663d9534fcdf870483176065e0cfd\$lut for cells of type $lut. Using template $paramod$a9fc6e1212e2c97f661279eebf7fa89d410eb14a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut. Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut. Using template $paramod$12d55b60f0f4993cdeef74f2f65f385722841c5f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut. Using template $paramod$d2714c8e745a1556f41422d88e68656f7be2eb51\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. Using template $paramod$1dd7a5c891be6b5e588bf490f9181c98b47eb85b\$lut for cells of type $lut. Using template $paramod$45d35c067ded9854bad436d064758afc38659286\$lut for cells of type $lut. Using template $paramod$f2c253cb1591c42693eb1b069547e485143b1380\$lut for cells of type $lut. Using template $paramod$001d9634602f00137f774620efde4c651c7a59ca\$lut for cells of type $lut. Using template $paramod$477da4277c03c2ef33b36398805e65ce04b52e70\$lut for cells of type $lut. Using template $paramod$2883108cb47604e8d9f302b6fd523eca1a3ace81\$lut for cells of type $lut. Using template $paramod$bde6c96e44b0f8e6d9db97eafdf28d77ceaa9a96\$lut for cells of type $lut. Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. Using template $paramod$e834b489836dc2a7c596ec512b5ef9ba9ad2775a\$lut for cells of type $lut. Using template $paramod$03254b0b74a5189a21be27a1c43c46b760fa1667\$lut for cells of type $lut. Using template $paramod$016c6b3e48d8831902f83ae4b26b25597f23e8f6\$lut for cells of type $lut. Using template $paramod$70a934594406e8042bf2854c778fef542ef3ea5f\$lut for cells of type $lut. Using template $paramod$f8e581416d80e5fec72b39b773d5caa38d849fd4\$lut for cells of type $lut. Using template $paramod$1160aede01e9ab6dcfa503383e2229788e9ffafa\$lut for cells of type $lut. Using template $paramod$c39b4ae3eed03ff4e0ef2a41844cc5ea3df00d09\$lut for cells of type $lut. Using template $paramod$2c35b9f28f24ebda7f83478d571e81b467da1e5a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111001 for cells of type $lut. Using template $paramod$839e999d5d6d8eb7437283d4e381e98fbb5a0661\$lut for cells of type $lut. Using template $paramod$3c1e0804d1af5aaa2e5655322bd9e7bbbb2824d7\$lut for cells of type $lut. Using template $paramod$d10d29a83d60e3648b73c68f96b306ed2c95752c\$lut for cells of type $lut. Using template $paramod$ee3ba3939f6ccdb74bf420a252d58cdb86511937\$lut for cells of type $lut. Using template $paramod$1e3591dfeb518b0c8652685df4a8b5656bda70e4\$lut for cells of type $lut. Using template $paramod$484ba5c141c51c4d427876f8fc46c5c9444310ea\$lut for cells of type $lut. Using template $paramod$82a63e9f3e2dbe14a104845bd1f28d8c531231c1\$lut for cells of type $lut. Using template $paramod$91d8a65ba401a359c939c05b1ef35906ed49f46c\$lut for cells of type $lut. Using template $paramod$519c6505614669234b4f1b4f9e828dfdf30342c3\$lut for cells of type $lut. Using template $paramod$20aed23cfb094b5b509692d283e984fd3ae774ee\$lut for cells of type $lut. Using template $paramod$e0286d7bdebdb6346cb367bb1962e01892ba2e32\$lut for cells of type $lut. Using template $paramod$d2a869c5b04ed722d58afd0416d02bc935977960\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut. Using template $paramod$b6d7b8802225d3fe3444a1b7fbd727be1d62f151\$lut for cells of type $lut. Using template $paramod$c39ac4152492f4d6cc3ff7242ee0430dc69040dc\$lut for cells of type $lut. Using template $paramod$c78b629ab7f81eac7af8758481352cb811c66fac\$lut for cells of type $lut. Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut. Using template $paramod$0c4bf7f90dfa61960f1a574188c7812e994dad89\$lut for cells of type $lut. Using template $paramod$057ec71729eca16233589e1a8c2264ade2c2bf20\$lut for cells of type $lut. Using template $paramod$64c98a93c00f2932cdb01ce29e3a216b58ad51fe\$lut for cells of type $lut. Using template $paramod$f19e0addf0432e011114eb8bbb6406e1dcb11806\$lut for cells of type $lut. Using template $paramod$42d0b0a209a5f6c215d0ed73d1e9e0b51376abab\$lut for cells of type $lut. Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut. Using template $paramod$4834046533425f54583d6bd31e49deb63455e1a5\$lut for cells of type $lut. Using template $paramod$5ce73828b344e16078d967e70a9dd3a5947a62ef\$lut for cells of type $lut. Using template $paramod$39609bab676feaa12362bba2f22c314b1812df3f\$lut for cells of type $lut. Using template $paramod$a3fda36819921c4387df4e71d21434c8bddecb9d\$lut for cells of type $lut. Using template $paramod$d89685a2e05dd7a5927850f88c298f6b8adf4958\$lut for cells of type $lut. Using template $paramod$f940b3836b816258cf0bf1afa7ea5d3b0e7a8025\$lut for cells of type $lut. Using template $paramod$1484e566cd9b267bc86d8f478764b9c8f5d2cfda\$lut for cells of type $lut. Using template $paramod$74c0f3179b5cebe485563ea55e9b637e7ee5c0c3\$lut for cells of type $lut. Using template $paramod$38400b76de2b00d7d5f8f09de118b82fd1b8be0a\$lut for cells of type $lut. Using template $paramod$8c44cb82fe5eb5fdc35eb37d69d525d979e8ea29\$lut for cells of type $lut. Using template $paramod$eddf9bacb9fcc52ccbe510b8a241ce669774b5ae\$lut for cells of type $lut. Using template $paramod$1388910074660eccb2997958ff0ebc81267551ac\$lut for cells of type $lut. Using template $paramod$dc8eb389b2fc3ec6a78d93ff9b548b7fd27b6950\$lut for cells of type $lut. Using template $paramod$94e65f323749ab2f501acf5577af42456678fff9\$lut for cells of type $lut. Using template $paramod$2c1875de701f39453798b76f5b327fe456cc0991\$lut for cells of type $lut. Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc\$lut for cells of type $lut. Using template $paramod$6e2b27a23561eba4d5d7a3612a01502854865858\$lut for cells of type $lut. Using template $paramod$05c5f6a110cf1477117aed2d0c02c0941fa470d5\$lut for cells of type $lut. Using template $paramod$b2a4860cd839ff40d9dca4c3f237b2b534267028\$lut for cells of type $lut. Using template $paramod$5592e32ec588080518282546fe4472f0960034a5\$lut for cells of type $lut. Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod$446d5374f1a9a50c11eb107999155fc0219be593\$lut for cells of type $lut. Using template $paramod$e484b1e0bd351ba5af34f5fd66a8e850cc5b8335\$lut for cells of type $lut. Using template $paramod$e4194407746abfe058895841c3172bf999a9aea8\$lut for cells of type $lut. Using template $paramod$138cb12c2aeb8bc72920026ffe90a83668621cff\$lut for cells of type $lut. Using template $paramod$52db6bb7957e1ac14a8a12d878c26f69b361d8f4\$lut for cells of type $lut. Using template $paramod$2edd70269a3d9c60910e16ab662036c0bfc68f99\$lut for cells of type $lut. Using template $paramod$ded47024c1e124b6a6f34673c4b4fa433fc51973\$lut for cells of type $lut. Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut. Using template $paramod$75d5c453cca75cc7a7ca320c4fb7be0932b6aaa7\$lut for cells of type $lut. Using template $paramod$4c0221505c29b55a66f4801128a7e9ab143964dc\$lut for cells of type $lut. Using template $paramod$a499ab036f8e9e3a2a354adde65e5565a4c54f48\$lut for cells of type $lut. Using template $paramod$a5810b3064bbc05b2c453025774af99926f05666\$lut for cells of type $lut. Using template $paramod$9d2bc8567cb21a9a4d5b9dc8ad6814de07860744\$lut for cells of type $lut. Using template $paramod$3d98cbd933baee327b5d76a0c6e6cddc5563d2bd\$lut for cells of type $lut. Using template $paramod$a4404e742e43b8bf8bde71df8b64cbe0c6ba02bd\$lut for cells of type $lut. Using template $paramod$41271b185c0299e54b5a93c3a0fde10b3867cc20\$lut for cells of type $lut. Using template $paramod$544249908774c7a1dca2fc8a3c7177a6481326c2\$lut for cells of type $lut. Using template $paramod$df429cc43592bbf0319e70d604a42d52a9cf6f5e\$lut for cells of type $lut. Using template $paramod$9e8f31376df946f3035e5c8587caff26c5cadef3\$lut for cells of type $lut. Using template $paramod$7bee76741eb51df66260977432d861248a5c6f1e\$lut for cells of type $lut. Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut. Using template $paramod$a50f1c411368f4b7b265d7b2b2e06d07b921e41d\$lut for cells of type $lut. Using template $paramod$1dbc005c3ca46176ed5f71d3318762a2498d170f\$lut for cells of type $lut. Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut. Using template $paramod$44587907eb547902863ad65ee925d87164ab0cc4\$lut for cells of type $lut. Using template $paramod$d6000d96f7daae023aea1d235aa57406d3b9e9d2\$lut for cells of type $lut. Using template $paramod$90746f9df6189ff182ef59b9886f8bfd02877b10\$lut for cells of type $lut. Using template $paramod$6c51c1ba6c39f0c09b896d52432b366f116bd3c1\$lut for cells of type $lut. Using template $paramod$651e836885d95717c36e69441422c3fe04ee5f4d\$lut for cells of type $lut. Using template $paramod$1a10df59f43f252ae2ee713b788731ad5d18c6f5\$lut for cells of type $lut. Using template $paramod$98952e7df78e79758a5486ff33df5300f3e245a4\$lut for cells of type $lut. Using template $paramod$596ad0b7767e5887bee0132d372815146b00b3d8\$lut for cells of type $lut. Using template $paramod$7bea309d7d8ce7961641c3f6a135f4cf429f27ee\$lut for cells of type $lut. Using template $paramod$d6199152dfe33a54ba53b6c297ad544f87120cc3\$lut for cells of type $lut. Using template $paramod$9ff5810d0d4313c60ea05d2ef2f28b920dd1f8ee\$lut for cells of type $lut. Using template $paramod$d8119e7cf18bdd1d72e1822e569d9c40a2fc5848\$lut for cells of type $lut. Using template $paramod$0ee0167fb5dd83bdfe7197fff23e2c7146c57037\$lut for cells of type $lut. Using template $paramod$243bb36d22429e9a7da808df9977557ddc9af8b1\$lut for cells of type $lut. Using template $paramod$323dbb47a6d14615772fecb6fe7c4bec277e6c6b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut. Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut. Using template $paramod$adc0b354bb960519a616db7423a6274fc380540e\$lut for cells of type $lut. Using template $paramod$c990f7379e83ad809a31b86179f8fefe4157407d\$lut for cells of type $lut. Using template $paramod$c300babb3a57c71f3e871162e0ddccef1b7e02eb\$lut for cells of type $lut. Using template $paramod$f8cfc0cf2fe9042f3d2a22988630f603b85823b8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001000 for cells of type $lut. Using template $paramod$ef1cc14162296fd4d0d07385991da6aec0946444\$lut for cells of type $lut. Using template $paramod$11b6a2e0b5538d16dbffc5ea22a12a0e43c1e883\$lut for cells of type $lut. Using template $paramod$2e91260c662bedefee0c75d5d1389234e222db20\$lut for cells of type $lut. Using template $paramod$3774ca4b9dc2cd8733efd43d0d39fb00093ab9db\$lut for cells of type $lut. Using template $paramod$60e01561cadcff25188deca814511e4a10e72d35\$lut for cells of type $lut. Using template $paramod$3ec5e45cb3e54de9dbe908707155b5f9917c9370\$lut for cells of type $lut. Using template $paramod$9cf044275e70b6dc34d2f815a6f8ffc23f9694a0\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut. Using template $paramod$1632c1c0242796acfc963a05742c4acd2f475c4e\$lut for cells of type $lut. Using template $paramod$5532555bd33a32c48c14a1b5df5f5a426d575a95\$lut for cells of type $lut. Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod$b600d182ae966d09f33a746441e104587fe7a58f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut. Using template $paramod$be8603be04ad7fe468c5e5081d8353d91ba0a5d5\$lut for cells of type $lut. Using template $paramod$7a7c36c002f6bb2c4b7a9cd984699e39b8979235\$lut for cells of type $lut. Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut. Using template $paramod$7dc54714f419a5824dc4d8c99430f41ce98ff17c\$lut for cells of type $lut. Using template $paramod$55290dc5b2d325b1a51b6c31876bbb759b0b4b79\$lut for cells of type $lut. Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut. Using template $paramod$46f1d8b1a6d9e3bf408191f0efd26153403b81c4\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod$a9ef64c6deb70a46d2aae4debf7ee3a62e9cab80\$lut for cells of type $lut. Using template $paramod$7705a137b75d9b4c84ffff15aa3d8cc8b6bf45e5\$lut for cells of type $lut. Using template $paramod$d7c87e01028a8e76f94ba02b569a998b96e0a4a6\$lut for cells of type $lut. Using template $paramod$52e8ac6fbc5873870a62e236fe0a79280f986c96\$lut for cells of type $lut. Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0\$lut for cells of type $lut. Using template $paramod$9121ce01630c3ca8583fc82f729fbf1ade868ca5\$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. Using template $paramod$6c430fdac7c8de22eef411b9343949faeb96df89\$lut for cells of type $lut. Using template $paramod$c2d01df1255284b52e28d023171bdb3cbd0234c3\$lut for cells of type $lut. Using template $paramod$be7b9b4fe304f35e2a126a3893cf799cf6d216a8\$lut for cells of type $lut. Using template $paramod$eabde4761c91679426ef5401ae1b2c95bf56e107\$lut for cells of type $lut. Using template $paramod$4677c74bda4fb75c3e61a5d4cbba75e6dc86d66f\$lut for cells of type $lut. Using template $paramod$4c0675f3fd6607b2ac56112b11e78347ff84405c\$lut for cells of type $lut. Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut. Using template $paramod$f39b8ca7b5d76b51a97d51c784ffe8ef759c2d90\$lut for cells of type $lut. Using template $paramod$3157fa832b22dc18f3d0af48e34f0b3515d295c2\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut. Using template $paramod$b630841ffe384aa82d56ca891c9ab4b8f65c57b5\$lut for cells of type $lut. Using template $paramod$a29dc9226a883358910d3758606f48686bda2689\$lut for cells of type $lut. Using template $paramod$22ab56550807ac1ca0030e7dda21f0acdae3746b\$lut for cells of type $lut. Using template $paramod$7cb124c70a03beaadbfbe222fb45b14291f43c3a\$lut for cells of type $lut. Using template $paramod$b831bcea202ffe191b9cfca325ae473ce1968012\$lut for cells of type $lut. Using template $paramod$832803f2a65700892a12287ffb94f8698e0aabe8\$lut for cells of type $lut. Using template $paramod$20ae08042fc7a6110f21bed475d0fa2def6f1ace\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut. Using template $paramod$3416dacc8eaab1f89b3d6b7398df3da766d29ef2\$lut for cells of type $lut. Using template $paramod$9cf976b4f3a576aa2cd6b51304cf5de7fc836fbd\$lut for cells of type $lut. Using template $paramod$f43cab8aa6c1193bdf668a7656513357898a14b3\$lut for cells of type $lut. Using template $paramod$f58e0d90afc57a738914697b6a4a7319b30d7e7e\$lut for cells of type $lut. Using template $paramod$6d05ee5be4fbc817e6482b590e1831ddde15ffbe\$lut for cells of type $lut. Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut. Using template $paramod$de04cb9fed08da92a34d101e5e82912c17d40d8e\$lut for cells of type $lut. Using template $paramod$31dd3095c5b92111b3ce5d19ad3675b7812fd5aa\$lut for cells of type $lut. Using template $paramod$8d103d56ba2e5b2b0cb8f3953ed45cb049c7b560\$lut for cells of type $lut. Using template $paramod$dae799e1fb7e48933e3e893f69e2fb8479219fd3\$lut for cells of type $lut. Using template $paramod$0d98dc10c74f08927e02f9dbb8997446e190eab8\$lut for cells of type $lut. Using template $paramod$b0cead1f76b95bf15933fb262b7a0b5c2f45d8d0\$lut for cells of type $lut. Using template $paramod$680bdad2f3943dd4c4a682cfc6af86d3fbef3b45\$lut for cells of type $lut. Using template $paramod$a7508ca2c5f4328fc833ada341699df9d78a902f\$lut for cells of type $lut. Using template $paramod$9c19d833dd9ffdc4bd1ab8f9744d8ea5e36e63e9\$lut for cells of type $lut. Using template $paramod$785192217a356b0d7e0772eb4b12ee1e5fe0b4c4\$lut for cells of type $lut. Using template $paramod$4fd3428c4b8b1accf8f8fb4bb88555a2b5fa688d\$lut for cells of type $lut. Using template $paramod$49ab19a22e1fd7295fb9532145f2ec0684b263d7\$lut for cells of type $lut. Using template $paramod$3f44941fc257f07863a23ce4464b5e4a473f3bb9\$lut for cells of type $lut. Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut. Using template $paramod$37129f471929e0d8c6476cfb8515143808dde8ed\$lut for cells of type $lut. Using template $paramod$e2cc34de30993c43dc2241134ff545c2455051b4\$lut for cells of type $lut. Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e\$lut for cells of type $lut. Using template $paramod$085cb83d0db09780ae5aa544a0f286ba9445143f\$lut for cells of type $lut. Using template $paramod$f5f41ee5d60dede31a2b59f58ec46b167939d713\$lut for cells of type $lut. Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b\$lut for cells of type $lut. Using template $paramod$f03663c7f91be924d1e9df8220b895406b3f6489\$lut for cells of type $lut. Using template $paramod$0de12c77a963d013da84a5a3b60328cb37ae3db8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut. Using template $paramod$9dd9fc0d64f276af5e5e26957a810dbcde906de4\$lut for cells of type $lut. Using template $paramod$76a3573bcdc463a06a69af63dc6e05bcdfd81fc9\$lut for cells of type $lut. Using template $paramod$f109125ffdede8321ac65719b1066c75ff1eaef0\$lut for cells of type $lut. Using template $paramod$f25cfeb07793f4c9b87758158af8df76472138cf\$lut for cells of type $lut. Using template $paramod$ea5280fce2698f0f291737e66fca69a1d9d058e1\$lut for cells of type $lut. Using template $paramod$3bc826339407d68f080842161835f11a965aed20\$lut for cells of type $lut. Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut. Using template $paramod$fd97122a395b4d6cfdf7073c6f4a72cdee64f935\$lut for cells of type $lut. Using template $paramod$e906e72cbd10abfe84b88bb112d24de91dc6cf81\$lut for cells of type $lut. Using template $paramod$5f6eb11925e6a648832498cf89c8e0856ca5ed27\$lut for cells of type $lut. Using template $paramod$a5d5c745abad930299600272e8260a256cf53240\$lut for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut. Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut. Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut. Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut. Using template $paramod$a6597eda4608f36e684c1dd07ed552fcbec112b2\$lut for cells of type $lut. Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. Using template $paramod$ffa7dea9842ce4733654e5ab5680784eef5333e1\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut. Using template $paramod$2a33a26c90afee023a1fe3cf8eef8dc85c41cb0a\$lut for cells of type $lut. Using template $paramod$0991a7d821b08546bfc9cc8a8fe32b50ae49e395\$lut for cells of type $lut. Using template $paramod$db463350fb0280e25d23606a53a58162e645fbf9\$lut for cells of type $lut. Using template $paramod$a92ef96f3dcd66156673e123558627f39a98a195\$lut for cells of type $lut. Using template $paramod$16b032a3b95627c9d873efd51f1f1382dbf256b9\$lut for cells of type $lut. Using template $paramod$1894df8dda90b159180fd45229357926a3631ab8\$lut for cells of type $lut. Using template $paramod$cc2a4402680f2ea2f7744fec1de78f512aa59d4b\$lut for cells of type $lut. Using template $paramod$41b25c02685725ef8ad91ddeb097a869680781c4\$lut for cells of type $lut. Using template $paramod$974840c9604255c9d99bc139671e0ae6240d8c85\$lut for cells of type $lut. Using template $paramod$43fcaa45efd96b9c6d062bd4d10bc02322f56638\$lut for cells of type $lut. Using template $paramod$6069048ea7c45159713a0558424cdfb243a46dfe\$lut for cells of type $lut. Using template $paramod$a2a239e169b719e301098d0e44b37605e4e45297\$lut for cells of type $lut. Using template $paramod$217a9a1525479446327d3a0746724862c0fc4d60\$lut for cells of type $lut. Using template $paramod$af6bfc66edfa832be553173935a94fd15de7c168\$lut for cells of type $lut. Using template $paramod$0f606255eb7d6cca83986bf43f862e40bba225ef\$lut for cells of type $lut. Using template $paramod$2297cb6f1903c0c59406b08315956c6c9e882e5c\$lut for cells of type $lut. Using template $paramod$2ed551a2d163091995ebe715a2d2b4c87338d90c\$lut for cells of type $lut. Using template $paramod$4db8e9f6768cc0f49eeabffd6db44f73af7ae008\$lut for cells of type $lut. Using template $paramod$d1580d6829c851fd195021e675a70ead86bfa0dc\$lut for cells of type $lut. Using template $paramod$f86839a21484e6e27d2a0762dd2119d471222455\$lut for cells of type $lut. Using template $paramod$784dd5f01e5de46d9c485bef5a2222c42876a5fc\$lut for cells of type $lut. Using template $paramod$a3eef05f12c6da06772a29f92a7a6f81efea9d17\$lut for cells of type $lut. Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut. Using template $paramod$129218383b268f13fb6b12716576104bf2454428\$lut for cells of type $lut. Using template $paramod$b482d305d17b85448f1eb6eb18c3d50230d62ecc\$lut for cells of type $lut. Using template $paramod$9e0d5e3cbbbadb2b139aaae0b912cff38011856c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110101 for cells of type $lut. Using template $paramod$8646c58a25e4b66789954e8b657ef7bcaab0aeef\$lut for cells of type $lut. Using template $paramod$a5abed192044ee4cfd15bb8b611b0c10f32947ca\$lut for cells of type $lut. Using template $paramod$e6cfc2a250ad5b0b3da266fa46a057a6eca6e3d9\$lut for cells of type $lut. Using template $paramod$fe1497207981e9e4f2f9556fad9970ec052e0a6d\$lut for cells of type $lut. Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. Using template $paramod$ff4c34c892697f83ba0d96e47f38056385f2a0fc\$lut for cells of type $lut. Using template $paramod$d6dea393ae47e273ca899e3d6cb21e8cafb62fd2\$lut for cells of type $lut. Using template $paramod$83cb19296515f545f4c69bf6713ff705a6b55de0\$lut for cells of type $lut. Using template $paramod$71f530e8a7f4f89f2e3e5502a552426c66ceedaa\$lut for cells of type $lut. Using template $paramod$92d3b086976ce77e65158c062812eb1264c2f288\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. Using template $paramod$49a3f6ab8f8346cf2ace3353f08779649f8e62e8\$lut for cells of type $lut. Using template $paramod$7929d818ff6cdab401756b40b10229878e94bd76\$lut for cells of type $lut. Using template $paramod$4385b611926e5c0509dba4de58311d325da0ff0d\$lut for cells of type $lut. Using template $paramod$99f282532c29942fbb2a9e103b50d87f80a6f0ac\$lut for cells of type $lut. Using template $paramod$dbe302e2055f5f85fca1ab0927b7743105f90562\$lut for cells of type $lut. Using template $paramod$6023c671e114c4eb0467aa8a0b08e183f33ec2fd\$lut for cells of type $lut. Using template $paramod$7ee8fddb6ce57c49f103c4d21eb6fc8b17f4949a\$lut for cells of type $lut. Using template $paramod$c0661e411f50d4a5911689cfa604d9d594fdf8b0\$lut for cells of type $lut. Using template $paramod$7f0125821bf1676e1e7a9e160604b043f73a73b2\$lut for cells of type $lut. Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut. Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut. Using template $paramod$7ed3d685a887e531dc8f4f21b9907d4766cf861f\$lut for cells of type $lut. Using template $paramod$a75fe1683a97958e61513f004cf91c3458c2f88e\$lut for cells of type $lut. Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut. Using template $paramod$4d7f17f71543a1e7fc1835bd79c4827a43f2e844\$lut for cells of type $lut. Using template $paramod$f3a9cb4a6dcd55c9015bfb659b637a7c07b996c0\$lut for cells of type $lut. Using template $paramod$c24ed72ebb67e9ead6029e42e909ef7fc0abbb11\$lut for cells of type $lut. Using template $paramod$ffeabad369d5f343a57a8cf782e3b79504bde11b\$lut for cells of type $lut. Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut. Using template $paramod$02750f8d568bd99efbda01449a05e084a3143ca8\$lut for cells of type $lut. Using template $paramod$fb4ed309581bcd972f41afa8566ae8b9812c7f6c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut. Using template $paramod$9dfe2a25d99d8640a9f67a2438aaca85b684d257\$lut for cells of type $lut. Using template $paramod$64b84593fae19d6c4d7d26333a195e5cc6b30160\$lut for cells of type $lut. Using template $paramod$e03cd8e8a49e77c888661124604e34849b676141\$lut for cells of type $lut. Using template $paramod$6f527ad842b6bfe0b6a4f71c5f351694f4beb3d7\$lut for cells of type $lut. Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut. Using template $paramod$1d0525724ac068b5dfb483a798d6d5f207b20d29\$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. Using template $paramod$d646cd5cb36fb1f9dd2b06f584b3b88b2dec1d24\$lut for cells of type $lut. Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut. Using template $paramod$4ebbf381cf64b08e3304ae8194da41d0cd1eaa92\$lut for cells of type $lut. Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut. Using template $paramod$413d040dcd860cd74ca61a70644516a95d328ae7\$lut for cells of type $lut. Using template $paramod$fdf742b1b8ec731910cd575c9aab947a6c0075bf\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut. Using template $paramod$b297295e19b03521716155b85537bbe86d6a9ae6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011100 for cells of type $lut. Using template $paramod$5d465bcb0b72d0207b19ca10d090492e09d0263d\$lut for cells of type $lut. Using template $paramod$cba7d4f63aea5e4b3faf052f9f9805e0c6d202cb\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. Using template $paramod$6e424bd4a747f8421ac946af3d9bb3a47fd0b233\$lut for cells of type $lut. Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut. Using template $paramod$c600b4b1adc22857e1c1ba3b6aeb516fabe09da0\$lut for cells of type $lut. Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut. Using template $paramod$9c6e6a10ea00e5b0682f6243b802d7839a398197\$lut for cells of type $lut. Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut. Using template $paramod$432f26b811c14bf54c5e87c8670ec65cbcaf38ac\$lut for cells of type $lut. Using template $paramod$f19bb98065b4fd82c0d3adf2bdd66b5e0c3971a1\$lut for cells of type $lut. Using template $paramod$117b4ac929d164ff303b0e43081fcca142b79922\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod$5c0eb292ef891be47277bee5c25eaa71b34b43e2\$lut for cells of type $lut. Using template $paramod$f94cf08026d21db794b98b1a8efaec5f34ff8975\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut. Using template $paramod$4721519bef85e75f87d1f147d88c627c84abf942\$lut for cells of type $lut. Using template $paramod$1129345a9c7b3078e6c7add333928412ca5f8936\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010111 for cells of type $lut. Using template $paramod$66a21d6ecac0a869f10dfeecf6235898a47b3b78\$lut for cells of type $lut. Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26\$lut for cells of type $lut. Using template $paramod$769bdbbde83614df0f4ab5f54e777ded51bb10ce\$lut for cells of type $lut. Using template $paramod$60b15f75db265c2df1639c67e355ac6d2da5e6a7\$lut for cells of type $lut. Using template $paramod$505ca6f83efadae0442899a08af73f5288142a52\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011111 for cells of type $lut. Using template $paramod$fb5496753f4cd235e71c284b2ffee9d41a960ca2\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. Using template $paramod$eaefffc34a63d2d03fc8295bf3934082e33226c1\$lut for cells of type $lut. Using template $paramod$23c406d3302544ed79a645df17e697e360ff2a8d\$lut for cells of type $lut. Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut. Using template $paramod$b18f60dfd13c21d3e472b89652353f3f5342b450\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111011 for cells of type $lut. Using template $paramod$c79843a7a21eda73c585e76a35dd51b0a4d6fd36\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut. No more expansions possible. <suppressed ~8097 debug messages> 22.44. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in top. Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$7620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80455.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$7401.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7364.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$7303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7222.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$7212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$7182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7172.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$7167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$6708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$6482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$6482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$6279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5712.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$5694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$5603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$5603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6547.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$6095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$6613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$6601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$5877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$5877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5950.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5950.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5950.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$6490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$6490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$6791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$6770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6758.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6347.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6347.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6347.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[15].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80523.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80522.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$6741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80528.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80529.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80530.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80532.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$5887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80524.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$6843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80537.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80536.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$6833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80531.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80533.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80534.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80535.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$5475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$4408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$5854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80543.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80545.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$5806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80539.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80541.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80540.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$4859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$5274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5644.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4971.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4927.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4913.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4556.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4551.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$5640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$5640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$5640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5229.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5194.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4365.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4831.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4744.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4722.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4629.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4328.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5124.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$4613.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4230.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$5455.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5436.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5363.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5081.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5035.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4885.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4880.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4866.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4533.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4528.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$4509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4800.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4786.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$5410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$5263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$4664.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$3988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4385.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$4214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$4214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4110.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4084.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$3850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[20].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[28].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$10137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$10394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$10519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$10614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$10753.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$10909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$10995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$11254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$11416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[25].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$11632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$11791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$12050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$12130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$12270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$auto$opt_dff.cc:219:make_patterns_logic$3626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$3796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3796.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$3810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$3816.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$3823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$3838.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3870.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$3881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$3908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$3913.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$3925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$3971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$3971.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4188.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4225.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5955.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4346.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4369.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4125.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4396.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4416.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4421.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4427.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4446.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4464.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4540.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4576.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4576.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4633.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4651.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4687.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80544.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$4728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4763.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4769.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4809.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4847.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4866.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4896.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4919.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4927.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4940.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4963.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7063.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$4981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$4981.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$4997.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5018.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5056.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5088.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5101.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5138.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5128.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5161.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5175.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$6123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5251.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5251.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5274.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5299.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5322.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5355.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5387.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5410.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5419.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5419.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5445.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6189.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5490.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$5490.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5502.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5509.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5283.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5649.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5663.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5722.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5732.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5854.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5877.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5887.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5896.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5950.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5984.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6123.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6203.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6216.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6226.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$6261.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$6279.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$6289.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6334.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6347.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6357.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6397.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6407.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6421.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6439.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6448.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6490.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6164.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6541.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6564.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$6587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$6619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6665.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6689.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$6708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6720.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6370.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6713.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$6776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6786.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5925.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$5704.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6833.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6741.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6867.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6894.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6904.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6918.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6154.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6954.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$6968.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5816.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$5940.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$7023.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7032.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$7045.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$7058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$7072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7079.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7135.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$80388$lut$aiger80387$7142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7191.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7238.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7244.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7317.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7375.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7383.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7416.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7458.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7484.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7510.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$7515.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7530.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$aiger80387$7571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7576.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$7595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7933.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$7984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$8022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$8026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$8038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$8132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$8161.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$8170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$80388$lut$auto$fsm_map.cc:170:map_fsm$3380[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$aiger80387$8211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$8254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$8333.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$8410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$8538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$8710.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$8818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$8881.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$8957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$9134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$9226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$9350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$9485.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$9612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$9738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$9974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$auto$fsm_map.cc:170:map_fsm$3380[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$auto$fsm_map.cc:170:map_fsm$3380[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[21].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[29].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80413.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80467.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[19].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$80388$lut$auto$rtlil.cc:2582:Mux$3838[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80412.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80431.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80449.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$80388$lut$aiger80387$6270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$80527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Removed 0 unused cells and 7066 unused wires. 22.45. Executing AUTONAME pass. Renamed 295568 objects in module top (245 iterations). <suppressed ~10262 debug messages> 22.46. Executing HIERARCHY pass (managing design hierarchy). 22.46.1. Analyzing design hierarchy.. Top module: \top 22.46.2. Analyzing design hierarchy.. Top module: \top Removed 0 unused modules. 22.47. Printing statistics. === top === Number of wires: 4512 Number of wire bits: 13453 Number of public wires: 4512 Number of public wire bits: 13453 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 6347 $_TBUF_ 6 $scopeinfo 30 CCU2C 116 L6MUX21 355 LUT4 3809 PFUMX 837 TRELLIS_DPR16X4 308 TRELLIS_FF 886 22.48. Executing CHECK pass (checking for obvious problems). Checking module top... Found and reported 0 problems. 22.49. Executing JSON backend. Warnings: 2 unique messages, 3 total End of script. Logfile hash: 5fa650bc76, CPU: user 7.62s system 0.08s, MEM: 210.59 MB peak Yosys 0.38+120 (git sha1 1e42b4f0f, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) Time spent: 49% 1x abc9_exe (7 sec), 9% 11x techmap (1 sec), ... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (NextPNR) [Pipeline] sh + /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained Info: constraining clock net 'clk' to 25.00 MHz Info: Logic utilisation before packing: Info: Total LUT4s: 5889/43848 13% Info: logic LUTs: 3809/43848 8% Info: carry LUTs: 232/43848 0% Info: RAM LUTs: 1232/ 5481 22% Info: RAMW LUTs: 616/10962 5% Info: Total DFFs: 886/43848 2% Info: Packing IOs.. Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y Info: pin 'gpios[5]$tr_io' constrained to Bel 'X0/Y23/PIOC'. Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y Info: pin 'gpios[4]$tr_io' constrained to Bel 'X0/Y44/PIOA'. Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y23/PIOA'. Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y Info: pin 'gpios[2]$tr_io' constrained to Bel 'X90/Y23/PIOD'. Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y Info: pin 'gpios[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'. Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y Info: pin 'gpios[0]$tr_io' constrained to Bel 'X0/Y44/PIOB'. Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'. Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'. Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'. Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'. Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'. Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'. Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'. Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'. Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'. Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'. Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'. Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 397 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: Checksum: 0x8f8789cf Info: Device utilisation: Info: TRELLIS_IO: 18/ 245 7% Info: DCCA: 1/ 56 1% Info: DP16KD: 0/ 108 0% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 886/43848 2% Info: TRELLIS_COMB: 5963/43848 13% Info: TRELLIS_RAMW: 308/ 5481 5% Info: Placed 18 cells based on constraints. Info: Creating initial analytic placement for 3438 cells, random placement wirelen = 296598. Info: at initial placer iter 0, wirelen = 2315 Info: at initial placer iter 1, wirelen = 1820 Info: at initial placer iter 2, wirelen = 1697 Info: at initial placer iter 3, wirelen = 1673 Info: Running main analytical placer, max placement attempts per cell = 6436872. Info: at iteration #1, type ALL: wirelen solved = 1662, spread = 38362, legal = 38874; time = 0.17s Info: at iteration #2, type ALL: wirelen solved = 3975, spread = 30505, legal = 31086; time = 0.24s Info: at iteration #3, type ALL: wirelen solved = 6150, spread = 30199, legal = 30767; time = 0.16s Info: at iteration #4, type ALL: wirelen solved = 8378, spread = 27651, legal = 28412; time = 0.16s Info: at iteration #5, type ALL: wirelen solved = 10159, spread = 27091, legal = 27745; time = 0.15s Info: at iteration #6, type ALL: wirelen solved = 11714, spread = 27873, legal = 28430; time = 0.16s Info: at iteration #7, type ALL: wirelen solved = 13324, spread = 26744, legal = 27339; time = 0.16s Info: at iteration #8, type ALL: wirelen solved = 14086, spread = 25716, legal = 26334; time = 0.16s Info: at iteration #9, type ALL: wirelen solved = 14856, spread = 26231, legal = 26800; time = 0.15s Info: at iteration #10, type ALL: wirelen solved = 15538, spread = 25271, legal = 26070; time = 0.15s Info: at iteration #11, type ALL: wirelen solved = 15857, spread = 25244, legal = 25999; time = 0.15s Info: at iteration #12, type ALL: wirelen solved = 16212, spread = 26125, legal = 26786; time = 0.16s Info: at iteration #13, type ALL: wirelen solved = 16871, spread = 25788, legal = 26507; time = 0.18s Info: at iteration #14, type ALL: wirelen solved = 17429, spread = 25305, legal = 26074; time = 0.19s Info: at iteration #15, type ALL: wirelen solved = 17370, spread = 25677, legal = 26315; time = 0.15s Info: at iteration #16, type ALL: wirelen solved = 18116, spread = 25710, legal = 26383; time = 0.14s Info: HeAP Placer Time: 4.26s Info: of which solving equations: 2.57s Info: of which spreading cells: 0.34s Info: of which strict legalisation: 0.10s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 4606, wirelen = 25999 Info: at iteration #5: temp = 0.000000, timing cost = 2902, wirelen = 23090 [80%] Tech-Mapping Phase 3 completed [90%] Tech-Mapping Phase 4 completed WARN (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":226) WARN (NL0002) : The module "MUX" instantiated to "PCSourceMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":152) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29) WARN (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":29) [95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed Info: at iteration #10: temp = 0.000000, timing cost = 2741, wirelen = 22229 [100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed GowinSynthesis finish Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed Processing netlist completed Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst" Info: at iteration #15: temp = 0.000000, timing cost = 2518, wirelen = 21852 Physical Constraint parsed completed Running placement...... Info: at iteration #20: temp = 0.000000, timing cost = 2522, wirelen = 21719 ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source run.tcl # read_verilog "main.v" Info: at iteration #23: temp = 0.000000, timing cost = 2401, wirelen = 21694 Info: SA placement time 15.03s Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 32.74 MHz (PASS at 25.00 MHz) Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 9.99 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.52 ns Info: Slack histogram: Info: legend: * represents 53 endpoint(s) Info: + represents [1,53) endpoint(s) Info: [ 9460, 10949) |+ Info: [ 10949, 12438) | Info: [ 12438, 13927) |+ Info: [ 13927, 15416) |+ Info: [ 15416, 16905) |**+ Info: [ 16905, 18394) |***+ Info: [ 18394, 19883) |******+ Info: [ 19883, 21372) |****+ Info: [ 21372, 22861) |*****+ Info: [ 22861, 24350) |*****************+ Info: [ 24350, 25839) |******+ Info: [ 25839, 27328) |************************************************************ Info: [ 27328, 28817) |**********************************+ Info: [ 28817, 30306) |****+ Info: [ 30306, 31795) |*+ Info: [ 31795, 33284) |**+ Info: [ 33284, 34773) |********+ Info: [ 34773, 36262) |************+ Info: [ 36262, 37751) |****+ Info: [ 37751, 39240) |*******+ Info: Checksum: 0xb787c032 Info: Routing globals... Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 28382 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| [10%] Placement Phase 0 completed Info: 1000 | 156 843 | 156 843 | 27580| 1.14 1.14| Info: 2000 | 278 1721 | 122 878 | 26831| 0.33 1.47| Info: 3000 | 417 2582 | 139 861 | 26071| 0.27 1.75| Info: 4000 | 572 3427 | 155 845 | 25311| 0.24 1.99| Info: 5000 | 713 4286 | 141 859 | 24564| 0.25 2.24| Info: 6000 | 860 5139 | 147 853 | 23797| 0.28 2.52| [20%] Placement Phase 1 completed Info: 7000 | 1044 5955 | 184 816 | 23102| 0.30 2.82| Info: 8000 | 1216 6783 | 172 828 | 22412| 0.25 3.07| Info: 9000 | 1425 7574 | 209 791 | 21692| 0.26 3.33| Info: 10000 | 1641 8358 | 216 784 | 20969| 0.24 3.58| Info: 11000 | 1830 9169 | 189 811 | 20407| 0.28 3.86| Info: 12000 | 2068 9931 | 238 762 | 19813| 0.28 4.14| Info: 13000 | 2271 10728 | 203 797 | 19093| 0.27 4.41| Info: 14000 | 2533 11466 | 262 738 | 18475| 0.29 4.70| Info: 15000 | 2837 12162 | 304 696 | 17984| 0.32 5.02| Info: 16000 | 3035 12964 | 198 802 | 17241| 0.31 5.33| Info: 17000 | 3358 13641 | 323 677 | 16644| 0.33 5.66| Info: 18000 | 3599 14400 | 241 759 | 15934| 0.30 5.96| Info: 19000 | 3888 15111 | 289 711 | 15422| 0.38 6.33| Info: 20000 | 4234 15765 | 346 654 | 14864| 0.33 6.66| Info: 21000 | 4551 16448 | 317 683 | 14264| 0.31 6.97| Info: 22000 | 4819 17180 | 268 732 | 13741| 0.31 7.28| Info: 23000 | 5248 17751 | 429 571 | 13322| 0.32 7.60| Info: 24000 | 5723 18276 | 475 525 | 12936| 0.32 7.92| Info: 25000 | 6127 18872 | 404 596 | 12503| 0.30 8.22| Info: 26000 | 6492 19507 | 365 635 | 11986| 0.33 8.55| Info: 27000 | 6801 20190 | 309 683 | 11340| 0.29 8.84| Info: 28000 | 7091 20809 | 290 619 | 10666| 0.26 9.11| Info: 29000 | 7495 21296 | 404 487 | 10099| 0.26 9.37| Info: 30000 | 7890 21841 | 395 545 | 9557| 0.28 9.65| Info: 31000 | 8265 22415 | 375 574 | 9031| 0.30 9.95| Info: 32000 | 8529 23009 | 264 594 | 8338| 0.24 10.19| read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1322.492 ; gain = 97.836 ; free physical = 10034 ; free virtual = 28662 # read_verilog ../../debug/reset.v # read_verilog ../../src/core/alu_control.v # read_verilog ../../src/core/alu.v # read_verilog ../../src/core/control_unit.v # read_verilog ../../src/core/core.v # read_verilog ../../src/core/immediate_generator.v # read_verilog ../../src/core/mux.v # read_verilog ../../src/core/pc.v # read_verilog ../../src/core/registers.v # read_verilog ../../src/core/csr_unit.v # read_verilog ../../src/peripheral/bus.v # read_verilog ../../src/peripheral/gpio.v # read_verilog ../../src/peripheral/gpios.v # read_verilog ../../src/peripheral/leds.v # read_verilog ../../src/peripheral/memory.v # read_verilog ../../src/peripheral/soc.v # read_verilog ../../src/peripheral/uart_rx.v # read_verilog ../../src/peripheral/uart_tx.v # read_verilog ../../src/peripheral/uart.v # read_verilog ../../src/peripheral/fifo.v # read_xdc "digilent_nexys4_ddr.xdc" # set_property PROCESSING_ORDER EARLY [get_files digilent_nexys4_ddr.xdc] # synth_design -top "top" -part "xc7a100tcsg324-1" Command: synth_design -top top -part xc7a100tcsg324-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' Info: 33000 | 8762 23696 | 233 687 | 7600| 0.22 10.40| Info: 34000 | 9073 24362 | 311 666 | 6941| 0.25 10.65| Info: 35000 | 9402 25025 | 329 663 | 6287| 0.27 10.93| Info: 36000 | 9715 25708 | 313 683 | 5677| 0.34 11.27| Info: 37000 | 9770 26649 | 55 941 | 4734| 0.12 11.39| Info: 38000 | 9777 27638 | 7 989 | 3741| 0.06 11.45| Info: 39000 | 9803 28600 | 26 962 | 2771| 0.08 11.53| Info: 40000 | 9873 29524 | 70 924 | 1850| 0.21 11.74| INFO: [Device 21-403] Loading part xc7a100tcsg324-1 Info: 41000 | 10000 30343 | 127 819 | 998| 0.28 12.02| Info: 42000 | 10037 31009 | 37 666 | 52| 0.48 12.50| Info: 42051 | 10037 31028 | 0 19 | 0| 0.08 12.58| Info: Routing complete. Info: Router1 time 12.58s Info: Checksum: 0x5e635f5b Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source SOC.Core.temp_address_TRELLIS_FF_Q_31.Q Info: 0.9 1.4 Net SOC.Core.temp_address[0] (18,33) -> (16,33) Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_Z.D Info: Defined in: Info: Risco-5/src/core/core.v:62.47-62.59 Info: 0.2 1.6 Source SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_Z.F Info: 1.3 2.9 Net SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C[0] (16,33) -> (34,30) Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_A.A Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.4 3.3 Source SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_A.OFX Info: 0.0 3.3 Net SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_A_Z_PFUMX_BLUT_Z (34,30) -> (34,30) Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_A_Z_PFUMX_BLUT_ALUT_LUT4_Z.FXB Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.54-157.56 Info: 0.2 3.6 Source SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_A_Z_PFUMX_BLUT_ALUT_LUT4_Z.OFX Info: 0.0 3.6 Net SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_D0 (34,30) -> (34,30) Info: Sink SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXA Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.66-157.68 Info: 0.2 3.8 Source SOC.Core.RegisterBank.registers.0.1_DO_3_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_ALUT_LUT4_Z_C_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 0.7 4.5 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_3_C_LUT4_Z_D_LUT4_D_B_LUT4_Z_D_LUT4_Z_C_L6MUX21_SD_Z_PFUMX_Z_ALUT_LUT4_Z_D[4] (34,30) -> (30,30) Info: Sink SOC.Core.Control_Unit.nextstate_LUT4_Z_3_C_LUT4_Z_D_LUT4_D_B_LUT4_Z_D_LUT4_Z_C_L6MUX21_SD_Z_PFUMX_Z_BLUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 4.8 Source SOC.Core.Control_Unit.nextstate_LUT4_Z_3_C_LUT4_Z_D_LUT4_D_B_LUT4_Z_D_LUT4_Z_C_L6MUX21_SD_Z_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 1.9 6.6 Net SOC.Core.Control_Unit.nextstate_LUT4_Z_3_C_LUT4_Z_D_LUT4_D_B_LUT4_Z_D_LUT4_Z_C_L6MUX21_SD_Z[3] (30,30) -> (14,26) Info: Sink SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_BLUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 6.9 Source SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 0.7 7.6 Net SOC.Core.RegisterBank.registers.0.2_DO_LUT4_A_Z_PFUMX_BLUT_Z[6] (14,26) -> (14,25) Info: Sink SOC.Core.RegisterBank.registers.0.3_DO_2_LUT4_A_Z_PFUMX_BLUT_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 7.8 Source SOC.Core.RegisterBank.registers.0.3_DO_2_LUT4_A_Z_PFUMX_BLUT_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 0.6 8.4 Net SOC.Core.RegisterBank.registers.0.3_DO_2_LUT4_A_Z_PFUMX_BLUT_Z[5] (14,25) -> (15,25) Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 8.7 Source SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 0.0 8.7 Net SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_D1 (15,25) -> (15,25) Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72 Info: 0.2 8.9 Source SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 1.3 10.2 Net SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z[1] (15,25) -> (21,20) Info: Sink SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_LUT4_Z_D_LUT4_A.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 10.5 Source SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_LUT4_Z_D_LUT4_A.F Info: 1.4 11.9 Net SOC.Core.RegisterBank.registers.0.7_DO_LUT4_A_Z_PFUMX_C0_Z_LUT4_Z_D_LUT4_A_Z[5] (21,20) -> (22,29) Info: Sink SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_C0_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 12.2 Source SOC.Core.RegisterBank.registers.0.0_DO_2_LUT4_A_Z_PFUMX_BLUT_Z_PFUMX_C0_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 1.3 13.4 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_Z_D_LUT4_C_Z_LUT4_C_1_Z[5] (22,29) -> (17,26) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_PFUMX_Z_C0_LUT4_Z_D_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 13.7 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_PFUMX_Z_C0_LUT4_Z_D_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 1.0 14.7 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_PFUMX_Z_C0_LUT4_Z_D[6] (17,26) -> (23,25) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_Z_C_LUT4_Z_1.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 14.9 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_Z_C_LUT4_Z_1.F Info: 0.4 15.3 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_Z_C[2] (23,25) -> (23,25) Info: Sink SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_Z.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 15.6 Source SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z_LUT4_Z.F Info: 1.3 16.8 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_10_B_LUT4_Z_C_PFUMX_Z_C0_LUT4_Z_C_CCU2C_S1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_LUT4_C_Z_LUT4_C_Z[3] (23,25) -> (18,28) Info: Sink SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_BLUT_LUT4_Z.D Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.4 17.2 Source SOC.Core.Alu.ALU_out_S_PFUMX_Z_7_BLUT_LUT4_Z.OFX Info: 1.2 18.5 Net SOC.Core.alu_out[11] (18,28) -> (17,33) Info: Sink SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_C_1_D_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M Info: Defined in: Info: Risco-5/src/core/core.v:58.31-58.38 Info: 0.3 18.8 Source SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_C_1_D_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 1.2 20.0 Net SOC.Core.Control_Unit.save_write_value_LUT4_Z_D_LUT4_C_1_D_LUT4_C_Z[1] (17,33) -> (20,27) Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.B Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 20.2 Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F Info: 0.0 20.2 Net SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT (20,27) -> (20,27) Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1 Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.30-141.32 Info: 0.2 20.4 Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 0.0 20.4 Net SOC.Core.Pc.load_L6MUX21_Z_D1 (20,27) -> (20,27) Info: Sink SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40 Info: 0.2 20.6 Source SOC.Core.Pc.load_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 1.6 22.3 Net SOC.Core.pc_load (20,27) -> (30,35) Info: Sink SOC.Core.Pc.Output_TRELLIS_FF_Q_9.CE Info: Defined in: Info: Risco-5/src/core/core.v:50.32-50.39 Info: 0.0 22.3 Setup SOC.Core.Pc.Output_TRELLIS_FF_Q_9.CE Info: 5.4 ns logic, 16.8 ns routing Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': Info: curr total Info: 0.0 0.0 Source gpios[2]$tr_io.O Info: 4.8 4.8 Net gpios[2]$TRELLIS_IO_IN (90,23) -> (8,23) Info: Sink SOC.GPIOS.Gpios[2].data_in_LUT4_B.A Info: Defined in: Info: Risco-5/fpga/ecp5/main.v:7.16-7.21 Info: 0.2 5.0 Source SOC.GPIOS.Gpios[2].data_in_LUT4_B.F Info: 0.9 5.9 Net SOC.GPIOS.Gpios[2].data_in_LUT4_B_Z[2] (8,23) -> (8,23) Info: Sink SOC.Core.read_data_LUT4_Z_21.C Info: Defined in: Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 6.1 Source SOC.Core.read_data_LUT4_Z_21.F Info: 1.5 7.6 Net SOC.read_data[2] (8,23) -> (17,20) Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_29.M Info: Defined in: Info: Risco-5/src/peripheral/soc.v:22.34-22.43 Info: 0.0 7.6 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_29.M Info: 0.5 ns logic, 7.2 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>': Info: curr total Info: 0.5 0.5 Source SOC.GPIOS.Gpios[2].direction_TRELLIS_FF_Q.Q Info: 4.1 4.6 Net SOC.GPIOS.gpio_direction[2] (4,23) -> (72,23) Info: Sink SOC.GPIOS.Gpios[2].direction_LUT4_D.D Info: Defined in: Info: Risco-5/src/peripheral/gpios.v:16.19-16.33 Info: 0.2 4.8 Source SOC.GPIOS.Gpios[2].direction_LUT4_D.F Info: 1.2 6.1 Net gpios_$_TBUF__Y_3_E (72,23) -> (82,23) Info: Sink gpios[2]$tr_io$invert_T.A Info: 0.2 6.3 Source gpios[2]$tr_io$invert_T.F Info: 1.0 7.2 Net gpios[2]$tr_io$invert_T$conn$Z (82,23) -> (90,23) Info: Sink gpios[2]$tr_io.T Info: 1.0 ns logic, 6.2 ns routing Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 44.93 MHz (PASS at 25.00 MHz) Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.64 ns Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.25 ns Info: Slack histogram: Info: legend: * represents 50 endpoint(s) Info: + represents [1,50) endpoint(s) Info: [ 17743, 18809) |+ Info: [ 18809, 19875) |*+ Info: [ 19875, 20941) |**+ Info: [ 20941, 22007) |********+ Info: [ 22007, 23073) |***+ Info: [ 23073, 24139) |*+ Info: [ 24139, 25205) |**+ Info: [ 25205, 26271) |*******************+ Info: [ 26271, 27337) |******+ Info: [ 27337, 28403) |***+ Info: [ 28403, 29469) |************************************************************ Info: [ 29469, 30535) |***********************+ Info: [ 30535, 31601) |*****************+ Info: [ 31601, 32667) |***+ Info: [ 32667, 33733) |**+ Info: [ 33733, 34799) |****+ Info: [ 34799, 35865) |******+ Info: [ 35865, 36931) |*************+ Info: [ 36931, 37997) |*****+ Info: [ 37997, 39063) |*******+ Info: Program finished normally. [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (ECPPACK) [Pipeline] sh + /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // stage [Pipeline] } INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 345875 [30%] Placement Phase 2 completed --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2076.215 ; gain = 403.746 ; free physical = 9143 ; free virtual = 27843 --------------------------------------------------------------------------------- INFO: [Synth 8-11241] undeclared symbol 'pc_source', assumed default net type 'wire' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:142] WARNING: [Synth 8-11065] parameter 'SET_DIRECTION' becomes localparam in 'GPIOS' with formal parameter declaration list [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:19] WARNING: [Synth 8-11065] parameter 'READ' becomes localparam in 'GPIOS' with formal parameter declaration list [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:20] WARNING: [Synth 8-9400] empty statement in sequential block [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:54] INFO: [Synth 8-6157] synthesizing module 'top' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1] INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1] Parameter CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1] WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:24] WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 3 connections declared, but only 2 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:24] INFO: [Synth 8-6157] synthesizing module 'Risco_5_SOC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1] Parameter CLOCK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter MEMORY_SIZE bound to: 2048 - type: integer Parameter MEMORY_FILE bound to: ../../software/memory/teste_uart_fpga.hex - type: string Parameter GPIO_WIDHT bound to: 8 - type: integer Parameter UART_BUFFER_SIZE bound to: 16 - type: integer INFO: [Synth 8-6157] synthesizing module 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:1] Parameter BOOT_ADDRESS bound to: 0 - type: integer INFO: [Synth 8-6157] synthesizing module 'PC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1] INFO: [Synth 8-6155] done synthesizing module 'PC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1] INFO: [Synth 8-6157] synthesizing module 'MUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1] INFO: [Synth 8-6155] done synthesizing module 'MUX' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1] INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1] INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1] INFO: [Synth 8-6157] synthesizing module 'Control_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:1] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:156] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:332] INFO: [Synth 8-6155] done synthesizing module 'Control_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:1] INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1] INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:33] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:10] INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1] INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1] INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1] INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1] INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1] INFO: [Synth 8-6157] synthesizing module 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1] INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:117] INFO: [Synth 8-6155] done synthesizing module 'CSR_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1] INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:1] WARNING: [Synth 8-7071] port 'halt' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33] WARNING: [Synth 8-7071] port 'interruption_request_external' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33] WARNING: [Synth 8-7071] port 'interruption_request_timer' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33] WARNING: [Synth 8-7071] port 'interruption_request_software' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33] WARNING: [Synth 8-7071] port 'interruption_request_fast' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33] WARNING: [Synth 8-7023] instance 'Core' of module 'Core' has 14 connections declared, but only 9 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33] INFO: [Synth 8-6157] synthesizing module 'Memory' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1] Parameter MEMORY_FILE bound to: ../../software/memory/teste_uart_fpga.hex - type: string Parameter MEMORY_SIZE bound to: 2048 - type: integer INFO: [Synth 8-3876] $readmem data file '../../software/memory/teste_uart_fpga.hex' is read successfully [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:35] INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1] INFO: [Synth 8-6157] synthesizing module 'BUS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1] INFO: [Synth 8-6155] done synthesizing module 'BUS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1] INFO: [Synth 8-6157] synthesizing module 'LEDs' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1] INFO: [Synth 8-6155] done synthesizing module 'LEDs' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1] INFO: [Synth 8-6157] synthesizing module 'UART' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter BUFFER_SIZE bound to: 16 - type: integer INFO: [Synth 8-6157] synthesizing module 'FIFO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1] Parameter DEPTH bound to: 16 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1] INFO: [Synth 8-6157] synthesizing module 'uart_tool_rx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tool_rx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10] INFO: [Synth 8-6157] synthesizing module 'uart_tool_tx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tool_tx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10] INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1] INFO: [Synth 8-6157] synthesizing module 'GPIOS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1] Parameter WIDHT bound to: 8 - type: integer INFO: [Synth 8-6157] synthesizing module 'GPIO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1] INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1] INFO: [Synth 8-6155] done synthesizing module 'GPIOS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1] INFO: [Synth 8-6155] done synthesizing module 'Risco_5_SOC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1] INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1] WARNING: [Synth 8-6014] Unused sequential element tx_fifo_read_reg was removed. [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:160] WARNING: [Synth 8-7129] Port address[31] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[7] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[6] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[5] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[4] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[3] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[1] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[31] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[16] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[15] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[14] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[13] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[12] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[11] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[10] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[9] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port write_data[8] in module GPIOS is either unconnected or has no load WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port address[31] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[30] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[29] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[28] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[27] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[26] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[25] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[24] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[23] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[22] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[21] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[20] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[19] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[18] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[17] in module LEDs is either unconnected or has no load WARNING: [Synth 8-7129] Port address[16] in module LEDs is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2165.152 ; gain = 492.684 ; free physical = 9026 ; free virtual = 27729 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2179.996 ; gain = 507.527 ; free physical = 9021 ; free virtual = 27724 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2179.996 ; gain = 507.527 ; free physical = 9021 ; free virtual = 27724 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2179.996 ; gain = 0.000 ; free physical = 9022 ; free virtual = 27725 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2327.746 ; gain = 0.000 ; free physical = 8977 ; free virtual = 27696 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2327.781 ; gain = 0.000 ; free physical = 8980 ; free virtual = 27698 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2327.781 ; gain = 655.312 ; free physical = 8978 ; free virtual = 27697 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2327.781 ; gain = 655.312 ; free physical = 8978 ; free virtual = 27697 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2327.781 ; gain = 655.312 ; free physical = 8978 ; free virtual = 27697 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- RESET_COUNTER | 00 | 01 IDLE | 01 | 10 INIT | 10 | 00 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FETCH | 00000000000000000000000000000000000000000000001 | 000000 VALIDATE_FETCH | 00000000000000000000000000000000000000000000010 | 101110 DECODE | 00000000000000000000000000000000000000000000100 | 000001 MEMADR | 00000000000000000000000000000000000000000001000 | 000010 MEMREAD_UNALIGNED | 00000000000000000000000000000000000000000010000 | 010110 LOAD_FIRST_BLOCK | 00000000000000000000000000000000000000000100000 | 010000 SAVE_FIRST_BLOCK | 00000000000000000000000000000000000000001000000 | 010001 CALC_NEXT_ADDRESS | 00000000000000000000000000000000000000010000000 | 010010 READ_SECOND_BLOCK | 00000000000000000000000000000000000000100000000 | 010011 LOAD_SECOND_BLOCK | 00000000000000000000000000000000000001000000000 | 010100 MERGE_BLOCKS | 00000000000000000000000000000000000010000000000 | 010101 FILTER_ALU_WB | 00000000000000000000000000000000000100000000000 | 010111 MEMREAD | 00000000000000000000000000000000001000000000000 | 000011 MEMWB | 00000000000000000000000000000000010000000000000 | 000100 MEMWRITE_UNALIGNED | 00000000000000000000000000000000100000000000000 | 011000 GEN_FIRST_BLOCK_PART_1 | 00000000000000000000000000000001000000000000000 | 011001 GEN_FIRST_BLOCK_PART_2 | 00000000000000000000000000000010000000000000000 | 011010 GEN_SECOND_BLOCK_PART_1 | 00000000000000000000000000000100000000000000000 | 011011 GEN_SECOND_BLOCK_PART_2 | 00000000000000000000000000001000000000000000000 | 011100 MERGE_WRITE_BLOCKS | 00000000000000000000000000010000000000000000000 | 011101 SWAP_VALUE_DIRECTION | 00000000000000000000000000100000000000000000000 | 011110 CLEAR_VALUE_HALF_BYTE_ONE_BLOCK | 00000000000000000000000001000000000000000000000 | 100010 CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_2 | 00000000000000000000000010000000000000000000000 | 100011 CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_3 | 00000000000000000000000100000000000000000000000 | 100100 CLEAR_VALUE | 00000000000000000000001000000000000000000000000 | 011111 MERGE_WRITE_VALUE_1 | 00000000000000000000010000000000000000000000000 | 100000 WRITE_VALUE_1 | 00000000000000000000100000000000000000000000000 | 100001 CALC_SECOND_BLOCK_ADDRESS_TO_WRITE | 00000000000000000001000000000000000000000000000 | 100101 READ_SECOND_BLOCK_TO_WRITE | 00000000000000000010000000000000000000000000000 | 100110 LOAD_SECOND_BLOCK_TO_WRITE | 00000000000000000100000000000000000000000000000 | 100111 LOAD_SECOND_BLOCK_TO_WRITE_2 | 00000000000000001000000000000000000000000000000 | 101000 SWAP_VALUE_DIRECTION_2 | 00000000000000010000000000000000000000000000000 | 101001 CLEAR_VALUE_PART_2 | 00000000000000100000000000000000000000000000000 | 101010 CLEAR_VALUE_PART_2_1 | 00000000000001000000000000000000000000000000000 | 101011 MERGE_WRITE_VALUE_2 | 00000000000010000000000000000000000000000000000 | 101100 WRITE_VALUE_2 | 00000000000100000000000000000000000000000000000 | 101101 MEMWRITE | 00000000001000000000000000000000000000000000000 | 000101 EXECUTER | 00000000010000000000000000000000000000000000000 | 000110 EXECUTEI | 00000000100000000000000000000000000000000000000 | 001000 JAL | 00000001000000000000000000000000000000000000000 | 001001 BRANCH | 00000010000000000000000000000000000000000000000 | 001010 AUIPC | 00000100000000000000000000000000000000000000000 | 001100 LUI | 00001000000000000000000000000000000000000000000 | 001101 JALR_PC | 00010000000000000000000000000000000000000000000 | 001110 JALR | 00100000000000000000000000000000000000000000000 | 001011 ALUWB | 01000000000000000000000000000000000000000000000 | 000111 EXECUTECSR | 10000000000000000000000000000000000000000000000 | 001111 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit' WARNING: [Synth 8-327] inferring latch for variable 'aluop_out_reg' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:12] --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_RECV | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_SEND | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 0000 | 0000 COPY_WRITE_BUFFER | 0001 | 0100 WRITE | 0010 | 0010 READ | 0011 | 0001 READ_RX_FIFO_EMPTY | 0100 | 0110 READ_TX_FIFO_EMPTY | 0101 | 0111 READ_RX_FIFO_FULL | 0110 | 1000 READ_TX_FIFO_FULL | 0111 | 1001 WB | 1000 | 0101 FINISH | 1001 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2327.781 ; gain = 655.312 ; free physical = 8978 ; free virtual = 27698 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 1 3 Input 32 Bit Adders := 1 2 Input 10 Bit Adders := 2 2 Input 6 Bit Adders := 6 2 Input 5 Bit Adders := 1 2 Input 4 Bit Adders := 2 2 Input 3 Bit Adders := 2 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 32 Bit XORs := 1 +---XORs : 2 Bit Wide XORs := 1 +---Registers : 64 Bit Registers := 2 33 Bit Registers := 1 32 Bit Registers := 50 10 Bit Registers := 2 8 Bit Registers := 8 6 Bit Registers := 5 4 Bit Registers := 2 3 Bit Registers := 1 1 Bit Registers := 13 +---RAMs : 16K Bit (512 X 32 bit) RAMs := 1 128 Bit (16 X 8 bit) RAMs := 2 +---Muxes : 4 Input 64 Bit Muxes := 1 47 Input 47 Bit Muxes := 1 2 Input 47 Bit Muxes := 17 11 Input 47 Bit Muxes := 1 3 Input 33 Bit Muxes := 1 2 Input 32 Bit Muxes := 8 8 Input 32 Bit Muxes := 1 15 Input 32 Bit Muxes := 1 6 Input 32 Bit Muxes := 1 4 Input 32 Bit Muxes := 1 10 Input 32 Bit Muxes := 2 2 Input 8 Bit Muxes := 3 3 Input 6 Bit Muxes := 1 2 Input 6 Bit Muxes := 4 2 Input 5 Bit Muxes := 1 47 Input 4 Bit Muxes := 1 9 Input 4 Bit Muxes := 1 10 Input 4 Bit Muxes := 2 23 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 3 6 Input 4 Bit Muxes := 1 5 Input 3 Bit Muxes := 1 2 Input 3 Bit Muxes := 3 4 Input 3 Bit Muxes := 2 47 Input 3 Bit Muxes := 3 10 Input 3 Bit Muxes := 2 3 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 16 47 Input 2 Bit Muxes := 2 4 Input 2 Bit Muxes := 4 3 Input 1 Bit Muxes := 6 2 Input 1 Bit Muxes := 68 47 Input 1 Bit Muxes := 12 4 Input 1 Bit Muxes := 3 6 Input 1 Bit Muxes := 5 10 Input 1 Bit Muxes := 8 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template. [50%] Placement Phase 3 completed Running routing...... [60%] Routing Phase 0 completed --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2327.781 ; gain = 655.312 ; free physical = 8902 ; free virtual = 27632 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Preliminary Mapping Report (see note below) +------------+-----------------------------+-----------+----------------------+-----------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-----------------------------+-----------+----------------------+-----------------+ |top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 | |top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 | |top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 | +------------+-----------------------------+-----------+----------------------+-----------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- [70%] Routing Phase 1 completed --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2327.781 ; gain = 655.312 ; free physical = 8888 ; free virtual = 27625 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 2327.781 ; gain = 655.312 ; free physical = 8887 ; free virtual = 27624 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +------------+-----------------------------+-----------+----------------------+-----------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-----------------------------+-----------+----------------------+-----------------+ |top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 | |top | SOC/Uart/RX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 | |top | SOC/Uart/TX_FIFO/memory_reg | Implied | 16 x 8 | RAM32M x 2 | +------------+-----------------------------+-----------+----------------------+-----------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 2327.781 ; gain = 655.312 ; free physical = 8885 ; free virtual = 27622 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2327.781 ; gain = 655.312 ; free physical = 8884 ; free virtual = 27621 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2327.781 ; gain = 655.312 ; free physical = 8884 ; free virtual = 27621 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2327.781 ; gain = 655.312 ; free physical = 8878 ; free virtual = 27615 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- [80%] Routing Phase 2 completed --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2327.781 ; gain = 655.312 ; free physical = 8875 ; free virtual = 27612 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2327.781 ; gain = 655.312 ; free physical = 8877 ; free virtual = 27615 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2327.781 ; gain = 655.312 ; free physical = 8877 ; free virtual = 27615 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFG | 2| |2 |CARRY4 | 39| |3 |LUT1 | 13| |4 |LUT2 | 185| |5 |LUT3 | 247| |6 |LUT4 | 237| |7 |LUT5 | 300| |8 |LUT6 | 1598| |9 |MUXF7 | 431| |10 |MUXF8 | 2| |11 |RAM256X1S | 64| |12 |RAM32M | 2| |13 |RAM32X1D | 4| |14 |FDRE | 1956| |15 |FDSE | 4| |16 |LD | 4| |17 |IBUF | 3| |18 |IOBUF | 8| |19 |OBUF | 9| +------+----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2327.781 ; gain = 655.312 ; free physical = 8877 ; free virtual = 27615 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 62 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2327.781 ; gain = 507.527 ; free physical = 8878 ; free virtual = 27615 Synthesis Optimization Complete : Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2327.781 ; gain = 655.312 ; free physical = 8878 ; free virtual = 27615 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2327.781 ; gain = 0.000 ; free physical = 9152 ; free virtual = 27893 INFO: [Netlist 29-17] Analyzing 554 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2391.777 ; gain = 0.000 ; free physical = 9150 ; free virtual = 27891 INFO: [Project 1-111] Unisim Transformation Summary: A total of 82 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 8 instances LD => LDCE: 4 instances RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances Synth Design complete | Checksum: 3e51092a INFO: [Common 17-83] Releasing license: Synthesis 76 Infos, 114 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:51 ; elapsed = 00:00:52 . Memory (MB): peak = 2391.812 ; gain = 1069.320 ; free physical = 9145 ; free virtual = 27886 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2025.597; main = 1742.217; forked = 424.702 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3297.402; main = 2391.781; forked = 969.652 # opt_design Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2455.809 ; gain = 63.996 ; free physical = 9141 ; free virtual = 27883 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 17d66fb94 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2568.621 ; gain = 112.812 ; free physical = 9055 ; free virtual = 27814 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: 17d66fb94 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.527 ; gain = 0.000 ; free physical = 8794 ; free virtual = 27552 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 17d66fb94 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.527 ; gain = 0.000 ; free physical = 8794 ; free virtual = 27552 Phase 1 Initialization | Checksum: 17d66fb94 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2817.527 ; gain = 0.000 ; free physical = 8794 ; free virtual = 27552 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: 17d66fb94 Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2817.527 ; gain = 0.000 ; free physical = 8790 ; free virtual = 27549 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: 17d66fb94 Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2817.527 ; gain = 0.000 ; free physical = 8790 ; free virtual = 27549 Phase 2 Timer Update And Timing Data Collection | Checksum: 17d66fb94 Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2817.527 ; gain = 0.000 ; free physical = 8790 ; free virtual = 27549 Phase 3 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 17d66fb94 Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2817.527 ; gain = 0.000 ; free physical = 8792 ; free virtual = 27551 Retarget | Checksum: 17d66fb94 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 17d66fb94 Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.2 . Memory (MB): peak = 2817.527 ; gain = 0.000 ; free physical = 8792 ; free virtual = 27551 Constant propagation | Checksum: 17d66fb94 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep Phase 5 Sweep | Checksum: 148cfddca Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2817.527 ; gain = 0.000 ; free physical = 8792 ; free virtual = 27551 Sweep | Checksum: 148cfddca INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 1 cells Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 148cfddca Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2849.543 ; gain = 32.016 ; free physical = 8790 ; free virtual = 27549 BUFG optimization | Checksum: 148cfddca INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 148cfddca Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.3 . Memory (MB): peak = 2849.543 ; gain = 32.016 ; free physical = 8789 ; free virtual = 27548 Shift Register Optimization | Checksum: 148cfddca INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 233fcf466 Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2849.543 ; gain = 32.016 ; free physical = 8791 ; free virtual = 27550 Post Processing Netlist | Checksum: 233fcf466 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1065a0b3c Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2849.543 ; gain = 32.016 ; free physical = 8786 ; free virtual = 27545 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2849.543 ; gain = 0.000 ; free physical = 8785 ; free virtual = 27544 Phase 9.2 Verifying Netlist Connectivity | Checksum: 1065a0b3c Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2849.543 ; gain = 32.016 ; free physical = 8785 ; free virtual = 27543 Phase 9 Finalization | Checksum: 1065a0b3c Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2849.543 ; gain = 32.016 ; free physical = 8785 ; free virtual = 27543 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 0 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 8 | 1 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 1065a0b3c Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2849.543 ; gain = 32.016 ; free physical = 8785 ; free virtual = 27543 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2849.543 ; gain = 0.000 ; free physical = 8784 ; free virtual = 27543 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 1065a0b3c Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2849.543 ; gain = 0.000 ; free physical = 8784 ; free virtual = 27543 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 1065a0b3c Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2849.543 ; gain = 0.000 ; free physical = 8784 ; free virtual = 27543 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2849.543 ; gain = 0.000 ; free physical = 8784 ; free virtual = 27543 Ending Netlist Obfuscation Task | Checksum: 1065a0b3c Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2849.543 ; gain = 0.000 ; free physical = 8784 ; free virtual = 27543 INFO: [Common 17-83] Releasing license: Implementation 18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2849.543 ; gain = 457.730 ; free physical = 8784 ; free virtual = 27543 # place_design Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-83] Releasing license: Implementation INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2881.559 ; gain = 0.000 ; free physical = 8785 ; free virtual = 27545 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c0efab92 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2881.559 ; gain = 0.000 ; free physical = 8785 ; free virtual = 27545 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2881.559 ; gain = 0.000 ; free physical = 8785 ; free virtual = 27545 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1168202fb Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.76 . Memory (MB): peak = 2881.559 ; gain = 0.000 ; free physical = 8784 ; free virtual = 27548 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 208a4c0f6 Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8784 ; free virtual = 27548 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208a4c0f6 Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8784 ; free virtual = 27548 Phase 1 Placer Initialization | Checksum: 208a4c0f6 Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8784 ; free virtual = 27548 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1de90280c Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8777 ; free virtual = 27542 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2158f8a93 Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8777 ; free virtual = 27542 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 2158f8a93 Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8777 ; free virtual = 27542 Phase 2.4 Global Placement Core WARN (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew [90%] Routing Phase 3 completed Phase 2.4.1 UpdateTiming Before Physical Synthesis Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1bd3086e3 Time (s): cpu = 00:00:15 ; elapsed = 00:00:04 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8756 ; free virtual = 27522 Phase 2.4.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 71 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 Running timing analysis...... INFO: [Physopt 32-1138] End 1 Pass. Optimized 30 nets or LUTs. Breaked 0 LUT, combined 30 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 8756 ; free virtual = 27524 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 30 | 30 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 30 | 30 | 0 | 4 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.4.2 Physical Synthesis In Placer | Checksum: 13fd60444 Time (s): cpu = 00:00:15 ; elapsed = 00:00:05 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8752 ; free virtual = 27520 Phase 2.4 Global Placement Core | Checksum: 1bcc20026 Time (s): cpu = 00:00:19 ; elapsed = 00:00:05 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8756 ; free virtual = 27524 Phase 2 Global Placement | Checksum: 1bcc20026 Time (s): cpu = 00:00:19 ; elapsed = 00:00:05 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8756 ; free virtual = 27524 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1f7ed1fb5 Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8754 ; free virtual = 27522 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c5aed417 Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8756 ; free virtual = 27524 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 165831a1b Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8756 ; free virtual = 27524 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1dffa75f1 Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8756 ; free virtual = 27524 Phase 3.5 Small Shape Detail Placement [95%] Timing analysis completed Placement and routing completed Bitstream generation in progress...... Phase 3.5 Small Shape Detail Placement | Checksum: 2495072c8 Time (s): cpu = 00:00:21 ; elapsed = 00:00:07 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8752 ; free virtual = 27529 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 2500b3b7c Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8752 ; free virtual = 27529 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1a2761762 Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8752 ; free virtual = 27529 Phase 3 Detail Placement | Checksum: 1a2761762 Time (s): cpu = 00:00:22 ; elapsed = 00:00:07 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8752 ; free virtual = 27529 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: 1d05202b8 Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=9.081 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: 1824db9b8 Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 8758 ; free virtual = 27534 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: 1824db9b8 Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 8758 ; free virtual = 27534 Phase 4.1.1.1 BUFG Insertion | Checksum: 1d05202b8 Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8758 ; free virtual = 27534 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=9.081. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1d27eca9b Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8758 ; free virtual = 27534 Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8758 ; free virtual = 27534 Phase 4.1 Post Commit Optimization | Checksum: 1d27eca9b Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8758 ; free virtual = 27534 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1d27eca9b Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8758 ; free virtual = 27534 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 4x4| |___________|___________________|___________________| | South| 1x1| 1x1| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: 1d27eca9b Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8758 ; free virtual = 27534 Phase 4.3 Placer Reporting | Checksum: 1d27eca9b Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8758 ; free virtual = 27534 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 8758 ; free virtual = 27534 Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8758 ; free virtual = 27534 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 172aa4118 Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8758 ; free virtual = 27534 Ending Placer Task | Checksum: dd0ed08b Time (s): cpu = 00:00:25 ; elapsed = 00:00:09 . Memory (MB): peak = 2888.586 ; gain = 7.027 ; free physical = 8758 ; free virtual = 27534 29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:09 . Memory (MB): peak = 2888.586 ; gain = 39.043 ; free physical = 8758 ; free virtual = 27534 # report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt # report_utilization -file digilent_nexys4ddr_utilization_place.rpt # report_io -file digilent_nexys4ddr_io.rpt report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 8750 ; free virtual = 27527 # report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt report_control_sets: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 8746 ; free virtual = 27524 # report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt # route_design Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design Checksum: PlaceDB: a88f9ee7 ConstDB: 0 ShapeSum: 347f31a4 RouteDB: 0 Bitstream generation completed Running power analysis...... [100%] Power analysis completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed Tue Jun 18 02:07:32 2024 [Pipeline] } [Pipeline] // stage [Pipeline] } Post Restoration Checksum: NetGraph: 6e34220a | NumContArr: 4c668841 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 23fec9f85 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 9046 ; free virtual = 27835 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 23fec9f85 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 9046 ; free virtual = 27835 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 23fec9f85 Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 9046 ; free virtual = 27835 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 3269063f7 Time (s): cpu = 00:00:37 ; elapsed = 00:00:28 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 9011 ; free virtual = 27800 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.996 | TNS=0.000 | WHS=-0.066 | THS=-0.066 | Router Utilization Summary Global Vertical Routing Utilization = 0.00047874 % Global Horizontal Routing Utilization = 0.0004973 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 3858 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 3854 Number of Partially Routed Nets = 4 Number of Node Overlaps = 2 Phase 2 Router Initialization | Checksum: 276001bf3 Time (s): cpu = 00:00:39 ; elapsed = 00:00:28 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 9012 ; free virtual = 27801 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 276001bf3 Time (s): cpu = 00:00:39 ; elapsed = 00:00:28 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 9012 ; free virtual = 27801 Phase 3.2 Initial Net Routing Phase 3.2 Initial Net Routing | Checksum: 1e209afe4 Time (s): cpu = 00:00:40 ; elapsed = 00:00:29 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 9012 ; free virtual = 27801 Phase 3 Initial Routing | Checksum: 1e209afe4 Time (s): cpu = 00:00:40 ; elapsed = 00:00:29 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 9012 ; free virtual = 27801 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 581 Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.788 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 20fe18fd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 9000 ; free virtual = 27790 Phase 4 Rip-up And Reroute | Checksum: 20fe18fd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 9000 ; free virtual = 27790 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 20fe18fd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 9000 ; free virtual = 27790 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 20fe18fd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 9000 ; free virtual = 27790 Phase 5 Delay and Skew Optimization | Checksum: 20fe18fd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 9000 ; free virtual = 27790 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 28643b874 Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 8999 ; free virtual = 27790 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.884 | TNS=0.000 | WHS=0.247 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 28643b874 Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 8999 ; free virtual = 27790 Phase 6 Post Hold Fix | Checksum: 28643b874 Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 8999 ; free virtual = 27789 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.769117 % Global Horizontal Routing Utilization = 0.951904 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 28643b874 Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 8998 ; free virtual = 27788 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 28643b874 Time (s): cpu = 00:00:44 ; elapsed = 00:00:30 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 8996 ; free virtual = 27786 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 2bb4935b9 Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 8999 ; free virtual = 27789 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=8.884 | TNS=0.000 | WHS=0.247 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 2bb4935b9 Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 8999 ; free virtual = 27789 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing Phase 11 Post-Route Event Processing | Checksum: 19ff923a6 Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 8998 ; free virtual = 27788 Ending Routing Task | Checksum: 19ff923a6 Time (s): cpu = 00:00:45 ; elapsed = 00:00:31 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 8997 ; free virtual = 27788 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:32 . Memory (MB): peak = 2888.586 ; gain = 0.000 ; free physical = 8997 ; free virtual = 27788 # report_timing_summary -no_header -no_detailed_paths INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (2258) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (7344) 5. checking no_input_delay (10) 6. checking no_output_delay (17) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (2258) --------------------------- There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[37]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[38]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[40]/Q (HIGH) There are 2246 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH) 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (7344) --------------------------------------------------- There are 7344 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (10) ------------------------------- There are 10 input ports with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (17) -------------------------------- There are 17 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 8.908 0.000 0 1 0.263 0.000 0 1 4.500 0.000 0 3 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- sys_clk_pin {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- sys_clk_pin 8.908 0.000 0 1 0.263 0.000 0 1 4.500 0.000 0 3 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- # report_route_status -file digilent_nexys4ddr_route_status.rpt # report_drc -file digilent_nexys4ddr_drc.rpt Command: report_drc -file digilent_nexys4ddr_drc.rpt INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt. report_drc completed successfully # report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs # report_power -file digilent_nexys4ddr_power.rpt Command: report_power -file digilent_nexys4ddr_power.rpt Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully # write_bitstream -force "./build/out.bit" Command: write_bitstream -force ./build/out.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. WARNING: [DRC PDRC-153] Gated clock check: Net SOC/Core/Control_Unit/FSM_onehot_state_reg[40]_1[0] is a gated clock net sourced by a combinational pin SOC/Core/Control_Unit/aluop_out_reg[3]_i_2/O, cell SOC/Core/Control_Unit/aluop_out_reg[3]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./build/out.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 3204.602 ; gain = 248.145 ; free physical = 8609 ; free virtual = 27450 INFO: [Common 17-206] Exiting Vivado at Tue Jun 18 02:08:25 2024... [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Flash) [Pipeline] parallel [Pipeline] { (Branch: openFPGAloader ECP5) [Pipeline] { (Branch: openFPGAloader Tangnano 20k) [Pipeline] { (Branch: openFPGAloader Nexys 4 DDR) [Pipeline] stage [Pipeline] { (openFPGAloader ECP5) [Pipeline] stage [Pipeline] { (openFPGAloader Tangnano 20k) [Pipeline] stage [Pipeline] { (openFPGAloader Nexys 4 DDR) [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] lock Trying to acquire lock on [ecp5] Resource [ecp5] did not exist. Created. Lock acquired on [ecp5] [Pipeline] { [Pipeline] lock Trying to acquire lock on [tangnano20k] Resource [tangnano20k] did not exist. Created. Lock acquired on [tangnano20k] [Pipeline] { [Pipeline] lock Trying to acquire lock on [nexys4] Resource [nexys4] did not exist. Created. Lock acquired on [nexys4] [Pipeline] { [Pipeline] echo FPGA ECP5 Broqueada [Pipeline] sh [Pipeline] echo FPGA TangNano Broqueada + /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit empty Found 1 compatible device: 0x0d28 0x0204 0x3 DAPLink CMSIS-DAP Open file: DONE b3bdffff Parse file: DONE Enable configuration: DONE SRAM erase: DONE [Pipeline] sh [Pipeline] echo FPGA Nexys 4 Broqueada + echo gravando na tang nano gravando na tang nano [Pipeline] sh + cd Risco-5/fpga/nexys4_ddr + /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit empty Jtag frequency : requested 6.00MHz -> real 6.00MHz Open file DONE Parse file DONE load program [Pipeline] } Lock released on resource [tangnano20k] [Pipeline] // lock Loading: [====== ] 11.16%[Pipeline] } Load SRAM: [========= ] 18.00%[Pipeline] // script [Pipeline] } [Pipeline] // stage [Pipeline] } Loading: [============ ] 22.31% Load SRAM: [=================== ] 38.00% Loading: [================= ] 33.47% Load SRAM: [============================= ] 58.00% Loading: [======================= ] 44.62% Load SRAM: [======================================= ] 78.00% Loading: [============================ ] 55.78% Load SRAM: [================================================= ] 98.00% Load SRAM: [===================================================] 100.00% Done [Pipeline] } Lock released on resource [nexys4] Loading: [================================== ] 66.94%[Pipeline] // lock [Pipeline] } [Pipeline] // script [Pipeline] } [Pipeline] // stage [Pipeline] } Loading: [======================================== ] 78.09% Loading: [============================================= ] 89.25% Loading: [==================================================] 100.00% Done Disable configuration: DONE [Pipeline] } Lock released on resource [ecp5] [Pipeline] // lock [Pipeline] } [Pipeline] // script [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Testes) [Pipeline] parallel [Pipeline] { (Branch: ECP5 - Testes) [Pipeline] { (Branch: TangNano - Testes) [Pipeline] { (Branch: Nexys 4 - Testes) [Pipeline] stage [Pipeline] { (ECP5 - Testes) [Pipeline] stage [Pipeline] { (TangNano - Testes) [Pipeline] stage [Pipeline] { (Nexys 4 - Testes) [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] script [Pipeline] { [Pipeline] echo Rodando teste na ECP5 [Pipeline] lock Trying to acquire lock on [ecp5] Resource [ecp5] did not exist. Created. Lock acquired on [ecp5] [Pipeline] { [Pipeline] echo Rodando teste na tang nano [Pipeline] lock Trying to acquire lock on [tangnano20k] Resource [tangnano20k] did not exist. Created. Lock acquired on [tangnano20k] [Pipeline] { [Pipeline] echo Rodando teste na Nexys 4 [Pipeline] lock Trying to acquire lock on [nexys4] Resource [nexys4] did not exist. Created. Lock acquired on [nexys4] [Pipeline] { [Pipeline] echo FPGA ECP5 Broqueada [Pipeline] sh [Pipeline] echo FPGA TangNano Broqueada + echo testando na ecp5 testando na ecp5 [Pipeline] sh [Pipeline] echo FPGA Nexys 4 Broqueada + echo testando na tang nano testando na tang nano [Pipeline] sh + echo testando na tang nano testando na tang nano [Pipeline] } Lock released on resource [ecp5] [Pipeline] } Lock released on resource [tangnano20k] [Pipeline] // lock [Pipeline] // lock [Pipeline] echo ECP5 liberada [Pipeline] } [Pipeline] echo TangNano liberada [Pipeline] } [Pipeline] } Lock released on resource [nexys4] [Pipeline] // script [Pipeline] // script [Pipeline] // lock [Pipeline] } [Pipeline] } [Pipeline] echo TangNano liberada [Pipeline] } [Pipeline] // stage [Pipeline] // stage [Pipeline] // script [Pipeline] } [Pipeline] } [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline Finished: SUCCESS