Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Risco_5
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -Rf Risco-5/ build/
[Pipeline] sh
+ git clone https://github.com/JN513/Risco-5
Cloning into 'Risco-5'...
[Pipeline] sh
+ cd Risco-5
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (IVerilog)
[Pipeline] sh
+ mkdir -p build
[Pipeline] sh
+ cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/alu.v Risco-5/src/core/alu_control.v Risco-5/src/core/control_unit.v Risco-5/src/core/core.v Risco-5/src/core/csr_unit.v Risco-5/src/core/immediate_generator.v Risco-5/src/core/mdu.v Risco-5/src/core/mux.v Risco-5/src/core/pc.v Risco-5/src/core/registers.v Risco-5/src/peripheral/bus.v Risco-5/src/peripheral/fifo.v Risco-5/src/peripheral/gpio.v Risco-5/src/peripheral/gpios.v Risco-5/src/peripheral/leds.v Risco-5/src/peripheral/memory.v Risco-5/src/peripheral/pwm.v Risco-5/src/peripheral/soc.v Risco-5/src/peripheral/uart.v Risco-5/src/peripheral/uart_rx.v Risco-5/src/peripheral/uart_tx.v Risco-5/tests/soc_test.v
[Pipeline] sh
+ /eda/oss-cad-suite/bin/vvp build/soc_test.o
ERROR: Risco-5/src/peripheral/memory.v:35: $readmemh: Unable to open software/memory/generic.hex for reading.
VCD info: dumpfile build/soc.vcd opened for output.
Risco-5/tests/soc_test.v:42: $finish called at 3606 (1s)
[Pipeline] sh
+ rm -f Risco-5/software/memory/generic.hex
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Síntese)
[Pipeline] parallel
[Pipeline] { (Branch: OSS-Cad-Suite)
[Pipeline] { (Branch: Gowin)
[Pipeline] { (Branch: Vivado)
[Pipeline] stage
[Pipeline] { (OSS-Cad-Suite)
[Pipeline] stage
[Pipeline] { (Gowin)
[Pipeline] stage
[Pipeline] { (Vivado)
[Pipeline] stage
[Pipeline] { (Yosys)
[Pipeline] sh
[Pipeline] sh
+ rm -rf Risco-5/impl/pnr
[Pipeline] sh
+ cd Risco-5/fpga/nexys4_ddr
+ mkdir build
+ /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source run.tcl
[Pipeline] sh
+ mkdir -p Risco-5/impl/pnr
+ /eda/oss-cad-suite/bin/yosys -p                                          read_verilog Risco-5/fpga/ecp5/*.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.42+36 (git sha1 07daf61ae, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)

-- Running command `                                         read_verilog Risco-5/fpga/ecp5/*.v;                                         read_verilog Risco-5/debug/reset.v;                                         read_verilog Risco-5/src/core/*.v;                                         read_verilog Risco-5/src/peripheral/*.v;                                         synth_ecp5 -json ./build/out.json -abc9                                     ' --

1. Executing Verilog-2005 frontend: Risco-5/fpga/ecp5/main.v
Parsing Verilog input from `Risco-5/fpga/ecp5/main.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: Risco-5/debug/reset.v
Parsing Verilog input from `Risco-5/debug/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: Risco-5/src/core/alu.v
Parsing Verilog input from `Risco-5/src/core/alu.v' to AST representation.
Generating RTLIL representation for module `\Alu'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: Risco-5/src/core/alu_control.v
Parsing Verilog input from `Risco-5/src/core/alu_control.v' to AST representation.
Generating RTLIL representation for module `\ALU_Control'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: Risco-5/src/core/control_unit.v
Parsing Verilog input from `Risco-5/src/core/control_unit.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: Risco-5/src/core/core.v
Parsing Verilog input from `Risco-5/src/core/core.v' to AST representation.
Generating RTLIL representation for module `\Core'.
Risco-5/src/core/core.v:168: Warning: Identifier `\pc_source' is implicitly declared.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: Risco-5/src/core/csr_unit.v
Parsing Verilog input from `Risco-5/src/core/csr_unit.v' to AST representation.
Generating RTLIL representation for module `\CSR_Unit'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: Risco-5/src/core/immediate_generator.v
Parsing Verilog input from `Risco-5/src/core/immediate_generator.v' to AST representation.
Generating RTLIL representation for module `\Immediate_Generator'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: Risco-5/src/core/mdu.v
Parsing Verilog input from `Risco-5/src/core/mdu.v' to AST representation.
Generating RTLIL representation for module `\MDU'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: Risco-5/src/core/mux.v
Parsing Verilog input from `Risco-5/src/core/mux.v' to AST representation.
Generating RTLIL representation for module `\MUX'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: Risco-5/src/core/pc.v
Parsing Verilog input from `Risco-5/src/core/pc.v' to AST representation.
Generating RTLIL representation for module `\PC'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: Risco-5/src/core/registers.v
Parsing Verilog input from `Risco-5/src/core/registers.v' to AST representation.
Generating RTLIL representation for module `\Registers'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: Risco-5/src/peripheral/bus.v
Parsing Verilog input from `Risco-5/src/peripheral/bus.v' to AST representation.
Generating RTLIL representation for module `\BUS'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: Risco-5/src/peripheral/fifo.v
Parsing Verilog input from `Risco-5/src/peripheral/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpio.v
Parsing Verilog input from `Risco-5/src/peripheral/gpio.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (Risco-5/src/peripheral/gpio.v:9)
Generating RTLIL representation for module `\GPIO'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: Risco-5/src/peripheral/gpios.v
Parsing Verilog input from `Risco-5/src/peripheral/gpios.v' to AST representation.
Generating RTLIL representation for module `\GPIOS'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: Risco-5/src/peripheral/leds.v
Parsing Verilog input from `Risco-5/src/peripheral/leds.v' to AST representation.
Generating RTLIL representation for module `\LEDs'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: Risco-5/src/peripheral/memory.v
Parsing Verilog input from `Risco-5/src/peripheral/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: Risco-5/src/peripheral/pwm.v
Parsing Verilog input from `Risco-5/src/peripheral/pwm.v' to AST representation.
Generating RTLIL representation for module `\PWM'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: Risco-5/src/peripheral/soc.v
Parsing Verilog input from `Risco-5/src/peripheral/soc.v' to AST representation.
Generating RTLIL representation for module `\Risco_5_SOC'.
Successfully finished Verilog frontend.

21. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart.v
Parsing Verilog input from `Risco-5/src/peripheral/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

22. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_rx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_rx'.
Successfully finished Verilog frontend.

23. Executing Verilog-2005 frontend: Risco-5/src/peripheral/uart_tx.v
Parsing Verilog input from `Risco-5/src/peripheral/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tool_tx'.
Successfully finished Verilog frontend.

24. Executing SYNTH_ECP5 pass.

24.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

24.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

24.3. Executing HIERARCHY pass (managing design hierarchy).

24.3.1. Finding top of design hierarchy..
root of   0 design levels: uart_tool_tx        
root of   0 design levels: uart_tool_rx        
root of   1 design levels: UART                
root of   2 design levels: Risco_5_SOC         
root of   0 design levels: PWM                 
root of   0 design levels: Memory              
root of   0 design levels: LEDs                
root of   1 design levels: GPIOS               
root of   0 design levels: GPIO                
root of   0 design levels: FIFO                
root of   0 design levels: BUS                 
root of   0 design levels: Registers           
root of   0 design levels: PC                  
root of   0 design levels: MUX                 
root of   0 design levels: MDU                 
root of   0 design levels: Immediate_Generator 
root of   0 design levels: CSR_Unit            
root of   1 design levels: Core                
root of   0 design levels: Control_Unit        
root of   0 design levels: ALU_Control         
root of   0 design levels: Alu                 
root of   0 design levels: ResetBootSystem     
root of   3 design levels: top                 
Automatically selected top as design top module.

24.3.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:             \PWM
Used module:         \UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \MDU
Used module:             \PC
Used module:     \ResetBootSystem
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \MEMORY_SIZE = 2048
Parameter \MEMORY_FILE = 328'0010111000101110001011110010111000101110001011110111001101101111011001100111010001110111011000010111001001100101001011110110110101100101011011010110111101110010011110010010111101110100011001010111001101110100011001010101111101110101011000010111001001110100010111110110011001110000011001110110000100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6
Parameter \UART_BUFFER_SIZE = 16

24.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Risco_5_SOC'.
Parameter \CLOCK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \MEMORY_SIZE = 2048
Parameter \MEMORY_FILE = 328'0010111000101110001011110010111000101110001011110111001101101111011001100111010001110111011000010111001001100101001011110110110101100101011011010110111101110010011110010010111101110100011001010111001101110100011001010101111101110101011000010111001001110100010111110110011001110000011001110110000100101110011010000110010101111000
Parameter \GPIO_WIDHT = 6
Parameter \UART_BUFFER_SIZE = 16
Generating RTLIL representation for module `$paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC'.
Parameter \CYCLES = 20

24.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \WIDHT = 5

24.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 5
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \BUFFER_SIZE = 8

24.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \BUFFER_SIZE = 8
Generating RTLIL representation for module `$paramod$65634474087d1ba2b03796f9a45556e4bd507a57\UART'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

24.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \BOOT_ADDRESS = 0

24.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'.
Parameter \BOOT_ADDRESS = 0
Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.
Risco-5/src/core/core.v:168: Warning: Identifier `\pc_source' is implicitly declared.
Reprocessing module GPIOS because instantiated module PWM has become available.
Generating RTLIL representation for module `\GPIOS'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

24.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

24.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

24.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

24.3.12. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC
Used module:         \GPIOS
Used module:             \GPIO
Used module:             \PWM
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         \Memory
Used module:         \Core
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \MDU
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \WIDHT = 6

24.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\GPIOS'.
Parameter \WIDHT = 6
Generating RTLIL representation for module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \BUFFER_SIZE = 16

24.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \BUFFER_SIZE = 16
Generating RTLIL representation for module `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART'.
Parameter \MEMORY_FILE = 328'0010111000101110001011110010111000101110001011110111001101101111011001100111010001110111011000010111001001100101001011110110110101100101011011010110111101110010011110010010111101110100011001010111001101110100011001010101111101110101011000010111001001110100010111110110011001110000011001110110000100101110011010000110010101111000
Parameter \MEMORY_SIZE = 2048

24.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = 328'0010111000101110001011110010111000101110001011110111001101101111011001100111010001110111011000010111001001100101001011110110110101100101011011010110111101110010011110010010111101110100011001010111001101110100011001010101111101110101011000010111001001110100010111110110011001110000011001110110000100101110011010000110010101111000
Parameter \MEMORY_SIZE = 2048
Generating RTLIL representation for module `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory'.
Parameter \BOOT_ADDRESS = 0
Found cached RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.

24.3.16. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:             \PWM
Used module:         $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART
Used module:             \uart_tool_tx
Used module:             \uart_tool_rx
Used module:             \FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \MDU
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

24.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

24.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tool_rx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx'.
Parameter \DEPTH = 16
Parameter \WIDTH = 8

24.3.19. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 16
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO'.
Parameter \DEPTH = 16
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO'.

24.3.20. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:             \PWM
Used module:         $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx
Used module:             $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \MDU
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100

24.3.21. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC
Used module:         $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110
Used module:             \GPIO
Used module:             \PWM
Used module:         $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx
Used module:             $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO
Used module:         \LEDs
Used module:         \BUS
Used module:         $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory
Used module:         $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:             \CSR_Unit
Used module:             \Immediate_Generator
Used module:             \Alu
Used module:             \ALU_Control
Used module:             \Control_Unit
Used module:             \Registers
Used module:             \MUX
Used module:             \MDU
Used module:             \PC
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_rx'.
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tool_tx'.
Removing unused module `\GPIOS'.
Removing unused module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Removing unused module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Removing unused module `$paramod$65634474087d1ba2b03796f9a45556e4bd507a57\UART'.
Removing unused module `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000101'.
Removing unused module `\uart_tool_tx'.
Removing unused module `\uart_tool_rx'.
Removing unused module `\UART'.
Removing unused module `\Risco_5_SOC'.
Removing unused module `\Memory'.
Removing unused module `\FIFO'.
Removing unused module `\Core'.
Removing unused module `\ResetBootSystem'.
Removed 15 unused modules.

24.4. Executing PROC pass (convert processes to netlists).

24.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$735'.
Found and cleaned up 1 empty switch in `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:0$1465'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:128$122'.
Cleaned up 3 empty switches.

24.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$842 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$794 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$736 in module TRELLIS_DPR16X4.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:189$1558 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:178$1556 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:163$1548 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:152$1545 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:140$1539 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:125$1534 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:108$1529 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_rx.v:89$1520 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:167$1507 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:156$1505 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:141$1497 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:124$1483 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:109$1477 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart_tx.v:92$1472 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:59$1463 in module $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/memory.v:47$1426 in module $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:158$1409 in module $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.
Marked 7 switch rules as full_case in process $proc$Risco-5/src/peripheral/uart.v:64$1401 in module $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/pwm.v:11$499 in module PWM.
Marked 3 switch rules as full_case in process $proc$Risco-5/src/peripheral/gpios.v:61$1331 in module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/peripheral/leds.v:23$450 in module LEDs.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/core.v:273$1017 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/peripheral/fifo.v:28$1563 in module $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/registers.v:24$201 in module Registers.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/pc.v:15$190 in module PC.
Marked 5 switch rules as full_case in process $proc$Risco-5/src/core/mdu.v:88$137 in module MDU.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/mdu.v:50$129 in module MDU.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/immediate_generator.v:18$128 in module Immediate_Generator.
Marked 2 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:128$122 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:104$120 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/csr_unit.v:76$119 in module CSR_Unit.
Marked 5 switch rules as full_case in process $proc$Risco-5/debug/reset.v:24$845 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:683$87 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:673$86 in module Control_Unit.
Marked 21 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:152$40 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/control_unit.v:144$39 in module Control_Unit.
Removed 1 dead cases from process $proc$Risco-5/src/core/alu_control.v:9$31 in module ALU_Control.
Marked 4 switch rules as full_case in process $proc$Risco-5/src/core/alu_control.v:9$31 in module ALU_Control.
Marked 1 switch rules as full_case in process $proc$Risco-5/src/core/alu.v:26$11 in module Alu.
Removed a total of 1 dead cases.

24.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 16 redundant assignments.
Promoted 152 assignments to connections.

24.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$843'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:124$1560'.
  Set init value: \i = 0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:108$1513'.
  Set init value: \i = 0
Found init rule in `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:0$1465'.
  Set init value: \memory_response = 1'0
Found init rule in `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:0$1419'.
  Set init value: \state = 4'0000
  Set init value: \counter = 3'000
  Set init value: \read_data = 0
  Set init value: \response = 1'0
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
Found init rule in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:0$1398'.
  Set init value: \is_pwm = 2'00
Found init rule in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$453'.
  Set init value: \data = 0
Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$1023'.
  Set init value: \instruction_register = 0
  Set init value: \memory_register = 0
  Set init value: \alu_out_register = 0
  Set init value: \register_data_1 = 0
  Set init value: \register_data_2 = 0
  Set init value: \pc_old = 0
  Set init value: \temp_address = 0
  Set init value: \temp_reg2 = 0
  Set init value: \temp_write_value = 0
Found init rule in `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:0$1590'.
  Set init value: \counter = 6'000000
  Set init value: \read_ptr = 6'000000
  Set init value: \write_ptr = 6'000000
Found init rule in `\PC.$proc$Risco-5/src/core/pc.v:0$193'.
  Set init value: \Output = 0
Found init rule in `\MDU.$proc$Risco-5/src/core/mdu.v:0$173'.
  Set init value: \state_mul = 2'00
  Set init value: \state_div = 2'00
  Set init value: \Data_X = 0
  Set init value: \Data_Y = 0
  Set init value: \MUL_RD = 0
  Set init value: \acumulador = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$127'.
  Set init value: \mepc = 0
  Set init value: \mscratch = 0
  Set init value: \mcause = 0
  Set init value: \mtval = 0
  Set init value: \mtvec = 0
  Set init value: \mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \minstret = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \utime = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$851'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000
Found init rule in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$88'.
  Set init value: \state = 6'000000
  Set init value: \is_immediate = 1'0
  Set init value: \pc_write = 1'0
  Set init value: \ir_write = 1'0
  Set init value: \pc_source = 1'0
  Set init value: \reg_write = 1'0
  Set init value: \memory_read = 1'0
  Set init value: \memory_write = 1'0
  Set init value: \pc_write_cond = 1'0
  Set init value: \csr_write_enable = 1'0
  Set init value: \alu_input_selector = 1'0
  Set init value: \save_address = 1'0
  Set init value: \save_value = 1'0
  Set init value: \save_value_2 = 1'0
  Set init value: \save_write_value = 1'0
  Set init value: \control_memory_op = 1'0
  Set init value: \write_data_in = 1'0
  Set init value: \mdu_start = 1'0
  Set init value: \lorD = 2'00
  Set init value: \aluop = 2'00
  Set init value: \alu_src_a = 3'000
  Set init value: \alu_src_b = 3'000
  Set init value: \memory_to_reg = 3'000
  Set init value: \control_unit_memory_op = 3'010
  Set init value: \control_unit_aluop = 4'0000
  Set init value: \clear_hal_byte_one_block_option = 3'000
  Set init value: \clear_hal_byte_one_block_option_2 = 3'000
  Set init value: \nextstate = 6'000000

24.4.5. Executing PROC_ARST pass (detect async resets in processes).

24.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~133 debug messages>

24.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$843'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$842'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$794'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$793_EN[3:0]$800
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$793_DATA[3:0]$799
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$793_ADDR[3:0]$798
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$736'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$734_EN[3:0]$742
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$734_DATA[3:0]$741
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$734_ADDR[3:0]$740
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$735'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:124$1560'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1558'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1556'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1548'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1545'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1539'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1534'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1529'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1520'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:108$1513'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$1507'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$1505'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$1497'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$1483'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$1477'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$1472'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:0$1465'.
Creating decoders for process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:59$1463'.
     1/1: $1\read_data[31:0]
Creating decoders for process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1426'.
     1/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1461
     2/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_DATA[31:0]$1462
     3/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_ADDR[31:0]$1457
     4/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_ADDR[31:0]$1460
     5/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_DATA[31:0]$1459
     6/24: $3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1458
     7/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1448
     8/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_DATA[31:0]$1449
     9/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_ADDR[31:0]$1450
    10/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_DATA[31:0]$1455
    11/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1454
    12/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_ADDR[31:0]$1453
    13/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_DATA[31:0]$1452
    14/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1451
    15/24: $2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_ADDR[31:0]$1447
    16/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_DATA[31:0]$1445
    17/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1444
    18/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_ADDR[31:0]$1443
    19/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_DATA[31:0]$1442
    20/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1441
    21/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_ADDR[31:0]$1440
    22/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_DATA[31:0]$1439
    23/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1438
    24/24: $1$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_ADDR[31:0]$1437
Creating decoders for process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:39$1424'.
     1/1: $0\memory_response[0:0]
Creating decoders for process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:0$1419'.
Creating decoders for process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$1409'.
     1/5: $0\rx_fifo_write[0:0]
     2/5: $0\tx_fifo_read[0:0]
     3/5: $0\uart_tx_en[0:0]
     4/5: $0\rx_fifo_write_data[7:0]
     5/5: $0\uart_tx_data[7:0]
Creating decoders for process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1401'.
     1/8: $0\tx_fifo_write[0:0]
     2/8: $0\rx_fifo_read[0:0]
     3/8: $0\response[0:0]
     4/8: $0\write_data_buffer[31:0]
     5/8: $0\tx_fifo_write_data[7:0]
     6/8: $0\read_data[31:0]
     7/8: $0\counter[2:0]
     8/8: $0\state[3:0]
Creating decoders for process `\PWM.$proc$Risco-5/src/peripheral/pwm.v:11$499'.
     1/2: $0\pwm_out[0:0]
     2/2: $0\counter[31:0]
Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:0$1398'.
Creating decoders for process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1331'.
     1/21: $3$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1355
     2/21: $3$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_DATA[15:0]$1354
     3/21: $3$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_ADDR[0:0]$1353
     4/21: $3$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1352
     5/21: $3$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_DATA[15:0]$1351
     6/21: $3$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_ADDR[0:0]$1350
     7/21: $2$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1349
     8/21: $2$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_DATA[15:0]$1348
     9/21: $2$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_ADDR[0:0]$1347
    10/21: $2$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1346
    11/21: $2$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_DATA[15:0]$1345
    12/21: $2$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_ADDR[0:0]$1344
    13/21: $1$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1343
    14/21: $1$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_DATA[15:0]$1342
    15/21: $1$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_ADDR[0:0]$1341
    16/21: $1$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1340
    17/21: $1$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_DATA[15:0]$1339
    18/21: $1$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_ADDR[0:0]$1338
    19/21: $0\is_pwm[1:0]
    20/21: $0\gpio_value[5:0]
    21/21: $0\gpio_direction[5:0]
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:0$453'.
Creating decoders for process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$450'.
     1/1: $0\data[31:0]
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$1023'.
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$1017'.
     1/11: $0\alu_out_register[31:0]
     2/11: $0\register_data_2[31:0]
     3/11: $0\register_data_1[31:0]
     4/11: $0\memory_register[31:0]
     5/11: $0\mdu_out_reg[31:0]
     6/11: $0\temp_write_value[31:0]
     7/11: $0\temp_reg3[31:0]
     8/11: $0\temp_reg2[31:0]
     9/11: $0\temp_address[31:0]
    10/11: $0\pc_old[31:0]
    11/11: $0\instruction_register[31:0]
Creating decoders for process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:0$1590'.
Creating decoders for process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1563'.
     1/9: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1575
     2/9: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_DATA[7:0]$1574
     3/9: $2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_ADDR[5:0]$1573
     4/9: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1570
     5/9: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_DATA[7:0]$1569
     6/9: $1$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_ADDR[5:0]$1568
     7/9: $0\write_ptr[5:0]
     8/9: $0\read_ptr[5:0]
     9/9: $0\counter[5:0]
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:0$219'.
Creating decoders for process `\Registers.$proc$Risco-5/src/core/registers.v:24$201'.
     1/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$216
     2/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$196_DATA[31:0]$215
     3/9: $2$memwr$\registers$Risco-5/src/core/registers.v:28$196_ADDR[4:0]$214
     4/9: $2$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$217
     5/9: $1$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$208
     6/9: $1$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$212
     7/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$211
     8/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$196_DATA[31:0]$210
     9/9: $1$memwr$\registers$Risco-5/src/core/registers.v:28$196_ADDR[4:0]$209
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:0$193'.
Creating decoders for process `\PC.$proc$Risco-5/src/core/pc.v:15$190'.
     1/1: $0\Output[31:0]
Creating decoders for process `\MDU.$proc$Risco-5/src/core/mdu.v:0$173'.
Creating decoders for process `\MDU.$proc$Risco-5/src/core/mdu.v:88$137'.
     1/8: $0\state_div[1:0]
     2/8: $0\div_done[0:0]
     3/8: $0\divisor[63:0]
     4/8: $0\DIV_RD[31:0]
     5/8: $0\quociente_msk[31:0]
     6/8: $0\quociente[31:0]
     7/8: $0\dividendo[31:0]
     8/8: $0\negativo[0:0]
Creating decoders for process `\MDU.$proc$Risco-5/src/core/mdu.v:50$129'.
     1/6: $0\state_mul[1:0]
     2/6: $0\mul_done[0:0]
     3/6: $0\acumulador[63:0]
     4/6: $0\MUL_RD[31:0]
     5/6: $0\Data_Y[31:0]
     6/6: $0\Data_X[31:0]
Creating decoders for process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$128'.
     1/2: $2\immediate[31:0]
     2/2: $1\immediate[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$127'.
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:128$122'.
     1/1: $0\minstret[63:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'.
     1/7: $0\mcycle[63:0]
     2/7: $0\utime[63:0]
     3/7: $0\mtvec[31:0]
     4/7: $0\mtval[31:0]
     5/7: $0\mcause[31:0]
     6/7: $0\mscratch[31:0]
     7/7: $0\mepc[31:0]
Creating decoders for process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:76$119'.
     1/1: $0\csr_data_out[31:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$851'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$845'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$88'.
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$87'.
     1/2: $0\clear_hal_byte_one_block_option_2[2:0]
     2/2: $0\clear_hal_byte_one_block_option[2:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:673$86'.
     1/1: $0\wb_filter[2:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
     1/23: $0\mdu_start[0:0]
     2/23: $0\save_write_value[0:0]
     3/23: $0\write_data_in[0:0]
     4/23: $0\save_value_2[0:0]
     5/23: $0\save_value[0:0]
     6/23: $0\control_memory_op[0:0]
     7/23: $0\save_address[0:0]
     8/23: $0\control_unit_aluop[3:0]
     9/23: $0\alu_input_selector[0:0]
    10/23: $0\csr_write_enable[0:0]
    11/23: $0\is_immediate[0:0]
    12/23: $0\reg_write[0:0]
    13/23: $0\alu_src_a[2:0]
    14/23: $0\alu_src_b[2:0]
    15/23: $0\aluop[1:0]
    16/23: $0\pc_source[0:0]
    17/23: $0\memory_to_reg[2:0]
    18/23: $0\memory_write[0:0]
    19/23: $0\memory_read[0:0]
    20/23: $0\lorD[1:0]
    21/23: $0\ir_write[0:0]
    22/23: $0\pc_write[0:0]
    23/23: $0\pc_write_cond[0:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40'.
     1/21: $21\nextstate[5:0]
     2/21: $20\nextstate[5:0]
     3/21: $19\nextstate[5:0]
     4/21: $18\nextstate[5:0]
     5/21: $17\nextstate[5:0]
     6/21: $16\nextstate[5:0]
     7/21: $15\nextstate[5:0]
     8/21: $14\nextstate[5:0]
     9/21: $13\nextstate[5:0]
    10/21: $12\nextstate[5:0]
    11/21: $11\nextstate[5:0]
    12/21: $10\nextstate[5:0]
    13/21: $9\nextstate[5:0]
    14/21: $8\nextstate[5:0]
    15/21: $7\nextstate[5:0]
    16/21: $6\nextstate[5:0]
    17/21: $5\nextstate[5:0]
    18/21: $4\nextstate[5:0]
    19/21: $3\nextstate[5:0]
    20/21: $2\nextstate[5:0]
    21/21: $1\nextstate[5:0]
Creating decoders for process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:144$39'.
     1/1: $0\state[5:0]
Creating decoders for process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'.
     1/1: $0\aluop_out[3:0]
Creating decoders for process `\Alu.$proc$Risco-5/src/core/alu.v:26$11'.
     1/1: $1\ALU_out_S[31:0]

24.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1529'.
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$1472'.
No latch inferred for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.\read_data' from process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:59$1463'.
No latch inferred for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\period$Risco-5/src/peripheral/gpios.v:25$1323_EN' from process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:0$1398'.
No latch inferred for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:26$1324_EN' from process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:0$1398'.
No latch inferred for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:17$194_EN' from process `\Registers.$proc$Risco-5/src/core/registers.v:0$219'.
No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$128'.
No latch inferred for signal `\CSR_Unit.\csr_data_out' from process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:76$119'.
No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$87'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$87`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$87`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$87`.
No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option_2' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$87'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$87`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$87`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\clear_hal_byte_one_block_option_2 [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$87`.
No latch inferred for signal `\Control_Unit.\wb_filter' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:673$86'.
No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\csr_write_enable` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\alu_input_selector' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_input_selector` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\save_address' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_address` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\save_value' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\save_value_2' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value_2` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\save_write_value' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_write_value` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\control_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_memory_op` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\write_data_in' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\write_data_in` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\mdu_start' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\mdu_start` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\control_unit_memory_op' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
Removing init bit 1'1 for non-memory siginal `\Control_Unit.\control_unit_memory_op [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\control_unit_aluop' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73`.
No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [4]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [5]` in process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40`.
No latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'.
No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$Risco-5/src/core/alu.v:26$11'.

24.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$842'.
  created $dff cell `$procdff$4094' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$778_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$779_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$780_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$781_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$782_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$783_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$784_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$785_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$786_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$787_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$788_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$789_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$790_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$791_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$792_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$793_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$794'.
  created $dff cell `$procdff$4095' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$793_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$794'.
  created $dff cell `$procdff$4096' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$793_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$794'.
  created $dff cell `$procdff$4097' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$718_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$719_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$720_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$721_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$722_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$723_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$724_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$725_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$726_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$727_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$728_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$729_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$730_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$731_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$732_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$733_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$734_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$736'.
  created $dff cell `$procdff$4098' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$734_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$736'.
  created $dff cell `$procdff$4099' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$734_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$736'.
  created $dff cell `$procdff$4100' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$735'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1558'.
  created $dff cell `$procdff$4101' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1558'.
  created $dff cell `$procdff$4102' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1556'.
  created $dff cell `$procdff$4103' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1548'.
  created $dff cell `$procdff$4104' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1545'.
  created $dff cell `$procdff$4105' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1539'.
  created $dff cell `$procdff$4106' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1534'.
  created $dff cell `$procdff$4107' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1534'.
  created $dff cell `$procdff$4108' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1520'.
  created $dff cell `$procdff$4109' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$1507'.
  created $dff cell `$procdff$4110' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$1505'.
  created $dff cell `$procdff$4111' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$1497'.
  created $dff cell `$procdff$4112' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$1483'.
  created $dff cell `$procdff$4113' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$1477'.
  created $dff cell `$procdff$4114' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$1477'.
  created $dff cell `$procdff$4115' with positive edge clock.
Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_ADDR' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1426'.
  created $dff cell `$procdff$4116' with positive edge clock.
Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1426'.
  created $dff cell `$procdff$4117' with positive edge clock.
Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_DATA' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1426'.
  created $dff cell `$procdff$4118' with positive edge clock.
Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_ADDR' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1426'.
  created $dff cell `$procdff$4119' with positive edge clock.
Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1426'.
  created $dff cell `$procdff$4120' with positive edge clock.
Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_DATA' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1426'.
  created $dff cell `$procdff$4121' with positive edge clock.
Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_ADDR' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1426'.
  created $dff cell `$procdff$4122' with positive edge clock.
Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1426'.
  created $dff cell `$procdff$4123' with positive edge clock.
Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_DATA' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1426'.
  created $dff cell `$procdff$4124' with positive edge clock.
Creating register for signal `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.\memory_response' using process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:39$1424'.
  created $dff cell `$procdff$4125' with positive edge clock.
Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\uart_tx_en' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$1409'.
  created $dff cell `$procdff$4126' with positive edge clock.
Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\tx_fifo_read' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$1409'.
  created $dff cell `$procdff$4127' with positive edge clock.
Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\rx_fifo_write' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$1409'.
  created $dff cell `$procdff$4128' with positive edge clock.
Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\uart_tx_data' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$1409'.
  created $dff cell `$procdff$4129' with positive edge clock.
Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\rx_fifo_write_data' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$1409'.
  created $dff cell `$procdff$4130' with positive edge clock.
Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\state' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1401'.
  created $dff cell `$procdff$4131' with positive edge clock.
Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\counter' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1401'.
  created $dff cell `$procdff$4132' with positive edge clock.
Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\read_data' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1401'.
  created $dff cell `$procdff$4133' with positive edge clock.
Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\response' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1401'.
  created $dff cell `$procdff$4134' with positive edge clock.
Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\tx_fifo_write' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1401'.
  created $dff cell `$procdff$4135' with positive edge clock.
Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\rx_fifo_read' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1401'.
  created $dff cell `$procdff$4136' with positive edge clock.
Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\tx_fifo_write_data' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1401'.
  created $dff cell `$procdff$4137' with positive edge clock.
Creating register for signal `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.\write_data_buffer' using process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1401'.
  created $dff cell `$procdff$4138' with positive edge clock.
Creating register for signal `\PWM.\counter' using process `\PWM.$proc$Risco-5/src/peripheral/pwm.v:11$499'.
  created $dff cell `$procdff$4139' with positive edge clock.
Creating register for signal `\PWM.\pwm_out' using process `\PWM.$proc$Risco-5/src/peripheral/pwm.v:11$499'.
  created $dff cell `$procdff$4140' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_direction' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1331'.
  created $dff cell `$procdff$4141' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\gpio_value' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1331'.
  created $dff cell `$procdff$4142' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.\is_pwm' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1331'.
  created $dff cell `$procdff$4143' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_ADDR' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1331'.
  created $dff cell `$procdff$4144' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_DATA' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1331'.
  created $dff cell `$procdff$4145' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1331'.
  created $dff cell `$procdff$4146' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_ADDR' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1331'.
  created $dff cell `$procdff$4147' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_DATA' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1331'.
  created $dff cell `$procdff$4148' with positive edge clock.
Creating register for signal `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN' using process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1331'.
  created $dff cell `$procdff$4149' with positive edge clock.
Creating register for signal `\LEDs.\data' using process `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$450'.
  created $dff cell `$procdff$4150' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$1017'.
  created $dff cell `$procdff$4151' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$1017'.
  created $dff cell `$procdff$4152' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$1017'.
  created $dff cell `$procdff$4153' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$1017'.
  created $dff cell `$procdff$4154' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$1017'.
  created $dff cell `$procdff$4155' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$1017'.
  created $dff cell `$procdff$4156' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_address' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$1017'.
  created $dff cell `$procdff$4157' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_reg2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$1017'.
  created $dff cell `$procdff$4158' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_reg3' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$1017'.
  created $dff cell `$procdff$4159' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\temp_write_value' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$1017'.
  created $dff cell `$procdff$4160' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\mdu_out_reg' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$1017'.
  created $dff cell `$procdff$4161' with positive edge clock.
Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.\counter' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1563'.
  created $dff cell `$procdff$4162' with positive edge clock.
Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.\read_ptr' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1563'.
  created $dff cell `$procdff$4163' with positive edge clock.
Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.\write_ptr' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1563'.
  created $dff cell `$procdff$4164' with positive edge clock.
Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_ADDR' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1563'.
  created $dff cell `$procdff$4165' with positive edge clock.
Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_DATA' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1563'.
  created $dff cell `$procdff$4166' with positive edge clock.
Creating register for signal `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN' using process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1563'.
  created $dff cell `$procdff$4167' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$201'.
  created $dff cell `$procdff$4168' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$196_ADDR' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$201'.
  created $dff cell `$procdff$4169' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$196_DATA' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$201'.
  created $dff cell `$procdff$4170' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$201'.
  created $dff cell `$procdff$4171' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN' using process `\Registers.$proc$Risco-5/src/core/registers.v:24$201'.
  created $dff cell `$procdff$4172' with positive edge clock.
Creating register for signal `\PC.\Output' using process `\PC.$proc$Risco-5/src/core/pc.v:15$190'.
  created $dff cell `$procdff$4173' with positive edge clock.
Creating register for signal `\MDU.\div_done' using process `\MDU.$proc$Risco-5/src/core/mdu.v:88$137'.
  created $dff cell `$procdff$4174' with positive edge clock.
Creating register for signal `\MDU.\state_div' using process `\MDU.$proc$Risco-5/src/core/mdu.v:88$137'.
  created $dff cell `$procdff$4175' with positive edge clock.
Creating register for signal `\MDU.\negativo' using process `\MDU.$proc$Risco-5/src/core/mdu.v:88$137'.
  created $dff cell `$procdff$4176' with positive edge clock.
Creating register for signal `\MDU.\dividendo' using process `\MDU.$proc$Risco-5/src/core/mdu.v:88$137'.
  created $dff cell `$procdff$4177' with positive edge clock.
Creating register for signal `\MDU.\quociente' using process `\MDU.$proc$Risco-5/src/core/mdu.v:88$137'.
  created $dff cell `$procdff$4178' with positive edge clock.
Creating register for signal `\MDU.\quociente_msk' using process `\MDU.$proc$Risco-5/src/core/mdu.v:88$137'.
  created $dff cell `$procdff$4179' with positive edge clock.
Creating register for signal `\MDU.\DIV_RD' using process `\MDU.$proc$Risco-5/src/core/mdu.v:88$137'.
  created $dff cell `$procdff$4180' with positive edge clock.
Creating register for signal `\MDU.\divisor' using process `\MDU.$proc$Risco-5/src/core/mdu.v:88$137'.
  created $dff cell `$procdff$4181' with positive edge clock.
Creating register for signal `\MDU.\mul_done' using process `\MDU.$proc$Risco-5/src/core/mdu.v:50$129'.
  created $dff cell `$procdff$4182' with positive edge clock.
Creating register for signal `\MDU.\state_mul' using process `\MDU.$proc$Risco-5/src/core/mdu.v:50$129'.
  created $dff cell `$procdff$4183' with positive edge clock.
Creating register for signal `\MDU.\Data_X' using process `\MDU.$proc$Risco-5/src/core/mdu.v:50$129'.
  created $dff cell `$procdff$4184' with positive edge clock.
Creating register for signal `\MDU.\Data_Y' using process `\MDU.$proc$Risco-5/src/core/mdu.v:50$129'.
  created $dff cell `$procdff$4185' with positive edge clock.
Creating register for signal `\MDU.\MUL_RD' using process `\MDU.$proc$Risco-5/src/core/mdu.v:50$129'.
  created $dff cell `$procdff$4186' with positive edge clock.
Creating register for signal `\MDU.\acumulador' using process `\MDU.$proc$Risco-5/src/core/mdu.v:50$129'.
  created $dff cell `$procdff$4187' with positive edge clock.
Creating register for signal `\CSR_Unit.\minstret' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:128$122'.
  created $dff cell `$procdff$4188' with positive edge clock.
Creating register for signal `\CSR_Unit.\mepc' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'.
  created $dff cell `$procdff$4189' with positive edge clock.
Creating register for signal `\CSR_Unit.\mscratch' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'.
  created $dff cell `$procdff$4190' with positive edge clock.
Creating register for signal `\CSR_Unit.\mcause' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'.
  created $dff cell `$procdff$4191' with positive edge clock.
Creating register for signal `\CSR_Unit.\mtval' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'.
  created $dff cell `$procdff$4192' with positive edge clock.
Creating register for signal `\CSR_Unit.\mtvec' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'.
  created $dff cell `$procdff$4193' with positive edge clock.
Creating register for signal `\CSR_Unit.\mcycle' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'.
  created $dff cell `$procdff$4194' with positive edge clock.
Creating register for signal `\CSR_Unit.\utime' using process `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'.
  created $dff cell `$procdff$4195' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$845'.
  created $dff cell `$procdff$4196' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$845'.
  created $dff cell `$procdff$4197' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$845'.
  created $dff cell `$procdff$4198' with positive edge clock.
Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:144$39'.
  created $dff cell `$procdff$4199' with positive edge clock.

24.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$843'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$842'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$842'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$817'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$794'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$736'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$735'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:124$1560'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1558'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:189$1558'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1556'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:178$1556'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1548'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:163$1548'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1545'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:152$1545'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1539'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:140$1539'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1534'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:125$1534'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1529'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:108$1529'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1520'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.$proc$Risco-5/src/peripheral/uart_rx.v:89$1520'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:108$1513'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$1507'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:167$1507'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$1505'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:156$1505'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$1497'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:141$1497'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$1483'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:124$1483'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$1477'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:109$1477'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$1472'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.$proc$Risco-5/src/peripheral/uart_tx.v:92$1472'.
Removing empty process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:0$1465'.
Found and cleaned up 1 empty switch in `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:59$1463'.
Removing empty process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:59$1463'.
Found and cleaned up 3 empty switches in `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1426'.
Removing empty process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:47$1426'.
Found and cleaned up 1 empty switch in `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:39$1424'.
Removing empty process `$paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.$proc$Risco-5/src/peripheral/memory.v:39$1424'.
Removing empty process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:0$1419'.
Found and cleaned up 3 empty switches in `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$1409'.
Removing empty process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:158$1409'.
Found and cleaned up 9 empty switches in `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1401'.
Removing empty process `$paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.$proc$Risco-5/src/peripheral/uart.v:64$1401'.
Found and cleaned up 3 empty switches in `\PWM.$proc$Risco-5/src/peripheral/pwm.v:11$499'.
Removing empty process `PWM.$proc$Risco-5/src/peripheral/pwm.v:11$499'.
Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:0$1398'.
Found and cleaned up 3 empty switches in `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1331'.
Removing empty process `$paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.$proc$Risco-5/src/peripheral/gpios.v:61$1331'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:0$453'.
Found and cleaned up 2 empty switches in `\LEDs.$proc$Risco-5/src/peripheral/leds.v:23$450'.
Removing empty process `LEDs.$proc$Risco-5/src/peripheral/leds.v:23$450'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:0$1023'.
Found and cleaned up 6 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$1017'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$Risco-5/src/core/core.v:273$1017'.
Removing empty process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:0$1590'.
Found and cleaned up 3 empty switches in `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1563'.
Removing empty process `$paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.$proc$Risco-5/src/peripheral/fifo.v:28$1563'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:0$219'.
Found and cleaned up 2 empty switches in `\Registers.$proc$Risco-5/src/core/registers.v:24$201'.
Removing empty process `Registers.$proc$Risco-5/src/core/registers.v:24$201'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:0$193'.
Found and cleaned up 2 empty switches in `\PC.$proc$Risco-5/src/core/pc.v:15$190'.
Removing empty process `PC.$proc$Risco-5/src/core/pc.v:15$190'.
Removing empty process `MDU.$proc$Risco-5/src/core/mdu.v:0$173'.
Found and cleaned up 6 empty switches in `\MDU.$proc$Risco-5/src/core/mdu.v:88$137'.
Removing empty process `MDU.$proc$Risco-5/src/core/mdu.v:88$137'.
Found and cleaned up 4 empty switches in `\MDU.$proc$Risco-5/src/core/mdu.v:50$129'.
Removing empty process `MDU.$proc$Risco-5/src/core/mdu.v:50$129'.
Found and cleaned up 2 empty switches in `\Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$128'.
Removing empty process `Immediate_Generator.$proc$Risco-5/src/core/immediate_generator.v:18$128'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:0$127'.
Found and cleaned up 4 empty switches in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:128$122'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:128$122'.
Found and cleaned up 3 empty switches in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:104$120'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:76$119'.
Removing empty process `CSR_Unit.$proc$Risco-5/src/core/csr_unit.v:76$119'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:0$851'.
Found and cleaned up 5 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$845'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$Risco-5/debug/reset.v:24$845'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:0$88'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$87'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:683$87'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:673$86'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:673$86'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:337$73'.
Found and cleaned up 21 empty switches in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:152$40'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$Risco-5/src/core/control_unit.v:144$39'.
Removing empty process `Control_Unit.$proc$Risco-5/src/core/control_unit.v:144$39'.
Found and cleaned up 5 empty switches in `\ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'.
Removing empty process `ALU_Control.$proc$Risco-5/src/core/alu_control.v:9$31'.
Found and cleaned up 1 empty switch in `\Alu.$proc$Risco-5/src/core/alu.v:26$11'.
Removing empty process `Alu.$proc$Risco-5/src/core/alu.v:26$11'.
Cleaned up 133 empty switches.

24.4.12. Executing OPT_EXPR pass (perform const folding).
[Pipeline] sh
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.
<suppressed ~4 debug messages>
Optimizing module $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.
<suppressed ~17 debug messages>
Optimizing module PWM.
Optimizing module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
<suppressed ~2 debug messages>
Optimizing module LEDs.
<suppressed ~2 debug messages>
Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
<suppressed ~9 debug messages>
Optimizing module GPIO.
<suppressed ~1 debug messages>
Optimizing module $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.
<suppressed ~4 debug messages>
Optimizing module BUS.
<suppressed ~4 debug messages>
Optimizing module Registers.
<suppressed ~2 debug messages>
Optimizing module PC.
<suppressed ~2 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module MDU.
<suppressed ~17 debug messages>
Optimizing module Immediate_Generator.
Optimizing module CSR_Unit.
<suppressed ~1 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~7 debug messages>
Optimizing module Control_Unit.
<suppressed ~25 debug messages>
Optimizing module ALU_Control.
<suppressed ~4 debug messages>
Optimizing module Alu.
<suppressed ~1 debug messages>
Optimizing module $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC.
Optimizing module top.

24.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_rx.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tool_tx.
Deleting now unused module $paramod$870b2daf6c394301398f69058d05355fe7ad757c\Memory.
Deleting now unused module $paramod$2000247f8da78e726acc70cf9f9077ac6f93a8c1\UART.
Deleting now unused module PWM.
Deleting now unused module $paramod\GPIOS\WIDHT=s32'00000000000000000000000000000110.
Deleting now unused module LEDs.
Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Deleting now unused module GPIO.
Deleting now unused module $paramod$d662dacdc4a138ecc4c8da4e616ea7be3bb84705\FIFO.
Deleting now unused module BUS.
Deleting now unused module Registers.
Deleting now unused module PC.
Deleting now unused module MUX.
Deleting now unused module MDU.
Deleting now unused module Immediate_Generator.
Deleting now unused module CSR_Unit.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module Control_Unit.
Deleting now unused module ALU_Control.
Deleting now unused module Alu.
Deleting now unused module $paramod$17da5723ec326559b6c02dbd8a25e71c752daf0f\Risco_5_SOC.
<suppressed ~33 debug messages>

24.6. Executing TRIBUF pass.

24.7. Executing DEMINOUT pass (demote inout ports to input or output).

24.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~47 debug messages>

24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 86 unused cells and 979 unused wires.
<suppressed ~107 debug messages>

24.10. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

24.11. Executing OPT pass (performing simple optimizations).

24.11.1. Executing OPT_EXPR pass (perform const folding).
+ cd Risco-5/fpga/tangnano20k/
+ /eda/gowin/IDE/bin/gw_sh run.tcl
*** GOWIN Tcl Command Line Console  *** 
current device: GW2AR-18C  GW2AR-LV18QN88C8/I7
add new file: "pinout.cst"
add new file: "top.sdc"
add new file: "main.v"
add new file: "../../debug/reset.v"
add new file: "../../src/core/alu_control.v"
add new file: "../../src/core/alu.v"
add new file: "../../src/core/control_unit.v"
add new file: "../../src/core/core.v"
add new file: "../../src/core/immediate_generator.v"
add new file: "../../src/core/mux.v"
add new file: "../../src/core/pc.v"
add new file: "../../src/core/registers.v"
add new file: "../../src/core/csr_unit.v"
add new file: "../../src/core/mdu.v"
add new file: "../../src/peripheral/bus.v"
add new file: "../../src/peripheral/gpio.v"
add new file: "../../src/peripheral/gpios.v"
add new file: "../../src/peripheral/leds.v"
add new file: "../../src/peripheral/memory.v"
add new file: "../../src/peripheral/soc.v"
add new file: "../../src/peripheral/uart_rx.v"
add new file: "../../src/peripheral/uart_tx.v"
add new file: "../../src/peripheral/uart.v"
add new file: "../../src/peripheral/fifo.v"
add new file: "../../src/peripheral/pwm.v"
GowinSynthesis start
Running parser ...
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v'
Undeclared symbol 'pc_source', assumed default net type 'wire'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":168)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mdu.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v'
WARN  (EX3012) : Empty statement in sequential block("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":54)
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v'
Analyzing Verilog file '/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v'
WARN  (EX3073) : Port 'resetn_o' remains unconnected for this instance("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":18)
Compiling module 'top'("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":1)
Compiling module 'ResetBootSystem'("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":1)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v":37)
Compiling module 'Risco_5_SOC(CLOCK_FREQ=27000000,BIT_RATE=115200,MEMORY_SIZE=2048,MEMORY_FILE="../../software/memory/teste_uart_fpga.hex",UART_BUFFER_SIZE=16)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":1)
Compiling module 'Core(BOOT_ADDRESS=32'b00000000000000000000000000000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":2)
Compiling module 'PC'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v":1)
Compiling module 'MUX'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v":1)
Compiling module 'MDU'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mdu.v":6)
WARN  (EX3791) : Expression size 64 truncated to fit in target size 32("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mdu.v":116)
Compiling module 'Registers'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v":1)
Compiling module 'Control_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":2)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":546)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":553)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":566)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 3("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v":573)
Compiling module 'ALU_Control'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v":1)
Compiling module 'Alu'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v":1)
Compiling module 'Immediate_Generator'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v":1)
Compiling module 'CSR_Unit'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v":1)
Compiling module 'Memory(MEMORY_FILE="../../software/memory/teste_uart_fpga.hex",MEMORY_SIZE=2048)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":1)
Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v":16)
Optimizing module top.
<suppressed ~21 debug messages>

24.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~897 debug messages>
Removed a total of 299 cells.

24.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3274.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3283.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3299.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3318.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3320.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3338.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3359.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3383.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3411.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3441.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3474.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3510.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3558.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3608.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3659.
    dead port 1/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3712.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3714.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3767.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3769.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3821.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3882.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3884.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$3946.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Control_Unit.$procmux$4001.
    dead port 2/2 on $mux $flatten\SOC.\Core.\Immediate_Generator.$procmux$2655.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$2461.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$2467.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$2473.
    dead port 1/2 on $mux $flatten\SOC.\Core.\RegisterBank.$procmux$2479.
    dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2215.
    dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2218.
    dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2224.
    dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2227.
    dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2233.
    dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2236.
    dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2243.
    dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2246.
    dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2253.
    dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2256.
    dead port 2/2 on $mux $flatten\SOC.\GPIOS.$procmux$2263.
    dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2266.
    dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2272.
    dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2278.
    dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2284.
    dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2290.
    dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2296.
    dead port 1/2 on $mux $flatten\SOC.\GPIOS.$procmux$2302.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1893.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1895.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1902.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1904.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1911.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1913.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1920.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1922.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1929.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1931.
    dead port 1/2 on $mux $flatten\SOC.\Memory.$procmux$1938.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1940.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1946.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1952.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1958.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1964.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1970.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1976.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1982.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1988.
    dead port 2/2 on $mux $flatten\SOC.\Memory.$procmux$1994.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$2412.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$2418.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\RX_FIFO.$procmux$2424.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$2412.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$2418.
    dead port 1/2 on $mux $flatten\SOC.\Uart.\TX_FIFO.$procmux$2424.
Removed 74 multiplexer ports.
<suppressed ~163 debug messages>

24.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3109: { $auto$opt_reduce.cc:134:opt_pmux$4255 $flatten\SOC.\Core.\Control_Unit.$procmux$3039_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3119: $auto$opt_reduce.cc:134:opt_pmux$4257
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3123: { $flatten\SOC.\Core.\Control_Unit.$procmux$3030_CMP $auto$opt_reduce.cc:134:opt_pmux$4259 $flatten\SOC.\Core.\Control_Unit.$procmux$3014_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3025_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3143: $auto$opt_reduce.cc:134:opt_pmux$4261
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3168: $auto$opt_reduce.cc:134:opt_pmux$4263
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3190: $auto$opt_reduce.cc:134:opt_pmux$4265
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3255: $auto$opt_reduce.cc:134:opt_pmux$4267
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3021: $auto$opt_reduce.cc:134:opt_pmux$4269
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3024: $auto$opt_reduce.cc:134:opt_pmux$4271
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3935: { $auto$opt_reduce.cc:134:opt_pmux$4273 $flatten\SOC.\Core.\Control_Unit.$procmux$3883_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3942_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3941_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3940_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3939_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3938_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3937_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3936_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$4005: { $flatten\SOC.\Core.\Control_Unit.$procmux$3175_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3100_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3066_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2947_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3173_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2921_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3146_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3038_CMP $auto$opt_reduce.cc:134:opt_pmux$4277 $flatten\SOC.\Core.\Control_Unit.$procmux$2978_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3029_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2946_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2920_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2977_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3061_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2919_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2900_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2864_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2863_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2973_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3056_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2862_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2971_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2970_CMP $auto$opt_reduce.cc:134:opt_pmux$4275 $flatten\SOC.\Core.\Control_Unit.$procmux$2824_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2841_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2945_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2917_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2968_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2967_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2861_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2966_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2965_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2823_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2840_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2806_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3033_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$2730: { $flatten\SOC.\Core.\CSR_Unit.$procmux$2747_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2744_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2742_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2741_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2740_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2685_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2712_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2723_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2702_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2693_CMP $auto$opt_reduce.cc:134:opt_pmux$4285 $auto$opt_reduce.cc:134:opt_pmux$4283 $auto$opt_reduce.cc:134:opt_pmux$4281 $auto$opt_reduce.cc:134:opt_pmux$4279 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$2658: { $flatten\SOC.\Core.\Control_Unit.$procmux$3940_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3941_CMP $auto$opt_reduce.cc:134:opt_pmux$4289 $flatten\SOC.\Core.\Control_Unit.$procmux$3942_CMP $auto$opt_reduce.cc:134:opt_pmux$4287 $flatten\SOC.\Core.\Control_Unit.$procmux$3936_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$3944_CMP }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$2458:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0] }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3032: { $flatten\SOC.\Core.\Control_Unit.$procmux$2863_CMP $auto$opt_reduce.cc:134:opt_pmux$4301 $auto$opt_reduce.cc:134:opt_pmux$4299 $auto$opt_reduce.cc:134:opt_pmux$4297 $auto$opt_reduce.cc:134:opt_pmux$4295 $auto$opt_reduce.cc:134:opt_pmux$4293 $auto$opt_reduce.cc:134:opt_pmux$4291 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$2476:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [31:1] = { $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] $flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$2482:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:26$195_EN[31:0]$202 [0] }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2995: $auto$opt_reduce.cc:134:opt_pmux$4303
    Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2213:
      Old ports: A=16'0000000000000000, B=16'1111111111111111, Y=$flatten\SOC.\GPIOS.$procmux$2213_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\GPIOS.$procmux$2213_Y [0]
      New connections: $flatten\SOC.\GPIOS.$procmux$2213_Y [15:1] = { $flatten\SOC.\GPIOS.$procmux$2213_Y [0] $flatten\SOC.\GPIOS.$procmux$2213_Y [0] $flatten\SOC.\GPIOS.$procmux$2213_Y [0] $flatten\SOC.\GPIOS.$procmux$2213_Y [0] $flatten\SOC.\GPIOS.$procmux$2213_Y [0] $flatten\SOC.\GPIOS.$procmux$2213_Y [0] $flatten\SOC.\GPIOS.$procmux$2213_Y [0] $flatten\SOC.\GPIOS.$procmux$2213_Y [0] $flatten\SOC.\GPIOS.$procmux$2213_Y [0] $flatten\SOC.\GPIOS.$procmux$2213_Y [0] $flatten\SOC.\GPIOS.$procmux$2213_Y [0] $flatten\SOC.\GPIOS.$procmux$2213_Y [0] $flatten\SOC.\GPIOS.$procmux$2213_Y [0] $flatten\SOC.\GPIOS.$procmux$2213_Y [0] $flatten\SOC.\GPIOS.$procmux$2213_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2241:
      Old ports: A=16'0000000000000000, B=16'1111111111111111, Y=$flatten\SOC.\GPIOS.$procmux$2241_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\GPIOS.$procmux$2241_Y [0]
      New connections: $flatten\SOC.\GPIOS.$procmux$2241_Y [15:1] = { $flatten\SOC.\GPIOS.$procmux$2241_Y [0] $flatten\SOC.\GPIOS.$procmux$2241_Y [0] $flatten\SOC.\GPIOS.$procmux$2241_Y [0] $flatten\SOC.\GPIOS.$procmux$2241_Y [0] $flatten\SOC.\GPIOS.$procmux$2241_Y [0] $flatten\SOC.\GPIOS.$procmux$2241_Y [0] $flatten\SOC.\GPIOS.$procmux$2241_Y [0] $flatten\SOC.\GPIOS.$procmux$2241_Y [0] $flatten\SOC.\GPIOS.$procmux$2241_Y [0] $flatten\SOC.\GPIOS.$procmux$2241_Y [0] $flatten\SOC.\GPIOS.$procmux$2241_Y [0] $flatten\SOC.\GPIOS.$procmux$2241_Y [0] $flatten\SOC.\GPIOS.$procmux$2241_Y [0] $flatten\SOC.\GPIOS.$procmux$2241_Y [0] $flatten\SOC.\GPIOS.$procmux$2241_Y [0] }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2793: { $flatten\SOC.\Core.\Control_Unit.$procmux$2790_CMP $auto$opt_reduce.cc:134:opt_pmux$4305 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1890:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1890_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1890_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1890_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] $flatten\SOC.\Memory.$procmux$1890_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1935:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\SOC.\Memory.$procmux$1935_Y
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Memory.$procmux$1935_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1935_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] $flatten\SOC.\Memory.$procmux$1935_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1944:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\SOC.\Memory.$procmux$1944_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Memory.$procmux$1944_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1944_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] $flatten\SOC.\Memory.$procmux$1944_Y [0] }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3071: { $flatten\SOC.\Core.\Control_Unit.$procmux$3061_CMP $auto$opt_reduce.cc:134:opt_pmux$4319 $auto$opt_reduce.cc:134:opt_pmux$4317 $auto$opt_reduce.cc:134:opt_pmux$4315 $flatten\SOC.\Core.\Control_Unit.$procmux$2971_CMP $auto$opt_reduce.cc:134:opt_pmux$4313 $flatten\SOC.\Core.\Control_Unit.$procmux$2968_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2967_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2966_CMP $flatten\SOC.\Core.\Control_Unit.$procmux$2965_CMP $auto$opt_reduce.cc:134:opt_pmux$4311 $auto$opt_reduce.cc:134:opt_pmux$4309 $auto$opt_reduce.cc:134:opt_pmux$4307 }
    New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$2171: { $flatten\SOC.\Uart.$procmux$2165_CMP $flatten\SOC.\Uart.$procmux$2082_CMP $flatten\SOC.\Uart.$procmux$2107_CMP $flatten\SOC.\Uart.$procmux$2063_CMP $auto$opt_reduce.cc:134:opt_pmux$4321 $flatten\SOC.\Uart.$procmux$2089_CMP }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2822: $auto$opt_reduce.cc:134:opt_pmux$4323
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2839: $auto$opt_reduce.cc:134:opt_pmux$4325
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2860: $auto$opt_reduce.cc:134:opt_pmux$4327
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$2409:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$2409_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\RX_FIFO.$procmux$2409_Y [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$procmux$2409_Y [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$procmux$2409_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2409_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2409_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2409_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2409_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2409_Y [0] $flatten\SOC.\Uart.\RX_FIFO.$procmux$2409_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$2409:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$2409_Y
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Uart.\TX_FIFO.$procmux$2409_Y [0]
      New connections: $flatten\SOC.\Uart.\TX_FIFO.$procmux$2409_Y [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$procmux$2409_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2409_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2409_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2409_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2409_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2409_Y [0] $flatten\SOC.\Uart.\TX_FIFO.$procmux$2409_Y [0] }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2915: $auto$opt_reduce.cc:134:opt_pmux$4329
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2944: $auto$opt_reduce.cc:134:opt_pmux$4331
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2964: { $auto$opt_reduce.cc:134:opt_pmux$4335 $auto$opt_reduce.cc:134:opt_pmux$4333 }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$2485:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$217, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$2476_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:30$197_EN[31:0]$206 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\RegisterBank.$procmux$2488:
      Old ports: A=$flatten\SOC.\Core.\RegisterBank.$2$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$216, B=0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205
      New ports: A=$flatten\SOC.\Core.\RegisterBank.$procmux$2458_Y [0], B=1'0, Y=$flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0]
      New connections: $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [31:1] = { $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] $flatten\SOC.\Core.\RegisterBank.$0$memwr$\registers$Risco-5/src/core/registers.v:28$196_EN[31:0]$205 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2269:
      Old ports: A=16'0000000000000000, B=$flatten\SOC.\GPIOS.$3$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1355, Y=$flatten\SOC.\GPIOS.$procmux$2269_Y
      New ports: A=1'0, B=$flatten\SOC.\GPIOS.$procmux$2213_Y [0], Y=$flatten\SOC.\GPIOS.$procmux$2269_Y [0]
      New connections: $flatten\SOC.\GPIOS.$procmux$2269_Y [15:1] = { $flatten\SOC.\GPIOS.$procmux$2269_Y [0] $flatten\SOC.\GPIOS.$procmux$2269_Y [0] $flatten\SOC.\GPIOS.$procmux$2269_Y [0] $flatten\SOC.\GPIOS.$procmux$2269_Y [0] $flatten\SOC.\GPIOS.$procmux$2269_Y [0] $flatten\SOC.\GPIOS.$procmux$2269_Y [0] $flatten\SOC.\GPIOS.$procmux$2269_Y [0] $flatten\SOC.\GPIOS.$procmux$2269_Y [0] $flatten\SOC.\GPIOS.$procmux$2269_Y [0] $flatten\SOC.\GPIOS.$procmux$2269_Y [0] $flatten\SOC.\GPIOS.$procmux$2269_Y [0] $flatten\SOC.\GPIOS.$procmux$2269_Y [0] $flatten\SOC.\GPIOS.$procmux$2269_Y [0] $flatten\SOC.\GPIOS.$procmux$2269_Y [0] $flatten\SOC.\GPIOS.$procmux$2269_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2287:
      Old ports: A=16'0000000000000000, B=$flatten\SOC.\GPIOS.$3$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1352, Y=$flatten\SOC.\GPIOS.$procmux$2287_Y
      New ports: A=1'0, B=$flatten\SOC.\GPIOS.$procmux$2241_Y [0], Y=$flatten\SOC.\GPIOS.$procmux$2287_Y [0]
      New connections: $flatten\SOC.\GPIOS.$procmux$2287_Y [15:1] = { $flatten\SOC.\GPIOS.$procmux$2287_Y [0] $flatten\SOC.\GPIOS.$procmux$2287_Y [0] $flatten\SOC.\GPIOS.$procmux$2287_Y [0] $flatten\SOC.\GPIOS.$procmux$2287_Y [0] $flatten\SOC.\GPIOS.$procmux$2287_Y [0] $flatten\SOC.\GPIOS.$procmux$2287_Y [0] $flatten\SOC.\GPIOS.$procmux$2287_Y [0] $flatten\SOC.\GPIOS.$procmux$2287_Y [0] $flatten\SOC.\GPIOS.$procmux$2287_Y [0] $flatten\SOC.\GPIOS.$procmux$2287_Y [0] $flatten\SOC.\GPIOS.$procmux$2287_Y [0] $flatten\SOC.\GPIOS.$procmux$2287_Y [0] $flatten\SOC.\GPIOS.$procmux$2287_Y [0] $flatten\SOC.\GPIOS.$procmux$2287_Y [0] $flatten\SOC.\GPIOS.$procmux$2287_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1968:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1461, B=0, Y=$flatten\SOC.\Memory.$procmux$1968_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1890_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1968_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1968_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] $flatten\SOC.\Memory.$procmux$1968_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$1986:
      Old ports: A=$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1458, B=0, Y=$flatten\SOC.\Memory.$procmux$1986_Y
      New ports: A=$flatten\SOC.\Memory.$procmux$1935_Y [0], B=1'0, Y=$flatten\SOC.\Memory.$procmux$1986_Y [0]
      New connections: $flatten\SOC.\Memory.$procmux$1986_Y [31:1] = { $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] $flatten\SOC.\Memory.$procmux$1986_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$2018:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1448, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1944_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_EN[31:0]$1428 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\RX_FIFO.$procmux$2427:
      Old ports: A=$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1575, B=8'00000000, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566
      New ports: A=$flatten\SOC.\Uart.\RX_FIFO.$procmux$2409_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [0]
      New connections: $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [7:1] = { $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [0] $flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\TX_FIFO.$procmux$2427:
      Old ports: A=$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1575, B=8'00000000, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566
      New ports: A=$flatten\SOC.\Uart.\TX_FIFO.$procmux$2409_Y [0], B=1'0, Y=$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [0]
      New connections: $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [7:1] = { $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [0] $flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_EN[7:0]$1566 [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2305:
      Old ports: A=$flatten\SOC.\GPIOS.$2$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1349, B=16'0000000000000000, Y=$flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337
      New ports: A=$flatten\SOC.\GPIOS.$procmux$2269_Y [0], B=1'0, Y=$flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337 [0]
      New connections: $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337 [15:1] = { $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337 [0] $flatten\SOC.\GPIOS.$0$memwr$\duty_cycle$Risco-5/src/peripheral/gpios.v:71$1326_EN[15:0]$1337 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\GPIOS.$procmux$2314:
      Old ports: A=$flatten\SOC.\GPIOS.$2$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1346, B=16'0000000000000000, Y=$flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334
      New ports: A=$flatten\SOC.\GPIOS.$procmux$2287_Y [0], B=1'0, Y=$flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334 [0]
      New connections: $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334 [15:1] = { $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334 [0] $flatten\SOC.\GPIOS.$0$memwr$\period$Risco-5/src/peripheral/gpios.v:70$1325_EN[15:0]$1334 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$2000:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1454, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1968_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_EN[31:0]$1434 [0] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Memory.$procmux$2009:
      Old ports: A=0, B=$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1451, Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431
      New ports: A=1'0, B=$flatten\SOC.\Memory.$procmux$1986_Y [0], Y=$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0]
      New connections: $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [31:1] = { $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] $flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_EN[31:0]$1431 [0] }
  Optimizing cells in module \top.
Performed a total of 47 changes.

24.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~24 debug messages>
Removed a total of 8 cells.

24.11.6. Executing OPT_DFF pass (perform DFF optimizations).

24.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 403 unused wires.
<suppressed ~1 debug messages>

24.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

24.11.9. Rerunning OPT passes. (Maybe there is more to do..)

24.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~162 debug messages>

24.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Alu.$procmux$4079: { $flatten\SOC.\Core.\Alu.$procmux$4093_CMP $flatten\SOC.\Core.\Alu.$procmux$4092_CMP $flatten\SOC.\Core.\Alu.$procmux$4091_CMP $flatten\SOC.\Core.\Alu.$procmux$4090_CMP $auto$opt_reduce.cc:134:opt_pmux$4339 $flatten\SOC.\Core.\Alu.$procmux$4087_CMP $flatten\SOC.\Core.\Alu.$procmux$4086_CMP $flatten\SOC.\Core.\Alu.$procmux$4085_CMP $flatten\SOC.\Core.\Alu.$procmux$4084_CMP $flatten\SOC.\Core.\Alu.$procmux$4083_CMP $flatten\SOC.\Core.\Alu.$procmux$4082_CMP $auto$opt_reduce.cc:134:opt_pmux$4337 }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3071: { $flatten\SOC.\Core.\Control_Unit.$procmux$3061_CMP $auto$opt_reduce.cc:134:opt_pmux$4319 $auto$opt_reduce.cc:134:opt_pmux$4317 $auto$opt_reduce.cc:134:opt_pmux$4315 $flatten\SOC.\Core.\Control_Unit.$procmux$2971_CMP $auto$opt_reduce.cc:134:opt_pmux$4313 $auto$opt_reduce.cc:134:opt_pmux$4343 $auto$opt_reduce.cc:134:opt_pmux$4341 $auto$opt_reduce.cc:134:opt_pmux$4311 $auto$opt_reduce.cc:134:opt_pmux$4309 $auto$opt_reduce.cc:134:opt_pmux$4307 }
    New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$2171: { $flatten\SOC.\Uart.$procmux$2165_CMP $flatten\SOC.\Uart.$procmux$2107_CMP $auto$opt_reduce.cc:134:opt_pmux$4345 $auto$opt_reduce.cc:134:opt_pmux$4321 $flatten\SOC.\Uart.$procmux$2089_CMP }
  Optimizing cells in module \top.
Performed a total of 3 changes.

24.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

24.11.13. Executing OPT_DFF pass (perform DFF optimizations).

24.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Compiling module 'BUS'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v":1)
Compiling module 'LEDs'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v":1)
Compiling module 'UART(CLK_FREQ=27000000,BIT_RATE=115200,BUFFER_SIZE=16)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v":1)
Compiling module 'FIFO(DEPTH=16)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":1)
Extracting RAM for identifier 'memory'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":16)
WARN  (EX3791) : Expression size 7 truncated to fit in target size 6("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v":40)
Compiling module 'uart_tool_rx(BIT_RATE=115200,CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v":10)
Compiling module 'uart_tool_tx(BIT_RATE=115200,CLK_HZ=27000000)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v":10)
Compiling module 'GPIOS(WIDHT=5)'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":1)
Compiling module 'GPIO'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v":1)
Compiling module 'PWM'("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v":1)
WARN  (EX2565) : Input 'halt' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_external' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_timer' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_software' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_fast[15]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_fast[14]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_fast[13]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_fast[12]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_fast[11]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_fast[10]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_fast[9]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_fast[8]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_fast[7]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_fast[6]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_fast[5]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_fast[4]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_fast[3]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_fast[2]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_fast[1]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
WARN  (EX2565) : Input 'interruption_request_fast[0]' on this instance is undriven. Assigning to 0, simulation mismatch possible. Please assign the input or remove the declaration("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v":43)
NOTE  (EX0101) : Current top module is "top"
Finding unused cells or wires in module \top..

24.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

24.11.16. Rerunning OPT passes. (Maybe there is more to do..)

24.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~162 debug messages>

24.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

24.11.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

24.11.20. Executing OPT_DFF pass (perform DFF optimizations).

24.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

24.11.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

24.11.23. Finished OPT passes. (There is nothing left to do.)

24.12. Executing FSM pass (extract and optimize FSM).

24.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.
Not marking top.SOC.Core.CSR_Unit.utime as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Not marking top.SOC.Core.Control_Unit.state as FSM state register:
    Register has an initialization value.
Not marking top.SOC.Core.Mdu.state_div as FSM state register:
    Register has an initialization value.
Not marking top.SOC.Core.Mdu.state_mul as FSM state register:
    Register has an initialization value.
Found FSM state register top.SOC.Uart.i_uart_rx.fsm_state.
Not marking top.SOC.Uart.i_uart_tx.fsm_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking top.SOC.Uart.state as FSM state register:
    Register has an initialization value.

24.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\SOC.Uart.i_uart_rx.fsm_state' from module `\top'.
  found $dff cell for state register: $flatten\SOC.\Uart.\i_uart_rx.$procdff$4103
  root of input selection tree: $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1524_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1537_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1550_Y
  found ctrl input: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1536_Y
  found state code: 3'000
  found ctrl input: \SOC.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \SOC.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \SOC.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1550_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:143$1541_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1537_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1536_Y
  found ctrl output: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1524_Y
  ctrl inputs: { \SOC.Uart.i_uart_rx.rxd_reg \SOC.Uart.i_uart_rx.next_bit \SOC.Uart.i_uart_rx.payload_done \ResetBootSystem.reset_o }
  ctrl outputs: { $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1524_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1536_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1537_Y $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:143$1541_Y $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1550_Y $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'0--0 ->      3'001 8'01010001
  transition:      3'000 4'1--0 ->      3'000 8'01010000
  transition:      3'000 4'---1 ->      3'000 8'01010000
  transition:      3'010 4'--00 ->      3'010 8'00100010
  transition:      3'010 4'--10 ->      3'011 8'00100011
  transition:      3'010 4'---1 ->      3'000 8'00100000
  transition:      3'001 4'-0-0 ->      3'001 8'00011001
  transition:      3'001 4'-1-0 ->      3'010 8'00011010
  transition:      3'001 4'---1 ->      3'000 8'00011000
  transition:      3'011 4'-0-0 ->      3'011 8'10010011
  transition:      3'011 4'-1-0 ->      3'000 8'10010000
  transition:      3'011 4'---1 ->      3'000 8'10010000

24.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$4346' from module `\top'.

24.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 7 unused cells and 7 unused wires.
<suppressed ~8 debug messages>

24.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$4346' from module `\top'.
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\SOC.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].

24.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$4346' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---

24.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$4346' from module `top':
-------------------------------------

  Information on FSM $fsm$\SOC.Uart.i_uart_rx.fsm_state$4346 (\SOC.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \ResetBootSystem.reset_o
    1: \SOC.Uart.i_uart_rx.payload_done
    2: \SOC.Uart.i_uart_rx.next_bit
    3: \SOC.Uart.i_uart_rx.rxd_reg

  Output signals:
    0: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:168$1550_Y
    1: $flatten\SOC.\Uart.\i_uart_rx.$ne$Risco-5/src/peripheral/uart_rx.v:143$1541_Y
    2: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:130$1537_Y
    3: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:128$1536_Y
    4: $flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:102$1524_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'1--0   ->     0 5'01010
      1:     0 4'---1   ->     0 5'01010
      2:     0 4'0--0   ->     2 5'01010
      3:     1 4'---1   ->     0 5'00100
      4:     1 4'--00   ->     1 5'00100
      5:     1 4'--10   ->     3 5'00100
      6:     2 4'---1   ->     0 5'00011
      7:     2 4'-1-0   ->     1 5'00011
      8:     2 4'-0-0   ->     2 5'00011
      9:     3 4'-1-0   ->     0 5'10010
     10:     3 4'---1   ->     0 5'10010
     11:     3 4'-0-0   ->     3 5'10010

-------------------------------------

24.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\SOC.Uart.i_uart_rx.fsm_state$4346' from module `\top'.

24.13. Executing OPT pass (performing simple optimizations).

24.13.1. Executing OPT_EXPR pass (perform const folding).
[5%] Running netlist conversion ...
WARN  (CV0016) : Input reset is unused("/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/main.v":3)
Running device independent optimization ...
Optimizing module top.
<suppressed ~5 debug messages>

24.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

24.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~161 debug messages>

24.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

24.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

24.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$4115 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1861_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1855_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1846_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1837_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1828_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1819_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1801_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1810_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4396 ($sdff) from module top (D = \SOC.Uart.uart_tx_data [7], Q = \SOC.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$4396 ($sdff) from module top (D = { $flatten\SOC.\Uart.\i_uart_tx.$procmux$1855_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1846_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1837_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1828_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1819_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1801_Y $flatten\SOC.\Uart.\i_uart_tx.$procmux$1810_Y }, Q = \SOC.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$4113 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1777_Y, Q = \SOC.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$4401 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1777_Y, Q = \SOC.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$4112 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1766_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$4407 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$1504_Y, Q = \SOC.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$4111 ($dff) from module top (D = \SOC.Uart.i_uart_tx.n_fsm_state, Q = \SOC.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_tx.$procdff$4110 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1755_Y, Q = \SOC.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$4412 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_tx.$procmux$1755_Y, Q = \SOC.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$4109 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1744_Y, Q = \SOC.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4418 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.recieved_data, Q = \SOC.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$4107 ($dff) from module top (D = { $flatten\SOC.\Uart.\i_uart_rx.$procmux$1721_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1712_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1703_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1694_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1685_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1676_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1658_Y $flatten\SOC.\Uart.\i_uart_rx.$procmux$1667_Y }, Q = \SOC.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4420 ($sdff) from module top (D = { \SOC.Uart.i_uart_rx.bit_sample \SOC.Uart.i_uart_rx.recieved_data [7:1] }, Q = \SOC.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$4106 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1640_Y, Q = \SOC.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$4424 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1544_Y, Q = \SOC.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$4105 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1635_Y, Q = \SOC.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4428 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg, Q = \SOC.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$4104 ($dff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$procmux$1627_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$4430 ($sdff) from module top (D = $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1555_Y, Q = \SOC.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$4102 ($dff) from module top (D = \rx, Q = \SOC.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\i_uart_rx.$procdff$4101 ($dff) from module top (D = \SOC.Uart.i_uart_rx.rxd_reg_0, Q = \SOC.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$4164 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$2436_Y, Q = \SOC.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4436 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:37$1579_Y, Q = \SOC.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$4163 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$2444_Y, Q = \SOC.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4438 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1585_Y [5:0], Q = \SOC.Uart.TX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\TX_FIFO.$procdff$4162 ($dff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$2452_Y, Q = \SOC.Uart.TX_FIFO.counter, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4444 ($sdff) from module top (D = $flatten\SOC.\Uart.\TX_FIFO.$procmux$2452_Y, Q = \SOC.Uart.TX_FIFO.counter).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$4164 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$2436_Y, Q = \SOC.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4448 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:37$1579_Y, Q = \SOC.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$4163 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$2444_Y, Q = \SOC.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4450 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1585_Y [5:0], Q = \SOC.Uart.RX_FIFO.read_ptr).
Adding SRST signal on $flatten\SOC.\Uart.\RX_FIFO.$procdff$4162 ($dff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$2452_Y, Q = \SOC.Uart.RX_FIFO.counter, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4456 ($sdff) from module top (D = $flatten\SOC.\Uart.\RX_FIFO.$procmux$2452_Y, Q = \SOC.Uart.RX_FIFO.counter).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$4138 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2105_Y, Q = \SOC.Uart.write_data_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4460 ($sdff) from module top (D = $flatten\SOC.\Uart.$procmux$2105_Y, Q = \SOC.Uart.write_data_buffer).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$4137 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2123_Y, Q = \SOC.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4470 ($sdff) from module top (D = \SOC.Uart.write_data_buffer [7:0], Q = \SOC.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$4136 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2077_Y, Q = \SOC.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$4135 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2058_Y, Q = \SOC.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$4134 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2088_Y, Q = \SOC.Uart.response, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$4133 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2131_Y, Q = \SOC.Uart.read_data, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4491 ($sdff) from module top (D = $flatten\SOC.\Uart.$procmux$2131_Y, Q = \SOC.Uart.read_data).
Adding EN signal on $flatten\SOC.\Uart.$procdff$4132 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2157_Y, Q = \SOC.Uart.counter).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$4131 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2171_Y, Q = \SOC.Uart.state, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$4516 ($sdff) from module top (D = $flatten\SOC.\Uart.$procmux$2171_Y, Q = \SOC.Uart.state).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$4130 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2040_Y, Q = \SOC.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4520 ($sdff) from module top (D = \SOC.Uart.i_uart_rx.uart_rx_data, Q = \SOC.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$4129 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2045_Y, Q = \SOC.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4522 ($sdff) from module top (D = \SOC.Uart.tx_fifo_read_data, Q = \SOC.Uart.uart_tx_data).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$4128 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2025_Y, Q = \SOC.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Uart.$procdff$4126 ($dff) from module top (D = $flatten\SOC.\Uart.$procmux$2030_Y, Q = \SOC.Uart.uart_tx_en, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Leds.$procdff$4150 ($dff) from module top (D = $flatten\SOC.\Leds.$procmux$2358_Y, Q = \SOC.Leds.data, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4526 ($sdff) from module top (D = { \SOC.Leds.write_data [31:17] \SOC.GPIOS.write_data [16:0] }, Q = \SOC.Leds.data).
Adding SRST signal on $flatten\SOC.\GPIOS.\Pwm1.$procdff$4139 ($dff) from module top (D = $flatten\SOC.\GPIOS.\Pwm1.$add$Risco-5/src/peripheral/pwm.v:17$501_Y, Q = \SOC.GPIOS.Pwm1.counter, rval = 0).
Adding SRST signal on $flatten\SOC.\GPIOS.\Pwm0.$procdff$4139 ($dff) from module top (D = $flatten\SOC.\GPIOS.\Pwm0.$add$Risco-5/src/peripheral/pwm.v:17$501_Y, Q = \SOC.GPIOS.Pwm0.counter, rval = 0).
Adding EN signal on $flatten\SOC.\GPIOS.$procdff$4143 ($dff) from module top (D = \SOC.GPIOS.write_data [1:0], Q = \SOC.GPIOS.is_pwm).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$4142 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$2340_Y, Q = \SOC.GPIOS.gpio_value, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4543 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_value).
Adding SRST signal on $flatten\SOC.\GPIOS.$procdff$4141 ($dff) from module top (D = $flatten\SOC.\GPIOS.$procmux$2353_Y, Q = \SOC.GPIOS.gpio_direction, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4547 ($sdff) from module top (D = \SOC.GPIOS.write_data [5:0], Q = \SOC.GPIOS.gpio_direction).
Adding SRST signal on $flatten\SOC.\Core.\Pc.$procdff$4173 ($dff) from module top (D = $flatten\SOC.\Core.\Pc.$procmux$2496_Y, Q = \SOC.Core.Pc.Output, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4551 ($sdff) from module top (D = \SOC.Core.Pc.Input, Q = \SOC.Core.Pc.Output).
Adding EN signal on $flatten\SOC.\Core.\Mdu.$procdff$4187 ($dff) from module top (D = $flatten\SOC.\Core.\Mdu.$mul$Risco-5/src/core/mdu.v:74$134_Y, Q = \SOC.Core.Mdu.acumulador).
Adding SRST signal on $flatten\SOC.\Core.\Mdu.$procdff$4186 ($dff) from module top (D = $flatten\SOC.\Core.\Mdu.$procmux$2614_Y, Q = \SOC.Core.Mdu.MUL_RD, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4558 ($sdff) from module top (D = $flatten\SOC.\Core.\Mdu.$ternary$Risco-5/src/core/mdu.v:80$136_Y, Q = \SOC.Core.Mdu.MUL_RD).
Adding SRST signal on $flatten\SOC.\Core.\Mdu.$procdff$4183 ($dff) from module top (D = $flatten\SOC.\Core.\Mdu.$procmux$2591_Y, Q = \SOC.Core.Mdu.state_mul, rval = 2'00).
Adding SRST signal on $flatten\SOC.\Core.\Mdu.$procdff$4182 ($dff) from module top (D = $flatten\SOC.\Core.\Mdu.$procmux$2601_Y, Q = \SOC.Core.Mdu.mul_done, rval = 1'0).
Adding EN signal on $flatten\SOC.\Core.\Mdu.$procdff$4181 ($dff) from module top (D = $flatten\SOC.\Core.\Mdu.$procmux$2523_Y, Q = \SOC.Core.Mdu.divisor).
Adding EN signal on $flatten\SOC.\Core.\Mdu.$procdff$4180 ($dff) from module top (D = $flatten\SOC.\Core.\Mdu.$procmux$2534_Y, Q = \SOC.Core.Mdu.DIV_RD).
Adding EN signal on $flatten\SOC.\Core.\Mdu.$procdff$4179 ($dff) from module top (D = $flatten\SOC.\Core.\Mdu.$procmux$2543_Y, Q = \SOC.Core.Mdu.quociente_msk).
Adding SRST signal on $flatten\SOC.\Core.\Mdu.$procdff$4178 ($dff) from module top (D = $flatten\SOC.\Core.\Mdu.$procmux$2556_Y, Q = \SOC.Core.Mdu.quociente, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4585 ($sdff) from module top (D = $flatten\SOC.\Core.\Mdu.$procmux$2556_Y, Q = \SOC.Core.Mdu.quociente).
Adding EN signal on $flatten\SOC.\Core.\Mdu.$procdff$4177 ($dff) from module top (D = $flatten\SOC.\Core.\Mdu.$procmux$2569_Y, Q = \SOC.Core.Mdu.dividendo).
Adding EN signal on $flatten\SOC.\Core.\Mdu.$procdff$4176 ($dff) from module top (D = $flatten\SOC.\Core.\Mdu.$or$Risco-5/src/core/mdu.v:99$157_Y, Q = \SOC.Core.Mdu.negativo).
Adding SRST signal on $flatten\SOC.\Core.\Mdu.$procdff$4175 ($dff) from module top (D = $flatten\SOC.\Core.\Mdu.$procmux$2506_Y, Q = \SOC.Core.Mdu.state_div, rval = 2'00).
Adding SRST signal on $flatten\SOC.\Core.\Mdu.$procdff$4174 ($dff) from module top (D = $flatten\SOC.\Core.\Mdu.$procmux$2516_Y, Q = \SOC.Core.Mdu.div_done, rval = 1'0).
Adding SRST signal on $flatten\SOC.\Core.\Control_Unit.$procdff$4199 ($dff) from module top (D = \SOC.Core.Control_Unit.nextstate, Q = \SOC.Core.Control_Unit.state, rval = 6'000000).
Adding EN signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$4195 ($dff) from module top (D = 64'0000000000000000000000000000000000000000000000000000000000000000, Q = \SOC.Core.CSR_Unit.utime).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$4194 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:114$121_Y, Q = \SOC.Core.CSR_Unit.mcycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$4193 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$2686_Y, Q = \SOC.Core.CSR_Unit.mtvec, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4616 ($sdff) from module top (D = \SOC.Core.register_data_1, Q = \SOC.Core.CSR_Unit.mtvec).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$4192 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$2694_Y, Q = \SOC.Core.CSR_Unit.mtval, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4620 ($sdff) from module top (D = \SOC.Core.register_data_1, Q = \SOC.Core.CSR_Unit.mtval).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$4191 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$2703_Y, Q = \SOC.Core.CSR_Unit.mcause, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4624 ($sdff) from module top (D = \SOC.Core.register_data_1, Q = \SOC.Core.CSR_Unit.mcause).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$4190 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$2713_Y, Q = \SOC.Core.CSR_Unit.mscratch, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4628 ($sdff) from module top (D = \SOC.Core.register_data_1, Q = \SOC.Core.CSR_Unit.mscratch).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$4189 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$2724_Y, Q = \SOC.Core.CSR_Unit.mepc, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4632 ($sdff) from module top (D = { \SOC.Core.register_data_1 [31:2] 2'00 }, Q = \SOC.Core.CSR_Unit.mepc).
Adding SRST signal on $flatten\SOC.\Core.\CSR_Unit.$procdff$4188 ($dff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$2673_Y, Q = \SOC.Core.CSR_Unit.minstret, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4636 ($sdff) from module top (D = \SOC.Core.register_data_1, Q = \SOC.Core.CSR_Unit.minstret [63:32]).
Adding EN signal on $auto$ff.cc:266:slice$4636 ($sdff) from module top (D = $flatten\SOC.\Core.\CSR_Unit.$procmux$2671_Y [31:0], Q = \SOC.Core.CSR_Unit.minstret [31:0]).
Adding EN signal on $flatten\SOC.\Core.$procdff$4161 ($dff) from module top (D = \SOC.Core.mdu_out, Q = \SOC.Core.mdu_out_reg).
Adding SRST signal on $flatten\SOC.\Core.$procdff$4160 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$2378_Y, Q = \SOC.Core.temp_write_value, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4650 ($sdff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.temp_write_value).
Adding SRST signal on $flatten\SOC.\Core.$procdff$4159 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$2383_Y, Q = \SOC.Core.temp_reg3, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4652 ($sdff) from module top (D = \SOC.Core.alu_out_register, Q = \SOC.Core.temp_reg3).
Adding SRST signal on $flatten\SOC.\Core.$procdff$4158 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$2388_Y, Q = \SOC.Core.temp_reg2, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4654 ($sdff) from module top (D = \SOC.Core.memory_register, Q = \SOC.Core.temp_reg2).
Adding SRST signal on $flatten\SOC.\Core.$procdff$4157 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$2393_Y, Q = \SOC.Core.temp_address, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4656 ($sdff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.temp_address).
Adding SRST signal on $flatten\SOC.\Core.$procdff$4156 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$2398_Y, Q = \SOC.Core.pc_old, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4658 ($sdff) from module top (D = \SOC.Core.Pc.Output, Q = \SOC.Core.pc_old).
Adding SRST signal on $flatten\SOC.\Core.$procdff$4155 ($dff) from module top (D = \SOC.Core.register_data_2_out, Q = \SOC.Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$4154 ($dff) from module top (D = \SOC.Core.register_data_1_out, Q = \SOC.Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$4153 ($dff) from module top (D = \SOC.Core.Alu.ALU_out_S, Q = \SOC.Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$4152 ($dff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.memory_register, rval = 0).
Adding SRST signal on $flatten\SOC.\Core.$procdff$4151 ($dff) from module top (D = $flatten\SOC.\Core.$procmux$2403_Y, Q = \SOC.Core.instruction_register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4664 ($sdff) from module top (D = \SOC.Core.read_data, Q = \SOC.Core.instruction_register).
Adding EN signal on $flatten\ResetBootSystem.$procdff$4198 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$4197 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding EN signal on $flatten\ResetBootSystem.$procdff$4196 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$4633 ($sdffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$4633 ($sdffe) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 33 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 34 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 35 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 36 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 37 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 38 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 39 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 40 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 41 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 42 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 43 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 44 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 45 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 46 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 47 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 48 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 49 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 50 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 51 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 52 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 53 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 54 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 55 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 56 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 57 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 58 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 59 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 60 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 61 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 62 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.
Setting constant 0-bit at position 63 on $auto$ff.cc:266:slice$4614 ($dffe) from module top.

24.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 158 unused cells and 154 unused wires.
<suppressed ~159 debug messages>

24.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~15 debug messages>

24.13.9. Rerunning OPT passes. (Maybe there is more to do..)

24.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~116 debug messages>

24.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$4426: { \SOC.Uart.i_uart_rx.fsm_state [3:2] \SOC.Uart.i_uart_rx.fsm_state [0] \ResetBootSystem.reset_o }
    New ctrl vector for $pmux cell $flatten\SOC.\Core.\CSR_Unit.$procmux$2730: { $flatten\SOC.\Core.\CSR_Unit.$procmux$2742_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2741_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2740_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2685_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2712_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2723_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2702_CMP $flatten\SOC.\Core.\CSR_Unit.$procmux$2693_CMP $auto$opt_reduce.cc:134:opt_pmux$4285 $auto$opt_reduce.cc:134:opt_pmux$4283 $auto$opt_reduce.cc:134:opt_pmux$4281 $auto$opt_reduce.cc:134:opt_pmux$4279 }
  Optimizing cells in module \top.
Performed a total of 2 changes.

24.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~63 debug messages>
Removed a total of 21 cells.

24.13.13. Executing OPT_DFF pass (perform DFF optimizations).

24.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 3 unused cells and 24 unused wires.
<suppressed ~4 debug messages>

24.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

24.13.16. Rerunning OPT passes. (Maybe there is more to do..)

24.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~116 debug messages>

24.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

24.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

24.13.20. Executing OPT_DFF pass (perform DFF optimizations).

24.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

24.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

24.13.23. Finished OPT passes. (There is nothing left to do.)

24.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$4206 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$4208 (SOC.Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\SOC.\Core.\RegisterBank.$meminit$\registers$Risco-5/src/core/registers.v:17$218 (SOC.Core.RegisterBank.registers).
Removed top 31 address bits (of 32) from memory init port top.$flatten\SOC.\GPIOS.$meminit$\duty_cycle$Risco-5/src/peripheral/gpios.v:26$1397 (SOC.GPIOS.duty_cycle).
Removed top 31 address bits (of 32) from memory init port top.$flatten\SOC.\GPIOS.$meminit$\period$Risco-5/src/peripheral/gpios.v:25$1396 (SOC.GPIOS.period).
Removed top 31 address bits (of 32) from memory read port top.$flatten\SOC.\GPIOS.$memrd$\duty_cycle$Risco-5/src/peripheral/gpios.v:48$1392 (SOC.GPIOS.duty_cycle).
Removed top 31 address bits (of 32) from memory read port top.$flatten\SOC.\GPIOS.$memrd$\duty_cycle$Risco-5/src/peripheral/gpios.v:56$1394 (SOC.GPIOS.duty_cycle).
Removed top 31 address bits (of 32) from memory read port top.$flatten\SOC.\GPIOS.$memrd$\period$Risco-5/src/peripheral/gpios.v:49$1393 (SOC.GPIOS.period).
Removed top 31 address bits (of 32) from memory read port top.$flatten\SOC.\GPIOS.$memrd$\period$Risco-5/src/peripheral/gpios.v:57$1395 (SOC.GPIOS.period).
Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$4200 (SOC.Memory.memory).
Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$4201 (SOC.Memory.memory).
Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$auto$proc_memwr.cc:45:proc_memwr$4202 (SOC.Memory.memory).
Removed top 23 address bits (of 32) from memory init port top.$flatten\SOC.\Memory.$meminit$\memory$Risco-5/src/peripheral/memory.v:0$1464 (SOC.Memory.memory).
Removed top 23 address bits (of 32) from memory read port top.$flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:24$1423 (SOC.Memory.memory).
Removed top 2 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$4205 (SOC.Uart.RX_FIFO.memory).
Removed top 2 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:20$1562 (SOC.Uart.RX_FIFO.memory).
Removed top 2 address bits (of 6) from memory init port top.$flatten\SOC.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$4205 (SOC.Uart.TX_FIFO.memory).
Removed top 2 address bits (of 6) from memory read port top.$flatten\SOC.\Uart.\TX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:20$1562 (SOC.Uart.TX_FIFO.memory).
Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$2778_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$849 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$848 ($add).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$848 ($add).
Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$847 ($lt).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$4677 ($ne).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$4672 ($ne).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$4646 ($ne).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$4592 ($ne).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$4566 ($ne).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\GPIOS.$ternary$Risco-5/src/peripheral/gpios.v:35$1330 ($mux).
Removed top 3 bits (of 8) from port B of cell top.$flatten\SOC.\GPIOS.$procmux$2214_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell top.$flatten\SOC.\GPIOS.$procmux$2242_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell top.$flatten\SOC.\GPIOS.$procmux$2327_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell top.$flatten\SOC.\GPIOS.$procmux$2339_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$ne$Risco-5/src/peripheral/uart.v:113$1406 ($ne).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$2063_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$2082_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$2089_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$2107_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$2134_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.$procmux$2135_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$2190_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$2191_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.$procmux$2192_CMP0 ($eq).
Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$2433 ($mux).
Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$procmux$2421 ($mux).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:45$1586 ($eq).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1585 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1584 ($add).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:40$1583 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\TX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:37$1577 ($eq).
Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$2433 ($mux).
Removed top 2 bits (of 6) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$procmux$2421 ($mux).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:45$1586 ($eq).
Removed top 26 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1585 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1584 ($add).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:40$1583 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Uart.\RX_FIFO.$eq$Risco-5/src/peripheral/fifo.v:37$1577 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:113$1533 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:112$1532 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:111$1531 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:110$1530 ($mux).
Removed top 2 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:103$1525 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_rx.$eq$Risco-5/src/peripheral/uart_rx.v:101$1523 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:146$1499 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:131$1491 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:129$1489 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:127$1486 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$ne$Risco-5/src/peripheral/uart_tx.v:127$1485 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:114$1481 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:97$1476 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:96$1475 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:95$1474 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:94$1473 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:88$1469 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\SOC.\Uart.\i_uart_tx.$eq$Risco-5/src/peripheral/uart_tx.v:86$1467 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Bus.$eq$Risco-5/src/peripheral/bus.v:53$225 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Memory.$procmux$1886_CMP0 ($eq).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$2003 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$2012 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$2021 ($mux).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:114$121 ($add).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\MemoryAddressMUX.$eq$Risco-5/src/core/mux.v:15$175 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$eq$Risco-5/src/core/mux.v:17$177 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$eq$Risco-5/src/core/mux.v:16$176 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\MemoryDataMUX.$eq$Risco-5/src/core/mux.v:15$175 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$eq$Risco-5/src/core/mux.v:17$177 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$eq$Risco-5/src/core/mux.v:16$176 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputAMUX.$eq$Risco-5/src/core/mux.v:15$175 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:17$177 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:16$176 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:15$175 ($eq).
Removed top 1 bits (of 2) from mux cell top.$flatten\SOC.\Core.\Mdu.$procmux$2594 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\Mdu.$procmux$2592_CMP0 ($eq).
Removed top 1 bits (of 2) from mux cell top.$flatten\SOC.\Core.\Mdu.$procmux$2509 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\Mdu.$procmux$2507_CMP0 ($eq).
Removed top 32 bits (of 64) from port Y of cell top.$flatten\SOC.\Core.\Mdu.$sub$Risco-5/src/core/mdu.v:116$160 ($sub).
Removed top 32 bits (of 64) from port B of cell top.$flatten\SOC.\Core.\Mdu.$sub$Risco-5/src/core/mdu.v:116$160 ($sub).
Removed top 31 bits (of 32) from port B of cell top.$flatten\SOC.\Core.\Mdu.$eq$Risco-5/src/core/mdu.v:109$158 ($eq).
Removed top 32 bits (of 64) from port A of cell top.$flatten\SOC.\Core.\Mdu.$mul$Risco-5/src/core/mdu.v:74$134 ($mul).
Removed top 32 bits (of 64) from port B of cell top.$flatten\SOC.\Core.\Mdu.$mul$Risco-5/src/core/mdu.v:74$134 ($mul).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3944_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3942_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3939_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3938_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3883_CMP0 ($eq).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3765 ($mux).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3709 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3657 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3606 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3556 ($mux).
Removed top 1 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3508 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3472 ($mux).
Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3439 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3409 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3357 ($mux).
Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3297 ($mux).
Removed top 5 bits (of 6) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3272 ($mux).
Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3173_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3146_CMP0 ($eq).
Removed top 5 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3066_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3061_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3056_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3042_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3040_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3039_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3038_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3036_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3035_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3030_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3029_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3028_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3027_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3023_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3022_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$3014_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2978_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2977_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2973_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2972_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2947_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2946_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2921_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2920_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2919_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2900_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2864_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2863_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2862_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2793 ($pmux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2791_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$procmux$2790_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:566$82 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:546$76 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:263$55 ($eq).
Removed top 5 bits (of 7) from port B of cell top.$flatten\SOC.\Core.\Control_Unit.$eq$Risco-5/src/core/control_unit.v:191$42 ($eq).
Removed top 1 bits (of 3) from mux cell top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:111$38 ($mux).
Removed top 1 bits (of 4) from mux cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$4065 ($mux).
Removed top 2 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$4063_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$4062_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$4061_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\SOC.\Core.\ALU_Control.$procmux$4077_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$4092_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$4091_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$4090_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$4089_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\SOC.\Core.\Alu.$procmux$4082_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:53$28 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:37$17 ($mux).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2740_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2723_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2712_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2702_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2693_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2685_CMP0 ($eq).
Removed top 32 bits (of 64) from mux cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2671 ($mux).
Removed cell top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2668 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1956 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1974 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1992 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1908 ($mux).
Removed top 23 bits (of 32) from mux cell top.$flatten\SOC.\Memory.$procmux$1917 ($mux).
Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$848_Y.
Removed top 1 bits (of 4) from wire top.$flatten\SOC.\Core.\ALU_Control.$procmux$4065_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:37$17_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Alu.$ternary$Risco-5/src/core/alu.v:53$28_Y.
Removed top 32 bits (of 64) from wire top.$flatten\SOC.\Core.\CSR_Unit.$procmux$2671_Y.
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$10\nextstate[5:0].
Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$11\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$12\nextstate[5:0].
Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$13\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$14\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$16\nextstate[5:0].
Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$19\nextstate[5:0].
Removed top 5 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$21\nextstate[5:0].
Removed top 1 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$6\nextstate[5:0].
Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$7\nextstate[5:0].
Removed top 4 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$8\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\SOC.\Core.\Control_Unit.$9\nextstate[5:0].
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:546$76_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:566$82_Y.
Removed top 1 bits (of 2) from wire top.$flatten\SOC.\Core.\Mdu.$procmux$2509_Y.
Removed top 1 bits (of 2) from wire top.$flatten\SOC.\Core.\Mdu.$procmux$2594_Y.
Removed top 32 bits (of 64) from wire top.$flatten\SOC.\Core.\Mdu.$sub$Risco-5/src/core/mdu.v:116$160_Y.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_ADDR[31:0]$1430.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_ADDR[31:0]$1427.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$0$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_ADDR[31:0]$1433.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:50$1420_ADDR[31:0]$1450.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_ADDR[31:0]$1447.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$2$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_ADDR[31:0]$1453.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:52$1421_ADDR[31:0]$1457.
Removed top 23 bits (of 32) from wire top.$flatten\SOC.\Memory.$3$memwr$\memory$Risco-5/src/peripheral/memory.v:54$1422_ADDR[31:0]$1460.
Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_ADDR[5:0]$1564.
Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_ADDR[5:0]$1573.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1584_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\RX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1585_Y.
Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$0$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_ADDR[5:0]$1564.
Removed top 2 bits (of 6) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$2$memwr$\memory$Risco-5/src/peripheral/fifo.v:36$1561_ADDR[5:0]$1573.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1584_Y.
Removed top 26 bits (of 32) from wire top.$flatten\SOC.\Uart.\TX_FIFO.$ternary$Risco-5/src/peripheral/fifo.v:40$1585_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:110$1530_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:111$1531_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:112$1532_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:113$1533_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:94$1473_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:95$1474_Y.
Removed top 31 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:96$1475_Y.
Removed top 30 bits (of 32) from wire top.$flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:97$1476_Y.

24.15. Executing PEEPOPT pass (run peephole optimizers).

24.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 48 unused wires.
<suppressed ~1 debug messages>

24.17. Executing SHARE pass (SAT-based resource sharing).
Found 6 cells in module top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\SOC.\Uart.\RX_FIFO.$memrd$\memory$Risco-5/src/peripheral/fifo.v:20$1562 ($memrd):
    Found 1 activation_patterns using ctrl signal { \SOC.Uart.RX_FIFO.empty $flatten\SOC.\Uart.$procmux$2082_CMP $flatten\SOC.\Uart.$ne$Risco-5/src/peripheral/uart.v:113$1406_Y }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Memory.$memrd$\memory$Risco-5/src/peripheral/memory.v:24$1423 ($memrd):
    Found 7 activation_patterns using ctrl signal { $flatten\SOC.\Memory.$procmux$1887_CMP $flatten\SOC.\Memory.$procmux$1886_CMP $flatten\SOC.\Memory.$procmux$1885_CMP $flatten\SOC.\Memory.$procmux$1884_CMP \SOC.Memory.option [1:0] \SOC.Memory.memory_write $flatten\SOC.\Bus.$eq$Risco-5/src/peripheral/bus.v:48$221_Y }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\RegisterBank.$memrd$\registers$Risco-5/src/core/registers.v:22$200 ($memrd):
    Found 12 activation_patterns using ctrl signal { $flatten\SOC.\Core.\Alu.$procmux$4082_CMP $flatten\SOC.\Core.\Alu.$procmux$4083_CMP $flatten\SOC.\Core.\Alu.$procmux$4084_CMP $flatten\SOC.\Core.\Alu.$procmux$4085_CMP $flatten\SOC.\Core.\Alu.$procmux$4086_CMP $flatten\SOC.\Core.\Alu.$procmux$4087_CMP $flatten\SOC.\Core.\Alu.$procmux$4090_CMP $flatten\SOC.\Core.\Alu.$procmux$4091_CMP $flatten\SOC.\Core.\Alu.$procmux$4092_CMP $flatten\SOC.\Core.\Alu.$procmux$4093_CMP $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:14$174_Y $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:15$175_Y $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:16$176_Y $flatten\SOC.\Core.\AluInputBMUX.$eq$Risco-5/src/core/mux.v:17$177_Y $auto$opt_reduce.cc:134:opt_pmux$4339 $auto$opt_reduce.cc:134:opt_pmux$4337 }.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$sshr$Risco-5/src/core/alu.v:51$26 ($sshr):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$4082_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shr$Risco-5/src/core/alu.v:49$25 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$4083_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\SOC.\Core.\Alu.$shl$Risco-5/src/core/alu.v:47$24 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\SOC.\Core.\Alu.$procmux$4084_CMP.
    No candidates found.

24.18. Executing TECHMAP pass (map to technology primitives).

24.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

24.18.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~140 debug messages>

24.19. Executing OPT_EXPR pass (perform const folding).
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
Optimizing module top.

24.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

24.21. Executing TECHMAP pass (map to technology primitives).

24.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

24.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

24.21.3. Continuing TECHMAP pass.
Using template $paramod$e88c2150f27e199b5b4c38f191932e407250eaa3\_80_mul for cells of type $mul.
Using template $paramod$fac210dc6e441ade6153a47dcf32d681f9d41bee\_80_mul for cells of type $__mul.
Using template $paramod$de927ffa49f2a1327665483e9418148a52f3d36b\_80_mul for cells of type $__mul.
Using template $paramod$f84b7e774a64cf6bd61391522b3eee9d216e6e7e\_80_mul for cells of type $__mul.
Using template $paramod$ba1b36458f074a6329f9cad9c8b71be8774bccea\_80_mul for cells of type $__mul.
Using template $paramod$0c59eac522c8fc6cf582c390b8c4bd5bae1bb887\_80_mul for cells of type $__mul.
Using template $paramod$84e4af21b083f56ce59bb3210f4da5751fbe9bb3\_80_mul for cells of type $__mul.
Using template $paramod$7c1afd677c664a6f211892c24ab4c74153b5be67\$__MUL18X18 for cells of type $__MUL18X18.
Using template $paramod$bef2a6330e4e8c17c10f220fb2d17af741212f04\$__MUL18X18 for cells of type $__MUL18X18.
Using template $paramod$e5ade21dea2c4d51df0cdca72b2a93a08fd8e7d1\$__MUL18X18 for cells of type $__MUL18X18.
Using template $paramod$ab0a030b3329c9db46a487d220064a2a8467942a\$__MUL18X18 for cells of type $__MUL18X18.
No more expansions possible.
<suppressed ~670 debug messages>

24.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $techmap$flatten\SOC.\Core.\Mdu.$mul$Risco-5/src/core/mdu.v:74$134.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4746 ($add).
  creating $macc model for $techmap$flatten\SOC.\Core.\Mdu.$mul$Risco-5/src/core/mdu.v:74$134.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4743 ($add).
  creating $macc model for $techmap$flatten\SOC.\Core.\Mdu.$mul$Risco-5/src/core/mdu.v:74$134.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$4740 ($add).
  creating $macc model for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$848 ($add).
  creating $macc model for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:150$1006 ($add).
  creating $macc model for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:148$1005 ($sub).
  creating $macc model for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14 ($add).
  creating $macc model for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15 ($sub).
  creating $macc model for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:114$121 ($add).
  creating $macc model for $flatten\SOC.\Core.\Mdu.$neg$Risco-5/src/core/mdu.v:127$166 ($neg).
  creating $macc model for $flatten\SOC.\Core.\Mdu.$neg$Risco-5/src/core/mdu.v:129$168 ($neg).
  creating $macc model for $flatten\SOC.\Core.\Mdu.$neg$Risco-5/src/core/mdu.v:97$142 ($neg).
  creating $macc model for $flatten\SOC.\Core.\Mdu.$neg$Risco-5/src/core/mdu.v:98$146 ($neg).
  creating $macc model for $flatten\SOC.\Core.\Mdu.$sub$Risco-5/src/core/mdu.v:116$160 ($sub).
  creating $macc model for $flatten\SOC.\GPIOS.\Pwm0.$add$Risco-5/src/peripheral/pwm.v:17$501 ($add).
  creating $macc model for $flatten\SOC.\GPIOS.\Pwm1.$add$Risco-5/src/peripheral/pwm.v:17$501 ($add).
  creating $macc model for $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:115$1408 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1576 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1578 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1584 ($add).
  creating $macc model for $flatten\SOC.\Uart.\RX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1582 ($sub).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1576 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1578 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1584 ($add).
  creating $macc model for $flatten\SOC.\Uart.\TX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1582 ($sub).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1544 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1555 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:132$1493 ($add).
  creating $macc model for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$1504 ($add).
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$1504.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:132$1493.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1555.
  creating $alu model for $macc $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1544.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1582.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1584.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1578.
  creating $alu model for $macc $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1576.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1582.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1584.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1578.
  creating $alu model for $macc $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1576.
  creating $alu model for $macc $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:115$1408.
  creating $alu model for $macc $flatten\SOC.\GPIOS.\Pwm1.$add$Risco-5/src/peripheral/pwm.v:17$501.
  creating $alu model for $macc $flatten\SOC.\GPIOS.\Pwm0.$add$Risco-5/src/peripheral/pwm.v:17$501.
  creating $alu model for $macc $flatten\SOC.\Core.\Mdu.$sub$Risco-5/src/core/mdu.v:116$160.
  creating $alu model for $macc $flatten\SOC.\Core.\Mdu.$neg$Risco-5/src/core/mdu.v:98$146.
  creating $alu model for $macc $flatten\SOC.\Core.\Mdu.$neg$Risco-5/src/core/mdu.v:97$142.
  creating $alu model for $macc $flatten\SOC.\Core.\Mdu.$neg$Risco-5/src/core/mdu.v:129$168.
  creating $alu model for $macc $flatten\SOC.\Core.\Mdu.$neg$Risco-5/src/core/mdu.v:127$166.
  creating $alu model for $macc $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:114$121.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15.
  creating $alu model for $macc $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14.
  creating $alu model for $macc $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:148$1005.
  creating $alu model for $macc $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:150$1006.
  creating $alu model for $macc $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$848.
  creating $alu model for $macc $techmap$flatten\SOC.\Core.\Mdu.$mul$Risco-5/src/core/mdu.v:74$134.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$4740.
  creating $alu model for $macc $techmap$flatten\SOC.\Core.\Mdu.$mul$Risco-5/src/core/mdu.v:74$134.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4743.
  creating $alu model for $macc $techmap$flatten\SOC.\Core.\Mdu.$mul$Risco-5/src/core/mdu.v:74$134.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4746.
  creating $alu model for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$847 ($lt): new $alu
  creating $alu model for $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:53$27 ($ge): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15.
  creating $alu model for $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:37$16 ($lt): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15.
  creating $alu model for $flatten\SOC.\Core.\Mdu.$le$Risco-5/src/core/mdu.v:115$159 ($le): new $alu
  creating $alu model for $flatten\SOC.\GPIOS.\Pwm0.$lt$Risco-5/src/peripheral/pwm.v:16$500 ($lt): new $alu
  creating $alu model for $flatten\SOC.\GPIOS.\Pwm0.$lt$Risco-5/src/peripheral/pwm.v:23$502 ($lt): new $alu
  creating $alu model for $flatten\SOC.\GPIOS.\Pwm1.$lt$Risco-5/src/peripheral/pwm.v:16$500 ($lt): new $alu
  creating $alu model for $flatten\SOC.\GPIOS.\Pwm1.$lt$Risco-5/src/peripheral/pwm.v:23$502 ($lt): new $alu
  creating $alu model for $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$849 ($eq): merged with $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$847.
  creating $alu model for $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23 ($eq): merged with $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15.
  creating $alu cell for $flatten\SOC.\GPIOS.\Pwm1.$lt$Risco-5/src/peripheral/pwm.v:23$502: $auto$alumacc.cc:485:replace_alu$4761
  creating $alu cell for $flatten\SOC.\GPIOS.\Pwm1.$lt$Risco-5/src/peripheral/pwm.v:16$500: $auto$alumacc.cc:485:replace_alu$4772
  creating $alu cell for $flatten\SOC.\GPIOS.\Pwm0.$lt$Risco-5/src/peripheral/pwm.v:23$502: $auto$alumacc.cc:485:replace_alu$4783
  creating $alu cell for $flatten\SOC.\GPIOS.\Pwm0.$lt$Risco-5/src/peripheral/pwm.v:16$500: $auto$alumacc.cc:485:replace_alu$4794
  creating $alu cell for $flatten\SOC.\Core.\Mdu.$le$Risco-5/src/core/mdu.v:115$159: $auto$alumacc.cc:485:replace_alu$4805
  creating $alu cell for $flatten\ResetBootSystem.$lt$Risco-5/debug/reset.v:36$847, $flatten\ResetBootSystem.$eq$Risco-5/debug/reset.v:38$849: $auto$alumacc.cc:485:replace_alu$4818
  creating $alu cell for $techmap$flatten\SOC.\Core.\Mdu.$mul$Risco-5/src/core/mdu.v:74$134.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4746: $auto$alumacc.cc:485:replace_alu$4829
  creating $alu cell for $techmap$flatten\SOC.\Core.\Mdu.$mul$Risco-5/src/core/mdu.v:74$134.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4743: $auto$alumacc.cc:485:replace_alu$4832
  creating $alu cell for $techmap$flatten\SOC.\Core.\Mdu.$mul$Risco-5/src/core/mdu.v:74$134.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$4740: $auto$alumacc.cc:485:replace_alu$4835
  creating $alu cell for $flatten\ResetBootSystem.$add$Risco-5/debug/reset.v:37$848: $auto$alumacc.cc:485:replace_alu$4838
  creating $alu cell for $flatten\SOC.\Core.$add$Risco-5/src/core/core.v:150$1006: $auto$alumacc.cc:485:replace_alu$4841
  creating $alu cell for $flatten\SOC.\Core.$sub$Risco-5/src/core/core.v:148$1005: $auto$alumacc.cc:485:replace_alu$4844
  creating $alu cell for $flatten\SOC.\Core.\Alu.$add$Risco-5/src/core/alu.v:33$14: $auto$alumacc.cc:485:replace_alu$4847
  creating $alu cell for $flatten\SOC.\Core.\Alu.$sub$Risco-5/src/core/alu.v:35$15, $flatten\SOC.\Core.\Alu.$ge$Risco-5/src/core/alu.v:53$27, $flatten\SOC.\Core.\Alu.$lt$Risco-5/src/core/alu.v:37$16, $flatten\SOC.\Core.\Alu.$eq$Risco-5/src/core/alu.v:45$23: $auto$alumacc.cc:485:replace_alu$4850
  creating $alu cell for $flatten\SOC.\Core.\CSR_Unit.$add$Risco-5/src/core/csr_unit.v:114$121: $auto$alumacc.cc:485:replace_alu$4863
  creating $alu cell for $flatten\SOC.\Core.\Mdu.$neg$Risco-5/src/core/mdu.v:127$166: $auto$alumacc.cc:485:replace_alu$4866
  creating $alu cell for $flatten\SOC.\Core.\Mdu.$neg$Risco-5/src/core/mdu.v:129$168: $auto$alumacc.cc:485:replace_alu$4869
  creating $alu cell for $flatten\SOC.\Core.\Mdu.$neg$Risco-5/src/core/mdu.v:97$142: $auto$alumacc.cc:485:replace_alu$4872
  creating $alu cell for $flatten\SOC.\Core.\Mdu.$neg$Risco-5/src/core/mdu.v:98$146: $auto$alumacc.cc:485:replace_alu$4875
  creating $alu cell for $flatten\SOC.\Core.\Mdu.$sub$Risco-5/src/core/mdu.v:116$160: $auto$alumacc.cc:485:replace_alu$4878
  creating $alu cell for $flatten\SOC.\GPIOS.\Pwm0.$add$Risco-5/src/peripheral/pwm.v:17$501: $auto$alumacc.cc:485:replace_alu$4881
  creating $alu cell for $flatten\SOC.\GPIOS.\Pwm1.$add$Risco-5/src/peripheral/pwm.v:17$501: $auto$alumacc.cc:485:replace_alu$4884
  creating $alu cell for $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:115$1408: $auto$alumacc.cc:485:replace_alu$4887
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1576: $auto$alumacc.cc:485:replace_alu$4890
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1578: $auto$alumacc.cc:485:replace_alu$4893
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1584: $auto$alumacc.cc:485:replace_alu$4896
  creating $alu cell for $flatten\SOC.\Uart.\RX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1582: $auto$alumacc.cc:485:replace_alu$4899
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:35$1576: $auto$alumacc.cc:485:replace_alu$4902
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:37$1578: $auto$alumacc.cc:485:replace_alu$4905
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$add$Risco-5/src/peripheral/fifo.v:40$1584: $auto$alumacc.cc:485:replace_alu$4908
  creating $alu cell for $flatten\SOC.\Uart.\TX_FIFO.$sub$Risco-5/src/peripheral/fifo.v:39$1582: $auto$alumacc.cc:485:replace_alu$4911
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:146$1544: $auto$alumacc.cc:485:replace_alu$4914
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_rx.$add$Risco-5/src/peripheral/uart_rx.v:171$1555: $auto$alumacc.cc:485:replace_alu$4917
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:132$1493: $auto$alumacc.cc:485:replace_alu$4920
  creating $alu cell for $flatten\SOC.\Uart.\i_uart_tx.$add$Risco-5/src/peripheral/uart_tx.v:149$1504: $auto$alumacc.cc:485:replace_alu$4923
  created 35 $alu and 0 $macc cells.

24.23. Executing OPT pass (performing simple optimizations).

24.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~7 debug messages>

24.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

24.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~116 debug messages>

24.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

24.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

24.23.6. Executing OPT_DFF pass (perform DFF optimizations).

24.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 4 unused cells and 69 unused wires.
<suppressed ~5 debug messages>

24.23.8. Executing OPT_EXPR pass (perform const folding).
[25%] Optimizing Phase 2 completed
Running inference ...
Optimizing module top.

24.23.9. Rerunning OPT passes. (Maybe there is more to do..)

24.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~116 debug messages>

24.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

24.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

24.23.13. Executing OPT_DFF pass (perform DFF optimizations).

24.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

24.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

24.23.16. Finished OPT passes. (There is nothing left to do.)

24.24. Executing MEMORY pass.

24.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

24.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

24.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing top.SOC.Core.RegisterBank.registers write port 0.
  Analyzing top.SOC.Core.RegisterBank.registers write port 1.
  Analyzing top.SOC.Core.RegisterBank.registers write port 2.
  Analyzing top.SOC.GPIOS.duty_cycle write port 0.
  Analyzing top.SOC.GPIOS.period write port 0.
  Analyzing top.SOC.Memory.memory write port 0.
  Analyzing top.SOC.Memory.memory write port 1.
  Analyzing top.SOC.Memory.memory write port 2.
  Analyzing top.SOC.Uart.RX_FIFO.memory write port 0.
  Analyzing top.SOC.Uart.TX_FIFO.memory write port 0.

24.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

24.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\SOC.Core.RegisterBank.registers'[0] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[1] in module `\top': no output FF found.
Checking read port `\SOC.Core.RegisterBank.registers'[2] in module `\top': merging output FF to cell.
    Write port 0: don't care on collision.
    Write port 1: non-transparent.
    Write port 2: non-transparent.
Checking read port `\SOC.GPIOS.duty_cycle'[0] in module `\top': no output FF found.
Checking read port `\SOC.GPIOS.duty_cycle'[1] in module `\top': no output FF found.
Checking read port `\SOC.GPIOS.period'[0] in module `\top': no output FF found.
Checking read port `\SOC.GPIOS.period'[1] in module `\top': no output FF found.
Checking read port `\SOC.Memory.memory'[0] in module `\top': no output FF found.
Checking read port `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': no output FF found.
Checking read port `\SOC.Uart.TX_FIFO.memory'[0] in module `\top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port address `\SOC.Core.RegisterBank.registers'[0] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.Core.RegisterBank.registers'[1] in module `\top': address FF has fully-defined init value, not supported.
Checking read port address `\SOC.GPIOS.duty_cycle'[0] in module `\top': no address FF found.
Checking read port address `\SOC.GPIOS.duty_cycle'[1] in module `\top': no address FF found.
Checking read port address `\SOC.GPIOS.period'[0] in module `\top': no address FF found.
Checking read port address `\SOC.GPIOS.period'[1] in module `\top': no address FF found.
Checking read port address `\SOC.Memory.memory'[0] in module `\top': no address FF found.
Checking read port address `\SOC.Uart.RX_FIFO.memory'[0] in module `\top': address FF has fully-defined init value, not supported.

24.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 44 unused wires.
<suppressed ~7 debug messages>

24.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
  Merging ports 0, 2 (address 5'00000).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers by address:
Consolidating read ports of memory top.SOC.GPIOS.duty_cycle by address:
  Merging ports 0, 1 (address 1'1).
Consolidating read ports of memory top.SOC.GPIOS.period by address:
  Merging ports 0, 1 (address 1'1).
Consolidating write ports of memory top.SOC.Memory.memory by address:
  Merging ports 0, 1 (address { \SOC.Memory.address [10:8] \SOC.GPIOS.address [7:2] }).
  Merging ports 0, 2 (address { \SOC.Memory.address [10:8] \SOC.GPIOS.address [7:2] }).
Consolidating write ports of memory top.SOC.Core.RegisterBank.registers using sat-based resource sharing:
  Checking group clocked with posedge \clk, width 32: ports 0, 1.
  Common input cone for all EN signals: 14 cells.
  Size of unconstrained SAT problem: 110 variables, 305 clauses
  Merging port 1 into port 0.

24.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

24.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 8 unused cells and 10 unused wires.
<suppressed ~9 debug messages>

24.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed

24.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

24.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory top.SOC.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_
Extracted data FF from read port 2 of top.SOC.Core.RegisterBank.registers: $\SOC.Core.RegisterBank.registers$rdreg[2]
using FF mapping for memory top.SOC.GPIOS.duty_cycle
using FF mapping for memory top.SOC.GPIOS.period
mapping memory top.SOC.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory top.SOC.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
mapping memory top.SOC.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of top.SOC.Uart.TX_FIFO.memory: $\SOC.Uart.TX_FIFO.memory$rdreg[0]
<suppressed ~841 debug messages>

24.27. Executing TECHMAP pass (map to technology primitives).

24.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

24.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
[55%] Inferring Phase 3 completed
Running technical mapping ...
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

24.27.3. Continuing TECHMAP pass.
Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$4e27082c5debfe2224cd4cfb46d57ecd26c2e614\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$293d72fa1e0ef78bf22001caecec6073cc652851\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$37d30a593e04dcef256e10d58b011be7c79b1d1f\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$394227e87be903825446790353e91eb2c5e10934\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$02769dd26fe80f975fe33f4663ba95c7f0fadfe5\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$898e3b9b58dbd39d9c6ca83e9bea083cb54c924d\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$e36787c87f120885851706179ae5031aec78e0c5\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$f9f95b558f368450632c01b302c670921c7d458c\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~443 debug messages>

24.28. Executing OPT pass (performing simple optimizations).

24.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~127 debug messages>

24.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

24.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$4666 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$2758_Y, Q = \ResetBootSystem.counter, rval = 6'000000).
Adding SRST signal on $auto$ff.cc:266:slice$4576 ($dffe) from module top (D = \SOC.Core.Mdu.quociente_msk [31:1], Q = \SOC.Core.Mdu.quociente_msk [30:0], rval = 31'0000000000000000000000000000000).
Adding SRST signal on $auto$ff.cc:266:slice$4562 ($dffe) from module top (D = $flatten\SOC.\Core.\Mdu.$procmux$2526_Y [63], Q = \SOC.Core.Mdu.divisor [63], rval = 1'0).

24.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 2272 unused wires.
<suppressed ~3 debug messages>

24.28.5. Rerunning OPT passes. (Removed registers in this run.)

24.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

24.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

24.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$5806 ($dffe) from module top (D = \SOC.Core.Mdu.divisor [31:1], Q = \SOC.Core.Mdu.divisor [30:0], rval = 31'0000000000000000000000000000000).
Adding SRST signal on $auto$ff.cc:266:slice$5802 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$4690 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$5805 ($sdffce) from module top.

24.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 1 unused wires.
<suppressed ~2 debug messages>

24.28.10. Rerunning OPT passes. (Removed registers in this run.)

24.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

24.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

24.28.13. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$5808 ($dffe) from module top (D = $flatten\SOC.\Core.\Mdu.$procmux$2526_Y [62], Q = \SOC.Core.Mdu.divisor [62], rval = 1'0).

24.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

24.28.15. Rerunning OPT passes. (Removed registers in this run.)

24.28.16. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

24.28.17. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

24.28.18. Executing OPT_DFF pass (perform DFF optimizations).

24.28.19. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

24.28.20. Finished fast OPT passes.

24.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
Mapping memory \SOC.GPIOS.duty_cycle in module \top:
  created 2 $dff cells and 0 static cells of width 16.
  read interface: 0 $dff and 0 $mux cells.
  write interface: 2 write mux blocks.
Mapping memory \SOC.GPIOS.period in module \top:
  created 2 $dff cells and 0 static cells of width 16.
  read interface: 0 $dff and 0 $mux cells.
  write interface: 2 write mux blocks.

24.30. Executing OPT pass (performing simple optimizations).

24.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

24.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

24.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$5005: $auto$rtlil.cc:2489:ReduceOr$4999 -> 1'1
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\PCSourceMUX.$ternary$Risco-5/src/core/mux.v:15$188.
Removed 1 multiplexer ports.
<suppressed ~78 debug messages>

24.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$4990:
      Old ports: A={ \SOC.Memory.buffer [31:16] \SOC.GPIOS.write_data [15:0] }, B={ \SOC.Leds.write_data [31:17] \SOC.GPIOS.write_data [16:0] }, Y=$auto$rtlil.cc:2603:Mux$4991
      New ports: A=\SOC.Memory.buffer [31:16], B={ \SOC.Leds.write_data [31:17] \SOC.GPIOS.write_data [16] }, Y=$auto$rtlil.cc:2603:Mux$4991 [31:16]
      New connections: $auto$rtlil.cc:2603:Mux$4991 [15:0] = \SOC.GPIOS.write_data [15:0]
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2767: { $flatten\ResetBootSystem.$procmux$2762_CMP $flatten\ResetBootSystem.$procmux$2761_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2770:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2770_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2770_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2770_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$4057:
      Old ports: A=4'1001, B=4'0011, Y=$flatten\SOC.\Core.\ALU_Control.$procmux$4057_Y
      New ports: A=2'10, B=2'01, Y={ $flatten\SOC.\Core.\ALU_Control.$procmux$4057_Y [3] $flatten\SOC.\Core.\ALU_Control.$procmux$4057_Y [1] }
      New connections: { $flatten\SOC.\Core.\ALU_Control.$procmux$4057_Y [2] $flatten\SOC.\Core.\ALU_Control.$procmux$4057_Y [0] } = 2'01
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\ALU_Control.$procmux$4065:
      Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$4691 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4691 [2]
      New connections: $auto$wreduce.cc:461:run$4691 [1:0] = 2'10
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$2964:
      Old ports: A=4'0000, B=8'10001001, Y=\SOC.Core.control_unit_aluop
      New ports: A=2'00, B=4'1011, Y={ \SOC.Core.control_unit_aluop [3] \SOC.Core.control_unit_aluop [0] }
      New connections: \SOC.Core.control_unit_aluop [2:1] = 2'00
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3190:
      Old ports: A=2'00, B=2'10, Y=\SOC.Core.lorD
      New ports: A=1'0, B=1'1, Y=\SOC.Core.lorD [1]
      New connections: \SOC.Core.lorD [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3281:
      Old ports: A=6'101101, B=6'000000, Y=$flatten\SOC.\Core.\Control_Unit.$20\nextstate[5:0]
      New ports: A=1'1, B=1'0, Y=$flatten\SOC.\Core.\Control_Unit.$20\nextstate[5:0] [0]
      New connections: $flatten\SOC.\Core.\Control_Unit.$20\nextstate[5:0] [5:1] = { $flatten\SOC.\Core.\Control_Unit.$20\nextstate[5:0] [0] 1'0 $flatten\SOC.\Core.\Control_Unit.$20\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$20\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3316:
      Old ports: A=6'000000, B=6'100101, Y=$flatten\SOC.\Core.\Control_Unit.$18\nextstate[5:0]
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\Control_Unit.$18\nextstate[5:0] [0]
      New connections: $flatten\SOC.\Core.\Control_Unit.$18\nextstate[5:0] [5:1] = { $flatten\SOC.\Core.\Control_Unit.$18\nextstate[5:0] [0] 2'00 $flatten\SOC.\Core.\Control_Unit.$18\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3357:
      Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$4701 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4701 [2]
      New connections: $auto$wreduce.cc:461:run$4701 [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3381:
      Old ports: A=6'011111, B=6'100010, Y=$flatten\SOC.\Core.\Control_Unit.$15\nextstate[5:0]
      New ports: A=2'01, B=2'10, Y={ $flatten\SOC.\Core.\Control_Unit.$15\nextstate[5:0] [5] $flatten\SOC.\Core.\Control_Unit.$15\nextstate[5:0] [0] }
      New connections: $flatten\SOC.\Core.\Control_Unit.$15\nextstate[5:0] [4:1] = { $flatten\SOC.\Core.\Control_Unit.$15\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$15\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$15\nextstate[5:0] [0] 1'1 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3409:
      Old ports: A=3'110, B=3'011, Y=$auto$wreduce.cc:461:run$4700 [2:0]
      New ports: A=2'10, B=2'01, Y={ $auto$wreduce.cc:461:run$4700 [2] $auto$wreduce.cc:461:run$4700 [0] }
      New connections: $auto$wreduce.cc:461:run$4700 [1] = 1'1
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3472:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$4698 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$4698 [2] $auto$wreduce.cc:461:run$4698 [0] }
      New connections: $auto$wreduce.cc:461:run$4698 [1] = $auto$wreduce.cc:461:run$4698 [0]
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3508:
      Old ports: A=5'00000, B=5'10010, Y=$auto$wreduce.cc:461:run$4697 [4:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4697 [1]
      New connections: { $auto$wreduce.cc:461:run$4697 [4:2] $auto$wreduce.cc:461:run$4697 [0] } = { $auto$wreduce.cc:461:run$4697 [1] 3'000 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3556:
      Old ports: A=3'101, B=3'000, Y=$auto$wreduce.cc:461:run$4696 [2:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4696 [0]
      New connections: $auto$wreduce.cc:461:run$4696 [2:1] = { $auto$wreduce.cc:461:run$4696 [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3606:
      Old ports: A=3'110, B=3'000, Y=$auto$wreduce.cc:461:run$4707 [2:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4707 [1]
      New connections: { $auto$wreduce.cc:461:run$4707 [2] $auto$wreduce.cc:461:run$4707 [0] } = { $auto$wreduce.cc:461:run$4707 [1] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3709:
      Old ports: A=5'00101, B=5'11000, Y=$auto$wreduce.cc:461:run$4705 [4:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$4705 [3] $auto$wreduce.cc:461:run$4705 [0] }
      New connections: { $auto$wreduce.cc:461:run$4705 [4] $auto$wreduce.cc:461:run$4705 [2:1] } = { $auto$wreduce.cc:461:run$4705 [3] $auto$wreduce.cc:461:run$4705 [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3765:
      Old ports: A=5'00011, B=5'10110, Y=$auto$wreduce.cc:461:run$4704 [4:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$4704 [2] $auto$wreduce.cc:461:run$4704 [0] }
      New connections: { $auto$wreduce.cc:461:run$4704 [4:3] $auto$wreduce.cc:461:run$4704 [1] } = { $auto$wreduce.cc:461:run$4704 [2] 2'01 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3819:
      Old ports: A={ 1'0 $auto$wreduce.cc:461:run$4705 [4:0] }, B={ 1'0 $auto$wreduce.cc:461:run$4704 [4:0] }, Y=$flatten\SOC.\Core.\Control_Unit.$5\nextstate[5:0]
      New ports: A=$auto$wreduce.cc:461:run$4705 [4:0], B=$auto$wreduce.cc:461:run$4704 [4:0], Y=$flatten\SOC.\Core.\Control_Unit.$5\nextstate[5:0] [4:0]
      New connections: $flatten\SOC.\Core.\Control_Unit.$5\nextstate[5:0] [5] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3880:
      Old ports: A=6'000110, B=6'101111, Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0]
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [0]
      New connections: $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [5:1] = { $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [0] 1'0 $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [0] 2'11 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3999:
      Old ports: A=6'000000, B=6'101110, Y=$flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0]
      New ports: A=1'0, B=1'1, Y=$flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1]
      New connections: { $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [5:2] $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [0] } = { $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] 1'0 $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] $flatten\SOC.\Core.\Control_Unit.$2\nextstate[5:0] [1] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$ternary$Risco-5/src/core/control_unit.v:111$38:
      Old ports: A=2'11, B=2'01, Y=\SOC.Core.Control_Unit.second_block_write_src_b [1:0]
      New ports: A=1'1, B=1'0, Y=\SOC.Core.Control_Unit.second_block_write_src_b [1]
      New connections: \SOC.Core.Control_Unit.second_block_write_src_b [0] = 1'1
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Immediate_Generator.$procmux$2651:
      Old ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:20] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24:20] 20'00000000000000000000 \SOC.Core.instruction_register [31:20] 27'000000000000000000000000000 \SOC.Core.instruction_register [24:20] }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0]
      New ports: A={ \SOC.Core.instruction_register [31] \SOC.Core.instruction_register [31:25] }, B={ \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] \SOC.Core.instruction_register [24] 1'0 \SOC.Core.instruction_register [31:25] 8'00000000 }, Y=$flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12:5]
      New connections: { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [31:13] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [4:0] } = { $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\SOC.\Core.\Immediate_Generator.$2\immediate[31:0] [12] \SOC.Core.instruction_register [24:20] }
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Mdu.$procmux$2523:
      Old ports: A={ 1'0 $flatten\SOC.\Core.\Mdu.$procmux$2526_Y [62:31] 31'0000000000000000000000000000000 }, B={ 2'00 \SOC.Core.Mdu.divisor [62:1] }, Y=$flatten\SOC.\Core.\Mdu.$procmux$2523_Y
      New ports: A={ $flatten\SOC.\Core.\Mdu.$procmux$2526_Y [62:31] 31'0000000000000000000000000000000 }, B={ 1'0 \SOC.Core.Mdu.divisor [62:1] }, Y=$flatten\SOC.\Core.\Mdu.$procmux$2523_Y [62:0]
      New connections: $flatten\SOC.\Core.\Mdu.$procmux$2523_Y [63] = 1'0
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Memory.$procmux$1883:
      Old ports: A=\SOC.Memory.buffer, B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7:0] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:0] 24'000000000000000000000000 \SOC.Memory.buffer [7:0] 16'0000000000000000 \SOC.Memory.buffer [15:0] }, Y=\SOC.Bus.slave_0_read_data
      New ports: A=\SOC.Memory.buffer [31:8], B={ \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [7] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15] \SOC.Memory.buffer [15:8] 40'0000000000000000000000000000000000000000 \SOC.Memory.buffer [15:8] }, Y=\SOC.Bus.slave_0_read_data [31:8]
      New connections: \SOC.Bus.slave_0_read_data [7:0] = \SOC.Memory.buffer [7:0]
    New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$2157: $auto$opt_reduce.cc:134:opt_pmux$5845
    New ctrl vector for $pmux cell $flatten\SOC.\Uart.$procmux$2171: { $flatten\SOC.\Uart.$procmux$2165_CMP $flatten\SOC.\Uart.$procmux$2107_CMP $auto$opt_reduce.cc:134:opt_pmux$5847 $flatten\SOC.\Uart.$procmux$2088_Y }
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.$procmux$2188:
      Old ports: A=4'0001, B=16'0110011110001001, Y=$flatten\SOC.\Uart.$procmux$2188_Y
      New ports: A=3'001, B=12'010011100101, Y={ $flatten\SOC.\Uart.$procmux$2188_Y [3] $flatten\SOC.\Uart.$procmux$2188_Y [1:0] }
      New connections: $flatten\SOC.\Uart.$procmux$2188_Y [2] = $flatten\SOC.\Uart.$procmux$2188_Y [1]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_rx.$procmux$1739:
      Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$4729 [0] 1'0 $auto$wreduce.cc:461:run$4730 [1:0] 2'01 \SOC.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$4732 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$4729 [0] $auto$wreduce.cc:461:run$4730 [1:0] 1'1 \SOC.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$4732 [1:0] }, Y=\SOC.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_rx.$ternary$Risco-5/src/peripheral/uart_rx.v:113$1533:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$4732 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4732 [0]
      New connections: $auto$wreduce.cc:461:run$4732 [1] = $auto$wreduce.cc:461:run$4732 [0]
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Uart.\i_uart_tx.$procmux$1876:
      Old ports: A=3'000, B={ 2'00 \SOC.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$4734 [1:0] 2'01 \SOC.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$4736 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \SOC.Uart.uart_tx_en $auto$wreduce.cc:461:run$4734 [1:0] 1'1 \SOC.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$4736 [1:0] }, Y=\SOC.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \SOC.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.\i_uart_tx.$ternary$Risco-5/src/peripheral/uart_tx.v:97$1476:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$4736 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4736 [0]
      New connections: $auto$wreduce.cc:461:run$4736 [1] = $auto$wreduce.cc:461:run$4736 [0]
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$5846: { $flatten\SOC.\Uart.$procmux$2135_CMP $flatten\SOC.\Uart.$procmux$2134_CMP $flatten\SOC.\Uart.$procmux$2133_CMP $flatten\SOC.\Uart.$procmux$2132_CMP $flatten\SOC.\Uart.$procmux$2082_CMP $flatten\SOC.\Uart.$procmux$2063_CMP }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $auto$memory_share.cc:273:consolidate_wr_by_addr$4994:
      Old ports: A=$auto$rtlil.cc:2603:Mux$4991, B={ \SOC.Memory.buffer [31:8] \SOC.GPIOS.write_data [7:0] }, Y=$auto$rtlil.cc:2603:Mux$4995
      New ports: A={ $auto$rtlil.cc:2603:Mux$4991 [31:16] \SOC.GPIOS.write_data [15:8] }, B=\SOC.Memory.buffer [31:8], Y=$auto$rtlil.cc:2603:Mux$4995 [31:8]
      New connections: $auto$rtlil.cc:2603:Mux$4995 [7:0] = \SOC.GPIOS.write_data [7:0]
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2776:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2770_Y, Y=$flatten\ResetBootSystem.$procmux$2776_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2770_Y [1], Y=$flatten\ResetBootSystem.$procmux$2776_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2776_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3336:
      Old ports: A=6'100001, B=$flatten\SOC.\Core.\Control_Unit.$18\nextstate[5:0], Y=$flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0]
      New ports: A=2'01, B={ $flatten\SOC.\Core.\Control_Unit.$18\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$18\nextstate[5:0] [0] }, Y={ $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [2] $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] }
      New connections: { $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [5:3] $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [1] } = { $flatten\SOC.\Core.\Control_Unit.$17\nextstate[5:0] [0] 3'000 }
    Consolidated identical input bits for $pmux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3935:
      Old ports: A=6'000000, B={ 6'000010 $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] 42'001000001001001010001100001101001110001111 }, Y=$flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0]
      New ports: A=5'00000, B={ 5'00010 $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [0] $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [0] 2'11 $flatten\SOC.\Core.\Control_Unit.$4\nextstate[5:0] [0] 35'01000010010101001100011010111001111 }, Y={ $flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0] [5] $flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0] [3:0] }
      New connections: $flatten\SOC.\Core.\Control_Unit.$3\nextstate[5:0] [4] = 1'0
    Consolidated identical input bits for $mux cell $flatten\SOC.\Uart.$procmux$2193:
      Old ports: A=4'0000, B=$flatten\SOC.\Uart.$procmux$2188_Y, Y=$flatten\SOC.\Uart.$procmux$2193_Y
      New ports: A=3'000, B={ $flatten\SOC.\Uart.$procmux$2188_Y [3] $flatten\SOC.\Uart.$procmux$2188_Y [1:0] }, Y={ $flatten\SOC.\Uart.$procmux$2193_Y [3] $flatten\SOC.\Uart.$procmux$2193_Y [1:0] }
      New connections: $flatten\SOC.\Uart.$procmux$2193_Y [2] = $flatten\SOC.\Uart.$procmux$2193_Y [1]
  Optimizing cells in module \top.
Performed a total of 41 changes.

24.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

24.30.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$4501 ($dffe) from module top (D = $flatten\SOC.\Uart.$add$Risco-5/src/peripheral/uart.v:115$1408_Y, Q = \SOC.Uart.counter, rval = 3'000).

24.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2 unused cells and 12 unused wires.
<suppressed ~3 debug messages>

24.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~8 debug messages>

24.30.9. Rerunning OPT passes. (Maybe there is more to do..)

24.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\SOC.\Core.\MemoryAddressMUX.$ternary$Risco-5/src/core/mux.v:16$187.
Removed 1 multiplexer ports.
<suppressed ~79 debug messages>

24.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\SOC.\Core.\Control_Unit.$procmux$3819:
      Old ports: A={ $auto$wreduce.cc:461:run$4704 [4] $auto$wreduce.cc:461:run$4704 [4] $auto$wreduce.cc:461:run$4704 [0] 1'0 $auto$wreduce.cc:461:run$4704 [0] }, B={ $auto$wreduce.cc:461:run$4704 [4] 1'0 $auto$wreduce.cc:461:run$4704 [4] 1'1 $auto$wreduce.cc:461:run$4704 [0] }, Y=$flatten\SOC.\Core.\Control_Unit.$5\nextstate[5:0] [4:0]
      New ports: A={ $auto$wreduce.cc:461:run$4704 [4] $auto$wreduce.cc:461:run$4704 [0] 1'0 }, B={ 1'0 $auto$wreduce.cc:461:run$4704 [4] 1'1 }, Y=$flatten\SOC.\Core.\Control_Unit.$5\nextstate[5:0] [3:1]
      New connections: { $flatten\SOC.\Core.\Control_Unit.$5\nextstate[5:0] [4] $flatten\SOC.\Core.\Control_Unit.$5\nextstate[5:0] [0] } = { $auto$wreduce.cc:461:run$4704 [4] $auto$wreduce.cc:461:run$4704 [0] }
  Optimizing cells in module \top.
Performed a total of 1 changes.

24.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

24.30.13. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $memory\SOC.GPIOS.period[1]$5834 ($dff) from module top (D = \SOC.GPIOS.write_data [15:0], Q = \SOC.GPIOS.period[1]).
Adding EN signal on $memory\SOC.GPIOS.period[0]$5832 ($dff) from module top (D = \SOC.GPIOS.write_data [15:0], Q = \SOC.GPIOS.period[0]).
Adding EN signal on $memory\SOC.GPIOS.duty_cycle[1]$5818 ($dff) from module top (D = \SOC.GPIOS.write_data [15:0], Q = \SOC.GPIOS.duty_cycle[1]).
Adding EN signal on $memory\SOC.GPIOS.duty_cycle[0]$5816 ($dff) from module top (D = \SOC.GPIOS.write_data [15:0], Q = \SOC.GPIOS.duty_cycle[0]).
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$4411 ($sdff) from module top.

24.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 4 unused cells and 10 unused wires.
<suppressed ~5 debug messages>

24.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

24.30.16. Rerunning OPT passes. (Maybe there is more to do..)

24.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~76 debug messages>

24.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

24.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

24.30.20. Executing OPT_DFF pass (perform DFF optimizations).

24.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

24.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

24.30.23. Finished OPT passes. (There is nothing left to do.)

24.31. Executing TECHMAP pass (map to technology primitives).

24.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

24.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

24.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $sdffce.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $eq.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $reduce_bool.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $bmux.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using template $paramod$2407ada40cc3dda6c6015be2b49b748cddb5a800\_90_demux for cells of type $demux.
Using template $paramod$8a99b868050f542c83270fc93de09787e35f2c64\_80_ecp5_alu for cells of type $alu.
Using template $paramod$2bd81f420048247ff6903399c560fe0f8bd48ccc\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $ne.
Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux.
Using template $paramod$73d715d333263ca9cf422f13d07e21664e3ab775\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $dff.
Using template $paramod$2126a3039e9678f6a4bd73d35a1f58ee2616afb2\_80_ecp5_alu for cells of type $alu.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $tribuf.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$b098bc6f249c0ac91c4d6e19d54b23c285914115\_90_pmux for cells of type $pmux.
Using template $paramod$20d3ee62d72123142eb855d7ddafd835e31ba009\_90_pmux for cells of type $pmux.
Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux.
Using template $paramod$a04dd9d4d8b430140c4ff94b50470fb380fda2a0\_80_ecp5_alu for cells of type $alu.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu.
Using template $paramod$19e9557905baa9d3741d0daa66e2ef076e9bab7d\_90_pmux for cells of type $pmux.
Using template $paramod$2116a631f856d4d4902c2618dca73dafa3b8c9c0\_90_alu for cells of type $alu.
Using template $paramod$c6baa65225090ac0a120feab1b920965244aa496\_80_ecp5_alu for cells of type $alu.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using template $paramod$730057d8259da96d4776b15a47b747852ed4c479\_90_pmux for cells of type $pmux.
Using template $paramod$6c2ddb6b4192501673ebd4ff4d32f9d262417221\_90_pmux for cells of type $pmux.
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
Using template $paramod$e25898cce02b4d043ab08e065e45db8cf66c901c\_90_pmux for cells of type $pmux.
Using template $paramod$a285b5a57fe61eabc57c91b8c412748ee1151a85\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $reduce_xor.
Using template $paramod$95ab7b964273918a033d1324366ecc612d202989\_90_pmux for cells of type $pmux.
Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\_90_pmux for cells of type $pmux.
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$5180471e6f22625c8e3c4261cd538e11648586b5\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$335cfd09f1afa8139c4aafcbbe5f361887b79c5e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$ed6389a5938b09f91843a91d67becca5abedb1bd\_90_pmux for cells of type $pmux.
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux.
Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~5297 debug messages>

24.32. Executing OPT pass (performing simple optimizations).

24.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~7526 debug messages>

24.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~4971 debug messages>
Removed a total of 1657 cells.

24.32.3. Executing OPT_DFF pass (perform DFF optimizations).

24.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).

****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

source run.tcl
# read_verilog "main.v"
Finding unused cells or wires in module \top..
Removed 1205 unused cells and 4649 unused wires.
<suppressed ~1206 debug messages>

24.32.5. Finished fast OPT passes.

24.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

24.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

24.35. Executing TECHMAP pass (map to technology primitives).

24.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

24.35.2. Continuing TECHMAP pass.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_.
Using template $paramod\$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_.
No more expansions possible.
<suppressed ~1489 debug messages>

24.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~16 debug messages>

24.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

24.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in top.

24.39. Executing ATTRMVCP pass (move or copy attributes).

24.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 7559 unused wires.
<suppressed ~1 debug messages>

24.41. Executing TECHMAP pass (map to technology primitives).

24.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

24.41.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

24.42. Executing ABC9 pass.

24.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

24.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

24.42.3. Executing PROC pass (convert processes to netlists).

24.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$29728'.
Cleaned up 1 empty switch.

24.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29729 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

24.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

24.42.3.4. Executing PROC_INIT pass (extract init attributes).

24.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

24.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29729'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29727_EN[3:0]$29735
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29727_DATA[3:0]$29734
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29727_ADDR[3:0]$29733
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$29728'.

24.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29722_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29717_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29711_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29712_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29713_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29714_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29718_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29719_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29723_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29715_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29724_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29720_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29716_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29725_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29721_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29726_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29727_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29729'.
  created $dff cell `$procdff$29779' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29727_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29729'.
  created $dff cell `$procdff$29780' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29727_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29729'.
  created $dff cell `$procdff$29781' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$29728'.
  created direct connection (no actual register cell created).

24.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29753'.
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29729'.
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$29728'.
Cleaned up 1 empty switch.

24.42.3.12. Executing OPT_EXPR pass (perform const folding).

24.42.4. Executing PROC pass (convert processes to netlists).

24.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$29799'.
Cleaned up 1 empty switch.

24.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29800 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

24.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

24.42.4.4. Executing PROC_INIT pass (extract init attributes).

24.42.4.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

24.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29800'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29798_EN[3:0]$29804
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29798_DATA[3:0]$29806
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29798_ADDR[3:0]$29805
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$29799'.

24.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29788_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29795_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29790_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29785_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29782_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29794_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29789_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29793_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29784_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29797_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29796_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29792_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29783_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29791_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29787_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29786_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29798_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29800'.
  created $dff cell `$procdff$29850' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29798_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29800'.
  created $dff cell `$procdff$29851' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29798_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29800'.
  created $dff cell `$procdff$29852' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$29799'.
  created direct connection (no actual register cell created).

24.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29824'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29800'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$29799'.
Cleaned up 1 empty switch.

24.42.4.12. Executing OPT_EXPR pass (perform const folding).

24.42.5. Executing PROC pass (convert processes to netlists).

24.42.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$29870'.
Cleaned up 1 empty switch.

24.42.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29871 in module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

24.42.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

24.42.5.4. Executing PROC_INIT pass (extract init attributes).

24.42.5.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

24.42.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
Creating decoders for process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29871'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29869_EN[3:0]$29876
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29869_DATA[3:0]$29877
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29869_ADDR[3:0]$29875
Creating decoders for process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$29870'.

24.42.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.\i' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29862_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29857_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29855_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29868_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29863_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29858_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29867_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29853_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29854_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29856_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29866_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29859_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29860_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29864_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29865_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29861_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29869_ADDR' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29871'.
  created $dff cell `$procdff$29921' with positive edge clock.
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29869_EN' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29871'.
  created $dff cell `$procdff$29922' with positive edge clock.
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29869_DATA' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29871'.
  created $dff cell `$procdff$29923' with positive edge clock.
Creating register for signal `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$29870'.
  created direct connection (no actual register cell created).

24.42.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29895'.
Found and cleaned up 1 empty switch in `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29871'.
Removing empty process `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$29870'.
Cleaned up 1 empty switch.

24.42.5.12. Executing OPT_EXPR pass (perform const folding).

24.42.6. Executing PROC pass (convert processes to netlists).

24.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$29941'.
Cleaned up 1 empty switch.

24.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29942 in module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

24.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

24.42.6.4. Executing PROC_INIT pass (extract init attributes).

24.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

24.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
Creating decoders for process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29942'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29940_EN[3:0]$29946
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29940_DATA[3:0]$29947
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29940_ADDR[3:0]$29948
Creating decoders for process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$29941'.

24.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29925_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.\i' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29936_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29931_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29926_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29924_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29935_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29939_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29934_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29933_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29932_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29938_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29927_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29928_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29937_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29929_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29930_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29940_EN' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29942'.
  created $dff cell `$procdff$29992' with positive edge clock.
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29940_DATA' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29942'.
  created $dff cell `$procdff$29993' with positive edge clock.
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$29940_ADDR' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29942'.
  created $dff cell `$procdff$29994' with positive edge clock.
Creating register for signal `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.\muxwre' using process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$29941'.
  created direct connection (no actual register cell created).

24.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$29966'.
Found and cleaned up 1 empty switch in `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$29942'.
Removing empty process `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$29941'.
Cleaned up 1 empty switch.

24.42.6.12. Executing OPT_EXPR pass (perform const folding).

24.42.7. Executing PROC pass (convert processes to netlists).

24.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30012'.
Cleaned up 1 empty switch.

24.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30013 in module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

24.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

24.42.7.4. Executing PROC_INIT pass (extract init attributes).

24.42.7.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

24.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
Creating decoders for process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30013'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30011_EN[3:0]$30019
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30011_DATA[3:0]$30017
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30011_ADDR[3:0]$30018
Creating decoders for process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30012'.

24.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.\i' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30007_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30008_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30003_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29998_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30010_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30006_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30005_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30001_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29997_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29995_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30009_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30004_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29999_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30002_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$29996_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30000_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30011_DATA' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30013'.
  created $dff cell `$procdff$30063' with positive edge clock.
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30011_ADDR' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30013'.
  created $dff cell `$procdff$30064' with positive edge clock.
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30011_EN' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30013'.
  created $dff cell `$procdff$30065' with positive edge clock.
Creating register for signal `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.\muxwre' using process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30012'.
  created direct connection (no actual register cell created).

24.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30037'.
Found and cleaned up 1 empty switch in `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30013'.
Removing empty process `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30012'.
Cleaned up 1 empty switch.

24.42.7.12. Executing OPT_EXPR pass (perform const folding).

24.42.8. Executing PROC pass (convert processes to netlists).

24.42.8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30083'.
Cleaned up 1 empty switch.

24.42.8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30084 in module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

24.42.8.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

24.42.8.4. Executing PROC_INIT pass (extract init attributes).

24.42.8.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.8.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

24.42.8.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
Creating decoders for process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30084'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30082_EN[3:0]$30090
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30082_DATA[3:0]$30089
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30082_ADDR[3:0]$30088
Creating decoders for process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30083'.

24.42.8.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.8.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.\i' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30076_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30070_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30080_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30075_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30069_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30073_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30074_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30072_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30071_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30067_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30066_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30081_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30078_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30068_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30079_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30077_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30082_ADDR' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30084'.
  created $dff cell `$procdff$30134' with positive edge clock.
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30082_DATA' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30084'.
  created $dff cell `$procdff$30135' with positive edge clock.
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30082_EN' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30084'.
  created $dff cell `$procdff$30136' with positive edge clock.
Creating register for signal `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.\muxwre' using process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30083'.
  created direct connection (no actual register cell created).

24.42.8.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.8.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30108'.
Found and cleaned up 1 empty switch in `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30084'.
Removing empty process `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30083'.
Cleaned up 1 empty switch.

24.42.8.12. Executing OPT_EXPR pass (perform const folding).

24.42.9. Executing PROC pass (convert processes to netlists).

24.42.9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30154'.
Cleaned up 1 empty switch.

24.42.9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30155 in module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

24.42.9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

24.42.9.4. Executing PROC_INIT pass (extract init attributes).

24.42.9.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.9.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

24.42.9.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
Creating decoders for process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30155'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30153_EN[3:0]$30159
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30153_DATA[3:0]$30160
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30153_ADDR[3:0]$30161
Creating decoders for process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30154'.

24.42.9.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.9.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.\i' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30151_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30150_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30145_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30144_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30139_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30149_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30138_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30148_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30147_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30143_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30142_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30141_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30137_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30152_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30146_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30140_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30153_EN' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30155'.
  created $dff cell `$procdff$30205' with positive edge clock.
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30153_DATA' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30155'.
  created $dff cell `$procdff$30206' with positive edge clock.
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30153_ADDR' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30155'.
  created $dff cell `$procdff$30207' with positive edge clock.
Creating register for signal `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30154'.
  created direct connection (no actual register cell created).

24.42.9.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30179'.
Found and cleaned up 1 empty switch in `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30155'.
Removing empty process `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30154'.
Cleaned up 1 empty switch.

24.42.9.12. Executing OPT_EXPR pass (perform const folding).

24.42.10. Executing PROC pass (convert processes to netlists).

24.42.10.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30225'.
Cleaned up 1 empty switch.

24.42.10.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30226 in module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

24.42.10.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

24.42.10.4. Executing PROC_INIT pass (extract init attributes).

24.42.10.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.10.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

24.42.10.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
Creating decoders for process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30226'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30224_EN[3:0]$30230
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30224_DATA[3:0]$30231
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30224_ADDR[3:0]$30232
Creating decoders for process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30225'.

24.42.10.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.10.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.\i' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30221_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30220_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30215_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30214_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30209_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30223_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30219_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30218_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30217_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30213_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30212_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30211_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30222_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30216_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30210_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30208_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30224_EN' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30226'.
  created $dff cell `$procdff$30276' with positive edge clock.
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30224_DATA' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30226'.
  created $dff cell `$procdff$30277' with positive edge clock.
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30224_ADDR' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30226'.
  created $dff cell `$procdff$30278' with positive edge clock.
Creating register for signal `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.\muxwre' using process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30225'.
  created direct connection (no actual register cell created).

24.42.10.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.10.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30250'.
Found and cleaned up 1 empty switch in `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30226'.
Removing empty process `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30225'.
Cleaned up 1 empty switch.

24.42.10.12. Executing OPT_EXPR pass (perform const folding).

24.42.11. Executing PROC pass (convert processes to netlists).

24.42.11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30296'.
Cleaned up 1 empty switch.

24.42.11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30297 in module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

24.42.11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

24.42.11.4. Executing PROC_INIT pass (extract init attributes).

24.42.11.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.11.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

24.42.11.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
Creating decoders for process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30297'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30295_EN[3:0]$30303
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30295_DATA[3:0]$30301
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30295_ADDR[3:0]$30302
Creating decoders for process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30296'.

24.42.11.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.11.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.\i' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30291_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30290_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30284_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30289_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30288_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30282_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30279_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30292_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30286_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30280_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30283_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30285_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30294_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30287_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30281_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30293_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30295_DATA' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30297'.
  created $dff cell `$procdff$30347' with positive edge clock.
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30295_ADDR' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30297'.
  created $dff cell `$procdff$30348' with positive edge clock.
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30295_EN' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30297'.
  created $dff cell `$procdff$30349' with positive edge clock.
Creating register for signal `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.\muxwre' using process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30296'.
  created direct connection (no actual register cell created).

24.42.11.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30321'.
Found and cleaned up 1 empty switch in `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30297'.
Removing empty process `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30296'.
Cleaned up 1 empty switch.

24.42.11.12. Executing OPT_EXPR pass (perform const folding).

24.42.12. Executing PROC pass (convert processes to netlists).

24.42.12.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30367'.
Cleaned up 1 empty switch.

24.42.12.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30368 in module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

24.42.12.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

24.42.12.4. Executing PROC_INIT pass (extract init attributes).

24.42.12.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.12.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

24.42.12.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
Creating decoders for process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30368'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30366_EN[3:0]$30373
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30366_DATA[3:0]$30372
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30366_ADDR[3:0]$30374
Creating decoders for process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30367'.

24.42.12.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.12.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.\i' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30361_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30360_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30355_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30364_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30365_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30354_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30363_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30358_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30359_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30357_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30353_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30352_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30351_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30350_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30362_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30356_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30366_DATA' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30368'.
  created $dff cell `$procdff$30418' with positive edge clock.
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30366_EN' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30368'.
  created $dff cell `$procdff$30419' with positive edge clock.
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30366_ADDR' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30368'.
  created $dff cell `$procdff$30420' with positive edge clock.
Creating register for signal `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30367'.
  created direct connection (no actual register cell created).

24.42.12.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.12.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30392'.
Found and cleaned up 1 empty switch in `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30368'.
Removing empty process `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30367'.
Cleaned up 1 empty switch.

24.42.12.12. Executing OPT_EXPR pass (perform const folding).

24.42.13. Executing SCC pass (detecting logic loops).
Found an SCC: $auto$simplemap.cc:75:simplemap_bitop$20375 $auto$opt_expr.cc:613:replace_const_cells$27843 $auto$ff.cc:266:slice$8778 $auto$simplemap.cc:75:simplemap_bitop$20382 $auto$simplemap.cc:38:simplemap_not$18804 $auto$ff.cc:266:slice$8785 $auto$simplemap.cc:38:simplemap_not$18825 $auto$ff.cc:266:slice$8806 $auto$simplemap.cc:126:simplemap_reduce$8236 $auto$simplemap.cc:38:simplemap_not$18826 $auto$ff.cc:266:slice$8807 $auto$simplemap.cc:38:simplemap_not$20715 $auto$ff.cc:266:slice$8805 $auto$simplemap.cc:126:simplemap_reduce$8225 $auto$simplemap.cc:75:simplemap_bitop$20381 $auto$simplemap.cc:38:simplemap_not$18803 $auto$ff.cc:266:slice$8784 $auto$simplemap.cc:38:simplemap_not$18816 $auto$ff.cc:266:slice$8797 $auto$simplemap.cc:38:simplemap_not$18817 $auto$ff.cc:266:slice$8798 $auto$simplemap.cc:126:simplemap_reduce$8231 $auto$simplemap.cc:38:simplemap_not$18815 $auto$ff.cc:266:slice$8796 $auto$simplemap.cc:75:simplemap_bitop$20380 $auto$simplemap.cc:38:simplemap_not$18802 $auto$ff.cc:266:slice$8783 $auto$simplemap.cc:126:simplemap_reduce$8240 $auto$simplemap.cc:126:simplemap_reduce$8224 $auto$simplemap.cc:75:simplemap_bitop$20379 $auto$simplemap.cc:38:simplemap_not$18801 $auto$ff.cc:266:slice$8782 $auto$simplemap.cc:75:simplemap_bitop$20378 $auto$simplemap.cc:38:simplemap_not$18800 $auto$ff.cc:266:slice$8781 $auto$simplemap.cc:38:simplemap_not$18828 $auto$ff.cc:266:slice$8809 $auto$simplemap.cc:126:simplemap_reduce$8246 $auto$simplemap.cc:126:simplemap_reduce$8237 $auto$simplemap.cc:38:simplemap_not$18827 $auto$ff.cc:266:slice$8808 $auto$simplemap.cc:126:simplemap_reduce$8223 $auto$simplemap.cc:75:simplemap_bitop$20377 $auto$simplemap.cc:38:simplemap_not$18799 $auto$ff.cc:266:slice$8780 $auto$simplemap.cc:126:simplemap_reduce$8248 $auto$simplemap.cc:126:simplemap_reduce$8239 $auto$simplemap.cc:126:simplemap_reduce$8222 $auto$simplemap.cc:75:simplemap_bitop$20376 $auto$simplemap.cc:38:simplemap_not$18798 $auto$alumacc.cc:485:replace_alu$4794.slice[6].ccu2c_i $auto$alumacc.cc:485:replace_alu$4794.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$4794.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$4794.slice[0].ccu2c_i $auto$ff.cc:266:slice$8779 $auto$simplemap.cc:75:simplemap_bitop$20383 $auto$simplemap.cc:38:simplemap_not$18805 $auto$ff.cc:266:slice$8786 $auto$alumacc.cc:485:replace_alu$4794.slice[8].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$8226 $auto$simplemap.cc:75:simplemap_bitop$20384 $auto$simplemap.cc:38:simplemap_not$18806 $auto$ff.cc:266:slice$8787 $auto$simplemap.cc:75:simplemap_bitop$20385 $auto$simplemap.cc:38:simplemap_not$18807 $auto$ff.cc:266:slice$8788 $auto$alumacc.cc:485:replace_alu$4794.slice[10].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$8241 $auto$simplemap.cc:126:simplemap_reduce$8227 $auto$simplemap.cc:75:simplemap_bitop$20386 $auto$simplemap.cc:38:simplemap_not$18808 $auto$ff.cc:266:slice$8789 $auto$simplemap.cc:75:simplemap_bitop$20387 $auto$simplemap.cc:38:simplemap_not$18809 $auto$ff.cc:266:slice$8790 $auto$simplemap.cc:75:simplemap_bitop$20390 $auto$simplemap.cc:38:simplemap_not$18812 $auto$ff.cc:266:slice$8793 $auto$alumacc.cc:485:replace_alu$4794.slice[12].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$8228 $auto$simplemap.cc:75:simplemap_bitop$20388 $auto$simplemap.cc:38:simplemap_not$18810 $auto$ff.cc:266:slice$8791 $auto$alumacc.cc:485:replace_alu$4794.slice[14].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$8253 $auto$simplemap.cc:126:simplemap_reduce$8249 $auto$simplemap.cc:126:simplemap_reduce$8242 $auto$simplemap.cc:126:simplemap_reduce$8229 $auto$simplemap.cc:75:simplemap_bitop$20389 $auto$simplemap.cc:38:simplemap_not$18811 $auto$ff.cc:266:slice$8792 $auto$simplemap.cc:38:simplemap_not$18822 $auto$ff.cc:266:slice$8803 $auto$simplemap.cc:126:simplemap_reduce$8235 $auto$simplemap.cc:38:simplemap_not$18823 $auto$ff.cc:266:slice$8804 $auto$simplemap.cc:38:simplemap_not$18819 $auto$ff.cc:266:slice$8800 $auto$simplemap.cc:126:simplemap_reduce$8233 $auto$simplemap.cc:38:simplemap_not$18820 $auto$ff.cc:266:slice$8801 $auto$simplemap.cc:126:simplemap_reduce$8244 $auto$simplemap.cc:126:simplemap_reduce$8232 $auto$simplemap.cc:38:simplemap_not$18818 $auto$ff.cc:266:slice$8799 $auto$simplemap.cc:126:simplemap_reduce$8251 $auto$simplemap.cc:126:simplemap_reduce$8245 $auto$simplemap.cc:126:simplemap_reduce$8234 $auto$simplemap.cc:38:simplemap_not$18821 $auto$ff.cc:266:slice$8802 $auto$simplemap.cc:38:simplemap_not$18813 $auto$ff.cc:266:slice$8794 $auto$simplemap.cc:38:simplemap_not$7665 $auto$alumacc.cc:485:replace_alu$4794.slice[30].ccu2c_i $auto$alumacc.cc:485:replace_alu$4794.slice[28].ccu2c_i $auto$alumacc.cc:485:replace_alu$4794.slice[26].ccu2c_i $auto$alumacc.cc:485:replace_alu$4794.slice[24].ccu2c_i $auto$alumacc.cc:485:replace_alu$4794.slice[22].ccu2c_i $auto$alumacc.cc:485:replace_alu$4794.slice[20].ccu2c_i $auto$alumacc.cc:485:replace_alu$4794.slice[18].ccu2c_i $auto$alumacc.cc:485:replace_alu$4794.slice[16].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$8256 $auto$simplemap.cc:126:simplemap_reduce$8254 $auto$simplemap.cc:126:simplemap_reduce$8250 $auto$simplemap.cc:126:simplemap_reduce$8243 $auto$simplemap.cc:126:simplemap_reduce$8230 $auto$simplemap.cc:38:simplemap_not$18814 $auto$ff.cc:266:slice$8795 $auto$simplemap.cc:126:simplemap_reduce$7896 $auto$simplemap.cc:75:simplemap_bitop$7664
Found an SCC: $auto$simplemap.cc:75:simplemap_bitop$20055 $auto$simplemap.cc:38:simplemap_not$19991 $auto$ff.cc:266:slice$9181 $auto$simplemap.cc:75:simplemap_bitop$20059 $auto$simplemap.cc:38:simplemap_not$19835 $auto$ff.cc:266:slice$9185 $auto$simplemap.cc:75:simplemap_bitop$20061 $auto$simplemap.cc:38:simplemap_not$19837 $auto$ff.cc:266:slice$9187 $auto$simplemap.cc:75:simplemap_bitop$20063 $auto$simplemap.cc:38:simplemap_not$19999 $auto$ff.cc:266:slice$9189 $auto$simplemap.cc:75:simplemap_bitop$20066 $auto$simplemap.cc:38:simplemap_not$19842 $auto$ff.cc:266:slice$9192 $auto$simplemap.cc:38:simplemap_not$19854 $auto$ff.cc:266:slice$9204 $auto$simplemap.cc:38:simplemap_not$20175 $auto$ff.cc:266:slice$9205 $auto$simplemap.cc:38:simplemap_not$20021 $auto$ff.cc:266:slice$9211 $auto$simplemap.cc:126:simplemap_reduce$12587 $auto$simplemap.cc:38:simplemap_not$20022 $auto$ff.cc:266:slice$9212 $auto$simplemap.cc:38:simplemap_not$20167 $auto$ff.cc:266:slice$9197 $auto$alumacc.cc:485:replace_alu$4772.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$12572 $auto$simplemap.cc:75:simplemap_bitop$20056 $auto$simplemap.cc:38:simplemap_not$20152 $auto$ff.cc:266:slice$9182 $auto$simplemap.cc:75:simplemap_bitop$20057 $auto$simplemap.cc:38:simplemap_not$19833 $auto$ff.cc:266:slice$9183 $auto$alumacc.cc:485:replace_alu$4772.slice[2].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$12589 $auto$simplemap.cc:126:simplemap_reduce$12573 $auto$simplemap.cc:75:simplemap_bitop$20058 $auto$simplemap.cc:38:simplemap_not$20154 $auto$ff.cc:266:slice$9184 $auto$alumacc.cc:485:replace_alu$4772.slice[4].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$12574 $auto$simplemap.cc:75:simplemap_bitop$20060 $auto$simplemap.cc:38:simplemap_not$19836 $auto$ff.cc:266:slice$9186 $auto$alumacc.cc:485:replace_alu$4772.slice[6].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$12598 $auto$simplemap.cc:126:simplemap_reduce$12590 $auto$simplemap.cc:126:simplemap_reduce$12575 $auto$simplemap.cc:75:simplemap_bitop$20062 $auto$simplemap.cc:38:simplemap_not$20158 $auto$ff.cc:266:slice$9188 $auto$alumacc.cc:485:replace_alu$4772.slice[8].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$12576 $auto$simplemap.cc:75:simplemap_bitop$20064 $auto$simplemap.cc:38:simplemap_not$20160 $auto$ff.cc:266:slice$9190 $auto$alumacc.cc:485:replace_alu$4772.slice[10].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$12591 $auto$simplemap.cc:126:simplemap_reduce$12577 $auto$simplemap.cc:75:simplemap_bitop$20065 $auto$simplemap.cc:38:simplemap_not$19841 $auto$ff.cc:266:slice$9191 $auto$simplemap.cc:75:simplemap_bitop$20067 $auto$simplemap.cc:38:simplemap_not$19843 $auto$ff.cc:266:slice$9193 $auto$alumacc.cc:485:replace_alu$4772.slice[12].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$12578 $auto$simplemap.cc:75:simplemap_bitop$20068 $auto$simplemap.cc:38:simplemap_not$19844 $auto$ff.cc:266:slice$9194 $auto$ff.cc:266:slice$9195 $auto$alumacc.cc:485:replace_alu$4772.slice[14].ccu2c_i $auto$simplemap.cc:75:simplemap_bitop$20070 $auto$simplemap.cc:38:simplemap_not$19846 $auto$ff.cc:266:slice$9196 $auto$alumacc.cc:485:replace_alu$4772.slice[16].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$12580 $auto$simplemap.cc:38:simplemap_not$19848 $auto$ff.cc:266:slice$9198 $auto$simplemap.cc:38:simplemap_not$19849 $auto$ff.cc:266:slice$9199 $auto$alumacc.cc:485:replace_alu$4772.slice[18].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$12593 $auto$simplemap.cc:126:simplemap_reduce$12581 $auto$simplemap.cc:38:simplemap_not$19850 $auto$ff.cc:266:slice$9200 $auto$simplemap.cc:38:simplemap_not$20171 $auto$ff.cc:266:slice$9201 $auto$alumacc.cc:485:replace_alu$4772.slice[20].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$12582 $auto$simplemap.cc:38:simplemap_not$19852 $auto$ff.cc:266:slice$9202 $auto$alumacc.cc:485:replace_alu$4772.slice[22].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$12600 $auto$simplemap.cc:126:simplemap_reduce$12594 $auto$simplemap.cc:126:simplemap_reduce$12583 $auto$simplemap.cc:38:simplemap_not$19853 $auto$ff.cc:266:slice$9203 $auto$alumacc.cc:485:replace_alu$4772.slice[24].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$12584 $auto$simplemap.cc:38:simplemap_not$20016 $auto$ff.cc:266:slice$9206 $auto$simplemap.cc:38:simplemap_not$19857 $auto$ff.cc:266:slice$9207 $auto$alumacc.cc:485:replace_alu$4772.slice[26].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$12595 $auto$simplemap.cc:126:simplemap_reduce$12585 $auto$simplemap.cc:38:simplemap_not$20018 $auto$ff.cc:266:slice$9208 $auto$simplemap.cc:38:simplemap_not$19859 $auto$ff.cc:266:slice$9209 $auto$simplemap.cc:38:simplemap_not$7666 $auto$alumacc.cc:485:replace_alu$4772.slice[30].ccu2c_i $auto$alumacc.cc:485:replace_alu$4772.slice[28].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$12604 $auto$simplemap.cc:126:simplemap_reduce$12601 $auto$simplemap.cc:126:simplemap_reduce$12596 $auto$simplemap.cc:126:simplemap_reduce$12586 $auto$simplemap.cc:38:simplemap_not$19860 $auto$ff.cc:266:slice$9210 $auto$simplemap.cc:126:simplemap_reduce$7902 $auto$simplemap.cc:75:simplemap_bitop$7355 $auto$simplemap.cc:126:simplemap_reduce$12606 $auto$simplemap.cc:126:simplemap_reduce$12603 $auto$simplemap.cc:126:simplemap_reduce$12599 $auto$simplemap.cc:126:simplemap_reduce$12592 $auto$simplemap.cc:126:simplemap_reduce$12579 $auto$simplemap.cc:75:simplemap_bitop$20069 $auto$simplemap.cc:38:simplemap_not$19845
Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$27577 $auto$simplemap.cc:267:simplemap_mux$17997 $auto$simplemap.cc:126:simplemap_reduce$17984 $auto$simplemap.cc:126:simplemap_reduce$17981 $auto$opt_expr.cc:613:replace_const_cells$27533 $auto$ff.cc:266:slice$9685 $auto$simplemap.cc:126:simplemap_reduce$9819 $auto$simplemap.cc:126:simplemap_reduce$9804 $auto$ff.cc:266:slice$9686 $auto$ff.cc:266:slice$9687 $auto$simplemap.cc:75:simplemap_bitop$17992 $auto$simplemap.cc:196:simplemap_lognot$9824 $auto$simplemap.cc:126:simplemap_reduce$9822 $auto$simplemap.cc:126:simplemap_reduce$9820 $auto$opt_expr.cc:613:replace_const_cells$27579 $auto$simplemap.cc:196:simplemap_lognot$9809 $auto$simplemap.cc:126:simplemap_reduce$9807 $auto$simplemap.cc:126:simplemap_reduce$9805 $auto$ff.cc:266:slice$9688 $auto$simplemap.cc:126:simplemap_reduce$8119 $auto$simplemap.cc:126:simplemap_reduce$8117 $auto$simplemap.cc:225:simplemap_logbin$9750 $auto$simplemap.cc:196:simplemap_lognot$9760 $auto$simplemap.cc:126:simplemap_reduce$9758 $auto$opt_expr.cc:613:replace_const_cells$27581 $auto$simplemap.cc:267:simplemap_mux$17996 $auto$simplemap.cc:126:simplemap_reduce$17989 $auto$simplemap.cc:126:simplemap_reduce$17986 $auto$simplemap.cc:75:simplemap_bitop$17994 $auto$simplemap.cc:267:simplemap_mux$9791 $auto$simplemap.cc:225:simplemap_logbin$9794
Found an SCC: $auto$opt_expr.cc:613:replace_const_cells$27583 $auto$ff.cc:266:slice$9689 $auto$simplemap.cc:126:simplemap_reduce$9839 $auto$ff.cc:266:slice$9690 $auto$ff.cc:266:slice$9694 $auto$simplemap.cc:126:simplemap_reduce$9841 $auto$simplemap.cc:38:simplemap_not$17408 $auto$ff.cc:266:slice$9693 $auto$simplemap.cc:38:simplemap_not$17407 $auto$ff.cc:266:slice$9692 $auto$simplemap.cc:126:simplemap_reduce$9840 $auto$ff.cc:266:slice$9691 $auto$simplemap.cc:38:simplemap_not$17410 $auto$ff.cc:266:slice$9695 $auto$simplemap.cc:126:simplemap_reduce$9845 $auto$simplemap.cc:126:simplemap_reduce$9842 $auto$simplemap.cc:38:simplemap_not$17411 $auto$ff.cc:266:slice$9696 $auto$ff.cc:266:slice$9697 $auto$simplemap.cc:126:simplemap_reduce$8113 $auto$simplemap.cc:196:simplemap_lognot$9851 $auto$simplemap.cc:126:simplemap_reduce$9849 $auto$simplemap.cc:126:simplemap_reduce$9847 $auto$simplemap.cc:126:simplemap_reduce$9844
Found an SCC: $auto$simplemap.cc:38:simplemap_not$18692 $auto$ff.cc:266:slice$9545 $auto$simplemap.cc:126:simplemap_reduce$9640 $auto$simplemap.cc:126:simplemap_reduce$9667 $auto$ff.cc:266:slice$9546 $auto$simplemap.cc:38:simplemap_not$18694 $auto$ff.cc:266:slice$9547 $auto$simplemap.cc:126:simplemap_reduce$9645 $auto$simplemap.cc:126:simplemap_reduce$9641 $auto$simplemap.cc:126:simplemap_reduce$9672 $auto$simplemap.cc:126:simplemap_reduce$9668 $auto$simplemap.cc:38:simplemap_not$18695 $auto$ff.cc:266:slice$9548 $auto$simplemap.cc:38:simplemap_not$18696 $auto$ff.cc:266:slice$9549 $auto$simplemap.cc:126:simplemap_reduce$9669 $auto$simplemap.cc:126:simplemap_reduce$9642 $auto$simplemap.cc:38:simplemap_not$18697 $auto$ff.cc:266:slice$9550 $auto$simplemap.cc:38:simplemap_not$18698 $auto$ff.cc:266:slice$9551 $auto$simplemap.cc:126:simplemap_reduce$9646 $auto$simplemap.cc:126:simplemap_reduce$9643 $auto$simplemap.cc:126:simplemap_reduce$9675 $auto$simplemap.cc:126:simplemap_reduce$9673 $auto$simplemap.cc:126:simplemap_reduce$9670 $auto$opt_expr.cc:613:replace_const_cells$27537 $auto$ff.cc:266:slice$9552 $auto$simplemap.cc:196:simplemap_lognot$9679 $auto$simplemap.cc:126:simplemap_reduce$9677 $auto$ff.cc:266:slice$9553 $auto$simplemap.cc:167:logic_reduce$8125 $auto$simplemap.cc:225:simplemap_logbin$9624 $auto$simplemap.cc:225:simplemap_logbin$9625 $auto$simplemap.cc:196:simplemap_lognot$9652 $auto$simplemap.cc:126:simplemap_reduce$9650 $auto$simplemap.cc:126:simplemap_reduce$9648
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$8086 $auto$simplemap.cc:126:simplemap_reduce$7913 $auto$simplemap.cc:126:simplemap_reduce$8079 $auto$simplemap.cc:126:simplemap_reduce$8077 $auto$simplemap.cc:126:simplemap_reduce$8040 $auto$simplemap.cc:126:simplemap_reduce$8038 $auto$opt_expr.cc:613:replace_const_cells$28035 $auto$opt_expr.cc:613:replace_const_cells$27839 $auto$ff.cc:266:slice$12983 $auto$dfflegalize.cc:941:flip_pol$28175 $auto$ff.cc:485:convert_ce_over_srst$28173 $auto$simplemap.cc:126:simplemap_reduce$8855 $auto$ff.cc:266:slice$12984 $auto$dfflegalize.cc:941:flip_pol$28179 $auto$ff.cc:485:convert_ce_over_srst$28177 $auto$ff.cc:266:slice$12985 $auto$dfflegalize.cc:941:flip_pol$28183 $auto$ff.cc:485:convert_ce_over_srst$28181 $auto$simplemap.cc:126:simplemap_reduce$7917 $auto$simplemap.cc:126:simplemap_reduce$7915 $auto$simplemap.cc:126:simplemap_reduce$7912 $auto$simplemap.cc:126:simplemap_reduce$8047 $auto$simplemap.cc:126:simplemap_reduce$8857
Found an SCC: $auto$simplemap.cc:38:simplemap_not$18709 $auto$simplemap.cc:126:simplemap_reduce$6310 $auto$simplemap.cc:38:simplemap_not$18710 $auto$ff.cc:266:slice$9215 $auto$ff.cc:479:convert_ce_over_srst$28253 $auto$simplemap.cc:38:simplemap_not$18712 $auto$ff.cc:266:slice$9217 $auto$ff.cc:479:convert_ce_over_srst$28257 $auto$simplemap.cc:126:simplemap_reduce$6314 $auto$simplemap.cc:126:simplemap_reduce$6311 $auto$ff.cc:266:slice$9216 $auto$ff.cc:479:convert_ce_over_srst$28255 $auto$simplemap.cc:38:simplemap_not$18714 $auto$ff.cc:266:slice$9219 $auto$ff.cc:479:convert_ce_over_srst$28261 $auto$simplemap.cc:126:simplemap_reduce$7784 $auto$simplemap.cc:126:simplemap_reduce$6316 $auto$simplemap.cc:126:simplemap_reduce$6312 $auto$ff.cc:266:slice$9218 $auto$ff.cc:479:convert_ce_over_srst$28259 $auto$simplemap.cc:126:simplemap_reduce$7755 $auto$simplemap.cc:38:simplemap_not$6308 $auto$simplemap.cc:75:simplemap_bitop$6306 $auto$simplemap.cc:38:simplemap_not$6307 $auto$alumacc.cc:485:replace_alu$4818.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$4818.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$4818.slice[0].ccu2c_i $auto$ff.cc:266:slice$9214 $auto$ff.cc:479:convert_ce_over_srst$28251 $auto$simplemap.cc:126:simplemap_reduce$7768 $auto$simplemap.cc:126:simplemap_reduce$7766 $auto$simplemap.cc:126:simplemap_reduce$7787 $auto$simplemap.cc:126:simplemap_reduce$7785
Found 7 SCCs in module top.
Found 7 SCCs.

24.42.14. Executing ABC9_OPS pass (helper functions for ABC9).

24.42.15. Executing PROC pass (convert processes to netlists).

24.42.15.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

24.42.15.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

24.42.15.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

24.42.15.4. Executing PROC_INIT pass (extract init attributes).

24.42.15.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.15.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

24.42.15.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

24.42.15.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.15.9. Executing PROC_DFF pass (convert process syncs to FFs).

24.42.15.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.15.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

24.42.15.12. Executing OPT_EXPR pass (perform const folding).

24.42.16. Executing TECHMAP pass (map to technology primitives).

24.42.16.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

24.42.16.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~180 debug messages>

24.42.17. Executing OPT pass (performing simple optimizations).

24.42.17.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.
Optimizing module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.
Optimizing module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.
Optimizing module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.
Optimizing module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.
Optimizing module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.
Optimizing module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.
Optimizing module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.

24.42.17.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

24.42.17.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

24.42.17.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.
Performed a total of 0 changes.

24.42.17.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

24.42.17.6. Executing OPT_DFF pass (perform DFF optimizations).

24.42.17.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4..

24.42.17.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.
Optimizing module $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.
Optimizing module $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.
Optimizing module $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.
Optimizing module $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.
Optimizing module $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Optimizing module $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.

24.42.17.9. Finished OPT passes. (There is nothing left to do.)

24.42.18. Executing TECHMAP pass (map to technology primitives).

24.42.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

24.42.18.2. Continuing TECHMAP pass.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4 for cells of type $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.
Using template $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4 for cells of type $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.
Using template $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4 for cells of type $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.
Using template $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4 for cells of type $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.
Using template $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4 for cells of type $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4 for cells of type $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.
Using template $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4 for cells of type $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.
Using template $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4 for cells of type $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~320 debug messages>

24.42.19. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

24.42.20. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

24.42.21. Executing ABC9_OPS pass (helper functions for ABC9).

24.42.22. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

24.42.23. Executing TECHMAP pass (map to technology primitives).

24.42.23.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

24.42.23.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $and.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~219 debug messages>

24.42.24. Executing OPT pass (performing simple optimizations).

24.42.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~18 debug messages>

24.42.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

24.42.24.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

24.42.24.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

24.42.24.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

24.42.24.6. Executing OPT_DFF pass (perform DFF optimizations).

24.42.24.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

24.42.24.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

24.42.24.9. Rerunning OPT passes. (Maybe there is more to do..)

24.42.24.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

24.42.24.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

24.42.24.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

24.42.24.13. Executing OPT_DFF pass (perform DFF optimizations).

24.42.24.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

24.42.24.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

24.42.24.16. Finished OPT passes. (There is nothing left to do.)

24.42.25. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

24.42.26. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 5024 cells with 30082 new cells, skipped 4115 cells.
  replaced 4 cell types:
    1690 $_OR_
     171 $_XOR_
       4 $_ORNOT_
    3159 $_MUX_
  not replaced 28 cell types:
      33 $scopeinfo
     513 $_NOT_
    1225 $_AND_
       6 $_TBUF_
    1352 TRELLIS_FF
       4 MULT18X18D
       1 $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4
       1 $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4
       1 $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4
       1 $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4
       1 $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4
       1 $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4
      24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4
       1 $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4
     365 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
       1 $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4_$abc9_byp
       1 $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4_$abc9_byp
       1 $__ABC9_SCC_BREAKER
       1 $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4_$abc9_byp
     276 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
      24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4
     276 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4

24.42.26.1. Executing ABC9_OPS pass (helper functions for ABC9).

24.42.26.2. Executing ABC9_OPS pass (helper functions for ABC9).

24.42.26.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 12909 AND gates and 37581 wires from module `top' to a netlist network with 2728 inputs and 1324 outputs.

24.42.26.4. Executing ABC9_EXE pass (technology mapping using ABC9).

24.42.26.5. Executing ABC9.
read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1317.090 ; gain = 0.023 ; free physical = 2813 ; free virtual = 27198
# read_verilog ../../debug/reset.v
# read_verilog ../../src/core/alu_control.v
# read_verilog ../../src/core/alu.v
# read_verilog ../../src/core/control_unit.v
# read_verilog ../../src/core/core.v
# read_verilog ../../src/core/immediate_generator.v
# read_verilog ../../src/core/mux.v
# read_verilog ../../src/core/pc.v
# read_verilog ../../src/core/registers.v
# read_verilog ../../src/core/csr_unit.v
# read_verilog ../../src/core/mdu.v
# read_verilog ../../src/peripheral/bus.v
# read_verilog ../../src/peripheral/gpio.v
# read_verilog ../../src/peripheral/gpios.v
# read_verilog ../../src/peripheral/leds.v
# read_verilog ../../src/peripheral/memory.v
# read_verilog ../../src/peripheral/soc.v
# read_verilog ../../src/peripheral/uart_rx.v
# read_verilog ../../src/peripheral/uart_tx.v
# read_verilog ../../src/peripheral/uart.v
# read_verilog ../../src/peripheral/fifo.v
# read_verilog ../../src/peripheral/pwm.v
# read_xdc "digilent_nexys4_ddr.xdc"
# set_property PROCESSING_ORDER EARLY [get_files digilent_nexys4_ddr.xdc]
# synth_design -top "top" -part "xc7a100tcsg324-1"
Command: synth_design -top top -part xc7a100tcsg324-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   2728/   1324  and =   11344  lev =   54 (2.90)  mem = 0.32 MB  box = 673  bb = 308
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   2728/   1324  and =   14961  lev =   57 (2.60)  mem = 0.35 MB  ch = 1703  box = 657  bb = 308
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   64. Obj =  148. Set =  672. CutMin = no
ABC: Node =   14961.  Ch =  1505.  Total mem =    4.21 MB. Peak cut mem =    0.26 MB.
ABC: P:  Del = 6432.00.  Ar =   16414.0.  Edge =    18372.  Cut =   191046.  T =     0.05 sec
ABC: P:  Del = 6406.00.  Ar =   16391.0.  Edge =    18192.  Cut =   187993.  T =     0.05 sec
ABC: P:  Del = 6406.00.  Ar =    8184.0.  Edge =    14756.  Cut =   435438.  T =     0.10 sec
ABC: F:  Del = 6406.00.  Ar =    5588.0.  Edge =    12657.  Cut =   325269.  T =     0.08 sec
ABC: A:  Del = 6406.00.  Ar =    5138.0.  Edge =    12006.  Cut =   320616.  T =     0.12 sec
ABC: A:  Del = 6406.00.  Ar =    5096.0.  Edge =    11961.  Cut =   315980.  T =     0.12 sec
ABC: Total time =     0.53 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   2728/   1324  and =   11677  lev =   40 (2.69)  mem = 0.32 MB  box = 657  bb = 308
ABC: Mapping (K=7)  :  lut =   2959  edge =   11353  lev =   13 (1.35)  Boxes are not in a topological order. Switching to level computation without boxes.
ABC: levB =   40  mem = 0.16 MB
ABC: LUT = 2959 : 2=319 10.8 %  3=830 28.1 %  4=1192 40.3 %  5=372 12.6 %  6=125 4.2 %  7=121 4.1 %  Ave = 3.84
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 8.01 seconds, total: 8.01 seconds

24.42.26.6. Executing AIGER frontend.
<suppressed ~8132 debug messages>
Removed 17304 unused cells and 31107 unused wires.

24.42.26.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     2988
ABC RESULTS:   $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells:       24
ABC RESULTS:   $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      349
ABC RESULTS:   $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4_$abc9_byp cells:        1
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:      276
ABC RESULTS:           input signals:      379
ABC RESULTS:          output signals:      250
Removing temp directory.

24.42.27. Executing TECHMAP pass (map to technology primitives).

24.42.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

24.42.27.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4 for cells of type $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4.
Using template $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4 for cells of type $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4.
Using template $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4 for cells of type $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4.
Using template $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4 for cells of type $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4.
Using template $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4 for cells of type $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4.
Using template $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4 for cells of type $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4.
Using template $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4 for cells of type $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4.
Using template $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4 for cells of type $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000111 for cells of type $__ABC9_SCC_BREAKER.
Using template $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$8fd90a9843c1ebd464d623394a8546af0238d84f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$b5af9a4586394b5542876148a89e2ec15fcfdd8a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$81720c82951ad72695c5caa9664f598362b55926\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$56712f8e75ef0b0874b9ca97f052a19395bc337a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$fb09305024ac07ff280d02ac90b581e1f3d3f3aa\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$85e1e7a02808ee6d40b8f633df090d29b38bc23e\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$ad0731c0f0cf4952a70086e24a4236c29fdb7161\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$0faf8afd50206cdaba8fc8c9c51aa0d60574416d\TRELLIS_DPR16X4_$abc9_byp.
No more expansions possible.
<suppressed ~1003 debug messages>
Removed 262 unused cells and 44491 unused wires.

24.43. Executing TECHMAP pass (map to technology primitives).

24.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

24.43.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$0dfe1a193e0a40c1376707c24f386773e3910cd7\$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod$f0169807cabb208126f94e3f71552cc012e8013f\$lut for cells of type $lut.
Using template $paramod$540d19b8a46cefa2c5fb0babb817359ee295fdd5\$lut for cells of type $lut.
Using template $paramod$94e65f323749ab2f501acf5577af42456678fff9\$lut for cells of type $lut.
Using template $paramod$b2a4860cd839ff40d9dca4c3f237b2b534267028\$lut for cells of type $lut.
Using template $paramod$bebc08b7465b8896e6f80b8ab858cd26f641bd39\$lut for cells of type $lut.
Using template $paramod$c5755466cc3efcd078262908b682d3435e3d1d82\$lut for cells of type $lut.
Using template $paramod$2dcbf4e07dd8c2636394980a9554b6e2f560e39c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101100 for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod$6e2b27a23561eba4d5d7a3612a01502854865858\$lut for cells of type $lut.
Using template $paramod$7d813eb49700f971f2635a434700eafdfa816bc3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$737669e4d3be4811bcf223101039449bd6e24467\$lut for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$32ccf65669c41e1e3bce1f16051f6d60ad96a2a0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut.
Using template $paramod$e8e38e13ba4ca36ee2f40f244789338dfa28acd1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011011 for cells of type $lut.
Using template $paramod$4313d6a4df5be8d101d4989de89eeec5b7d9f7b3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001011 for cells of type $lut.
Using template $paramod$de34f9bb0aa4b481098a4e38274bee7a6371d23a\$lut for cells of type $lut.
Using template $paramod$a8b7516c4ccadf4ab65906113028f2819d14ea8b\$lut for cells of type $lut.
Using template $paramod$2138947395b2081ed6e6597ce583b805b4f2fc75\$lut for cells of type $lut.
Using template $paramod$3c6be0cecca529b904c273ae6983e0f6d0361b11\$lut for cells of type $lut.
Using template $paramod$a743caf801766df40bcc22d49baa12a0bdc2f7fe\$lut for cells of type $lut.
Using template $paramod$8233fe5f3e32016e38f9f385f1fbeb88df751ed2\$lut for cells of type $lut.
Using template $paramod$8e1c82b304528085a78e4651c993ce9e1ef6b8a8\$lut for cells of type $lut.
Using template $paramod$bd57e9718a938c253993cb582d13218a9bcdcc54\$lut for cells of type $lut.
Using template $paramod$774a669204184147b38453b69c15da44a7cf748f\$lut for cells of type $lut.
Using template $paramod$835b481f851e62d27eb3f60e4771d55796942207\$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$5636998c7ce0b77a9e79012d4ef0c6d0a5a30e63\$lut for cells of type $lut.
Using template $paramod$7dca9f8a3e3d13833f0e6f1f02c05f0cba7a9a17\$lut for cells of type $lut.
Using template $paramod$bce98cbc4c7663d9534fcdf870483176065e0cfd\$lut for cells of type $lut.
Using template $paramod$03d0edf20ed1469b09ef5ea8e93986bf65c1867c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut.
Using template $paramod$7d86cbfaf200534c9fc4c863ebd2a8e9b34551b6\$lut for cells of type $lut.
Using template $paramod$342f1a76116d85ff17dbf486d865971fee6e955b\$lut for cells of type $lut.
Using template $paramod$b7046219cb4ceb512f59177dcf9f721c6bf8e2c3\$lut for cells of type $lut.
Using template $paramod$89f931611b66d827751f4a175a88569d5ab95376\$lut for cells of type $lut.
Using template $paramod$df5c8730c0a53792c3f54c2192a2221c27162fb5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$853b4c6d2cbefecad1316f73097bd72762fc43dd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$e412821338883e25f2e0d1a1d7fada158db69807\$lut for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut.
Using template $paramod$723be7177967d6866729df0ff463a602326a012e\$lut for cells of type $lut.
Using template $paramod$e2d13deaea8911100bb4f3c8af62f0b0ca2b4044\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$90dc599eed99da511e64ad217d69e7ff2c1e56cc\$lut for cells of type $lut.
Using template $paramod$5bdbbec36fe77f90500afb20f840bbbccf30a64e\$lut for cells of type $lut.
Using template $paramod$b68f9800cc1bf69afcfbc0567a25e43ebb01456c\$lut for cells of type $lut.
Using template $paramod$fbe3cb36e6cf24e42c140dad774695563e8b22d3\$lut for cells of type $lut.
Using template $paramod$cae45ff85b946d8cfe295bf4feda7db55ee71cea\$lut for cells of type $lut.
Using template $paramod$076deb7b432146fc56a2825020bc1b0504424a0f\$lut for cells of type $lut.
Using template $paramod$962b32d6c48ce9d245414172303bd8634ead6fab\$lut for cells of type $lut.
Using template $paramod$06e62c2045624c211a1abe4f2f36c8f22c688165\$lut for cells of type $lut.
Using template $paramod$1520b17247d5638c980af75a2ba3c0f9181105fe\$lut for cells of type $lut.
Using template $paramod$019daefcfb7e318edf028205b2bc9f676830766f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$96b088f55147e51e15ebfdcc7ca196b1bf514682\$lut for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut.
Using template $paramod$13dda25c6fcabb2c55db381a9dd85838fab0d63d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$abe95135649ff5332de374c6105b4d038a55882e\$lut for cells of type $lut.
Using template $paramod$d968e199ea396ec1669d272dadc967f3acfb80d5\$lut for cells of type $lut.
Using template $paramod$8d58c55d26490b5a99a369b5eb692d6122da9b60\$lut for cells of type $lut.
Using template $paramod$fde0101c87c794ccc02d9979638c7a9059f028ed\$lut for cells of type $lut.
Using template $paramod$01a2a62f8da18d4d07e2597d37a4b66d2b9bd228\$lut for cells of type $lut.
Using template $paramod$ad2c9f917ceac5bee50f5b12dcece0384b50f01d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$2294fd4459ef7d3b9af2d4a92528152f68757ad6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$fd612331c30e9d253090fdb1f8a32e43d927e731\$lut for cells of type $lut.
Using template $paramod$2844c7fef2a755a9af80c70990cd830291c4b71c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
Using template $paramod$3ceaaffe10e9f5053ae0fa08a67977d5e6337e7a\$lut for cells of type $lut.
Using template $paramod$28e08275c4793a5f7489ab05693de1f9d34a6c04\$lut for cells of type $lut.
Using template $paramod$ffcae1903fb2f26c23e35bb21442fbfeaf399890\$lut for cells of type $lut.
Using template $paramod$166cf715efc1df7067d016845ac3b08a3b3bfe5f\$lut for cells of type $lut.
Using template $paramod$d345781bc5d014060901f9e4c645b8d136f2a9c6\$lut for cells of type $lut.
Using template $paramod$70a934594406e8042bf2854c778fef542ef3ea5f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut.
Using template $paramod$c8f2b00a2feb859040935d06cafa51f6c4e20e0d\$lut for cells of type $lut.
Using template $paramod$de81bb4f24bddd9c01fb4a8d2c0db4e04ac2517e\$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$bde6c96e44b0f8e6d9db97eafdf28d77ceaa9a96\$lut for cells of type $lut.
Using template $paramod$a977fb3a4e30b200887394f8ff6c3df1befab9e3\$lut for cells of type $lut.
Using template $paramod$8160b8b9be4f6f305fbbdb593e4fbe32f3279c17\$lut for cells of type $lut.
Using template $paramod$5ff5c25c21f250f782a91d9433493387f404c6b8\$lut for cells of type $lut.
Using template $paramod$e2d4399e1e149b2bd3c04b32fc0d847bb8cdd6d6\$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod$d99a5f38831281ff4d02067d2eb0a956cb6f0120\$lut for cells of type $lut.
Using template $paramod$8a4588d24f9055f225ea56296a16276f3c824f54\$lut for cells of type $lut.
Using template $paramod$efd9db50f639c84b61057002b4119366b96c7abc\$lut for cells of type $lut.
Using template $paramod$ee3ba3939f6ccdb74bf420a252d58cdb86511937\$lut for cells of type $lut.
Using template $paramod$d315acbf930db7c20b3f4ac2dad3b7982b1f437c\$lut for cells of type $lut.
Using template $paramod$b6ebb0ea1200440e9f4d8451077c5efc796eb6bd\$lut for cells of type $lut.
Using template $paramod$8e2df60c6f844bb7122d00d18b4cc43e25eb4771\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$75666cd83f95cd3810dc34cfd303359c5f9c7bb4\$lut for cells of type $lut.
Using template $paramod$5bb6a3df4fcc48a307e6c6fd696456991f75487c\$lut for cells of type $lut.
Using template $paramod$2f715f5f333c8e8372874266dfef80384a9a4c10\$lut for cells of type $lut.
Using template $paramod$15850479ec8ad93e51479d70a228b15a822f3e2c\$lut for cells of type $lut.
Using template $paramod$38f9bf4dd2329347b8471f0a98443dd323386889\$lut for cells of type $lut.
Using template $paramod$ab7968dc0deaf99544ed4774ce8516eecd11ba1f\$lut for cells of type $lut.
Using template $paramod$406d62d1f3dea075f0fc8200672d85f94103d6b7\$lut for cells of type $lut.
Using template $paramod$874cfa5b80795dcb7c9fbf871ac1d8bdde4cb3d5\$lut for cells of type $lut.
Using template $paramod$babcaa27092cf78ca2016504379310fd6371f266\$lut for cells of type $lut.
Using template $paramod$6e46ec5a196ba1a24b8e69ab094cadc07c13ac1f\$lut for cells of type $lut.
Using template $paramod$503642b774ee08bb41ecbaafd3014c92ad9a6dae\$lut for cells of type $lut.
Using template $paramod$7e8fe64f22f1153a85bf31be98f3c990173d62ab\$lut for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$5a9973bc41def5ddf5b821420b2173a81b5efedb\$lut for cells of type $lut.
Using template $paramod$8feda2504ab37188ca041e37a96d51463bbecb45\$lut for cells of type $lut.
Using template $paramod$1333509391d9b66ea02c66f38ba188494775d191\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut.
Using template $paramod$acd43fba7f71b1295de78a2178234108f5c1feb6\$lut for cells of type $lut.
Using template $paramod$3b6ecab74560aa8f610963334a1381ed8cc4368d\$lut for cells of type $lut.
Using template $paramod$fba030b6f83d058f4eabda3719de30e5e245df39\$lut for cells of type $lut.
Using template $paramod$de8f8bba29d56316e95e77d4f2a0bc9ef73137bb\$lut for cells of type $lut.
Using template $paramod$5c3294d2efb88caf0474e72690e5c12ab871a3e8\$lut for cells of type $lut.
Using template $paramod$f7a16dfaec1d0d41c14e9d315873632f27b128eb\$lut for cells of type $lut.
Using template $paramod$db182247f849d4acf975f76879bc452bd225bb7c\$lut for cells of type $lut.
Using template $paramod$e590b9fb2eeda322debdb6a1dd18102c5ff35ddb\$lut for cells of type $lut.
Using template $paramod$97c5c4b22f8240a6fdaefd8f505e60d1ab0a1b07\$lut for cells of type $lut.
Using template $paramod$525425bfbe66d72ee88210d059d9a74f55ab8de8\$lut for cells of type $lut.
Using template $paramod$b744b4ecb2239836de672ec87e48bc796cf5da74\$lut for cells of type $lut.
Using template $paramod$62540f7fc73ef960ad3cd7745e860db515ae2ff9\$lut for cells of type $lut.
Using template $paramod$56166b373c73de694681c59ec29fd14c6b1016f8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$2014354416722209de7d48370ab008bc2278a034\$lut for cells of type $lut.
Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut.
Using template $paramod$497aa714ffa399423aed5fe789a8dd35df92638a\$lut for cells of type $lut.
Using template $paramod$d42b0de8b4a3e9906fa9d6ab621f01c51d52572a\$lut for cells of type $lut.
Using template $paramod$b55f45c6dc20e6c434e3ecfaac16a92e424cd4fe\$lut for cells of type $lut.
Using template $paramod$6062f7468cb0d137245b1f91bde8fe33780013f3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$51e6c0517d4da635b640734443ea7c582ee57165\$lut for cells of type $lut.
Using template $paramod$7d9ccb70889bd157510cb44f0d9d8a7e9be87b39\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$1843b3c15f2447d117e2d5de9b00f791ef5f9fa3\$lut for cells of type $lut.
Using template $paramod$7ed3d685a887e531dc8f4f21b9907d4766cf861f\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod$d646cd5cb36fb1f9dd2b06f584b3b88b2dec1d24\$lut for cells of type $lut.
Using template $paramod$bff60da521de773f8caf46fbc0845c3d7d3e2310\$lut for cells of type $lut.
Using template $paramod$d25a0f1ed4a99ef8d1bf6a91b3015ece3e01714b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut.
Using template $paramod$c958b3a888f937f082b94811ff62d71e32a2b4eb\$lut for cells of type $lut.
Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut.
Using template $paramod$8fd8efe0a495790cc9ddc97266933ea8a8cd7b45\$lut for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d\$lut for cells of type $lut.
Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$059968be1ef12c596bb5d360a749040b6777bf4a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e\$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$651e836885d95717c36e69441422c3fe04ee5f4d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut.
Using template $paramod$c9d86860d7b8a94fe4e147db4941c14e73dd3281\$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$f58e0d90afc57a738914697b6a4a7319b30d7e7e\$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod$fa45f28daf300aaa781ee4b9baa5ce968b1d8c66\$lut for cells of type $lut.
Using template $paramod$eeed37ce45abdda29d3e180f2d1dfc0c4c376530\$lut for cells of type $lut.
Using template $paramod$2c959eb814502b813fb2b3a30c8dfa8d0f5741f3\$lut for cells of type $lut.
Using template $paramod$aee61336c998922527dbf4df290a5deadf0b50fb\$lut for cells of type $lut.
Using template $paramod$0c822c65361ce832091b6c90f1a02f1ee0b109d4\$lut for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$d35161d1d7976dcc02e7c7d51172431be85143b4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010011 for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut.
Using template $paramod$1f313f85ef575d13bac75382f04905a8c8be8f57\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut.
Using template $paramod$9506ecf18c91672f3dae4008b6ad1f2863e8019f\$lut for cells of type $lut.
Using template $paramod$a76afe794e55ba422468b9db09d48da3f250b812\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$0fcb06ed76df01e8d45bc2b9e6c8a9b43fa42cb4\$lut for cells of type $lut.
Using template $paramod$63114da772fb28945ba24699e32f1e30ca7142f4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$5307f40f1b453046eb68ee1a10c3f82d605af6fc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod$6e4a86e6f1a5dc8f826898a131e83cdba4a4fc9e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod$a9ba23df824f693c44e722629fd8c1fae157385c\$lut for cells of type $lut.
Using template $paramod$7a0b348a7069d0c8f44afe945e212fcf3f3fd64c\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$feac1814a13647ff95d85e23385825c648d6c2ee\$lut for cells of type $lut.
Using template $paramod$64b84593fae19d6c4d7d26333a195e5cc6b30160\$lut for cells of type $lut.
Using template $paramod$338ce46cf7ff44b9974887dd2adee6c4e0530bed\$lut for cells of type $lut.
Using template $paramod$5348912da867a611a8088b6b8b27a62d65f1de6e\$lut for cells of type $lut.
Using template $paramod$a197ef6f3b51d411ae3e5b42b5d77a606c4fb11a\$lut for cells of type $lut.
Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut.
Using template $paramod$20235ca863361fbc253329cfc7eeea38c77404dc\$lut for cells of type $lut.
Using template $paramod$b600d182ae966d09f33a746441e104587fe7a58f\$lut for cells of type $lut.
Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut.
Using template $paramod$55290dc5b2d325b1a51b6c31876bbb759b0b4b79\$lut for cells of type $lut.
Using template $paramod$ee4719be90cb5e99ba51526a9f283fc572670293\$lut for cells of type $lut.
Using template $paramod$02e55836878a22873310c70e8a2ed14028fabfa5\$lut for cells of type $lut.
Using template $paramod$151cc61869e7cf4cf4bd07f6ebd8187604529cbc\$lut for cells of type $lut.
Using template $paramod$82687d3ad8130b5b49618b6a28f43c60b5130fe1\$lut for cells of type $lut.
Using template $paramod$156b067f9bd478768e9418f40b1597d24cee101b\$lut for cells of type $lut.
Using template $paramod$a48d96b3084901aac1f541d9be59ab6aad37df36\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
Using template $paramod$3f943b31daf852ed1ca222e5bb6488e4bbd6a0e6\$lut for cells of type $lut.
Using template $paramod$77b67ef20c955093353b18505577135db4a47988\$lut for cells of type $lut.
Using template $paramod$53ddb29e3b4b1f0a9210442a4e1d15cfdfbdc0ac\$lut for cells of type $lut.
Using template $paramod$423c1d3c85f1527f1b13840e7aac96070793abe0\$lut for cells of type $lut.
Using template $paramod$345e594e3e86fb5714f53304e99d8ef40a9499ad\$lut for cells of type $lut.
Using template $paramod$f672f1e5ea7eaf40630014635549af40fc023a51\$lut for cells of type $lut.
Using template $paramod$3e63470ea7a06b3eefdfb990254dd83d20fa13a7\$lut for cells of type $lut.
Using template $paramod$058a3c6c4a5973a6fa96322456e9fa0d3a1a38f6\$lut for cells of type $lut.
Using template $paramod$ebeb8e2b4db1d7c1c5771b9a4a1376b3c1ee7d3f\$lut for cells of type $lut.
Using template $paramod$d00f0d70a5a1199f4fe71b0baac412e2ff160d49\$lut for cells of type $lut.
Using template $paramod$c1bb015410c86d2840a6d1c937ecbbb24411f5ad\$lut for cells of type $lut.
Using template $paramod$819d4a515bc522124fe57d9a79ba264b48fb5794\$lut for cells of type $lut.
Using template $paramod$8e55a9cca77fc533dfed315558bf3940f6a7ff6b\$lut for cells of type $lut.
Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut.
Using template $paramod$b1241bb2f9028a57b5d511f41eb42255eb327e39\$lut for cells of type $lut.
Using template $paramod$27102b9cbeb32c3f0f3712aec95903cf8e16c53e\$lut for cells of type $lut.
Using template $paramod$cd05caaf261e4148f336c0ecc488c806e4433d99\$lut for cells of type $lut.
Using template $paramod$4f09540800ac966d6e31a7ccf5f32a559a8ce57a\$lut for cells of type $lut.
Using template $paramod$826d100c02a6a0812bdb18e359639bbc39e2fe3a\$lut for cells of type $lut.
Using template $paramod$793fc28cf61120083daef76d0ad6adfe307204e0\$lut for cells of type $lut.
Using template $paramod$80a3ad83b0cc21585fc9f61ce42c3a6c3efdaed2\$lut for cells of type $lut.
Using template $paramod$64c98a93c00f2932cdb01ce29e3a216b58ad51fe\$lut for cells of type $lut.
Using template $paramod$0086a2b7bdc8a5c0f6a4a9980bebe54b6094fcf9\$lut for cells of type $lut.
Using template $paramod$dc327062330ee79aecc5e2013660e3b5909921a1\$lut for cells of type $lut.
Using template $paramod$cc306551f2ef92af1bdf5e46abb2a1bb1e0c097c\$lut for cells of type $lut.
Using template $paramod$5289dac6f25369a9a495c69c724c25ee83ad0e78\$lut for cells of type $lut.
Using template $paramod$fd3ed3a223484aac184d1b7412ec4cfe4ca64c32\$lut for cells of type $lut.
Using template $paramod$e4b832d686d12318ec0715f027fe549b42e45c20\$lut for cells of type $lut.
Using template $paramod$52953750219effadf43093a566baf492fdd6b6c8\$lut for cells of type $lut.
Using template $paramod$cda77abd0958274040677353bd80a8ccf93def3e\$lut for cells of type $lut.
Using template $paramod$1c32560ec0c303e162cb9b2763509249559a7aaf\$lut for cells of type $lut.
Using template $paramod$26d876869d6ab003366d0470e095daef2ccfcbd7\$lut for cells of type $lut.
Using template $paramod$7dad2285b6a41fd718a0863efc009b14ae7d121a\$lut for cells of type $lut.
Using template $paramod$ac969d9398eb9421a30a342d303d11422783b5d2\$lut for cells of type $lut.
Using template $paramod$181733d3e31dcdcea8c52d0a4fc252b3aa453564\$lut for cells of type $lut.
Using template $paramod$e8ba44e4a3ee29c32776f6151b0293be3e5fa416\$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$93f1c54deb7807a91414920d43944a759a1a7e42\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut.
Using template $paramod$bea08a495d16293f8cc454a45845d26cde0762b6\$lut for cells of type $lut.
Using template $paramod$a670b08a47dd8a34f954c50cd06e9996d77e8467\$lut for cells of type $lut.
Using template $paramod$f5c5b56521a6811444a94cf8aec11258bf0a108d\$lut for cells of type $lut.
Using template $paramod$2649632427059f17a6997e51dd7f224fd1802b32\$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$a75fe1683a97958e61513f004cf91c3458c2f88e\$lut for cells of type $lut.
Using template $paramod$20f82dd03802038bc013e5804609eaebb5d257db\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
Using template $paramod$f3a9cb4a6dcd55c9015bfb659b637a7c07b996c0\$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut.
Using template $paramod$6fec0c69c74966bf6a58b2ea48b38192cd9a9b3a\$lut for cells of type $lut.
Using template $paramod$dc8eb389b2fc3ec6a78d93ff9b548b7fd27b6950\$lut for cells of type $lut.
Using template $paramod$984ca0c6352e12d6ffd84922066097b4751db8a6\$lut for cells of type $lut.
Using template $paramod$ede67ae6159d4864b11272c4fe0692c3419120cd\$lut for cells of type $lut.
Using template $paramod$6daddc933561edd888667575f3ac1ab3fee9d1a6\$lut for cells of type $lut.
Using template $paramod$97108e3cc0d0482a6e72e932e86430aa2177750b\$lut for cells of type $lut.
Using template $paramod$a8b2b0f3a3fd7b01c99e8d61bb72f602bd41af54\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10011100 for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
Using template $paramod$4524e782a2445e2755d4b27eb961b1f8898caa28\$lut for cells of type $lut.
Using template $paramod$a6b2d4693fada6bebbe4480262641915d709d280\$lut for cells of type $lut.
Using template $paramod$a05170b3f2d3fcb0bf88d37e810984e864962880\$lut for cells of type $lut.
Using template $paramod$d546db88fc169832512e499a9cdf9a41b89ab74e\$lut for cells of type $lut.
Using template $paramod$e15085f73db49a7ff8978584c77c14c5582438c2\$lut for cells of type $lut.
Using template $paramod$b4d0f4738a5ce50c7f36c2aa2ecc09cfb874f2b6\$lut for cells of type $lut.
Using template $paramod$9a383ca297ef012b6f33ce559547f89432250d88\$lut for cells of type $lut.
Using template $paramod$30caa5615ac52efdf43dfbf1b1a633232eb131b1\$lut for cells of type $lut.
Using template $paramod$413d040dcd860cd74ca61a70644516a95d328ae7\$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut.
Using template $paramod$beae4210b922fc9ba2fcc4008a7474b475e38c50\$lut for cells of type $lut.
Using template $paramod$c600b4b1adc22857e1c1ba3b6aeb516fabe09da0\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$0d4742cff20cb0e0e40b9af6c0257e3a276c0c2b\$lut for cells of type $lut.
Using template $paramod$a2024abf1a6d35bcb62c7cb6f3ec4a9a4c877d1d\$lut for cells of type $lut.
Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut.
Using template $paramod$44c0fe996e6f3f4ba8bae2e194245aa82c30fa47\$lut for cells of type $lut.
Using template $paramod$20ae971f03a8aabd14bc9c90601f9bed8100c9da\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$52acd744af558b1acd7f06b0e1d721506b042b9b\$lut for cells of type $lut.
Using template $paramod$92e85407afe4deea7d21f8df970bd67adaa57e19\$lut for cells of type $lut.
Using template $paramod$169e3ff199948acb6289d60ee69a6cbdb1d4057e\$lut for cells of type $lut.
Using template $paramod$47d363ae7b1a0e81207e02fe31af85b6bf36a2ac\$lut for cells of type $lut.
Using template $paramod$f7a897257decedfb6cc642e53d65fef7fc0df390\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$6b7c9c56fc2a32a479d463d5f3b0d3f4673b67f1\$lut for cells of type $lut.
Using template $paramod$7a73f9756d5c153bcd3667a54c2eeb22386fe779\$lut for cells of type $lut.
Using template $paramod$f109125ffdede8321ac65719b1066c75ff1eaef0\$lut for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut.
Using template $paramod$1a10df59f43f252ae2ee713b788731ad5d18c6f5\$lut for cells of type $lut.
Using template $paramod$c7017ce6f918370601990fdcd7ae7caf301de017\$lut for cells of type $lut.
Using template $paramod$da49ead6f31a43bab2d6c107c254e628a16f3330\$lut for cells of type $lut.
Using template $paramod$47a326ee296feaca60c97add5a2f7670de259bd9\$lut for cells of type $lut.
Using template $paramod$71039eaa750b63c13b47d102108a4d1b67d00b7c\$lut for cells of type $lut.
Using template $paramod$701bdd2a176f99a223efa70a10296db6cfa9e9ea\$lut for cells of type $lut.
Using template $paramod$3bb7b015790d2af03baf785d275cbd099cfe2c26\$lut for cells of type $lut.
Using template $paramod$409279b79277055c92c645b01c2deb7a6d1a6a87\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut.
Using template $paramod$5a2475f0ff8adfa6c48e46c1977dad3962daa33d\$lut for cells of type $lut.
Using template $paramod$41e5fb4b54b4882c2032553e433f0934b2710d7f\$lut for cells of type $lut.
Using template $paramod$57b0544f41a25c72a09d87f02afdb1a58250c2f7\$lut for cells of type $lut.
Using template $paramod$faf4b69e2195a9ce52b7c3bce83fa5ea343bc378\$lut for cells of type $lut.
Using template $paramod$1bdebc8ca51c9959207291a8b23284fd85b8c712\$lut for cells of type $lut.
Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707\$lut for cells of type $lut.
Using template $paramod$9f37a8bc96eb243b0046a932d032199006c99597\$lut for cells of type $lut.
Using template $paramod$5c32c59025c0b98f20e63f249d83e7ebb4b085e3\$lut for cells of type $lut.
Using template $paramod$af01034afe1bdbc87587d263805971d96e724ed7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod$f00c05041270394f87113db0be50ec9e2eaaa463\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut.
Using template $paramod$f6e4b9df06807cac5789d4518648b5ffebae2abf\$lut for cells of type $lut.
Using template $paramod$4d7f17f71543a1e7fc1835bd79c4827a43f2e844\$lut for cells of type $lut.
Using template $paramod$b0303f90d8bba91812b5ec0c0d88cce5f7058b25\$lut for cells of type $lut.
Using template $paramod$63b93fb099f48f0c09f0ff623677f8fb8aa6a591\$lut for cells of type $lut.
Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut.
Using template $paramod$12b93181fde40368887ce43b59fecaa09cb41fa7\$lut for cells of type $lut.
Using template $paramod$3a0a392069bc969f34c65c546a8c56fbbb67e282\$lut for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod$f25cfeb07793f4c9b87758158af8df76472138cf\$lut for cells of type $lut.
Using template $paramod$121599b3fbdeddaa7a6e475acb357ec6e605c151\$lut for cells of type $lut.
Using template $paramod$193d365ba3260f56de4ca734b1cedcf9dc72302b\$lut for cells of type $lut.
Using template $paramod$2c35b9f28f24ebda7f83478d571e81b467da1e5a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod$e5f53fb2cb3e702c9422ebddd3ba952e5a8f3401\$lut for cells of type $lut.
Using template $paramod$ec0594b0bfe148ce8b2de3de26a8c2f4fa6aba17\$lut for cells of type $lut.
Using template $paramod$437daf6001dfe62c64a2eeafc90fbbe8ac8aa10b\$lut for cells of type $lut.
Using template $paramod$a59854b679c443f21a6748ea460109b8241cb007\$lut for cells of type $lut.
Using template $paramod$8ae5e24171bca0b8d12d43741a6723f274290f92\$lut for cells of type $lut.
Using template $paramod$854ff015d7a74911eb1a429febd154d82349cce6\$lut for cells of type $lut.
Using template $paramod$6ce6c4dda5ce9efa48898d1f74f2fc04ce8cd8c5\$lut for cells of type $lut.
Using template $paramod$1bb26330f94b9f62b6acb8cc6af86c50c7c3906f\$lut for cells of type $lut.
Using template $paramod$4db3f0d067a6794efd5979ea33ffc0ce06e2e75c\$lut for cells of type $lut.
Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut.
Using template $paramod$9aba3ca4aa9e650a35f38a8d2fa20ec06fa72b4f\$lut for cells of type $lut.
Using template $paramod$f610396a8c1614f373f4d73e3d1e988bc93e396c\$lut for cells of type $lut.
Using template $paramod$2c59e7a1544bf28767105187ff4228811ca11188\$lut for cells of type $lut.
Using template $paramod$52fe991adab6b5954335e82cea7c40e1bf62bb83\$lut for cells of type $lut.
Using template $paramod$4c019fad677a6751d10c7683062ad8483ed51b71\$lut for cells of type $lut.
Using template $paramod$fce992df4978ad69e56d150579aa6ba47bc13a78\$lut for cells of type $lut.
Using template $paramod$b7685cb0c8a6753256bc84bc31d36a443c15fab7\$lut for cells of type $lut.
Using template $paramod$6831b9cef7a022e3f1f75ee9be876b0010a969bf\$lut for cells of type $lut.
Using template $paramod$4d7dc822e6ac78c7574e16060f5e26124cddca40\$lut for cells of type $lut.
Using template $paramod$cc0454b50e7a4bac6495b6e30a58ceb8dfd032c5\$lut for cells of type $lut.
Using template $paramod$18df3812bc12364e5ebcb6c3ed05c0294e4c26fc\$lut for cells of type $lut.
Using template $paramod$b10362b71f0fae22c5be855d27fcefe2e81551bf\$lut for cells of type $lut.
Using template $paramod$20ba583962918fa0136fc97b1558cc45cc91cc29\$lut for cells of type $lut.
Using template $paramod$f2972f00f781f1a033cecbb6cc420de13224764a\$lut for cells of type $lut.
Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut.
Using template $paramod$40350f819690aa4076e68bb97f929538214c76a7\$lut for cells of type $lut.
Using template $paramod$8384e66d408d22ab39dfb451efb7879731befeb8\$lut for cells of type $lut.
Using template $paramod$87e6e9473ffb0bf8a44e05d4dfdfaa6b36c50fee\$lut for cells of type $lut.
Using template $paramod$70f68cc10fbeada9b6fa90c3bb75475e348ca467\$lut for cells of type $lut.
Using template $paramod$0611a6f4596c6e7c8c64a645bcde93f7c0172cfe\$lut for cells of type $lut.
Using template $paramod$4658fedcd7ebe2858c93f54b88221dcf68c6bb6c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut.
Using template $paramod$6de442abe246ff8c0692702d40d84ce1c07479d9\$lut for cells of type $lut.
Using template $paramod$e7d64f726cdd332b51cd3c3817faf1fbe678944d\$lut for cells of type $lut.
Using template $paramod$1913d88eb5cc4b892aa05619194982a2263c7fe8\$lut for cells of type $lut.
Using template $paramod$28e055f3918a7bfe516a9785e5b7eac06b9939b6\$lut for cells of type $lut.
Using template $paramod$33e58adf67c6b686a154c9ce8ebbc4b04b8cabc5\$lut for cells of type $lut.
Using template $paramod$f94cf08026d21db794b98b1a8efaec5f34ff8975\$lut for cells of type $lut.
Using template $paramod$486e9253c65fbb8e04c0c19bc627fa9f3113c6b6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111011 for cells of type $lut.
Using template $paramod$e6373f95d94f09cf0da22adb8181976555d17288\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$50ec6039d9de561a6d0a8dc470847f22a306b04f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut.
Using template $paramod$4721519bef85e75f87d1f147d88c627c84abf942\$lut for cells of type $lut.
Using template $paramod$127c0f065cbdbfc01465fd58161d13b20251be83\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$223a1a0bfc3038108c8c5d096bc8fdc50fd540b0\$lut for cells of type $lut.
Using template $paramod$5cef017bac3ee3544d8521a777289133d35cb88c\$lut for cells of type $lut.
Using template $paramod$66a21d6ecac0a869f10dfeecf6235898a47b3b78\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010111 for cells of type $lut.
Using template $paramod$9f2f146893d269900bb68ba0244b254b88c2c459\$lut for cells of type $lut.
Using template $paramod$8e01d13e078e8177912f721c32dbabb20f78322d\$lut for cells of type $lut.
Using template $paramod$bf8a2eb9c34204449ae734db198784b474646269\$lut for cells of type $lut.
Using template $paramod$e098d38d00670bf1f66f3fff32b3e8f0f799bc39\$lut for cells of type $lut.
Using template $paramod$6c543b558919ff57a92ac09985ad349c5934cfed\$lut for cells of type $lut.
Using template $paramod$fb5496753f4cd235e71c284b2ffee9d41a960ca2\$lut for cells of type $lut.
Using template $paramod$a05130630e3bd6f8c42c35e2bee91a8488080c81\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110011 for cells of type $lut.
Using template $paramod$4541c098116f7292d10d7d30a0922be20fa68a41\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~8646 debug messages>

24.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$16382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$16360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9337.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9320.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9904.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9753.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$13656.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$13647.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9592.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$11288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$9285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$9285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$9285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$9285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$10167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$10143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10121.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$10095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$10095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$10095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$10095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$10095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$10083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$10083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$10083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$10083.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$10073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$10073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$10073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$10064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$10064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$10064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9952.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9952.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9929.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9048.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$9038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$10007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$10007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$5184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9170.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$9638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$9638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8536.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8350.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8177.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8070.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8016.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7775.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7681.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7725.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7604.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7604.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7604.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7604.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7566.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7527.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7409.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7359.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7321.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7272.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$7047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7023.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6830.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6767.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6813.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6684.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6483.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91604.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91604.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6403.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6289.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6175.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$6120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6068.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5993.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5955.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5950.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5950.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5950.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$5933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$5851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$5851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$5823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$5823.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5751.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5734.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5692.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5652.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$91384$lut$auto$rtlil.cc:2603:Mux$5003[12].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$11961.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$10007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91598.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10064.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$10073.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$10089.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91597.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$10143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$9285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$10212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$10230.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$10246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10479.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10545.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$10990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$10990.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$11008.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$11086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11129.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11155.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$11228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11616.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$11766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$11918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$12045.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$12080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$12096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$12153.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$12205.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$12249.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$12266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$12359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$12394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$12575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$12610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$12635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$12738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$12743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$12792.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$12827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$12868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$12950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$12985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13548.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$13575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$13643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$13665.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$13737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13757.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$13795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$13878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$13917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$13969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$14110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$14143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$14167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$14214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$14287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$14320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$14353.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$14375.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$14471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$14504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$14528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$14620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$14653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$14739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$14806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$14839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$14873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$14927.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$14985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$15095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$15128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$15157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$15167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$15219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$15270.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$15331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$15364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$15449.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$15482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$15518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$15592.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$15678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$15737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$15790.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$15800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$15897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$15905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$15963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$16021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$16025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$16104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$16137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$16156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$16223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$16233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$16283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$16316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$16360.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$16382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$16386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$16392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$16403.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11624.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5097.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5115.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5133.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5146.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$5237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5170.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5433.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$5437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5491.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$5512.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5679.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$5692.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$5709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$5851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5851.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5871.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$5933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$5914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$5927.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$5933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5950.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$5961.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$5961.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6036.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6115.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$6120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$6137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6143.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6212.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6268.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6295.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6351.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6371.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6371.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6427.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6444.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6463.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$6477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$6495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$6500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6575.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6652.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6735.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6791.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$6818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$6836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6836.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6892.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6909.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6965.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$6986.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$6986.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7071.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$7152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7162.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$7327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7327.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7399.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$7415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7415.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7484.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7495.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7495.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7572.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7649.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$7743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7743.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7799.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$7827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7833.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$7912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$7984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8076.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8201.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8254.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8248.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8356.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8412.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8426.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8504.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$12436.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8874.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$8910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$8938.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8968.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$8993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9038.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9090.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9118.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9213.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9261.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$10494.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$9294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9465.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$8675.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9532.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9561.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9565.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9579.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$10167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9701.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9728.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9762.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9195.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$91384$lut$aiger91383$9904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$9908.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9204.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$9952.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$9970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$9998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$91384$lut$aiger91383$16684.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$auto$opt_dff.cc:219:make_patterns_logic$4673.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$91384$lut$auto$fsm_map.cc:170:map_fsm$4353[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91492.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91387.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91397.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11271.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$aiger91383$11809.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$91384$lut$auto$rtlil.cc:2603:Mux$5003[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91389.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91391.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91394.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$91384$lut$aiger91383$9402.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91449.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91483.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91551.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91576.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91398.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91584.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91593.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91600.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91604.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91609.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91610.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91614.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91615.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91618.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91620.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91622.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91626.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$91631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Removed 0 unused cells and 7921 unused wires.

24.45. Executing AUTONAME pass.
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 3373372
Renamed 534905 objects in module top (278 iterations).
<suppressed ~13576 debug messages>

24.46. Executing HIERARCHY pass (managing design hierarchy).

24.46.1. Analyzing design hierarchy..
Top module:  \top

24.46.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

24.47. Printing statistics.

=== top ===

   Number of wires:               5999
   Number of wire bits:          16665
   Number of public wires:        5999
   Number of public wire bits:   16665
   Number of ports:                  6
   Number of port bits:             18
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               8212
     $_TBUF_                         6
     $scopeinfo                     33
     CCU2C                         345
     L6MUX21                       488
     LUT4                         4578
     MULT18X18D                      4
     PFUMX                        1106
     TRELLIS_DPR16X4               308
     TRELLIS_FF                   1344

24.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

24.49. Executing JSON backend.

Warnings: 2 unique messages, 3 total
End of script. Logfile hash: 527cce5e61, CPU: user 10.98s system 0.12s, MEM: 242.14 MB peak
Yosys 0.42+36 (git sha1 07daf61ae, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)
Time spent: 42% 1x abc9_exe (8 sec), 10% 1x autoname (2 sec), ...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (NextPNR)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6 --lpf-allow-unconstrained
Info: constraining clock net 'clk' to 25.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:      7116/43848    16%
Info:         logic LUTs:   4578/43848    10%
Info:         carry LUTs:    690/43848     1%
Info:           RAM LUTs:   1232/ 5481    22%
Info:          RAMW LUTs:    616/10962     5%

Info:      Total DFFs:      1344/43848     3%

Info: Packing IOs..
Info: $gpios[5]$iobuf_i: gpios_$_TBUF__Y.Y
Info: pin 'gpios[5]$tr_io' constrained to Bel 'X9/Y71/PIOB'.
Info: $gpios[4]$iobuf_i: gpios_$_TBUF__Y_1.Y
Info: pin 'gpios[4]$tr_io' constrained to Bel 'X4/Y71/PIOB'.
Info: $gpios[3]$iobuf_i: gpios_$_TBUF__Y_2.Y
Info: pin 'gpios[3]$tr_io' constrained to Bel 'X0/Y65/PIOB'.
Info: $gpios[2]$iobuf_i: gpios_$_TBUF__Y_3.Y
Info: pin 'gpios[2]$tr_io' constrained to Bel 'X9/Y71/PIOA'.
Info: $gpios[1]$iobuf_i: gpios_$_TBUF__Y_4.Y
Info: pin 'gpios[1]$tr_io' constrained to Bel 'X6/Y71/PIOA'.
Info: $gpios[0]$iobuf_i: gpios_$_TBUF__Y_5.Y
Info: pin 'gpios[0]$tr_io' constrained to Bel 'X4/Y71/PIOA'.
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'reset$tr_io' constrained to Bel 'X0/Y29/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y59/PIOA'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X15/Y71/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y44/PIOC'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y59/PIOC'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     661 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xc38d19a9

Info: Device utilisation:
Info: 	          TRELLIS_IO:      18/    245     7%
Info: 	                DCCA:       1/     56     1%
Info: 	              DP16KD:       0/    108     0%
Info: 	          MULT18X18D:       4/     72     5%
Info: 	              ALU54B:       0/     36     0%
Info: 	             EHXPLLL:       0/      4     0%
Info: 	             EXTREFB:       0/      2     0%
Info: 	                DCUA:       0/      2     0%
Info: 	           PCSCLKDIV:       0/      2     0%
Info: 	             IOLOGIC:       0/    160     0%
Info: 	            SIOLOGIC:       0/     85     0%
Info: 	                 GSR:       0/      1     0%
Info: 	               JTAGG:       0/      1     0%
Info: 	                OSCG:       0/      1     0%
Info: 	               SEDGA:       0/      1     0%
Info: 	                 DTR:       0/      1     0%
Info: 	             USRMCLK:       0/      1     0%
Info: 	             CLKDIVF:       0/      4     0%
Info: 	           ECLKSYNCB:       0/     10     0%
Info: 	             DLLDELD:       0/      8     0%
Info: 	              DDRDLL:       0/      4     0%
Info: 	             DQSBUFM:       0/     10     0%
Info: 	     TRELLIS_ECLKBUF:       0/      8     0%
Info: 	        ECLKBRIDGECS:       0/      2     0%
Info: 	                DCSC:       0/      2     0%
Info: 	          TRELLIS_FF:    1344/  43848     3%
Info: 	        TRELLIS_COMB:    7240/  43848    16%
Info: 	        TRELLIS_RAMW:     308/   5481     5%

Info: Placed 18 cells based on constraints.
Info: Creating initial analytic placement for 4016 cells, random placement wirelen = 360996.
Info:     at initial placer iter 0, wirelen = 2952
Info:     at initial placer iter 1, wirelen = 2211
Info:     at initial placer iter 2, wirelen = 2359
Info:     at initial placer iter 3, wirelen = 2410
Info: Running main analytical placer, max placement attempts per cell = 9934653.
Info:     at iteration #1, type ALL: wirelen solved = 2283, spread = 57656, legal = 57006; time = 0.21s
Info:     at iteration #2, type ALL: wirelen solved = 5997, spread = 45267, legal = 46151; time = 0.21s
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2028.781 ; gain = 403.715 ; free physical = 1687 ; free virtual = 26080
---------------------------------------------------------------------------------
Info:     at iteration #3, type ALL: wirelen solved = 8731, spread = 42162, legal = 44043; time = 0.21s
Info:     at iteration #4, type ALL: wirelen solved = 11528, spread = 41115, legal = 43595; time = 0.28s
Info:     at iteration #5, type ALL: wirelen solved = 13618, spread = 39076, legal = 41443; time = 0.28s
Info:     at iteration #6, type ALL: wirelen solved = 15799, spread = 35520, legal = 38431; time = 0.21s
INFO: [Synth 8-11241] undeclared symbol 'pc_source', assumed default net type 'wire' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:168]
WARNING: [Synth 8-9400] empty statement in sequential block [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:54]
INFO: [Synth 8-6157] synthesizing module 'top' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1]
	Parameter CYCLES bound to: 20 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/debug/reset.v:1]
WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:24]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 3 connections declared, but only 2 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:24]
INFO: [Synth 8-6157] synthesizing module 'Risco_5_SOC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
	Parameter CLOCK_FREQ bound to: 50000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter MEMORY_SIZE bound to: 2048 - type: integer 
	Parameter MEMORY_FILE bound to: ../../software/memory/teste_uart_fpga.hex - type: string 
	Parameter GPIO_WIDHT bound to: 8 - type: integer 
	Parameter UART_BUFFER_SIZE bound to: 16 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:2]
	Parameter BOOT_ADDRESS bound to: 0 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'PC' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'PC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/pc.v:1]
INFO: [Synth 8-6157] synthesizing module 'MUX' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1]
INFO: [Synth 8-6155] done synthesizing module 'MUX' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mux.v:1]
INFO: [Synth 8-6157] synthesizing module 'MDU' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mdu.v:6]
INFO: [Synth 8-6155] done synthesizing module 'MDU' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mdu.v:6]
INFO: [Synth 8-6157] synthesizing module 'Registers' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Registers' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/registers.v:1]
INFO: [Synth 8-6157] synthesizing module 'Control_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:2]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:166]
WARNING: [Synth 8-6090] variable 'mdu_start' is written by both blocking and non-blocking assignments, entire logic could be removed [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:658]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:363]
INFO: [Synth 8-6155] done synthesizing module 'Control_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/control_unit.v:2]
INFO: [Synth 8-6157] synthesizing module 'ALU_Control' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:34]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:11]
INFO: [Synth 8-6155] done synthesizing module 'ALU_Control' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:1]
INFO: [Synth 8-6157] synthesizing module 'Alu' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Alu' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu.v:1]
INFO: [Synth 8-6157] synthesizing module 'Immediate_Generator' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Immediate_Generator' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/immediate_generator.v:1]
INFO: [Synth 8-6157] synthesizing module 'CSR_Unit' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:117]
INFO: [Synth 8-6155] done synthesizing module 'CSR_Unit' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/csr_unit.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Core' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v:2]
WARNING: [Synth 8-7071] port 'halt' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
WARNING: [Synth 8-7071] port 'interruption_request_external' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
WARNING: [Synth 8-7071] port 'interruption_request_timer' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
WARNING: [Synth 8-7071] port 'interruption_request_software' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
WARNING: [Synth 8-7071] port 'interruption_request_fast' of module 'Core' is unconnected for instance 'Core' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
WARNING: [Synth 8-7023] instance 'Core' of module 'Core' has 14 connections declared, but only 9 given [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:33]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
	Parameter MEMORY_FILE bound to: ../../software/memory/teste_uart_fpga.hex - type: string 
	Parameter MEMORY_SIZE bound to: 2048 - type: integer 
INFO: [Synth 8-3876] $readmem data file '../../software/memory/teste_uart_fpga.hex' is read successfully [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:35]
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/memory.v:1]
INFO: [Synth 8-6157] synthesizing module 'BUS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6155] done synthesizing module 'BUS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/bus.v:1]
INFO: [Synth 8-6157] synthesizing module 'LEDs' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6155] done synthesizing module 'LEDs' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/leds.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
	Parameter CLK_FREQ bound to: 50000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter BUFFER_SIZE bound to: 16 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
	Parameter DEPTH bound to: 16 - type: integer 
	Parameter WIDTH bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_rx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 50000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_rx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_rx.v:10]
INFO: [Synth 8-6157] synthesizing module 'uart_tool_tx' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 50000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_tool_tx' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'GPIOS' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
	Parameter WIDHT bound to: 8 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'GPIO' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpio.v:1]
INFO: [Synth 8-6157] synthesizing module 'PWM' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v:1]
INFO: [Synth 8-6155] done synthesizing module 'PWM' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/pwm.v:1]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:66]
INFO: [Synth 8-6155] done synthesizing module 'GPIOS' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v:1]
INFO: [Synth 8-6155] done synthesizing module 'Risco_5_SOC' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/soc.v:1]
INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/main.v:1]
WARNING: [Synth 8-6014] Unused sequential element Data_X_reg was removed.  [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mdu.v:53]
WARNING: [Synth 8-6014] Unused sequential element Data_Y_reg was removed.  [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/mdu.v:54]
WARNING: [Synth 8-6014] Unused sequential element tx_fifo_read_reg was removed.  [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/uart.v:160]
WARNING: [Synth 8-7129] Port address[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[31] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[4] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[3] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[2] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module LEDs is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module LEDs is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Info:     at iteration #7, type ALL: wirelen solved = 15209, spread = 35600, legal = 38270; time = 0.24s
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2118.750 ; gain = 493.684 ; free physical = 1573 ; free virtual = 25968
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2133.594 ; gain = 508.527 ; free physical = 1570 ; free virtual = 25965
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2133.594 ; gain = 508.527 ; free physical = 1570 ; free virtual = 25965
---------------------------------------------------------------------------------
Info:     at iteration #8, type ALL: wirelen solved = 16886, spread = 33189, legal = 35473; time = 0.20s
Info:     at iteration #9, type ALL: wirelen solved = 18279, spread = 33338, legal = 35234; time = 0.19s
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2133.594 ; gain = 0.000 ; free physical = 1570 ; free virtual = 25965
Info:     at iteration #10, type ALL: wirelen solved = 18375, spread = 32649, legal = 34394; time = 0.19s
Info:     at iteration #11, type ALL: wirelen solved = 19413, spread = 31987, legal = 33631; time = 0.19s
Info:     at iteration #12, type ALL: wirelen solved = 19762, spread = 32207, legal = 33677; time = 0.19s
Info:     at iteration #13, type ALL: wirelen solved = 20642, spread = 31652, legal = 33654; time = 0.26s
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Info:     at iteration #14, type ALL: wirelen solved = 20871, spread = 32068, legal = 33893; time = 0.26s
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Info:     at iteration #15, type ALL: wirelen solved = 21534, spread = 31018, legal = 33107; time = 0.22s
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2284.344 ; gain = 0.000 ; free physical = 1551 ; free virtual = 25946
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2284.379 ; gain = 0.000 ; free physical = 1551 ; free virtual = 25946
Info:     at iteration #16, type ALL: wirelen solved = 21906, spread = 31238, legal = 33296; time = 0.19s
Info:     at iteration #17, type ALL: wirelen solved = 22408, spread = 31740, legal = 33723; time = 0.20s
Info:     at iteration #18, type ALL: wirelen solved = 23450, spread = 30637, legal = 32930; time = 0.21s
Info:     at iteration #19, type ALL: wirelen solved = 22790, spread = 31229, legal = 33949; time = 0.19s
Info:     at iteration #20, type ALL: wirelen solved = 23776, spread = 30902, legal = 33510; time = 0.19s
Info:     at iteration #21, type ALL: wirelen solved = 23790, spread = 30556, legal = 33997; time = 0.19s
Info:     at iteration #22, type ALL: wirelen solved = 23660, spread = 30938, legal = 34183; time = 0.23s
Info:     at iteration #23, type ALL: wirelen solved = 23889, spread = 30542, legal = 33836; time = 0.27s
Info: HeAP Placer Time: 7.72s
Info:   of which solving equations: 4.56s
Info:   of which spreading cells: 0.60s
Info:   of which strict legalisation: 0.24s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 4577, wirelen = 32930
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2284.379 ; gain = 659.312 ; free physical = 1500 ; free virtual = 25894
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2284.379 ; gain = 659.312 ; free physical = 1500 ; free virtual = 25894
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2284.379 ; gain = 659.312 ; free physical = 1500 ; free virtual = 25894
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
INFO: [Synth 8-802] inferred FSM for state register 'state_mul_reg' in module 'MDU'
INFO: [Synth 8-802] inferred FSM for state register 'state_div_reg' in module 'MDU'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'UART'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
           RESET_COUNTER |                               00 |                               01
                    IDLE |                               01 |                               10
                    INIT |                               10 |                               00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                              001 |                               00
                 OPERATE |                              010 |                               01
                  FINISH |                              100 |                               10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_mul_reg' using encoding 'one-hot' in module 'MDU'
Info:   at iteration #5: temp = 0.000000, timing cost = 4228, wirelen = 29524
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                   FETCH | 00000000000000000000000000000000000000000000000001 |                           000000
          VALIDATE_FETCH | 00000000000000000000000000000000000000000000000010 |                           101110
                  DECODE | 00000000000000000000000000000000000000000000000100 |                           000001
                  MEMADR | 00000000000000000000000000000000000000000000001000 |                           000010
       MEMREAD_UNALIGNED | 00000000000000000000000000000000000000000000010000 |                           010110
        LOAD_FIRST_BLOCK | 00000000000000000000000000000000000000000000100000 |                           010000
        SAVE_FIRST_BLOCK | 00000000000000000000000000000000000000000001000000 |                           010001
       CALC_NEXT_ADDRESS | 00000000000000000000000000000000000000000010000000 |                           010010
       READ_SECOND_BLOCK | 00000000000000000000000000000000000000000100000000 |                           010011
       LOAD_SECOND_BLOCK | 00000000000000000000000000000000000000001000000000 |                           010100
            MERGE_BLOCKS | 00000000000000000000000000000000000000010000000000 |                           010101
           FILTER_ALU_WB | 00000000000000000000000000000000000000100000000000 |                           010111
                 MEMREAD | 00000000000000000000000000000000000001000000000000 |                           000011
                   MEMWB | 00000000000000000000000000000000000010000000000000 |                           000100
      MEMWRITE_UNALIGNED | 00000000000000000000000000000000000100000000000000 |                           011000
  GEN_FIRST_BLOCK_PART_1 | 00000000000000000000000000000000001000000000000000 |                           011001
  GEN_FIRST_BLOCK_PART_2 | 00000000000000000000000000000000010000000000000000 |                           011010
 GEN_SECOND_BLOCK_PART_1 | 00000000000000000000000000000000100000000000000000 |                           011011
 GEN_SECOND_BLOCK_PART_2 | 00000000000000000000000000000001000000000000000000 |                           011100
      MERGE_WRITE_BLOCKS | 00000000000000000000000000000010000000000000000000 |                           011101
    SWAP_VALUE_DIRECTION | 00000000000000000000000000000100000000000000000000 |                           011110
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK | 00000000000000000000000000001000000000000000000000 |                           100010
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_2 | 00000000000000000000000000010000000000000000000000 |                           100011
CLEAR_VALUE_HALF_BYTE_ONE_BLOCK_3 | 00000000000000000000000000100000000000000000000000 |                           100100
             CLEAR_VALUE | 00000000000000000000000001000000000000000000000000 |                           011111
     MERGE_WRITE_VALUE_1 | 00000000000000000000000010000000000000000000000000 |                           100000
           WRITE_VALUE_1 | 00000000000000000000000100000000000000000000000000 |                           100001
CALC_SECOND_BLOCK_ADDRESS_TO_WRITE | 00000000000000000000001000000000000000000000000000 |                           100101
READ_SECOND_BLOCK_TO_WRITE | 00000000000000000000010000000000000000000000000000 |                           100110
LOAD_SECOND_BLOCK_TO_WRITE | 00000000000000000000100000000000000000000000000000 |                           100111
LOAD_SECOND_BLOCK_TO_WRITE_2 | 00000000000000000001000000000000000000000000000000 |                           101000
  SWAP_VALUE_DIRECTION_2 | 00000000000000000010000000000000000000000000000000 |                           101001
      CLEAR_VALUE_PART_2 | 00000000000000000100000000000000000000000000000000 |                           101010
    CLEAR_VALUE_PART_2_1 | 00000000000000001000000000000000000000000000000000 |                           101011
     MERGE_WRITE_VALUE_2 | 00000000000000010000000000000000000000000000000000 |                           101100
           WRITE_VALUE_2 | 00000000000000100000000000000000000000000000000000 |                           101101
                MEMWRITE | 00000000000001000000000000000000000000000000000000 |                           000101
                EXECUTER | 00000000000010000000000000000000000000000000000000 |                           000110
             EXECUTE_MDU | 00000000000100000000000000000000000000000000000000 |                           101111
                MDU_WAIT | 00000000001000000000000000000000000000000000000000 |                           110000
                  MDU_WB | 00000000010000000000000000000000000000000000000000 |                           110001
                EXECUTEI | 00000000100000000000000000000000000000000000000000 |                           001000
                     JAL | 00000001000000000000000000000000000000000000000000 |                           001001
                  BRANCH | 00000010000000000000000000000000000000000000000000 |                           001010
                   AUIPC | 00000100000000000000000000000000000000000000000000 |                           001100
                     LUI | 00001000000000000000000000000000000000000000000000 |                           001101
                 JALR_PC | 00010000000000000000000000000000000000000000000000 |                           001110
                    JALR | 00100000000000000000000000000000000000000000000000 |                           001011
                   ALUWB | 01000000000000000000000000000000000000000000000000 |                           000111
              EXECUTECSR | 10000000000000000000000000000000000000000000000000 |                           001111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_RECV |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_SEND |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                             0000 |                             0000
       COPY_WRITE_BUFFER |                             0001 |                             0100
                   WRITE |                             0010 |                             0010
                    READ |                             0011 |                             0001
      READ_RX_FIFO_EMPTY |                             0100 |                             0110
      READ_TX_FIFO_EMPTY |                             0101 |                             0111
       READ_RX_FIFO_FULL |                             0110 |                             1000
       READ_TX_FIFO_FULL |                             0111 |                             1001
                      WB |                             1000 |                             0101
                  FINISH |                             1001 |                             0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2284.379 ; gain = 659.312 ; free physical = 1496 ; free virtual = 25892
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input   32 Bit       Adders := 5     
	   3 Input   32 Bit       Adders := 2     
	   2 Input   10 Bit       Adders := 2     
	   2 Input    6 Bit       Adders := 6     
	   2 Input    5 Bit       Adders := 1     
	   2 Input    4 Bit       Adders := 2     
	   2 Input    3 Bit       Adders := 2     
	   2 Input    2 Bit       Adders := 1     
+---XORs : 
	   2 Input     32 Bit         XORs := 1     
+---XORs : 
	                2 Bit    Wide XORs := 1     
+---Registers : 
	               64 Bit    Registers := 4     
	               32 Bit    Registers := 57    
	               16 Bit    Registers := 4     
	               10 Bit    Registers := 2     
	                8 Bit    Registers := 8     
	                6 Bit    Registers := 5     
	                4 Bit    Registers := 2     
	                3 Bit    Registers := 1     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 18    
+---Multipliers : 
	              32x32  Multipliers := 1     
+---RAMs : 
	              16K Bit	(512 X 32 bit)          RAMs := 1     
	              128 Bit	(16 X 8 bit)          RAMs := 2     
+---Muxes : 
	   4 Input   64 Bit        Muxes := 2     
	  50 Input   50 Bit        Muxes := 1     
	   2 Input   50 Bit        Muxes := 19    
	  11 Input   50 Bit        Muxes := 1     
	   2 Input   32 Bit        Muxes := 12    
	   4 Input   32 Bit        Muxes := 4     
	   8 Input   32 Bit        Muxes := 1     
	  15 Input   32 Bit        Muxes := 1     
	   3 Input   32 Bit        Muxes := 1     
	   6 Input   32 Bit        Muxes := 1     
	  10 Input   32 Bit        Muxes := 2     
	   2 Input    8 Bit        Muxes := 3     
	   3 Input    6 Bit        Muxes := 1     
	   2 Input    6 Bit        Muxes := 4     
	   2 Input    5 Bit        Muxes := 1     
	  50 Input    4 Bit        Muxes := 1     
	   9 Input    4 Bit        Muxes := 1     
	  10 Input    4 Bit        Muxes := 2     
	  23 Input    4 Bit        Muxes := 1     
	   2 Input    4 Bit        Muxes := 3     
	   6 Input    4 Bit        Muxes := 1     
	   3 Input    3 Bit        Muxes := 1     
	   2 Input    3 Bit        Muxes := 4     
	   5 Input    3 Bit        Muxes := 1     
	   4 Input    3 Bit        Muxes := 2     
	  50 Input    3 Bit        Muxes := 3     
	  10 Input    3 Bit        Muxes := 2     
	   3 Input    2 Bit        Muxes := 1     
	   2 Input    2 Bit        Muxes := 17    
	   4 Input    2 Bit        Muxes := 5     
	  50 Input    2 Bit        Muxes := 2     
	   3 Input    1 Bit        Muxes := 6     
	   2 Input    1 Bit        Muxes := 78    
	   4 Input    1 Bit        Muxes := 6     
	  50 Input    1 Bit        Muxes := 12    
	   6 Input    1 Bit        Muxes := 12    
	  10 Input    1 Bit        Muxes := 8     
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
DSP Report: Generating DSP acumulador0, operation Mode is: A*B.
DSP Report: operator acumulador0 is absorbed into DSP acumulador0.
DSP Report: operator acumulador0 is absorbed into DSP acumulador0.
DSP Report: Generating DSP acumulador_reg, operation Mode is: (PCIN>>17)+A*B.
DSP Report: register acumulador_reg is absorbed into DSP acumulador_reg.
DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg.
DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg.
DSP Report: Generating DSP acumulador0, operation Mode is: A*B.
DSP Report: operator acumulador0 is absorbed into DSP acumulador0.
DSP Report: operator acumulador0 is absorbed into DSP acumulador0.
DSP Report: Generating DSP acumulador_reg, operation Mode is: (PCIN>>17)+A*B.
DSP Report: register acumulador_reg is absorbed into DSP acumulador_reg.
DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg.
DSP Report: operator acumulador0 is absorbed into DSP acumulador_reg.
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template. 
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[47]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[46]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[45]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[44]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[43]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[42]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[41]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[40]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[39]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[38]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[37]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[36]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[35]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[34]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[33]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[32]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[31]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[30]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[29]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[28]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[27]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[26]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[25]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[24]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[23]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[22]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[21]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[20]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[19]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[18]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[17]) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[47]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[46]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[45]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[44]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[43]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[42]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[41]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[40]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[39]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[38]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[37]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[36]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[35]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[34]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[33]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[32]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[31]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[30]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[29]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[28]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[27]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[26]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[25]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[24]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[23]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[22]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[21]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[20]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[19]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[18]__0) is unused and will be removed from module MDU.
WARNING: [Synth 8-3332] Sequential element (acumulador_reg[17]__0) is unused and will be removed from module MDU.
Info:   at iteration #10: temp = 0.000000, timing cost = 5167, wirelen = 28655
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN  (NL0002) : The module "ALU_Control" instantiated to "ALU_Control" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":238)
WARN  (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":255)
WARN  (NL0002) : The module "MUX" instantiated to "PCSourceMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":178)
[95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
[100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg"
Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Processing netlist completed
Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst"
Physical Constraint parsed completed
Running placement......
Info:   at iteration #15: temp = 0.000000, timing cost = 5159, wirelen = 28217
Info:   at iteration #20: temp = 0.000000, timing cost = 5185, wirelen = 28100
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
Info:   at iteration #23: temp = 0.000000, timing cost = 5144, wirelen = 28067 
Info: SA placement time 20.49s
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2284.379 ; gain = 659.312 ; free physical = 1262 ; free virtual = 25668
---------------------------------------------------------------------------------
 Sort Area is  acumulador0_3 : 0 0 : 2701 4912 : Used 1 time 0
 Sort Area is  acumulador0_3 : 0 1 : 2211 4912 : Used 1 time 0
 Sort Area is  acumulador0_0 : 0 0 : 2158 4062 : Used 1 time 0
 Sort Area is  acumulador0_0 : 0 1 : 1904 4062 : Used 1 time 0
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object                  | Inference | Size (Depth x Width) | Primitives      | 
+------------+-----------------------------+-----------+----------------------+-----------------+
|top         | SOC/Memory/memory_reg       | Implied   | 512 x 32             | RAM256X1S x 64  | 
|top         | SOC/Uart/RX_FIFO/memory_reg | Implied   | 16 x 8               | RAM32M x 2      | 
|top         | SOC/Uart/TX_FIFO/memory_reg | Implied   | 16 x 8               | RAM32M x 2      | 
+------------+-----------------------------+-----------+----------------------+-----------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.

DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping    | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|MDU         | A*B            | 18     | 15     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|MDU         | (PCIN>>17)+A*B | 15     | 15     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 1    | 
|MDU         | A*B            | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|MDU         | (PCIN>>17)+A*B | 18     | 15     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 1    | 
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 44.25 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 11.21 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 10.44 ns

Info: Slack histogram:
Info:  legend: * represents 39 endpoint(s)
Info:          + represents [1,39) endpoint(s)
Info: [ 17401,  18493) |+
Info: [ 18493,  19585) |+
Info: [ 19585,  20677) |*+
Info: [ 20677,  21769) |***+
Info: [ 21769,  22861) |***********+
Info: [ 22861,  23953) |********+
Info: [ 23953,  25045) |**************+
Info: [ 25045,  26137) |************+
Info: [ 26137,  27229) |**********+
Info: [ 27229,  28321) |************+
Info: [ 28321,  29413) |*************+
Info: [ 29413,  30505) |*****************************************+
Info: [ 30505,  31597) |************************************************************ 
Info: [ 31597,  32689) |*************************+
Info: [ 32689,  33781) |*****+
Info: [ 33781,  34873) |*************+
Info: [ 34873,  35965) |************+
Info: [ 35965,  37057) |**********+
Info: [ 37057,  38149) |*********+
Info: [ 38149,  39241) |********+
Info: Checksum: 0x56558f2c
Info: Routing globals...
Info:     routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0

Info: Routing..
Info: Setting up routing queue.
Info: Routing 33986 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |      145        854 |  145   854 |     33147|       0.77       0.77|
Info:       2000 |      332       1667 |  187   813 |     32633|       0.32       1.09|
Info:       3000 |      463       2536 |  131   869 |     31931|       0.27       1.36|
Info:       4000 |      658       3341 |  195   805 |     31217|       0.28       1.64|
Info:       5000 |      866       4133 |  208   792 |     30592|       0.31       1.95|
Info:       6000 |     1137       4862 |  271   729 |     30098|       0.31       2.25|
Info:       7000 |     1409       5590 |  272   728 |     29664|       0.28       2.54|
Info:       8000 |     1741       6258 |  332   668 |     29215|       0.31       2.85|
Info:       9000 |     2108       6891 |  367   633 |     28721|       0.26       3.11|
Info:      10000 |     2506       7493 |  398   602 |     28272|       0.30       3.41|
Info:      11000 |     2785       8214 |  279   721 |     27679|       0.31       3.72|
Info:      12000 |     3048       8951 |  263   737 |     27087|       0.31       4.03|
Info:      13000 |     3403       9596 |  355   645 |     26586|       0.32       4.35|
Info:      14000 |     3795      10204 |  392   608 |     26121|       0.32       4.68|
Info:      15000 |     4101      10898 |  306   694 |     25605|       0.30       4.98|
Info:      16000 |     4417      11582 |  316   684 |     25300|       0.31       5.29|
Info:      17000 |     4755      12244 |  338   662 |     24757|       0.32       5.62|
Info:      18000 |     5074      12925 |  319   681 |     24329|       0.36       5.98|
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2284.379 ; gain = 659.312 ; free physical = 1303 ; free virtual = 25709
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
Info:      19000 |     5385      13614 |  311   689 |     23793|       0.35       6.33|
Info:      20000 |     5719      14280 |  334   666 |     23424|       0.36       6.69|
Info:      21000 |     5991      15008 |  272   728 |     22886|       0.32       7.01|
Info:      22000 |     6277      15722 |  286   714 |     22371|       0.32       7.34|
Info:      23000 |     6588      16411 |  311   689 |     22068|       0.31       7.65|
Info:      24000 |     6916      17083 |  328   672 |     21540|       0.34       7.98|
Info:      25000 |     7241      17758 |  325   675 |     20985|       0.34       8.32|
Info:      26000 |     7565      18434 |  324   676 |     20456|       0.31       8.63|
Info:      27000 |     7996      19003 |  431   569 |     20190|       0.38       9.01|
Info:      28000 |     8371      19628 |  375   625 |     19725|       0.35       9.36|
Info:      29000 |     8752      20247 |  381   619 |     19252|       0.34       9.69|
Info:      30000 |     9175      20824 |  423   577 |     18858|       0.35      10.05|
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2284.379 ; gain = 659.312 ; free physical = 1283 ; free virtual = 25690
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object                  | Inference | Size (Depth x Width) | Primitives      | 
+------------+-----------------------------+-----------+----------------------+-----------------+
|top         | SOC/Memory/memory_reg       | Implied   | 512 x 32             | RAM256X1S x 64  | 
|top         | SOC/Uart/RX_FIFO/memory_reg | Implied   | 16 x 8               | RAM32M x 2      | 
|top         | SOC/Uart/TX_FIFO/memory_reg | Implied   | 16 x 8               | RAM32M x 2      | 
+------------+-----------------------------+-----------+----------------------+-----------------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
Info:      31000 |     9547      21452 |  372   628 |     18336|       0.31      10.36|
Info:      32000 |     9843      22156 |  296   704 |     17858|       0.34      10.70|
Info:      33000 |    10039      22960 |  196   804 |     17762|       0.31      11.01|
Info:      34000 |    10255      23744 |  216   784 |     17538|       0.41      11.42|
Info:      35000 |    10683      24316 |  428   572 |     17083|       0.40      11.81|
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2284.379 ; gain = 659.312 ; free physical = 1276 ; free virtual = 25682
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
Info:      36000 |    11078      24921 |  395   605 |     16645|       0.33      12.15|
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
Info:      37000 |    11414      25585 |  336   664 |     16191|       0.33      12.48|
Info:      38000 |    11823      26176 |  409   591 |     15823|       0.39      12.87|
Info:      39000 |    12222      26777 |  399   601 |     15452|       0.37      13.24|
Info:      40000 |    12683      27316 |  461   539 |     15077|       0.36      13.60|
Info:      41000 |    13151      27848 |  468   532 |     14653|       0.36      13.96|
Info:      42000 |    13592      28407 |  441   559 |     14252|       0.42      14.38|
Info:      43000 |    13941      29058 |  349   651 |     13917|       0.42      14.80|
Info:      44000 |    14338      29640 |  397   582 |     13540|       0.41      15.21|
Info:      45000 |    14673      30211 |  335   571 |     13014|       0.32      15.53|
Info:      46000 |    14990      30736 |  317   525 |     12424|       0.27      15.80|
Info:      47000 |    15276      31279 |  286   543 |     11818|       0.27      16.07|
Info:      48000 |    15577      31849 |  301   570 |     11300|       0.26      16.33|
Info:      49000 |    15913      32385 |  336   536 |     10708|       0.25      16.59|
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:49 ; elapsed = 00:00:49 . Memory (MB): peak = 2284.379 ; gain = 659.312 ; free physical = 1274 ; free virtual = 25681
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:49 ; elapsed = 00:00:49 . Memory (MB): peak = 2284.379 ; gain = 659.312 ; free physical = 1274 ; free virtual = 25681
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
Info:      50000 |    16238      33003 |  325   618 |     10154|       0.29      16.88|
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 2284.379 ; gain = 659.312 ; free physical = 1272 ; free virtual = 25679
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 2284.379 ; gain = 659.312 ; free physical = 1269 ; free virtual = 25676
---------------------------------------------------------------------------------
[30%] Placement Phase 2 completed
Info:      51000 |    16548      33658 |  310   655 |      9564|       0.35      17.22|
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 2284.379 ; gain = 659.312 ; free physical = 1265 ; free virtual = 25672
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 2284.379 ; gain = 659.312 ; free physical = 1273 ; free virtual = 25679
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

DSP Final Report (the ' indicates corresponding REG is set)
+------------+-------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping       | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
+------------+-------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|MDU         | A'*B'             | 17     | 18     | -      | -      | 48     | 1    | 1    | -    | -    | -     | 0    | 0    | 
|MDU         | (PCIN>>17+A'*B')' | 30     | 18     | -      | -      | 48     | 1    | 1    | -    | -    | -     | 0    | 1    | 
|MDU         | A'*B'             | 17     | 17     | -      | -      | 48     | 1    | 1    | -    | -    | -     | 0    | 0    | 
|MDU         | (PCIN>>17+A'*B')' | 17     | 18     | -      | -      | 48     | 1    | 1    | -    | -    | -     | 0    | 1    | 
+------------+-------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+


Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+----------+------+
|      |Cell      |Count |
+------+----------+------+
|1     |BUFG      |     2|
|2     |CARRY4    |   135|
|3     |DSP48E1   |     4|
|5     |LUT1      |   149|
|6     |LUT2      |   277|
|7     |LUT3      |   337|
|8     |LUT4      |   380|
|9     |LUT5      |   315|
|10    |LUT6      |  1553|
|11    |MUXF7     |   467|
|12    |MUXF8     |    15|
|13    |RAM256X1S |    64|
|14    |RAM32M    |     2|
|15    |RAM32X1D  |     4|
|16    |FDRE      |  2388|
|17    |FDSE      |     5|
|18    |IBUF      |     3|
|19    |IOBUF     |     8|
|20    |OBUF      |     9|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 2284.379 ; gain = 659.312 ; free physical = 1271 ; free virtual = 25678
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 123 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:47 ; elapsed = 00:00:48 . Memory (MB): peak = 2284.379 ; gain = 508.527 ; free physical = 1273 ; free virtual = 25680
Synthesis Optimization Complete : Time (s): cpu = 00:00:50 ; elapsed = 00:00:50 . Memory (MB): peak = 2284.379 ; gain = 659.312 ; free physical = 1273 ; free virtual = 25680
INFO: [Project 1-571] Translating synthesized netlist
Info:      52000 |    16903      34264 |  355   606 |      8985|       0.35      17.58|
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2284.379 ; gain = 0.000 ; free physical = 1560 ; free virtual = 25967
INFO: [Netlist 29-17] Analyzing 699 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
Info:      53000 |    17293      34843 |  390   579 |      8520|       0.40      17.97|
INFO: [Project 1-570] Preparing netlist for logic optimization
Info:      54000 |    17618      35505 |  325   662 |      7897|       0.32      18.30|
Info:      55000 |    17771      36291 |  153   786 |      7102|       0.31      18.60|
Info:      56000 |    17845      37212 |   74   921 |      6496|       0.27      18.88|
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Info:      57000 |    17866      38190 |   21   978 |      5517|       0.11      18.99|
Info:      58000 |    17900      39122 |   34   932 |      4577|       0.12      19.11|
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2356.375 ; gain = 0.000 ; free physical = 1533 ; free virtual = 25940
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 78 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 8 instances
  RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances

Info:      59000 |    17954      40047 |   54   925 |      3657|       0.17      19.28|
Synth Design complete | Checksum: 9b08c1b2
INFO: [Common 17-83] Releasing license: Synthesis
84 Infos, 176 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:00 ; elapsed = 00:00:57 . Memory (MB): peak = 2356.410 ; gain = 1039.320 ; free physical = 1528 ; free virtual = 25935
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2070.917; main = 1777.671; forked = 435.845
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3242.863; main = 2356.379; forked = 982.531
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design

Starting DRC Task
Info:      60000 |    18085      40811 |  131   764 |      2825|       0.27      19.55|
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.91 . Memory (MB): peak = 2420.406 ; gain = 63.996 ; free physical = 1506 ; free virtual = 25912

Starting Cache Timing Information Task
Info:      61000 |    18366      41524 |  281   713 |      2680|       1.67      21.22|
Info:      62000 |    18519      42299 |  153   775 |      1916|       0.63      21.85|
Info:      63000 |    18600      43154 |   81   855 |      1025|       0.28      22.13|
Info:      64000 |    18713      43881 |  113   727 |       316|       0.30      22.43|
Info:      64320 |    18718      44093 |    5   212 |         0|       0.13      22.56|
Info: Routing complete.
Info: Router1 time 22.56s
Info: Checksum: 0x69b4ddf2
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1dd6d8a2b

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2472.219 ; gain = 51.812 ; free physical = 1397 ; free virtual = 25804

Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_3.Q
Info:  1.4  2.0    Net SOC.Memory.memory_response_LUT4_B_Z_LUT4_Z_D[1] (22,23) -> (23,26)
Info:                Sink SOC.Core.Mdu.div_done_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_LUT4_D_Z_LUT4_Z_2_D_LUT4_Z.B
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  2.2  Source SOC.Core.Mdu.div_done_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_LUT4_D_Z_LUT4_Z_2_D_LUT4_Z.F
Info:  1.0  3.2    Net SOC.Core.Mdu.div_done_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_LUT4_D_Z_LUT4_Z_2_D[1] (23,26) -> (24,30)
Info:                Sink SOC.Core.Mdu.div_done_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_LUT4_D_Z_LUT4_Z_2_D_LUT4_C.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  3.4  Source SOC.Core.Mdu.div_done_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_LUT4_D_Z_LUT4_Z_2_D_LUT4_C.F
Info:  0.6  4.0    Net SOC.Core.Mdu.div_done_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_LUT4_D_Z_LUT4_Z_2_D_LUT4_C_Z[1] (24,30) -> (24,30)
Info:                Sink SOC.Leds.write_LUT4_Z_B_LUT4_Z_1.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  4.3  Source SOC.Leds.write_LUT4_Z_B_LUT4_Z_1.F
Info:  0.9  5.2    Net SOC.Leds.write_LUT4_Z_B[0] (24,30) -> (21,29)
Info:                Sink SOC.Memory.memory_response_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_D.C
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  5.4  Source SOC.Memory.memory_response_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_D.F
Info:  0.9  6.3    Net SOC.Memory.memory_response_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_LUT4_D_Z[2] (21,29) -> (19,29)
Info:                Sink SOC.GPIOS.address_LUT4_Z_1.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  6.6  Source SOC.GPIOS.address_LUT4_Z_1.F
Info:  1.9  8.5    Net SOC.address[4] (19,29) -> (11,20)
Info:                Sink SOC.Memory.memory.0.121$DPRAM_COMB3.C
Info:                Defined in:
Info:                  Risco-5/src/peripheral/soc.v:23.5-23.18
Info:  0.2  8.7  Source SOC.Memory.memory.0.121$DPRAM_COMB3.F
Info:  0.8  9.5    Net SOC.Memory.memory.0.97_DO[0] (11,20) -> (11,20)
Info:                Sink SOC.Memory.memory.0.97_DO_LUT4_A.A
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  9.8  Source SOC.Memory.memory.0.97_DO_LUT4_A.F
Info:  0.9 10.7    Net SOC.Memory.memory.0.97_DO_LUT4_A_Z[2] (11,20) -> (11,21)
Info:                Sink SOC.Memory.memory.0.193_DO_LUT4_A_Z_LUT4_Z.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 10.9  Source SOC.Memory.memory.0.193_DO_LUT4_A_Z_LUT4_Z.F
Info:  0.9 11.8    Net SOC.Memory.memory.0.193_DO_LUT4_A_Z[3] (11,21) -> (11,23)
Info:                Sink SOC.Memory.memory.0.193_DO_LUT4_A_Z_LUT4_B.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 12.0  Source SOC.Memory.memory.0.193_DO_LUT4_A_Z_LUT4_B.F
Info:  1.0 13.0    Net SOC.Core.read_data_LUT4_Z_7_B_LUT4_Z_1_C[0] (11,23) -> (15,25)
Info:                Sink SOC.Memory.memory.0.194_DO_3_LUT4_A_Z_PFUMX_C0_Z_LUT4_Z_1.B
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 13.3  Source SOC.Memory.memory.0.194_DO_3_LUT4_A_Z_PFUMX_C0_Z_LUT4_Z_1.F
Info:  1.3 14.6    Net SOC.Core.read_data_LUT4_Z_10_C_LUT4_Z_1_B[3] (15,25) -> (20,28)
Info:                Sink SOC.Memory.memory.0.167_DO_LUT4_A_Z_LUT4_C_Z_LUT4_A_Z_LUT4_Z_2.D
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 14.8  Source SOC.Memory.memory.0.167_DO_LUT4_A_Z_LUT4_C_Z_LUT4_A_Z_LUT4_Z_2.F
Info:  1.2 16.0    Net SOC.Core.read_data_LUT4_Z_15_B[3] (20,28) -> (29,28)
Info:                Sink SOC.Core.read_data_PFUMX_Z_13_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3 16.3  Source SOC.Core.read_data_PFUMX_Z_13_BLUT_LUT4_Z.OFX
Info:  2.0 18.3    Net SOC.read_data[29] (29,28) -> (28,6)
Info:                Sink SOC.Core.instruction_register_TRELLIS_FF_Q_2.M
Info:                Defined in:
Info:                  Risco-5/src/peripheral/soc.v:22.34-22.43
Info:  0.0 18.3  Setup SOC.Core.instruction_register_TRELLIS_FF_Q_2.M
Info: 3.4 ns logic, 14.9 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source gpios[3]$tr_io.O
Info:  3.6  3.6    Net gpios[3]$TRELLIS_IO_IN (0,65) -> (6,30)
Info:                Sink SOC.GPIOS.Gpios[3].data_in_LUT4_C.A
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:7.16-7.21
Info:  0.2  3.9  Source SOC.GPIOS.Gpios[3].data_in_LUT4_C.F
Info:  1.3  5.2    Net SOC.GPIOS.Gpios[3].data_in_LUT4_C_Z[4] (6,30) -> (7,20)
Info:                Sink SOC.GPIOS.Gpios[3].data_in_LUT4_C_Z_PFUMX_C0_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.3  5.4  Source SOC.GPIOS.Gpios[3].data_in_LUT4_C_Z_PFUMX_C0_BLUT_LUT4_Z.OFX
Info:  0.6  6.0    Net SOC.GPIOS.Gpios[3].data_in_LUT4_C_Z_PFUMX_C0_Z[1] (7,20) -> (7,20)
Info:                Sink SOC.Core.read_data_LUT4_Z_3.B
Info:                Defined in:
Info:                  /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  6.2  Source SOC.Core.read_data_LUT4_Z_3.F
Info:  2.2  8.5    Net SOC.read_data[3] (7,20) -> (18,5)
Info:                Sink SOC.Core.instruction_register_TRELLIS_FF_Q_27.M
Info:                Defined in:
Info:                  Risco-5/src/peripheral/soc.v:22.34-22.43
Info:  0.0  8.5  Setup SOC.Core.instruction_register_TRELLIS_FF_Q_27.M
Info: 0.7 ns logic, 7.7 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source SOC.Leds.data_TRELLIS_FF_Q_29.Q
Info:  4.1  4.7    Net SOC.Leds.data[2] (17,27) -> (75,31)
Info:                Sink led_LUT4_Z.D
Info:                Defined in:
Info:                  Risco-5/src/peripheral/leds.v:15.12-15.16
Info:  0.2  4.9  Source led_LUT4_Z.F
Info:  2.2  7.1    Net led[2]$TRELLIS_IO_OUT (75,31) -> (90,44)
Info:                Sink led[2]$tr_io.I
Info:                Defined in:
Info:                  Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 6.3 ns routing

Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 54.64 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                           -> posedge $glbnet$clk$TRELLIS_IO_IN: 8.46 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async>                          : 7.09 ns

Info: Slack histogram:
Info:  legend: * represents 48 endpoint(s)
Info:          + represents [1,48) endpoint(s)
Info: [ 21698,  22566) |+
Info: [ 22566,  23434) |*+
Info: [ 23434,  24302) |*****+
Info: [ 24302,  25170) |*******+
Info: [ 25170,  26038) |******+
Info: [ 26038,  26906) |******+
Info: [ 26906,  27774) |**************+
Info: [ 27774,  28642) |******+
Info: [ 28642,  29510) |*******+
Info: [ 29510,  30378) |********+
Info: [ 30378,  31246) |***************************+
Info: [ 31246,  32114) |************************************************************ 
Info: [ 32114,  32982) |*******************+
Info: [ 32982,  33850) |***+
Info: [ 33850,  34718) |*****+
Info: [ 34718,  35586) |*****+
Info: [ 35586,  36454) |***********+
Info: [ 36454,  37322) |********+
Info: [ 37322,  38190) |********+
Info: [ 38190,  39058) |*******+

Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit

Starting Logic Optimization Task

Phase 1 Initialization

Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 1dd6d8a2b

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2724.125 ; gain = 0.000 ; free physical = 1445 ; free virtual = 25874

Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1dd6d8a2b

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2724.125 ; gain = 0.000 ; free physical = 1438 ; free virtual = 25867
Phase 1 Initialization | Checksum: 1dd6d8a2b

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2724.125 ; gain = 0.000 ; free physical = 1437 ; free virtual = 25866

Phase 2 Timer Update And Timing Data Collection

Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 1dd6d8a2b

Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2724.125 ; gain = 0.000 ; free physical = 1408 ; free virtual = 25837

Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 1dd6d8a2b

Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2724.125 ; gain = 0.000 ; free physical = 1403 ; free virtual = 25833
Phase 2 Timer Update And Timing Data Collection | Checksum: 1dd6d8a2b

Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2724.125 ; gain = 0.000 ; free physical = 1403 ; free virtual = 25832

Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 5 inverters resulting in an inversion of 15 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: d170293e

Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2724.125 ; gain = 0.000 ; free physical = 1337 ; free virtual = 25766
Retarget | Checksum: d170293e
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 5 cells

Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 14571caa8

Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.3 . Memory (MB): peak = 2724.125 ; gain = 0.000 ; free physical = 1340 ; free virtual = 25769
Constant propagation | Checksum: 14571caa8
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 5 Sweep
Phase 5 Sweep | Checksum: f9bf0472

Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2724.125 ; gain = 0.000 ; free physical = 1341 ; free virtual = 25770
Sweep | Checksum: f9bf0472
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 0 cells

Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: f9bf0472

Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2756.141 ; gain = 32.016 ; free physical = 1334 ; free virtual = 25763
BUFG optimization | Checksum: f9bf0472
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: f9bf0472

Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2756.141 ; gain = 32.016 ; free physical = 1333 ; free virtual = 25762
Shift Register Optimization | Checksum: f9bf0472
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: d667be14

Time (s): cpu = 00:00:00.71 ; elapsed = 00:00:00.48 . Memory (MB): peak = 2756.141 ; gain = 32.016 ; free physical = 1340 ; free virtual = 25769
Post Processing Netlist | Checksum: d667be14
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells

Phase 9 Finalization

Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 161edae12

Time (s): cpu = 00:00:00.85 ; elapsed = 00:00:00.6 . Memory (MB): peak = 2756.141 ; gain = 32.016 ; free physical = 1334 ; free virtual = 25763

Phase 9.2 Verifying Netlist Connectivity

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2756.141 ; gain = 0.000 ; free physical = 1332 ; free virtual = 25761
Phase 9.2 Verifying Netlist Connectivity | Checksum: 161edae12

Time (s): cpu = 00:00:00.87 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2756.141 ; gain = 32.016 ; free physical = 1332 ; free virtual = 25761
Phase 9 Finalization | Checksum: 161edae12

Time (s): cpu = 00:00:00.87 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2756.141 ; gain = 32.016 ; free physical = 1332 ; free virtual = 25761
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |               5  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               8  |               0  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------


Ending Logic Optimization Task | Checksum: 161edae12

Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2756.141 ; gain = 32.016 ; free physical = 1341 ; free virtual = 25770
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2756.141 ; gain = 0.000 ; free physical = 1341 ; free virtual = 25770
[Pipeline] }

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 161edae12

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2756.141 ; gain = 0.000 ; free physical = 1452 ; free virtual = 25882

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 161edae12

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2756.141 ; gain = 0.000 ; free physical = 1452 ; free virtual = 25882

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2756.141 ; gain = 0.000 ; free physical = 1452 ; free virtual = 25881
Ending Netlist Obfuscation Task | Checksum: 161edae12

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2756.141 ; gain = 0.000 ; free physical = 1452 ; free virtual = 25881
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2756.141 ; gain = 399.730 ; free physical = 1452 ; free virtual = 25881
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2788.156 ; gain = 0.000 ; free physical = 1458 ; free virtual = 25888
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 9806b086

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2788.156 ; gain = 0.000 ; free physical = 1458 ; free virtual = 25888
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2788.156 ; gain = 0.000 ; free physical = 1458 ; free virtual = 25888

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[Pipeline] }
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 114d7fd39

Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.85 . Memory (MB): peak = 2788.156 ; gain = 0.000 ; free physical = 1458 ; free virtual = 25888

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 125b60ca1

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1458 ; free virtual = 25887

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 125b60ca1

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1456 ; free virtual = 25886
Phase 1 Placer Initialization | Checksum: 125b60ca1

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1454 ; free virtual = 25883

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1c3f86eaa

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1450 ; free virtual = 25879

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 184c1993a

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1447 ; free virtual = 25876

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 184c1993a

Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1446 ; free virtual = 25875

Phase 2.4 Global Placement Core

Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1b1dde496

Time (s): cpu = 00:00:20 ; elapsed = 00:00:05 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1448 ; free virtual = 25878

Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 84 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 36 nets or LUTs. Breaked 0 LUT, combined 36 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1450 ; free virtual = 25880

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            0  |             36  |                    36  |           0  |           1  |  00:00:00  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            0  |             36  |                    36  |           0  |           4  |  00:00:00  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.2 Physical Synthesis In Placer | Checksum: 113e4335e

Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1450 ; free virtual = 25880
Phase 2.4 Global Placement Core | Checksum: 161829d74

Time (s): cpu = 00:00:25 ; elapsed = 00:00:07 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25880
Phase 2 Global Placement | Checksum: 161829d74

Time (s): cpu = 00:00:25 ; elapsed = 00:00:07 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25880

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: ddc1282a

Time (s): cpu = 00:00:25 ; elapsed = 00:00:07 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1450 ; free virtual = 25880

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 125b04fec

Time (s): cpu = 00:00:25 ; elapsed = 00:00:07 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25880

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 54961911

Time (s): cpu = 00:00:25 ; elapsed = 00:00:07 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25880

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1500e6bb2

Time (s): cpu = 00:00:25 ; elapsed = 00:00:07 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25880

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 1c4c4c47b

Time (s): cpu = 00:00:27 ; elapsed = 00:00:08 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25881

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 161dceadd

Time (s): cpu = 00:00:27 ; elapsed = 00:00:09 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25881

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1154440bc

Time (s): cpu = 00:00:27 ; elapsed = 00:00:09 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25881
Phase 3 Detail Placement | Checksum: 1154440bc

Time (s): cpu = 00:00:27 ; elapsed = 00:00:09 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25881

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1ebd4e8ab

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.882 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 1f108af3c

Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1451 ; free virtual = 25881
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 1f108af3c

Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1451 ; free virtual = 25881
Phase 4.1.1.1 BUFG Insertion | Checksum: 1ebd4e8ab

Time (s): cpu = 00:00:31 ; elapsed = 00:00:10 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25881

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=8.882. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1e968a08c

Time (s): cpu = 00:00:31 ; elapsed = 00:00:10 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25881

Time (s): cpu = 00:00:31 ; elapsed = 00:00:10 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25881
Phase 4.1 Post Commit Optimization | Checksum: 1e968a08c

Time (s): cpu = 00:00:31 ; elapsed = 00:00:10 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25881

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1e968a08c

Time (s): cpu = 00:00:31 ; elapsed = 00:00:10 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25881

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                2x2|
|___________|___________________|___________________|
|      South|                1x1|                1x1|
|___________|___________________|___________________|
|       East|                1x1|                1x1|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 1e968a08c

Time (s): cpu = 00:00:31 ; elapsed = 00:00:10 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25881
Phase 4.3 Placer Reporting | Checksum: 1e968a08c

Time (s): cpu = 00:00:31 ; elapsed = 00:00:10 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25881

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1451 ; free virtual = 25881

Time (s): cpu = 00:00:31 ; elapsed = 00:00:10 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25881
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2374b9c3b

Time (s): cpu = 00:00:31 ; elapsed = 00:00:10 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25881
Ending Placer Task | Checksum: 17504ad5f

Time (s): cpu = 00:00:31 ; elapsed = 00:00:10 . Memory (MB): peak = 2795.184 ; gain = 7.027 ; free physical = 1451 ; free virtual = 25881
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:11 . Memory (MB): peak = 2795.184 ; gain = 39.043 ; free physical = 1451 ; free virtual = 25881
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
report_io: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1450 ; free virtual = 25880
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1447 ; free virtual = 25876
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs

Phase 1 Build RT Design
Checksum: PlaceDB: 7e6cbdf9 ConstDB: 0 ShapeSum: f697ef66 RouteDB: 0
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
Post Restoration Checksum: NetGraph: d3b39558 | NumContArr: e60077b4 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 33f060246

Time (s): cpu = 00:00:34 ; elapsed = 00:00:27 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1392 ; free virtual = 25822

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 33f060246

Time (s): cpu = 00:00:34 ; elapsed = 00:00:27 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1392 ; free virtual = 25822

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 33f060246

Time (s): cpu = 00:00:34 ; elapsed = 00:00:27 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1392 ; free virtual = 25822
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 21e0c0e7c

Time (s): cpu = 00:00:38 ; elapsed = 00:00:28 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1383 ; free virtual = 25812
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797  | TNS=0.000  | WHS=0.008  | THS=0.000  |


Router Utilization Summary
  Global Vertical Routing Utilization    = 8.70436e-05 %
  Global Horizontal Routing Utilization  = 7.10429e-05 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 4667
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 4666
  Number of Partially Routed Nets     = 1
  Number of Node Overlaps             = 0

Phase 2 Router Initialization | Checksum: 28c556322

Time (s): cpu = 00:00:40 ; elapsed = 00:00:29 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1373 ; free virtual = 25803

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 28c556322

Time (s): cpu = 00:00:40 ; elapsed = 00:00:29 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1373 ; free virtual = 25802

Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 24b42fd4c

Time (s): cpu = 00:00:42 ; elapsed = 00:00:29 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1372 ; free virtual = 25802
Phase 3 Initial Routing | Checksum: 24b42fd4c

Time (s): cpu = 00:00:42 ; elapsed = 00:00:29 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1371 ; free virtual = 25801

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 522
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.540  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 1de4c7464

Time (s): cpu = 00:00:45 ; elapsed = 00:00:30 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1377 ; free virtual = 25807
Phase 4 Rip-up And Reroute | Checksum: 1de4c7464

Time (s): cpu = 00:00:45 ; elapsed = 00:00:30 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1377 ; free virtual = 25807

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 1de4c7464

Time (s): cpu = 00:00:45 ; elapsed = 00:00:30 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1377 ; free virtual = 25807

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1de4c7464

Time (s): cpu = 00:00:45 ; elapsed = 00:00:30 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1377 ; free virtual = 25807
Phase 5 Delay and Skew Optimization | Checksum: 1de4c7464

Time (s): cpu = 00:00:45 ; elapsed = 00:00:30 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1377 ; free virtual = 25807

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 189d40d88

Time (s): cpu = 00:00:46 ; elapsed = 00:00:30 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1377 ; free virtual = 25807
INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.636  | TNS=0.000  | WHS=0.364  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 189d40d88

Time (s): cpu = 00:00:46 ; elapsed = 00:00:30 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1377 ; free virtual = 25807
Phase 6 Post Hold Fix | Checksum: 189d40d88

Time (s): cpu = 00:00:46 ; elapsed = 00:00:30 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1377 ; free virtual = 25807

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.892371 %
  Global Horizontal Routing Utilization  = 1.1082 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 189d40d88

Time (s): cpu = 00:00:46 ; elapsed = 00:00:31 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1377 ; free virtual = 25807

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 189d40d88

Time (s): cpu = 00:00:46 ; elapsed = 00:00:31 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1377 ; free virtual = 25806

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1f7d28ebb

Time (s): cpu = 00:00:46 ; elapsed = 00:00:31 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1377 ; free virtual = 25806

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.636  | TNS=0.000  | WHS=0.364  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 1f7d28ebb

Time (s): cpu = 00:00:47 ; elapsed = 00:00:31 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1377 ; free virtual = 25806
INFO: [Route 35-16] Router Completed Successfully

Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 26f2b4d79

Time (s): cpu = 00:00:47 ; elapsed = 00:00:31 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1369 ; free virtual = 25798
Ending Routing Task | Checksum: 26f2b4d79

Time (s): cpu = 00:00:47 ; elapsed = 00:00:31 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1377 ; free virtual = 25807

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:32 . Memory (MB): peak = 2795.184 ; gain = 0.000 ; free physical = 1371 ; free virtual = 25801
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (2683)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (8580)
5. checking no_input_delay (10)
6. checking no_output_delay (17)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (2683)
---------------------------
 There are 2683 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH)


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (8580)
---------------------------------------------------
 There are 8580 pins that are not constrained for maximum delay. (HIGH)

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (10)
-------------------------------
 There are 10 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (17)
--------------------------------
 There are 17 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      8.661        0.000                      0                    1        0.380        0.000                      0                    1        4.500        0.000                       0                     3  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock        Waveform(ns)       Period(ns)      Frequency(MHz)
-----        ------------       ----------      --------------
sys_clk_pin  {0.000 5.000}      10.000          100.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
sys_clk_pin         8.661        0.000                      0                    1        0.380        0.000                      0                    1        4.500        0.000                       0                     3  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
WARN  (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP SOC/Core/Mdu/acumulador0 output SOC/Core/Mdu/acumulador0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP SOC/Core/Mdu/acumulador0__0 output SOC/Core/Mdu/acumulador0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP SOC/Core/Mdu/acumulador0 multiplier stage SOC/Core/Mdu/acumulador0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP SOC/Core/Mdu/acumulador0__0 multiplier stage SOC/Core/Mdu/acumulador0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP SOC/Core/Mdu/acumulador_reg multiplier stage SOC/Core/Mdu/acumulador_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP SOC/Core/Mdu/acumulador_reg__0 multiplier stage SOC/Core/Mdu/acumulador_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 7 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Tue Jul  2 02:07:29 2024

[Pipeline] }
[Pipeline] // stage
Loading site data...
[Pipeline] }
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./build/out.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 3112.309 ; gain = 245.238 ; free physical = 1361 ; free virtual = 25804
INFO: [Common 17-206] Exiting Vivado at Tue Jul  2 02:07:33 2024...
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
	0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] sh
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz   -> real 6.00MHz  
Open file DONE
Parse file DONE
load program
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] }

Loading: [======                                            ] 10.49%[Pipeline] // script

Load SRAM: [=========                                         ] 18.00%[Pipeline] }
[Pipeline] // stage
[Pipeline] }

Loading: [===========                                       ] 20.97%
Load SRAM: [===================                               ] 38.00%
Loading: [================                                  ] 31.46%
Load SRAM: [=============================                     ] 58.00%
Loading: [=====================                             ] 41.95%
Load SRAM: [=======================================           ] 78.00%
Loading: [===========================                       ] 52.43%
Load SRAM: [================================================= ] 98.00%
Load SRAM: [===================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1
[Pipeline] }

Loading: [================================                  ] 62.92%Lock released on resource [nexys4]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }

Loading: [=====================================             ] 73.40%[Pipeline] // stage
[Pipeline] }

Loading: [==========================================        ] 83.89%
Loading: [================================================  ] 94.38%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
Rodando teste na Nexys 4
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ echo testando na ecp5
testando na ecp5
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo testando na tang nano
testando na tang nano
[Pipeline] sh
+ echo testando na tang nano
testando na tang nano
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // script
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS