Console Output

Started by user Julio Nunes Avelar
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/Risco-5
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf Risco-5
[Pipeline] sh
+ git clone --recursive https://github.com/JN513/Risco-5.git Risco-5
Cloning into 'Risco-5'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/Risco-5/Risco-5
[Pipeline] {
[Pipeline] sh
+ iverilog -o simulation.out -g2005 -s soc_tb src/core/alu.v src/core/alu_control.v src/core/control_unit.v src/core/core.v src/core/csr_unit.v src/core/immediate_generator.v src/core/mdu.v src/core/mux.v src/core/pc.v src/core/registers.v tests/soc_test.v src/peripheral/bus.v src/peripheral/fifo.v src/peripheral/gpios.v src/peripheral/gpio.v src/peripheral/leds.v src/peripheral/memory.v src/peripheral/pwm.v src/peripheral/soc.v src/peripheral/uart_rx.v src/peripheral/uart_tx.v src/peripheral/uart.v
+ vvp simulation.out
ERROR: src/peripheral/memory.v:35: $readmemh: Unable to open software/memory/generic.hex for reading.
VCD Error: tests/soc_test.v:32: Unable to open build/soc.vcd for output.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/Risco-5/Risco-5
[Pipeline] {
[Pipeline] dir
Running in /var/lib/jenkins/workspace/Risco-5/Risco-5
[Pipeline] {
[Pipeline] echo
Iniciando síntese para FPGA colorlight_i9.
[Pipeline] sh
[Pipeline] echo
Iniciando síntese para FPGA digilent_nexys4_ddr.
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b colorlight_i9
[Pipeline] sh
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b digilent_nexys4_ddr
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/Risco-5/Risco-5/build_colorlight_i9.tcl
Makefile executado com sucesso.
Sa��da do Makefile:
/eda/oss-cad-suite/bin/yosys -c /var/lib/jenkins/workspace/Risco-5/Risco-5/build_colorlight_i9.tcl -DID=0x6a6a6a6a -DCLOCK_FREQ=25000000 -DMEMORY_SIZE=4096

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)

-- Running command `read -define ID=0x6a6a6a6a CLOCK_FREQ=25000000 MEMORY_SIZE=4096' --

1. Executing Verilog-2005 frontend: /eda/processor-ci/rtl/Risco-5.v
Parsing Verilog input from `/eda/processor-ci/rtl/Risco-5.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v' to AST representation.
Generating RTLIL representation for module `\Alu'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu_control.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu_control.v' to AST representation.
Generating RTLIL representation for module `\ALU_Control'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v' to AST representation.
Generating RTLIL representation for module `\Control_Unit'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v' to AST representation.
Generating RTLIL representation for module `\Core'.
/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:187: Warning: Identifier `\pc_source' is implicitly declared.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v' to AST representation.
Generating RTLIL representation for module `\CSR_Unit'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/immediate_generator.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/immediate_generator.v' to AST representation.
Generating RTLIL representation for module `\Immediate_Generator'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v' to AST representation.
Generating RTLIL representation for module `\MDU'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mux.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mux.v' to AST representation.
Generating RTLIL representation for module `\MUX'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/pc.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/pc.v' to AST representation.
Generating RTLIL representation for module `\PC'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v
Parsing Verilog input from `/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v' to AST representation.
Generating RTLIL representation for module `\Registers'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/uart.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_rx'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tx'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/fifo.v
Parsing Verilog input from `/eda/processor-ci-controller/src/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/reset.v
Parsing Verilog input from `/eda/processor-ci-controller/src/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/clk_divider.v
Parsing Verilog input from `/eda/processor-ci-controller/src/clk_divider.v' to AST representation.
Generating RTLIL representation for module `\ClkDivider'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/memory.v
Parsing Verilog input from `/eda/processor-ci-controller/src/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/interpreter.v
Parsing Verilog input from `/eda/processor-ci-controller/src/interpreter.v' to AST representation.
Generating RTLIL representation for module `\Interpreter'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/controller.v
Parsing Verilog input from `/eda/processor-ci-controller/src/controller.v' to AST representation.
Generating RTLIL representation for module `\Controller'.
Successfully finished Verilog frontend.

21. Executing SYNTH_ECP5 pass.

21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

21.3. Executing HIERARCHY pass (managing design hierarchy).

21.3.1. Finding top of design hierarchy..
root of   2 design levels: Controller          
root of   0 design levels: Interpreter         
root of   0 design levels: Memory              
root of   0 design levels: ClkDivider          
root of   0 design levels: ResetBootSystem     
root of   0 design levels: FIFO                
root of   0 design levels: uart_tx             
root of   0 design levels: uart_rx             
root of   1 design levels: UART                
root of   0 design levels: Registers           
root of   0 design levels: PC                  
root of   0 design levels: MUX                 
root of   0 design levels: MDU                 
root of   0 design levels: Immediate_Generator 
root of   0 design levels: CSR_Unit            
root of   1 design levels: Core                
root of   0 design levels: Control_Unit        
root of   0 design levels: ALU_Control         
root of   0 design levels: Alu                 
root of   3 design levels: top                 
Automatically selected top as design top module.

21.3.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \ResetBootSystem
Used module:     \Core
Used module:         \CSR_Unit
Used module:         \Immediate_Generator
Used module:         \Alu
Used module:         \ALU_Control
Used module:         \Control_Unit
Used module:         \Registers
Used module:         \MUX
Used module:         \MDU
Used module:         \PC
Used module:     \Controller
Used module:         \Memory
Used module:         \UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \CYCLES = 20

21.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \BOOT_ADDRESS = 0

21.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\Core'.
Parameter \BOOT_ADDRESS = 0
Generating RTLIL representation for module `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000'.
/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:187: Warning: Identifier `\pc_source' is implicitly declared.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

21.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\Controller'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

21.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

21.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20

21.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12

21.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12
Generating RTLIL representation for module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

21.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

21.3.13. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:         \CSR_Unit
Used module:         \Immediate_Generator
Used module:         \Alu
Used module:         \ALU_Control
Used module:         \Control_Unit
Used module:         \Registers
Used module:         \MUX
Used module:         \MDU
Used module:         \PC
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         \Memory
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

21.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20

21.3.15. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32

21.3.16. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32
Generating RTLIL representation for module `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider'.

21.3.17. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:         \CSR_Unit
Used module:         \Immediate_Generator
Used module:         \Alu
Used module:         \ALU_Control
Used module:         \Control_Unit
Used module:         \Registers
Used module:         \MUX
Used module:         \MDU
Used module:         \PC
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

21.3.19. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

21.3.20. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:         \CSR_Unit
Used module:         \Immediate_Generator
Used module:         \Alu
Used module:         \ALU_Control
Used module:         \Control_Unit
Used module:         \Registers
Used module:         \MUX
Used module:         \MDU
Used module:         \PC
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider

21.3.21. Analyzing design hierarchy..
Top module:  \top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000
Used module:         \CSR_Unit
Used module:         \Immediate_Generator
Used module:         \Alu
Used module:         \ALU_Control
Used module:         \Control_Unit
Used module:         \Registers
Used module:         \MUX
Used module:         \MDU
Used module:         \PC
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Removing unused module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Removing unused module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Removing unused module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Removing unused module `\Controller'.
Removing unused module `\Interpreter'.
Removing unused module `\Memory'.
Removing unused module `\ClkDivider'.
Removing unused module `\ResetBootSystem'.
Removing unused module `\FIFO'.
Removing unused module `\uart_tx'.
Removing unused module `\uart_rx'.
Removing unused module `\UART'.
Removing unused module `\Core'.
Removed 15 unused modules.

21.4. Executing PROC pass (convert processes to netlists).

21.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$587'.
Found and cleaned up 1 empty switch in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$791'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$791'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:130$106'.
Cleaned up 3 empty switches.

21.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$694 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$646 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$588 in module TRELLIS_DPR16X4.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:36$971 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:25$963 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1164 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1162 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1154 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1151 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1145 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1140 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1135 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1126 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1113 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1111 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1103 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1089 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1083 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1078 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:57$1065 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:36$1056 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 15 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/interpreter.v:116$1020 in module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Removed 1 dead cases from process $proc$/eda/processor-ci-controller/modules/uart.v:203$1012 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:203$1012 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:187$1007 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:132$1002 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:74$997 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/memory.v:36$780 in module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/controller.v:113$769 in module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:305$723 in module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Marked 2 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:33$170 in module Registers.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/pc.v:15$159 in module PC.
Removed 1 dead cases from process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mux.v:14$158 in module MUX.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mux.v:14$158 in module MUX.
Marked 5 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:88$121 in module MDU.
Marked 4 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:50$113 in module MDU.
Marked 2 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/immediate_generator.v:18$112 in module Immediate_Generator.
Marked 2 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:130$106 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$104 in module CSR_Unit.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:78$103 in module CSR_Unit.
Marked 5 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/reset.v:25$697 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:703$79 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:693$78 in module Control_Unit.
Marked 21 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32 in module Control_Unit.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:149$31 in module Control_Unit.
Removed 1 dead cases from process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu_control.v:9$23 in module ALU_Control.
Marked 4 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu_control.v:9$23 in module ALU_Control.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:26$3 in module Alu.
Removed a total of 3 dead cases.

21.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 17 redundant assignments.
Promoted 141 assignments to connections.

21.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$695'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$996'.
  Set init value: \read_ptr = 6'000000
  Set init value: \write_ptr = 6'000000
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1166'.
  Set init value: \i = 0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1119'.
  Set init value: \i = 0
Found init rule in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1071'.
  Set init value: \clk_o_auto = 1'0
  Set init value: \clk_counter = 0
  Set init value: \pulse_counter = 0
Found init rule in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1049'.
  Set init value: \state = 8'00000000
  Set init value: \counter = 8'00000000
  Set init value: \read_buffer = 0
  Set init value: \timeout = 0
  Set init value: \accumulator = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1019'.
  Set init value: \read_data = 0
  Set init value: \read_response = 1'0
  Set init value: \write_response = 1'0
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
  Set init value: \counter_write = 3'000
  Set init value: \counter_read = 3'000
  Set init value: \state_read = 4'0000
  Set init value: \state_write = 4'0000
Found init rule in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:0$726'.
  Set init value: \instruction_register = 0
  Set init value: \memory_register = 0
  Set init value: \alu_out_register = 0
  Set init value: \register_data_1 = 0
  Set init value: \register_data_2 = 0
  Set init value: \pc_old = 0
Found init rule in `\PC.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/pc.v:0$162'.
  Set init value: \Output = 0
Found init rule in `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:0$157'.
  Set init value: \state_mul = 2'00
  Set init value: \state_div = 2'00
  Set init value: \Data_X = 0
  Set init value: \Data_Y = 0
  Set init value: \MUL_RD = 0
  Set init value: \acumulador = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:0$111'.
  Set init value: \mepc = 0
  Set init value: \mscratch = 0
  Set init value: \mcause = 0
  Set init value: \mtval = 0
  Set init value: \mtvec = 0
  Set init value: \mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \minstret = 64'0000000000000000000000000000000000000000000000000000000000000000
  Set init value: \utime = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$704'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000
Found init rule in `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:0$80'.
  Set init value: \memory_read = 1'0
  Set init value: \memory_write = 1'0
  Set init value: \is_immediate = 1'0
  Set init value: \pc_write = 1'0
  Set init value: \ir_write = 1'0
  Set init value: \pc_source = 1'0
  Set init value: \reg_write = 1'0
  Set init value: \pc_write_cond = 1'0
  Set init value: \csr_write_enable = 1'0
  Set init value: \alu_input_selector = 1'0
  Set init value: \save_address = 1'0
  Set init value: \save_value = 1'0
  Set init value: \save_value_2 = 1'0
  Set init value: \save_write_value = 1'0
  Set init value: \control_memory_op = 1'0
  Set init value: \write_data_in = 1'0
  Set init value: \mdu_start = 1'0
  Set init value: \lorD = 2'00
  Set init value: \aluop = 2'00
  Set init value: \alu_src_a = 3'000
  Set init value: \alu_src_b = 3'000
  Set init value: \memory_to_reg = 3'000
  Set init value: \control_unit_memory_op = 3'010
  Set init value: \control_unit_aluop = 4'0000
  Set init value: \state = 6'000000
  Set init value: \nextstate = 6'000000

21.4.5. Executing PROC_ARST pass (detect async resets in processes).

21.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~151 debug messages>

21.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$695'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$694'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$646'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$645_EN[3:0]$652
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$645_DATA[3:0]$651
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$645_ADDR[3:0]$650
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$588'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$586_EN[3:0]$594
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$586_DATA[3:0]$593
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$586_ADDR[3:0]$592
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$587'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$996'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$971'.
     1/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$983
     2/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_DATA[7:0]$982
     3/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_ADDR[5:0]$981
     4/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$977
     5/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_DATA[7:0]$976
     6/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_ADDR[5:0]$975
     7/7: $0\write_ptr[5:0]
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$963'.
     1/2: $0\read_ptr[5:0]
     2/2: $0\read_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1166'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1164'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1162'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1154'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1151'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1145'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1140'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1135'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1126'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1119'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1113'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1111'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1103'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1089'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1083'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1078'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1071'.
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1065'.
     1/1: $0\pulse_counter[31:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1056'.
     1/2: $0\clk_counter[31:0]
     2/2: $0\clk_o_auto[0:0]
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1049'.
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
     1/28: $0\state[7:0]
     2/28: $0\reset_bus[0:0]
     3/28: $0\memory_write[0:0]
     4/28: $0\memory_read[0:0]
     5/28: $0\write_pulse[0:0]
     6/28: $0\core_reset[0:0]
     7/28: $0\communication_write[0:0]
     8/28: $0\communication_read[0:0]
     9/28: $0\temp_buffer[63:0]
    10/28: $0\accumulator[63:0]
    11/28: $0\timeout_counter[31:0]
    12/28: $0\timeout[31:0]
    13/28: $0\read_buffer[31:0]
    14/28: $0\communication_buffer[31:0]
    15/28: $0\num_of_positions[23:0]
    16/28: $0\num_of_pages[23:0]
    17/28: $0\return_state[7:0]
    18/28: $0\memory_page_number[23:0]
    19/28: $0\memory_mux_selector[0:0]
    20/28: $0\end_position[31:0]
    21/28: $0\memory_page_size[23:0]
    22/28: $0\bus_mode[0:0]
    23/28: $0\num_of_cycles_to_pulse[31:0]
    24/28: $0\core_clk_enable[0:0]
    25/28: $0\communication_write_data[31:0]
    26/28: $0\counter[7:0]
    27/28: $0\write_data[31:0]
    28/28: $0\address[31:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1019'.
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1012'.
     1/4: $0\tx_fifo_read[0:0]
     2/4: $0\uart_tx_en[0:0]
     3/4: $0\tx_fifo_read_state[1:0]
     4/4: $0\uart_tx_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1007'.
     1/2: $0\rx_fifo_write[0:0]
     2/2: $0\rx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
     1/6: $0\tx_fifo_write[0:0]
     2/6: $0\write_response[0:0]
     3/6: $0\state_write[3:0]
     4/6: $0\counter_write[2:0]
     5/6: $0\write_data_buffer[31:0]
     6/6: $0\tx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$997'.
     1/5: $0\read_response[0:0]
     2/5: $0\rx_fifo_read[0:0]
     3/5: $0\state_read[3:0]
     4/5: $0\counter_read[2:0]
     5/5: $0\read_data[31:0]
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$790'.
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$780'.
     1/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$789
     2/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_DATA[31:0]$788
     3/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_ADDR[31:0]$787
     4/4: $0\read_sync[31:0]
Creating decoders for process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$769'.
     1/1: $0\finish_execution[0:0]
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:0$726'.
Creating decoders for process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:305$723'.
     1/7: $0\alu_out_register[31:0]
     2/7: $0\register_data_2[31:0]
     3/7: $0\register_data_1[31:0]
     4/7: $0\memory_register[31:0]
     5/7: $0\mdu_out_reg[31:0]
     6/7: $0\pc_old[31:0]
     7/7: $0\instruction_register[31:0]
Creating decoders for process `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:0$188'.
Creating decoders for process `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:33$170'.
     1/9: $2$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$185
     2/9: $2$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_DATA[31:0]$184
     3/9: $2$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_ADDR[4:0]$183
     4/9: $2$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$186
     5/9: $1$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$177
     6/9: $1$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$181
     7/9: $1$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$180
     8/9: $1$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_DATA[31:0]$179
     9/9: $1$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_ADDR[4:0]$178
Creating decoders for process `\PC.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/pc.v:0$162'.
Creating decoders for process `\PC.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/pc.v:15$159'.
     1/1: $0\Output[31:0]
Creating decoders for process `\MUX.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mux.v:14$158'.
     1/1: $1\S[31:0]
Creating decoders for process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:0$157'.
Creating decoders for process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:88$121'.
     1/8: $0\state_div[1:0]
     2/8: $0\div_done[0:0]
     3/8: $0\divisor[63:0]
     4/8: $0\DIV_RD[31:0]
     5/8: $0\quociente_msk[31:0]
     6/8: $0\quociente[31:0]
     7/8: $0\dividendo[31:0]
     8/8: $0\negativo[0:0]
Creating decoders for process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:50$113'.
     1/6: $0\state_mul[1:0]
     2/6: $0\mul_done[0:0]
     3/6: $0\acumulador[63:0]
     4/6: $0\MUL_RD[31:0]
     5/6: $0\Data_Y[31:0]
     6/6: $0\Data_X[31:0]
Creating decoders for process `\Immediate_Generator.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/immediate_generator.v:18$112'.
     1/2: $2\immediate[31:0]
     2/2: $1\immediate[31:0]
Creating decoders for process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:0$111'.
Creating decoders for process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:130$106'.
     1/1: $0\minstret[63:0]
Creating decoders for process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$104'.
     1/7: $0\mcycle[63:0]
     2/7: $0\utime[63:0]
     3/7: $0\mtvec[31:0]
     4/7: $0\mtval[31:0]
     5/7: $0\mcause[31:0]
     6/7: $0\mscratch[31:0]
     7/7: $0\mepc[31:0]
Creating decoders for process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:78$103'.
     1/1: $0\csr_data_out[31:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$704'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$697'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]
Creating decoders for process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:0$80'.
Creating decoders for process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:703$79'.
     1/2: $0\clear_hal_byte_one_block_option_2[2:0]
     2/2: $0\clear_hal_byte_one_block_option[2:0]
Creating decoders for process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:693$78'.
     1/1: $0\wb_filter[2:0]
Creating decoders for process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
     1/23: $0\mdu_start[0:0]
     2/23: $0\save_write_value[0:0]
     3/23: $0\write_data_in[0:0]
     4/23: $0\save_value_2[0:0]
     5/23: $0\save_value[0:0]
     6/23: $0\control_memory_op[0:0]
     7/23: $0\save_address[0:0]
     8/23: $0\control_unit_aluop[3:0]
     9/23: $0\alu_input_selector[0:0]
    10/23: $0\csr_write_enable[0:0]
    11/23: $0\is_immediate[0:0]
    12/23: $0\reg_write[0:0]
    13/23: $0\alu_src_a[2:0]
    14/23: $0\alu_src_b[2:0]
    15/23: $0\aluop[1:0]
    16/23: $0\pc_source[0:0]
    17/23: $0\memory_to_reg[2:0]
    18/23: $0\memory_write[0:0]
    19/23: $0\memory_read[0:0]
    20/23: $0\lorD[1:0]
    21/23: $0\ir_write[0:0]
    22/23: $0\pc_write[0:0]
    23/23: $0\pc_write_cond[0:0]
Creating decoders for process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32'.
     1/21: $21\nextstate[5:0]
     2/21: $20\nextstate[5:0]
     3/21: $19\nextstate[5:0]
     4/21: $18\nextstate[5:0]
     5/21: $17\nextstate[5:0]
     6/21: $16\nextstate[5:0]
     7/21: $15\nextstate[5:0]
     8/21: $14\nextstate[5:0]
     9/21: $13\nextstate[5:0]
    10/21: $12\nextstate[5:0]
    11/21: $11\nextstate[5:0]
    12/21: $10\nextstate[5:0]
    13/21: $9\nextstate[5:0]
    14/21: $8\nextstate[5:0]
    15/21: $7\nextstate[5:0]
    16/21: $6\nextstate[5:0]
    17/21: $5\nextstate[5:0]
    18/21: $4\nextstate[5:0]
    19/21: $3\nextstate[5:0]
    20/21: $2\nextstate[5:0]
    21/21: $1\nextstate[5:0]
Creating decoders for process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:149$31'.
     1/1: $0\state[5:0]
Creating decoders for process `\ALU_Control.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu_control.v:9$23'.
     1/1: $0\aluop_out[3:0]
Creating decoders for process `\Alu.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:26$3'.
     1/1: $0\ALU_out_S[31:0]

21.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1135'.
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1078'.
No latch inferred for signal `\Registers.$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:22$163_EN' from process `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:0$188'.
No latch inferred for signal `\MUX.\S' from process `\MUX.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mux.v:14$158'.
No latch inferred for signal `\Immediate_Generator.\immediate' from process `\Immediate_Generator.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/immediate_generator.v:18$112'.
No latch inferred for signal `\CSR_Unit.\csr_data_out' from process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:78$103'.
No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:703$79'.
No latch inferred for signal `\Control_Unit.\clear_hal_byte_one_block_option_2' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:703$79'.
No latch inferred for signal `\Control_Unit.\wb_filter' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:693$78'.
No latch inferred for signal `\Control_Unit.\memory_read' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_read` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\memory_write' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_write` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\is_immediate' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\is_immediate` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\pc_write' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\ir_write' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\ir_write` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\pc_source' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_source` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\reg_write' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\reg_write` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\pc_write_cond' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\pc_write_cond` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\csr_write_enable' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\csr_write_enable` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\alu_input_selector' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_input_selector` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\save_address' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_address` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\save_value' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\save_value_2' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_value_2` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\save_write_value' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\save_write_value` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\control_memory_op' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_memory_op` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\write_data_in' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\write_data_in` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\mdu_start' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\mdu_start` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\lorD' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [0]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\lorD [1]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\aluop' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [0]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\aluop [1]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\alu_src_a' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [0]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [1]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_a [2]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\alu_src_b' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [0]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [1]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\alu_src_b [2]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\memory_to_reg' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [0]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [1]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\memory_to_reg [2]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\control_unit_memory_op' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [0]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'1 for non-memory siginal `\Control_Unit.\control_unit_memory_op [1]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_memory_op [2]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\control_unit_aluop' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [0]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [1]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [2]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\control_unit_aluop [3]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65`.
No latch inferred for signal `\Control_Unit.\nextstate' from process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32'.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [0]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [1]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [2]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [3]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [4]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32`.
Removing init bit 1'0 for non-memory siginal `\Control_Unit.\nextstate [5]` in process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32`.
No latch inferred for signal `\ALU_Control.\aluop_out' from process `\ALU_Control.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu_control.v:9$23'.
No latch inferred for signal `\Alu.\ALU_out_S' from process `\Alu.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:26$3'.

21.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$694'.
  created $dff cell `$procdff$4122' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$630_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$631_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$632_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$633_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$634_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$635_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$636_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$637_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$638_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$639_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$640_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$641_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$642_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$643_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$644_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$645_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$646'.
  created $dff cell `$procdff$4123' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$645_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$646'.
  created $dff cell `$procdff$4124' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$645_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$646'.
  created $dff cell `$procdff$4125' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$570_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$571_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$572_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$573_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$574_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$575_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$576_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$577_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$578_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$579_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$580_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$581_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$582_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$583_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$584_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$585_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$586_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$588'.
  created $dff cell `$procdff$4126' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$586_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$588'.
  created $dff cell `$procdff$4127' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$586_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$588'.
  created $dff cell `$procdff$4128' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$587'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$971'.
  created $dff cell `$procdff$4129' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$971'.
  created $dff cell `$procdff$4130' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$971'.
  created $dff cell `$procdff$4131' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$971'.
  created $dff cell `$procdff$4132' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_data' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$963'.
  created $dff cell `$procdff$4133' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$963'.
  created $dff cell `$procdff$4134' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1164'.
  created $dff cell `$procdff$4135' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1164'.
  created $dff cell `$procdff$4136' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1162'.
  created $dff cell `$procdff$4137' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1154'.
  created $dff cell `$procdff$4138' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1151'.
  created $dff cell `$procdff$4139' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1145'.
  created $dff cell `$procdff$4140' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1140'.
  created $dff cell `$procdff$4141' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1140'.
  created $dff cell `$procdff$4142' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1126'.
  created $dff cell `$procdff$4143' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1113'.
  created $dff cell `$procdff$4144' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1111'.
  created $dff cell `$procdff$4145' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1103'.
  created $dff cell `$procdff$4146' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1089'.
  created $dff cell `$procdff$4147' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1083'.
  created $dff cell `$procdff$4148' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1083'.
  created $dff cell `$procdff$4149' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\pulse_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1065'.
  created $dff cell `$procdff$4150' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_o_auto' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1056'.
  created $dff cell `$procdff$4151' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1056'.
  created $dff cell `$procdff$4152' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4153' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4154' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\address' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4155' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4156' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4157' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4158' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4159' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4160' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4161' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4162' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_clk_enable' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4163' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_reset' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4164' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_cycles_to_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4165' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\reset_bus' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4166' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\bus_mode' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4167' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_size' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4168' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\end_position' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4169' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_mux_selector' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4170' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_number' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4171' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\return_state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4172' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_pages' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4173' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_positions' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4174' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4175' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\read_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4176' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4177' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout_counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4178' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\accumulator' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4179' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\temp_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
  created $dff cell `$procdff$4180' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_en' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1012'.
  created $dff cell `$procdff$4181' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1012'.
  created $dff cell `$procdff$4182' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1012'.
  created $dff cell `$procdff$4183' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read_state' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1012'.
  created $dff cell `$procdff$4184' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1007'.
  created $dff cell `$procdff$4185' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1007'.
  created $dff cell `$procdff$4186' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
  created $dff cell `$procdff$4187' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
  created $dff cell `$procdff$4188' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
  created $dff cell `$procdff$4189' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_data_buffer' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
  created $dff cell `$procdff$4190' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
  created $dff cell `$procdff$4191' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
  created $dff cell `$procdff$4192' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$997'.
  created $dff cell `$procdff$4193' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$997'.
  created $dff cell `$procdff$4194' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$997'.
  created $dff cell `$procdff$4195' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$997'.
  created $dff cell `$procdff$4196' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$997'.
  created $dff cell `$procdff$4197' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_write_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$790'.
  created $dff cell `$procdff$4198' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_read_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$790'.
  created $dff cell `$procdff$4199' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\read_sync' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$780'.
  created $dff cell `$procdff$4200' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_ADDR' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$780'.
  created $dff cell `$procdff$4201' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_DATA' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$780'.
  created $dff cell `$procdff$4202' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$780'.
  created $dff cell `$procdff$4203' with positive edge clock.
Creating register for signal `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.\finish_execution' using process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$769'.
  created $dff cell `$procdff$4204' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\instruction_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:305$723'.
  created $dff cell `$procdff$4205' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\memory_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:305$723'.
  created $dff cell `$procdff$4206' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\alu_out_register' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:305$723'.
  created $dff cell `$procdff$4207' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_1' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:305$723'.
  created $dff cell `$procdff$4208' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\register_data_2' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:305$723'.
  created $dff cell `$procdff$4209' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\pc_old' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:305$723'.
  created $dff cell `$procdff$4210' with positive edge clock.
Creating register for signal `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.\mdu_out_reg' using process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:305$723'.
  created $dff cell `$procdff$4211' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN' using process `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:33$170'.
  created $dff cell `$procdff$4212' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_ADDR' using process `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:33$170'.
  created $dff cell `$procdff$4213' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_DATA' using process `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:33$170'.
  created $dff cell `$procdff$4214' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN' using process `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:33$170'.
  created $dff cell `$procdff$4215' with positive edge clock.
Creating register for signal `\Registers.$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN' using process `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:33$170'.
  created $dff cell `$procdff$4216' with positive edge clock.
Creating register for signal `\PC.\Output' using process `\PC.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/pc.v:15$159'.
  created $dff cell `$procdff$4217' with positive edge clock.
Creating register for signal `\MDU.\div_done' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:88$121'.
  created $dff cell `$procdff$4218' with positive edge clock.
Creating register for signal `\MDU.\state_div' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:88$121'.
  created $dff cell `$procdff$4219' with positive edge clock.
Creating register for signal `\MDU.\negativo' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:88$121'.
  created $dff cell `$procdff$4220' with positive edge clock.
Creating register for signal `\MDU.\dividendo' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:88$121'.
  created $dff cell `$procdff$4221' with positive edge clock.
Creating register for signal `\MDU.\quociente' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:88$121'.
  created $dff cell `$procdff$4222' with positive edge clock.
Creating register for signal `\MDU.\quociente_msk' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:88$121'.
  created $dff cell `$procdff$4223' with positive edge clock.
Creating register for signal `\MDU.\DIV_RD' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:88$121'.
  created $dff cell `$procdff$4224' with positive edge clock.
Creating register for signal `\MDU.\divisor' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:88$121'.
  created $dff cell `$procdff$4225' with positive edge clock.
Creating register for signal `\MDU.\mul_done' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:50$113'.
  created $dff cell `$procdff$4226' with positive edge clock.
Creating register for signal `\MDU.\state_mul' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:50$113'.
  created $dff cell `$procdff$4227' with positive edge clock.
Creating register for signal `\MDU.\Data_X' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:50$113'.
  created $dff cell `$procdff$4228' with positive edge clock.
Creating register for signal `\MDU.\Data_Y' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:50$113'.
  created $dff cell `$procdff$4229' with positive edge clock.
Creating register for signal `\MDU.\MUL_RD' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:50$113'.
  created $dff cell `$procdff$4230' with positive edge clock.
Creating register for signal `\MDU.\acumulador' using process `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:50$113'.
  created $dff cell `$procdff$4231' with positive edge clock.
Creating register for signal `\CSR_Unit.\minstret' using process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:130$106'.
  created $dff cell `$procdff$4232' with positive edge clock.
Creating register for signal `\CSR_Unit.\mepc' using process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$104'.
  created $dff cell `$procdff$4233' with positive edge clock.
Creating register for signal `\CSR_Unit.\mscratch' using process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$104'.
  created $dff cell `$procdff$4234' with positive edge clock.
Creating register for signal `\CSR_Unit.\mcause' using process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$104'.
  created $dff cell `$procdff$4235' with positive edge clock.
Creating register for signal `\CSR_Unit.\mtval' using process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$104'.
  created $dff cell `$procdff$4236' with positive edge clock.
Creating register for signal `\CSR_Unit.\mtvec' using process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$104'.
  created $dff cell `$procdff$4237' with positive edge clock.
Creating register for signal `\CSR_Unit.\mcycle' using process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$104'.
  created $dff cell `$procdff$4238' with positive edge clock.
Creating register for signal `\CSR_Unit.\utime' using process `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$104'.
  created $dff cell `$procdff$4239' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$697'.
  created $dff cell `$procdff$4240' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$697'.
  created $dff cell `$procdff$4241' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$697'.
  created $dff cell `$procdff$4242' with positive edge clock.
Creating register for signal `\Control_Unit.\state' using process `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:149$31'.
  created $dff cell `$procdff$4243' with positive edge clock.

21.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$695'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$694'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$694'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$669'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$646'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$612'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$588'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$587'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$996'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$971'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$971'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$963'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$963'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1166'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1164'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1164'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1162'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1162'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1154'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1154'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1151'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1151'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1145'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1145'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1140'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1140'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1135'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1135'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1126'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1126'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1119'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1113'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1113'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1111'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1111'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1103'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1103'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1089'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1089'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1083'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1083'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1078'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1078'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1071'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1065'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1065'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1056'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1056'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1049'.
Found and cleaned up 15 empty switches in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1020'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1019'.
Found and cleaned up 3 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1012'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1012'.
Found and cleaned up 2 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1007'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1007'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1002'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$997'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$997'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$790'.
Found and cleaned up 2 empty switches in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$780'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$780'.
Found and cleaned up 4 empty switches in `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$769'.
Removing empty process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$769'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:0$726'.
Found and cleaned up 2 empty switches in `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:305$723'.
Removing empty process `$paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:305$723'.
Removing empty process `Registers.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:0$188'.
Found and cleaned up 2 empty switches in `\Registers.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:33$170'.
Removing empty process `Registers.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:33$170'.
Removing empty process `PC.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/pc.v:0$162'.
Found and cleaned up 2 empty switches in `\PC.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/pc.v:15$159'.
Removing empty process `PC.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/pc.v:15$159'.
Found and cleaned up 1 empty switch in `\MUX.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mux.v:14$158'.
Removing empty process `MUX.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mux.v:14$158'.
Removing empty process `MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:0$157'.
Found and cleaned up 6 empty switches in `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:88$121'.
Removing empty process `MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:88$121'.
Found and cleaned up 4 empty switches in `\MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:50$113'.
Removing empty process `MDU.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:50$113'.
Found and cleaned up 2 empty switches in `\Immediate_Generator.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/immediate_generator.v:18$112'.
Removing empty process `Immediate_Generator.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/immediate_generator.v:18$112'.
Removing empty process `CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:0$111'.
Found and cleaned up 4 empty switches in `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:130$106'.
Removing empty process `CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:130$106'.
Found and cleaned up 3 empty switches in `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$104'.
Removing empty process `CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:106$104'.
Found and cleaned up 1 empty switch in `\CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:78$103'.
Removing empty process `CSR_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:78$103'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$704'.
Found and cleaned up 6 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$697'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$697'.
Removing empty process `Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:0$80'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:703$79'.
Removing empty process `Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:703$79'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:693$78'.
Removing empty process `Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:693$78'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Removing empty process `Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:357$65'.
Found and cleaned up 21 empty switches in `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32'.
Removing empty process `Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:157$32'.
Found and cleaned up 1 empty switch in `\Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:149$31'.
Removing empty process `Control_Unit.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:149$31'.
Found and cleaned up 5 empty switches in `\ALU_Control.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu_control.v:9$23'.
Removing empty process `ALU_Control.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu_control.v:9$23'.
Found and cleaned up 1 empty switch in `\Alu.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:26$3'.
Removing empty process `Alu.$proc$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:26$3'.
Cleaned up 151 empty switches.

21.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
<suppressed ~5 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
<suppressed ~9 debug messages>
Optimizing module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
<suppressed ~15 debug messages>
Optimizing module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
<suppressed ~24 debug messages>
Optimizing module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
<suppressed ~3 debug messages>
Optimizing module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
<suppressed ~26 debug messages>
Optimizing module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
<suppressed ~6 debug messages>
Optimizing module Registers.
<suppressed ~2 debug messages>
Optimizing module PC.
<suppressed ~2 debug messages>
Optimizing module MUX.
<suppressed ~1 debug messages>
Optimizing module MDU.
<suppressed ~17 debug messages>
Optimizing module Immediate_Generator.
Optimizing module CSR_Unit.
<suppressed ~1 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~8 debug messages>
Optimizing module Control_Unit.
<suppressed ~25 debug messages>
Optimizing module ALU_Control.
<suppressed ~4 debug messages>
Optimizing module Alu.
<suppressed ~1 debug messages>
Optimizing module top.

21.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Deleting now unused module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Deleting now unused module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Deleting now unused module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Deleting now unused module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Deleting now unused module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Deleting now unused module $paramod\Core\BOOT_ADDRESS=32'00000000000000000000000000000000.
Deleting now unused module Registers.
Deleting now unused module PC.
Deleting now unused module MUX.
Deleting now unused module MDU.
Deleting now unused module Immediate_Generator.
Deleting now unused module CSR_Unit.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module Control_Unit.
Deleting now unused module ALU_Control.
Deleting now unused module Alu.
<suppressed ~25 debug messages>

21.6. Executing TRIBUF pass.

21.7. Executing DEMINOUT pass (demote inout ports to input or output).

21.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~50 debug messages>

21.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 119 unused cells and 977 unused wires.
<suppressed ~161 debug messages>

21.10. Executing CHECK pass (checking for obvious problems).
Checking module top...
Warning: Wire top.\miso is used but has no driver.
Warning: Wire top.\intr is used but has no driver.
Warning: Wire top.\ResetBootSystem.start is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [31] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [30] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [29] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [28] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [27] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [26] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [25] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [24] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [23] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [22] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [21] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [20] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [19] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [18] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [17] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [16] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [15] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [14] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [13] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [12] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [11] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [10] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [9] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [8] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [7] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [6] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [5] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [4] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [3] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [2] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [1] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.C [0] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [31] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [30] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [29] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [28] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [27] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [26] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [25] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [24] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [23] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [22] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [21] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [20] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [19] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [18] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [17] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [16] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [15] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [14] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [13] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [12] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [11] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [10] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [9] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [8] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [7] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [6] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [5] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [4] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [3] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [2] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [1] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.D [0] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [31] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [30] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [29] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [28] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [27] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [26] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [25] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [24] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [23] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [22] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [21] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [20] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [19] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [18] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [17] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [16] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [15] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [14] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [13] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [12] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [11] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [10] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [9] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [8] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [7] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [6] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [5] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [4] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [3] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [2] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [1] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.E [0] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [31] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [30] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [29] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [28] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [27] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [26] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [25] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [24] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [23] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [22] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [21] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [20] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [19] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [18] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [17] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [16] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [15] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [14] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [13] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [12] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [11] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [10] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [9] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [8] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [7] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [6] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [5] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [4] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [3] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [2] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [1] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.F [0] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [31] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [30] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [29] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [28] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [27] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [26] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [25] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [24] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [23] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [22] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [21] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [20] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [19] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [18] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [17] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [16] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [15] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [14] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [13] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [12] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [11] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [10] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [9] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [8] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [7] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [6] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [5] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [4] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [3] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [2] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [1] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.G [0] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [31] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [30] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [29] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [28] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [27] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [26] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [25] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [24] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [23] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [22] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [21] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [20] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [19] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [18] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [17] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [16] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [15] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [14] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [13] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [12] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [11] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [10] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [9] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [8] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [7] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [6] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [5] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [4] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [3] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [2] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [1] is used but has no driver.
Warning: Wire top.\Core.MemoryAddressMUX.H [0] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [31] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [30] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [29] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [28] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [27] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [26] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [25] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [24] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [23] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [22] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [21] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [20] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [19] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [18] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [17] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [16] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [15] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [14] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [13] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [12] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [11] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [10] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [9] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [8] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [7] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [6] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [5] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [4] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [3] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [2] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [1] is used but has no driver.
Warning: Wire top.\Core.AluInputBMUX.G [0] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [31] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [30] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [29] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [28] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [27] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [26] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [25] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [24] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [23] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [22] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [21] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [20] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [19] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [18] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [17] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [16] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [15] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [14] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [13] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [12] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [11] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [10] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [9] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [8] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [7] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [6] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [5] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [4] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [3] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [2] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [31] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [30] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [29] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [28] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [27] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [26] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [25] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [24] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [23] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [22] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [21] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [20] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [19] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [18] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [17] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [16] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [15] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [14] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [13] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [12] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [11] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [10] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [9] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [8] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [7] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [6] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [5] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [4] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [3] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [2] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [1] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.H [0] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [31] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [30] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [29] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [28] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [27] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [26] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [25] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [24] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [23] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [22] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [21] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [20] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [19] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [18] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [17] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [16] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [15] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [14] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [13] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [12] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [11] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [10] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [9] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [8] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [7] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [6] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [5] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [4] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [3] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [2] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [1] is used but has no driver.
Warning: Wire top.\Core.temp_write_value [0] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [1] is used but has no driver.
Warning: Wire top.\Core.AluInputAMUX.G [0] is used but has no driver.
Found and reported 323 problems.

21.11. Executing OPT pass (performing simple optimizations).

21.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~11 debug messages>

21.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~1065 debug messages>
Removed a total of 355 cells.

21.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1194.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1200.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1206.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1194.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1200.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1206.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3313.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3322.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3338.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3357.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3359.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3377.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3398.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3422.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3450.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3480.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3513.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3549.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3587.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3636.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3687.
    dead port 1/2 on $mux $flatten\Core.\Control_Unit.$procmux$3740.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3742.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3795.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3797.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3849.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3910.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3912.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$3974.
    dead port 2/2 on $mux $flatten\Core.\Control_Unit.$procmux$4029.
    dead port 2/2 on $mux $flatten\Core.\Immediate_Generator.$procmux$2692.
    dead port 1/9 on $pmux $flatten\Core.\MemoryAddressMUX.$procmux$2529.
    dead port 2/9 on $pmux $flatten\Core.\MemoryAddressMUX.$procmux$2529.
    dead port 3/9 on $pmux $flatten\Core.\MemoryAddressMUX.$procmux$2529.
    dead port 4/9 on $pmux $flatten\Core.\MemoryAddressMUX.$procmux$2529.
    dead port 1/9 on $pmux $flatten\Core.\PCSourceMUX.$procmux$2529.
    dead port 2/9 on $pmux $flatten\Core.\PCSourceMUX.$procmux$2529.
    dead port 3/9 on $pmux $flatten\Core.\PCSourceMUX.$procmux$2529.
    dead port 4/9 on $pmux $flatten\Core.\PCSourceMUX.$procmux$2529.
    dead port 5/9 on $pmux $flatten\Core.\PCSourceMUX.$procmux$2529.
    dead port 6/9 on $pmux $flatten\Core.\PCSourceMUX.$procmux$2529.
    dead port 1/2 on $mux $flatten\Core.\RegisterBank.$procmux$2489.
    dead port 1/2 on $mux $flatten\Core.\RegisterBank.$procmux$2495.
    dead port 1/2 on $mux $flatten\Core.\RegisterBank.$procmux$2501.
    dead port 1/2 on $mux $flatten\Core.\RegisterBank.$procmux$2507.
Removed 45 multiplexer ports.
<suppressed ~166 debug messages>

21.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2372: $auto$opt_reduce.cc:134:opt_pmux$4275
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1630: $auto$opt_reduce.cc:134:opt_pmux$4277
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1654: $auto$opt_reduce.cc:134:opt_pmux$4279
    New ctrl vector for $pmux cell $flatten\Core.\CSR_Unit.$procmux$2767: { $flatten\Core.\CSR_Unit.$procmux$2784_CMP $flatten\Core.\CSR_Unit.$procmux$2781_CMP $flatten\Core.\CSR_Unit.$procmux$2779_CMP $flatten\Core.\CSR_Unit.$procmux$2778_CMP $flatten\Core.\CSR_Unit.$procmux$2777_CMP $flatten\Core.\CSR_Unit.$procmux$2722_CMP $flatten\Core.\CSR_Unit.$procmux$2749_CMP $flatten\Core.\CSR_Unit.$procmux$2760_CMP $flatten\Core.\CSR_Unit.$procmux$2739_CMP $flatten\Core.\CSR_Unit.$procmux$2730_CMP $auto$opt_reduce.cc:134:opt_pmux$4287 $auto$opt_reduce.cc:134:opt_pmux$4285 $auto$opt_reduce.cc:134:opt_pmux$4283 $auto$opt_reduce.cc:134:opt_pmux$4281 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1676: $auto$opt_reduce.cc:134:opt_pmux$4289
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1687: $auto$opt_reduce.cc:134:opt_pmux$4291
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2832: { $flatten\Core.\Control_Unit.$procmux$2829_CMP $auto$opt_reduce.cc:134:opt_pmux$4293 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1735: $auto$opt_reduce.cc:134:opt_pmux$4295
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$2878: $auto$opt_reduce.cc:134:opt_pmux$4297
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3003: { $auto$opt_reduce.cc:134:opt_pmux$4301 $auto$opt_reduce.cc:134:opt_pmux$4299 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3034: $auto$opt_reduce.cc:134:opt_pmux$4303
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1777: $auto$opt_reduce.cc:134:opt_pmux$4305
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1802: { $flatten\Controller.\Interpreter.$procmux$1570_CMP $auto$opt_reduce.cc:134:opt_pmux$4307 $flatten\Controller.\Interpreter.$procmux$1560_CMP }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3060: $auto$opt_reduce.cc:134:opt_pmux$4309
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3063: $auto$opt_reduce.cc:134:opt_pmux$4311
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3071: { $flatten\Core.\Control_Unit.$procmux$3013_CMP $auto$opt_reduce.cc:134:opt_pmux$4323 $auto$opt_reduce.cc:134:opt_pmux$4321 $auto$opt_reduce.cc:134:opt_pmux$4319 $auto$opt_reduce.cc:134:opt_pmux$4317 $auto$opt_reduce.cc:134:opt_pmux$4315 $auto$opt_reduce.cc:134:opt_pmux$4313 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1855: { $auto$opt_reduce.cc:134:opt_pmux$4327 $auto$opt_reduce.cc:134:opt_pmux$4325 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Data_Memory.$procmux$2440:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0]
      New connections: $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [31:1] = { $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3110: { $flatten\Core.\Control_Unit.$procmux$3100_CMP $auto$opt_reduce.cc:134:opt_pmux$4341 $auto$opt_reduce.cc:134:opt_pmux$4339 $auto$opt_reduce.cc:134:opt_pmux$4337 $flatten\Core.\Control_Unit.$procmux$3010_CMP $auto$opt_reduce.cc:134:opt_pmux$4335 $flatten\Core.\Control_Unit.$procmux$3007_CMP $flatten\Core.\Control_Unit.$procmux$3006_CMP $flatten\Core.\Control_Unit.$procmux$3005_CMP $flatten\Core.\Control_Unit.$procmux$3004_CMP $auto$opt_reduce.cc:134:opt_pmux$4333 $auto$opt_reduce.cc:134:opt_pmux$4331 $auto$opt_reduce.cc:134:opt_pmux$4329 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1924: $auto$opt_reduce.cc:134:opt_pmux$4343
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1949: { $flatten\Controller.\Interpreter.$procmux$1570_CMP $auto$opt_reduce.cc:134:opt_pmux$4345 $flatten\Controller.\Interpreter.$procmux$1560_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1977: { $flatten\Controller.\Interpreter.$procmux$1556_CMP $flatten\Controller.\Interpreter.$procmux$1549_CMP $flatten\Controller.\Interpreter.$procmux$1538_CMP $flatten\Controller.\Interpreter.$procmux$1532_CMP $auto$opt_reduce.cc:134:opt_pmux$4347 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3148: { $auto$opt_reduce.cc:134:opt_pmux$4349 $flatten\Core.\Control_Unit.$procmux$3078_CMP }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3158: $auto$opt_reduce.cc:134:opt_pmux$4351
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3162: { $flatten\Core.\Control_Unit.$procmux$3069_CMP $auto$opt_reduce.cc:134:opt_pmux$4353 $flatten\Core.\Control_Unit.$procmux$3053_CMP $flatten\Core.\Control_Unit.$procmux$3064_CMP }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3182: $auto$opt_reduce.cc:134:opt_pmux$4355
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2009: { $auto$opt_reduce.cc:134:opt_pmux$4359 $auto$opt_reduce.cc:134:opt_pmux$4357 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3207: $auto$opt_reduce.cc:134:opt_pmux$4361
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3229: { $auto$opt_reduce.cc:134:opt_pmux$4365 $auto$opt_reduce.cc:134:opt_pmux$4363 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3294: $auto$opt_reduce.cc:134:opt_pmux$4367
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2091: { $flatten\Controller.\Interpreter.$procmux$1550_CMP $auto$opt_reduce.cc:134:opt_pmux$4369 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2102: { $flatten\Controller.\Interpreter.$procmux$1691_CMP $flatten\Controller.\Interpreter.$procmux$1590_CMP $auto$opt_reduce.cc:134:opt_pmux$4371 }
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2308: $auto$opt_reduce.cc:134:opt_pmux$4373
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2112: { $flatten\Controller.\Interpreter.$procmux$1589_CMP $auto$opt_reduce.cc:134:opt_pmux$4377 $auto$opt_reduce.cc:134:opt_pmux$4375 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3963: { $auto$opt_reduce.cc:134:opt_pmux$4379 $flatten\Core.\Control_Unit.$procmux$3911_CMP $flatten\Core.\Control_Unit.$procmux$3970_CMP $flatten\Core.\Control_Unit.$procmux$3969_CMP $flatten\Core.\Control_Unit.$procmux$3968_CMP $flatten\Core.\Control_Unit.$procmux$3967_CMP $flatten\Core.\Control_Unit.$procmux$3966_CMP $flatten\Core.\Control_Unit.$procmux$3965_CMP $flatten\Core.\Control_Unit.$procmux$3964_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1530: { $flatten\Controller.\Interpreter.$procmux$1624_CMP $flatten\Controller.\Interpreter.$procmux$1620_CMP $flatten\Controller.\Interpreter.$procmux$1616_CMP $flatten\Controller.\Interpreter.$procmux$1590_CMP $flatten\Controller.\Interpreter.$procmux$1589_CMP $flatten\Controller.\Interpreter.$procmux$1585_CMP $flatten\Controller.\Interpreter.$procmux$1584_CMP $flatten\Controller.\Interpreter.$procmux$1580_CMP $flatten\Controller.\Interpreter.$procmux$1570_CMP $flatten\Controller.\Interpreter.$procmux$1566_CMP $auto$opt_reduce.cc:134:opt_pmux$4387 $flatten\Controller.\Interpreter.$procmux$1561_CMP $flatten\Controller.\Interpreter.$procmux$1560_CMP $auto$opt_reduce.cc:134:opt_pmux$4385 $flatten\Controller.\Interpreter.$procmux$1555_CMP $flatten\Controller.\Interpreter.$procmux$1554_CMP $flatten\Controller.\Interpreter.$procmux$1549_CMP $flatten\Controller.\Interpreter.$procmux$1545_CMP $flatten\Controller.\Interpreter.$procmux$1544_CMP $auto$opt_reduce.cc:134:opt_pmux$4383 $flatten\Controller.\Interpreter.$procmux$1538_CMP $flatten\Controller.\Interpreter.$procmux$1537_CMP $flatten\Controller.\Interpreter.$procmux$1536_CMP $auto$opt_reduce.cc:134:opt_pmux$4381 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$4033: { $flatten\Core.\Control_Unit.$procmux$3214_CMP $flatten\Core.\Control_Unit.$procmux$3139_CMP $flatten\Core.\Control_Unit.$procmux$3105_CMP $flatten\Core.\Control_Unit.$procmux$3104_CMP $flatten\Core.\Control_Unit.$procmux$3212_CMP $flatten\Core.\Control_Unit.$procmux$3185_CMP $flatten\Core.\Control_Unit.$procmux$3077_CMP $auto$opt_reduce.cc:134:opt_pmux$4391 $flatten\Core.\Control_Unit.$procmux$3211_CMP $flatten\Core.\Control_Unit.$procmux$3017_CMP $flatten\Core.\Control_Unit.$procmux$3068_CMP $flatten\Core.\Control_Unit.$procmux$3102_CMP $flatten\Core.\Control_Unit.$procmux$3210_CMP $flatten\Core.\Control_Unit.$procmux$3016_CMP $flatten\Core.\Control_Unit.$procmux$3100_CMP $flatten\Core.\Control_Unit.$procmux$3209_CMP $flatten\Core.\Control_Unit.$procmux$3015_CMP $flatten\Core.\Control_Unit.$procmux$3014_CMP $flatten\Core.\Control_Unit.$procmux$3013_CMP $flatten\Core.\Control_Unit.$procmux$3012_CMP $flatten\Core.\Control_Unit.$procmux$3095_CMP $flatten\Core.\Control_Unit.$procmux$3094_CMP $flatten\Core.\Control_Unit.$procmux$3010_CMP $flatten\Core.\Control_Unit.$procmux$3009_CMP $auto$opt_reduce.cc:134:opt_pmux$4389 $flatten\Core.\Control_Unit.$procmux$3089_CMP $flatten\Core.\Control_Unit.$procmux$2880_CMP $flatten\Core.\Control_Unit.$procmux$3088_CMP $flatten\Core.\Control_Unit.$procmux$3208_CMP $flatten\Core.\Control_Unit.$procmux$3007_CMP $flatten\Core.\Control_Unit.$procmux$3006_CMP $flatten\Core.\Control_Unit.$procmux$3085_CMP $flatten\Core.\Control_Unit.$procmux$3005_CMP $flatten\Core.\Control_Unit.$procmux$3004_CMP $flatten\Core.\Control_Unit.$procmux$3082_CMP $flatten\Core.\Control_Unit.$procmux$2879_CMP $flatten\Core.\Control_Unit.$procmux$2845_CMP $flatten\Core.\Control_Unit.$procmux$3072_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2188: { $auto$opt_reduce.cc:134:opt_pmux$4393 $flatten\Controller.\Interpreter.$procmux$1589_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2212: { $flatten\Controller.\Interpreter.$procmux$1657_CMP $flatten\Controller.\Interpreter.$procmux$1656_CMP $auto$opt_reduce.cc:134:opt_pmux$4395 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2238: { $auto$opt_reduce.cc:134:opt_pmux$4397 $flatten\Controller.\Interpreter.$procmux$1656_CMP $flatten\Controller.\Interpreter.$procmux$1575_CMP $flatten\Controller.\Interpreter.$procmux$1570_CMP $flatten\Controller.\Interpreter.$procmux$1560_CMP }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Memory.$procmux$2440:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0]
      New connections: $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [31:1] = { $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_EN[31:0]$783 [0] }
    New ctrl vector for $pmux cell $flatten\Core.\Immediate_Generator.$procmux$2695: { $flatten\Core.\Control_Unit.$procmux$3968_CMP $flatten\Core.\Control_Unit.$procmux$3969_CMP $auto$opt_reduce.cc:134:opt_pmux$4401 $flatten\Core.\Control_Unit.$procmux$3970_CMP $auto$opt_reduce.cc:134:opt_pmux$4399 $flatten\Core.\Control_Unit.$procmux$3964_CMP $flatten\Core.\Control_Unit.$procmux$3972_CMP }
    Consolidated identical input bits for $mux cell $flatten\Core.\RegisterBank.$procmux$2486:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\RegisterBank.$procmux$2486_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Core.\RegisterBank.$procmux$2486_Y [0]
      New connections: $flatten\Core.\RegisterBank.$procmux$2486_Y [31:1] = { $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] $flatten\Core.\RegisterBank.$procmux$2486_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.\RegisterBank.$procmux$2504:
      Old ports: A=32'11111111111111111111111111111111, B=0, Y=$flatten\Core.\RegisterBank.$procmux$2504_Y
      New ports: A=1'1, B=1'0, Y=$flatten\Core.\RegisterBank.$procmux$2504_Y [0]
      New connections: $flatten\Core.\RegisterBank.$procmux$2504_Y [31:1] = { $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] $flatten\Core.\RegisterBank.$procmux$2504_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.\RegisterBank.$procmux$2510:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171
      New ports: A=1'0, B=1'1, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0]
      New connections: $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [31:1] = { $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:35$164_EN[31:0]$171 [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1209:
      Old ports: A=$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$983, B=8'00000000, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974
      New ports: A=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1191_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1209:
      Old ports: A=$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$983, B=8'00000000, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974
      New ports: A=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1191_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_EN[7:0]$974 [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.\RegisterBank.$procmux$2513:
      Old ports: A=$flatten\Core.\RegisterBank.$2$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$186, B=0, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175
      New ports: A=$flatten\Core.\RegisterBank.$procmux$2504_Y [0], B=1'0, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0]
      New connections: $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [31:1] = { $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:39$166_EN[31:0]$175 [0] }
    Consolidated identical input bits for $mux cell $flatten\Core.\RegisterBank.$procmux$2516:
      Old ports: A=$flatten\Core.\RegisterBank.$2$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$185, B=0, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174
      New ports: A=$flatten\Core.\RegisterBank.$procmux$2486_Y [0], B=1'0, Y=$flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0]
      New connections: $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [31:1] = { $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] $flatten\Core.\RegisterBank.$0$memwr$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:37$165_EN[31:0]$174 [0] }
  Optimizing cells in module \top.
Performed a total of 51 changes.

21.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~30 debug messages>
Removed a total of 10 cells.

21.11.6. Executing OPT_DFF pass (perform DFF optimizations).

21.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 425 unused wires.
<suppressed ~15 debug messages>

21.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.11.9. Rerunning OPT passes. (Maybe there is more to do..)

21.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~166 debug messages>

21.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1802: { $auto$opt_reduce.cc:134:opt_pmux$4307 $auto$opt_reduce.cc:134:opt_pmux$4403 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1949: { $auto$opt_reduce.cc:134:opt_pmux$4307 $auto$opt_reduce.cc:134:opt_pmux$4405 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2238: { $auto$opt_reduce.cc:134:opt_pmux$4397 $flatten\Controller.\Interpreter.$procmux$1656_CMP $flatten\Controller.\Interpreter.$procmux$1575_CMP $auto$opt_reduce.cc:134:opt_pmux$4407 }
    New ctrl vector for $pmux cell $flatten\Core.\Alu.$procmux$4107: { $flatten\Core.\Alu.$procmux$4121_CMP $flatten\Core.\Alu.$procmux$4120_CMP $flatten\Core.\Alu.$procmux$4119_CMP $flatten\Core.\Alu.$procmux$4118_CMP $auto$opt_reduce.cc:134:opt_pmux$4411 $flatten\Core.\Alu.$procmux$4115_CMP $flatten\Core.\Alu.$procmux$4114_CMP $flatten\Core.\Alu.$procmux$4113_CMP $flatten\Core.\Alu.$procmux$4112_CMP $flatten\Core.\Alu.$procmux$4111_CMP $flatten\Core.\Alu.$procmux$4110_CMP $auto$opt_reduce.cc:134:opt_pmux$4409 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$3110: { $flatten\Core.\Control_Unit.$procmux$3100_CMP $auto$opt_reduce.cc:134:opt_pmux$4341 $auto$opt_reduce.cc:134:opt_pmux$4339 $auto$opt_reduce.cc:134:opt_pmux$4337 $flatten\Core.\Control_Unit.$procmux$3010_CMP $auto$opt_reduce.cc:134:opt_pmux$4335 $auto$opt_reduce.cc:134:opt_pmux$4415 $auto$opt_reduce.cc:134:opt_pmux$4413 $auto$opt_reduce.cc:134:opt_pmux$4333 $auto$opt_reduce.cc:134:opt_pmux$4331 $auto$opt_reduce.cc:134:opt_pmux$4329 }
  Optimizing cells in module \top.
Performed a total of 5 changes.

21.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

21.11.13. Executing OPT_DFF pass (perform DFF optimizations).

21.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>

21.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.11.16. Rerunning OPT passes. (Maybe there is more to do..)

21.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~166 debug messages>

21.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.11.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.11.20. Executing OPT_DFF pass (perform DFF optimizations).

21.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.11.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.11.23. Finished OPT passes. (There is nothing left to do.)

21.12. Executing FSM pass (extract and optimize FSM).

21.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking top.Controller.Interpreter.return_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register top.Controller.Uart.i_uart_rx.fsm_state.
Not marking top.Controller.Uart.i_uart_tx.fsm_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking top.Controller.Uart.state_read as FSM state register:
    Register has an initialization value.
Not marking top.Controller.Uart.state_write as FSM state register:
    Register has an initialization value.
Found FSM state register top.Controller.Uart.tx_fifo_read_state.
Not marking top.Core.CSR_Unit.utime as FSM state register:
    Users of register don't seem to benefit from recoding.
    Register has an initialization value.
Not marking top.Core.Control_Unit.state as FSM state register:
    Register has an initialization value.
Not marking top.Core.Mdu.state_div as FSM state register:
    Register has an initialization value.
Not marking top.Core.Mdu.state_mul as FSM state register:
    Register has an initialization value.
Not marking top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.

21.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\Controller.Uart.i_uart_rx.fsm_state' from module `\top'.
  found $dff cell for state register: $flatten\Controller.\Uart.\i_uart_rx.$procdff$4137
  root of input selection tree: $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1130_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1143_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1156_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1142_Y
  found state code: 3'000
  found ctrl input: \Controller.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \Controller.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \Controller.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1156_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1147_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1143_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1142_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1130_Y
  ctrl inputs: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.rxd_reg \Controller.Uart.i_uart_rx.next_bit \Controller.Uart.i_uart_rx.payload_done }
  ctrl outputs: { $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1130_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1142_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1143_Y $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1147_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1156_Y $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'00-- ->      3'001 8'01010001
  transition:      3'000 4'01-- ->      3'000 8'01010000
  transition:      3'000 4'1--- ->      3'000 8'01010000
  transition:      3'010 4'0--0 ->      3'010 8'00100010
  transition:      3'010 4'0--1 ->      3'011 8'00100011
  transition:      3'010 4'1--- ->      3'000 8'00100000
  transition:      3'001 4'0-0- ->      3'001 8'00011001
  transition:      3'001 4'0-1- ->      3'010 8'00011010
  transition:      3'001 4'1--- ->      3'000 8'00011000
  transition:      3'011 4'0-0- ->      3'011 8'10010011
  transition:      3'011 4'0-1- ->      3'000 8'10010000
  transition:      3'011 4'1--- ->      3'000 8'10010000
Extracting FSM `\Controller.Uart.tx_fifo_read_state' from module `\top'.
  found $dff cell for state register: $flatten\Controller.\Uart.$procdff$4184
  root of input selection tree: $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0]
  found reset state: 2'00 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.$procmux$2269_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2264_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2271_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2258_CMP
  found state code: 2'00
  found state code: 2'11
  found state code: 2'10
  found ctrl input: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1016_Y
  found state code: 2'01
  found ctrl output: $flatten\Controller.\Uart.$procmux$2258_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2264_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2269_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2271_CMP
  ctrl inputs: { \ResetBootSystem.reset_o $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1016_Y }
  ctrl outputs: { $flatten\Controller.\Uart.$procmux$2271_CMP $flatten\Controller.\Uart.$procmux$2269_CMP $flatten\Controller.\Uart.$procmux$2264_CMP $flatten\Controller.\Uart.$procmux$2258_CMP $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] }
  transition:       2'00 2'00 ->       2'00 6'000100
  transition:       2'00 2'01 ->       2'01 6'000101
  transition:       2'00 2'1- ->       2'00 6'000100
  transition:       2'10 2'0- ->       2'11 6'001011
  transition:       2'10 2'1- ->       2'00 6'001000
  transition:       2'01 2'0- ->       2'10 6'100010
  transition:       2'01 2'1- ->       2'00 6'100000
  transition:       2'11 2'0- ->       2'00 6'010000
  transition:       2'11 2'1- ->       2'00 6'010000

21.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$4423' from module `\top'.
  Merging pattern 2'0- and 2'1- from group (3 0 6'010000).
  Merging pattern 2'1- and 2'0- from group (3 0 6'010000).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$4416' from module `\top'.

21.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 15 unused cells and 15 unused wires.
<suppressed ~16 debug messages>

21.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$4416' from module `\top'.
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$4423' from module `\top'.
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2269_CMP.
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2271_CMP.

21.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$4416' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---
Recoding FSM `$fsm$\Controller.Uart.tx_fifo_read_state$4423' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> ---1
  10 -> --1-
  01 -> -1--
  11 -> 1---

21.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$4416' from module `top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.i_uart_rx.fsm_state$4416 (\Controller.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \Controller.Uart.i_uart_rx.payload_done
    1: \Controller.Uart.i_uart_rx.next_bit
    2: \Controller.Uart.i_uart_rx.rxd_reg
    3: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1156_Y
    1: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1147_Y
    2: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1143_Y
    3: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1142_Y
    4: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1130_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'01--   ->     0 5'01010
      1:     0 4'1---   ->     0 5'01010
      2:     0 4'00--   ->     2 5'01010
      3:     1 4'1---   ->     0 5'00100
      4:     1 4'0--0   ->     1 5'00100
      5:     1 4'0--1   ->     3 5'00100
      6:     2 4'1---   ->     0 5'00011
      7:     2 4'0-1-   ->     1 5'00011
      8:     2 4'0-0-   ->     2 5'00011
      9:     3 4'0-1-   ->     0 5'10010
     10:     3 4'1---   ->     0 5'10010
     11:     3 4'0-0-   ->     3 5'10010

-------------------------------------

FSM `$fsm$\Controller.Uart.tx_fifo_read_state$4423' from module `top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.tx_fifo_read_state$4423 (\Controller.Uart.tx_fifo_read_state):

  Number of input signals:    2
  Number of output signals:   2
  Number of state bits:       4

  Input signals:
    0: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1016_Y
    1: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.$procmux$2258_CMP
    1: $flatten\Controller.\Uart.$procmux$2264_CMP

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 2'00   ->     0 2'01
      1:     0 2'1-   ->     0 2'01
      2:     0 2'01   ->     2 2'01
      3:     1 2'1-   ->     0 2'10
      4:     1 2'0-   ->     3 2'10
      5:     2 2'1-   ->     0 2'00
      6:     2 2'0-   ->     1 2'00
      7:     3 2'--   ->     0 2'00

-------------------------------------

21.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$4416' from module `\top'.
Mapping FSM `$fsm$\Controller.Uart.tx_fifo_read_state$4423' from module `\top'.

21.13. Executing OPT pass (performing simple optimizations).

21.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~9 debug messages>

21.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

21.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~164 debug messages>

21.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\ResetBootSystem.$procdff$4242 ($dff) from module top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$4240 ($dff) from module top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Adding SRST signal on $flatten\Core.\Pc.$procdff$4217 ($dff) from module top (D = $flatten\Core.\Pc.$procmux$2524_Y, Q = \Core.Pc.Output, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4511 ($sdff) from module top (D = \Core.Pc.Input, Q = \Core.Pc.Output).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4231 ($dff) from module top (D = $flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:74$118_Y, Q = \Core.Mdu.acumulador).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4230 ($dff) from module top (D = $flatten\Core.\Mdu.$procmux$2651_Y, Q = \Core.Mdu.MUL_RD, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4518 ($sdff) from module top (D = $flatten\Core.\Mdu.$ternary$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:80$120_Y, Q = \Core.Mdu.MUL_RD).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4227 ($dff) from module top (D = $flatten\Core.\Mdu.$procmux$2628_Y, Q = \Core.Mdu.state_mul, rval = 2'00).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4226 ($dff) from module top (D = $flatten\Core.\Mdu.$procmux$2638_Y, Q = \Core.Mdu.mul_done, rval = 1'0).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4225 ($dff) from module top (D = $flatten\Core.\Mdu.$procmux$2560_Y, Q = \Core.Mdu.divisor).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4224 ($dff) from module top (D = $flatten\Core.\Mdu.$procmux$2571_Y, Q = \Core.Mdu.DIV_RD).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4223 ($dff) from module top (D = $flatten\Core.\Mdu.$procmux$2580_Y, Q = \Core.Mdu.quociente_msk).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4222 ($dff) from module top (D = $flatten\Core.\Mdu.$procmux$2593_Y, Q = \Core.Mdu.quociente, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4545 ($sdff) from module top (D = $flatten\Core.\Mdu.$procmux$2593_Y, Q = \Core.Mdu.quociente).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4221 ($dff) from module top (D = $flatten\Core.\Mdu.$procmux$2606_Y, Q = \Core.Mdu.dividendo).
Adding EN signal on $flatten\Core.\Mdu.$procdff$4220 ($dff) from module top (D = $flatten\Core.\Mdu.$or$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:99$141_Y, Q = \Core.Mdu.negativo).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4219 ($dff) from module top (D = $flatten\Core.\Mdu.$procmux$2543_Y, Q = \Core.Mdu.state_div, rval = 2'00).
Adding SRST signal on $flatten\Core.\Mdu.$procdff$4218 ($dff) from module top (D = $flatten\Core.\Mdu.$procmux$2553_Y, Q = \Core.Mdu.div_done, rval = 1'0).
Adding SRST signal on $flatten\Core.\Control_Unit.$procdff$4243 ($dff) from module top (D = \Core.Control_Unit.nextstate, Q = \Core.Control_Unit.state, rval = 6'000000).
Adding EN signal on $flatten\Core.\CSR_Unit.$procdff$4239 ($dff) from module top (D = 64'0000000000000000000000000000000000000000000000000000000000000000, Q = \Core.CSR_Unit.utime).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4238 ($dff) from module top (D = $flatten\Core.\CSR_Unit.$add$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:116$105_Y, Q = \Core.CSR_Unit.mcycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4237 ($dff) from module top (D = $flatten\Core.\CSR_Unit.$procmux$2723_Y, Q = \Core.CSR_Unit.mtvec, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4576 ($sdff) from module top (D = \Core.register_data_1, Q = \Core.CSR_Unit.mtvec).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4236 ($dff) from module top (D = $flatten\Core.\CSR_Unit.$procmux$2731_Y, Q = \Core.CSR_Unit.mtval, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4580 ($sdff) from module top (D = \Core.register_data_1, Q = \Core.CSR_Unit.mtval).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4235 ($dff) from module top (D = $flatten\Core.\CSR_Unit.$procmux$2740_Y, Q = \Core.CSR_Unit.mcause, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4584 ($sdff) from module top (D = \Core.register_data_1, Q = \Core.CSR_Unit.mcause).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4234 ($dff) from module top (D = $flatten\Core.\CSR_Unit.$procmux$2750_Y, Q = \Core.CSR_Unit.mscratch, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4588 ($sdff) from module top (D = \Core.register_data_1, Q = \Core.CSR_Unit.mscratch).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4233 ($dff) from module top (D = $flatten\Core.\CSR_Unit.$procmux$2761_Y, Q = \Core.CSR_Unit.mepc, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4592 ($sdff) from module top (D = { \Core.register_data_1 [31:2] 2'00 }, Q = \Core.CSR_Unit.mepc).
Adding SRST signal on $flatten\Core.\CSR_Unit.$procdff$4232 ($dff) from module top (D = $flatten\Core.\CSR_Unit.$procmux$2710_Y, Q = \Core.CSR_Unit.minstret, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4596 ($sdff) from module top (D = \Core.register_data_1, Q = \Core.CSR_Unit.minstret [63:32]).
Adding EN signal on $auto$ff.cc:266:slice$4596 ($sdff) from module top (D = $flatten\Core.\CSR_Unit.$procmux$2708_Y [31:0], Q = \Core.CSR_Unit.minstret [31:0]).
Adding EN signal on $flatten\Core.$procdff$4211 ($dff) from module top (D = \Core.mdu_out, Q = \Core.mdu_out_reg).
Adding SRST signal on $flatten\Core.$procdff$4210 ($dff) from module top (D = $flatten\Core.$procmux$2475_Y, Q = \Core.pc_old, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4610 ($sdff) from module top (D = \Core.Pc.Output, Q = \Core.pc_old).
Adding SRST signal on $flatten\Core.$procdff$4209 ($dff) from module top (D = \Core.register_data_2_out, Q = \Core.register_data_2, rval = 0).
Adding SRST signal on $flatten\Core.$procdff$4208 ($dff) from module top (D = \Core.register_data_1_out, Q = \Core.register_data_1, rval = 0).
Adding SRST signal on $flatten\Core.$procdff$4207 ($dff) from module top (D = \Core.Alu.ALU_out_S, Q = \Core.alu_out_register, rval = 0).
Adding SRST signal on $flatten\Core.$procdff$4206 ($dff) from module top (D = \Core.read_data, Q = \Core.memory_register, rval = 0).
Adding SRST signal on $flatten\Core.$procdff$4205 ($dff) from module top (D = $flatten\Core.$procmux$2480_Y, Q = \Core.instruction_register, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4616 ($sdff) from module top (D = \Core.read_data, Q = \Core.instruction_register).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$4149 ($dff) from module top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1480_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1474_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1465_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1456_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1447_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1438_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1420_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1429_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4618 ($sdff) from module top (D = \Controller.Uart.uart_tx_data [7], Q = \Controller.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$4618 ($sdff) from module top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1474_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1465_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1456_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1447_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1438_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1420_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1429_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$4147 ($dff) from module top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1396_Y, Q = \Controller.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$4623 ($sdff) from module top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1396_Y, Q = \Controller.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$4146 ($dff) from module top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1385_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$4629 ($sdff) from module top (D = $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1110_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$4145 ($dff) from module top (D = \Controller.Uart.i_uart_tx.n_fsm_state, Q = \Controller.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$4144 ($dff) from module top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1374_Y, Q = \Controller.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$4634 ($sdff) from module top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1374_Y, Q = \Controller.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4143 ($dff) from module top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1363_Y, Q = \Controller.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4640 ($sdff) from module top (D = \Controller.Uart.i_uart_rx.recieved_data, Q = \Controller.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4141 ($dff) from module top (D = { $flatten\Controller.\Uart.\i_uart_rx.$procmux$1340_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1331_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1322_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1313_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1304_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1295_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1277_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1286_Y }, Q = \Controller.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4642 ($sdff) from module top (D = { \Controller.Uart.i_uart_rx.bit_sample \Controller.Uart.i_uart_rx.recieved_data [7:1] }, Q = \Controller.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4140 ($dff) from module top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1259_Y, Q = \Controller.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$4646 ($sdff) from module top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1150_Y, Q = \Controller.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4139 ($dff) from module top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1254_Y, Q = \Controller.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4650 ($sdff) from module top (D = \Controller.Uart.i_uart_rx.rxd_reg, Q = \Controller.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4138 ($dff) from module top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1246_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$4652 ($sdff) from module top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1161_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4136 ($dff) from module top (D = \rx, Q = \Controller.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$4135 ($dff) from module top (D = \Controller.Uart.i_uart_rx.rxd_reg_0, Q = \Controller.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$4134 ($dff) from module top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1223_Y, Q = \Controller.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4658 ($sdff) from module top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$970_Y [5:0], Q = \Controller.Uart.TX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$4133 ($dff) from module top (D = $flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$967_DATA, Q = \Controller.Uart.TX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$4129 ($dff) from module top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1218_Y, Q = \Controller.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4665 ($sdff) from module top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$986_Y [5:0], Q = \Controller.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$4134 ($dff) from module top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1223_Y, Q = \Controller.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4667 ($sdff) from module top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$970_Y [5:0], Q = \Controller.Uart.RX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$4133 ($dff) from module top (D = $flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$967_DATA, Q = \Controller.Uart.RX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$4129 ($dff) from module top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1218_Y, Q = \Controller.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$4674 ($sdff) from module top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$986_Y [5:0], Q = \Controller.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4197 ($dff) from module top (D = $flatten\Controller.\Uart.$procmux$2394_Y, Q = \Controller.Uart.state_read, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$4676 ($sdff) from module top (D = $flatten\Controller.\Uart.$procmux$2394_Y, Q = \Controller.Uart.state_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4196 ($dff) from module top (D = $flatten\Controller.\Uart.$procmux$2419_Y, Q = \Controller.Uart.counter_read, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$4680 ($sdff) from module top (D = $flatten\Controller.\Uart.$procmux$2419_Y, Q = \Controller.Uart.counter_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4195 ($dff) from module top (D = $flatten\Controller.\Uart.$procmux$2383_Y, Q = \Controller.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4194 ($dff) from module top (D = $flatten\Controller.\Uart.$procmux$2372_Y, Q = \Controller.Uart.read_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4193 ($dff) from module top (D = $flatten\Controller.\Uart.$procmux$2434_Y, Q = \Controller.Uart.read_data, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4698 ($sdff) from module top (D = $flatten\Controller.\Uart.$procmux$2432_Y, Q = \Controller.Uart.read_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4192 ($dff) from module top (D = $flatten\Controller.\Uart.$procmux$2316_Y, Q = \Controller.Uart.state_write, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$4704 ($sdff) from module top (D = $flatten\Controller.\Uart.$procmux$2316_Y, Q = \Controller.Uart.state_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4191 ($dff) from module top (D = $flatten\Controller.\Uart.$procmux$2338_Y, Q = \Controller.Uart.counter_write, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$4708 ($sdff) from module top (D = $flatten\Controller.\Uart.$procmux$2338_Y, Q = \Controller.Uart.counter_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4190 ($dff) from module top (D = $flatten\Controller.\Uart.$procmux$2352_Y, Q = \Controller.Uart.write_data_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4718 ($sdff) from module top (D = $flatten\Controller.\Uart.$procmux$2352_Y, Q = \Controller.Uart.write_data_buffer).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4189 ($dff) from module top (D = $flatten\Controller.\Uart.$procmux$2366_Y, Q = \Controller.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4728 ($sdff) from module top (D = \Controller.Uart.write_data_buffer [31:24], Q = \Controller.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4188 ($dff) from module top (D = $flatten\Controller.\Uart.$procmux$2298_Y, Q = \Controller.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4187 ($dff) from module top (D = $flatten\Controller.\Uart.$procmux$2308_Y, Q = \Controller.Uart.write_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4186 ($dff) from module top (D = $flatten\Controller.\Uart.$procmux$2289_Y, Q = \Controller.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4742 ($sdff) from module top (D = \Controller.Uart.i_uart_rx.uart_rx_data, Q = \Controller.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4185 ($dff) from module top (D = $flatten\Controller.\Uart.$procmux$2284_Y, Q = \Controller.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4183 ($dff) from module top (D = $flatten\Controller.\Uart.$procmux$2279_Y, Q = \Controller.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4745 ($sdff) from module top (D = \Controller.Uart.TX_FIFO.read_data, Q = \Controller.Uart.uart_tx_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4182 ($dff) from module top (D = $flatten\Controller.\Uart.$procmux$2255_Y, Q = \Controller.Uart.tx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$4181 ($dff) from module top (D = $flatten\Controller.\Uart.$procmux$2263_Y, Q = \Controller.Uart.uart_tx_en, rval = 1'0).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4180 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1802_Y, Q = \Controller.Interpreter.temp_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4179 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1845_Y, Q = \Controller.Interpreter.accumulator, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4762 ($sdff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1845_Y [63:8], Q = \Controller.Interpreter.accumulator [63:8]).
Adding EN signal on $auto$ff.cc:266:slice$4762 ($sdff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1845_Y [7:0], Q = \Controller.Interpreter.accumulator [7:0]).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4178 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1855_Y, Q = \Controller.Interpreter.timeout_counter, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4777 ($sdff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1855_Y, Q = \Controller.Interpreter.timeout_counter).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4177 ($dff) from module top (D = { 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, Q = \Controller.Interpreter.timeout).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4176 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1896_Y, Q = \Controller.Interpreter.read_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4175 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1924_Y, Q = \Controller.Interpreter.communication_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4793 ($sdff) from module top (D = \Controller.Uart.read_data, Q = \Controller.Interpreter.communication_buffer).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4174 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1949_Y, Q = \Controller.Interpreter.num_of_positions).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4173 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1971_Y, Q = \Controller.Interpreter.num_of_pages, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4804 ($sdff) from module top (D = \Controller.Interpreter.communication_buffer [31:8], Q = \Controller.Interpreter.num_of_pages).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4172 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1977_Y, Q = \Controller.Interpreter.return_state, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4806 ($sdff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1977_Y, Q = \Controller.Interpreter.return_state).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4171 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$2001_Y, Q = \Controller.Interpreter.memory_page_number).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4170 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$2009_Y, Q = \Controller.Interpreter.memory_mux_selector, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4821 ($sdff) from module top (D = $flatten\Controller.\Interpreter.$procmux$2009_Y, Q = \Controller.Interpreter.memory_mux_selector).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4169 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$2049_Y, Q = \Controller.Interpreter.end_position, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4825 ($sdff) from module top (D = $flatten\Controller.\Interpreter.$procmux$2049_Y, Q = \Controller.Interpreter.end_position).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4167 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$2091_Y, Q = \Controller.Interpreter.bus_mode, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4829 ($sdff) from module top (D = $flatten\Controller.\Interpreter.$procmux$2091_Y, Q = \Controller.Interpreter.bus_mode).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4166 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1630_Y, Q = \Controller.Interpreter.reset_bus, rval = 1'1).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4165 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$2102_Y, Q = \Controller.Interpreter.num_of_cycles_to_pulse).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4164 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1735_Y, Q = \Controller.Interpreter.core_reset, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4163 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$2112_Y, Q = \Controller.Interpreter.core_clk_enable, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4842 ($sdff) from module top (D = $flatten\Controller.\Interpreter.$procmux$2112_Y, Q = \Controller.Interpreter.core_clk_enable).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4162 ($dff) from module top (D = \Controller.Interpreter.read_buffer, Q = \Controller.Interpreter.communication_write_data).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4161 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1754_Y, Q = \Controller.Interpreter.communication_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4160 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1777_Y, Q = \Controller.Interpreter.communication_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4159 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1687_Y, Q = \Controller.Interpreter.write_pulse, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4158 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$2188_Y, Q = \Controller.Interpreter.counter, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$4858 ($sdff) from module top (D = $flatten\Controller.\Interpreter.$procmux$2188_Y, Q = \Controller.Interpreter.counter).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4157 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1530_Y, Q = \Controller.Interpreter.state, rval = 8'00000000).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4156 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$2212_Y, Q = \Controller.Interpreter.write_data).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$4155 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$2238_Y, Q = \Controller.Interpreter.address).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4154 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1654_Y, Q = \Controller.Interpreter.memory_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$4153 ($dff) from module top (D = $flatten\Controller.\Interpreter.$procmux$1676_Y, Q = \Controller.Interpreter.memory_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\ClkDivider.$procdff$4150 ($dff) from module top (D = $flatten\Controller.\ClkDivider.$procmux$1504_Y, Q = \Controller.ClkDivider.pulse_counter, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$4881 ($sdff) from module top (D = $flatten\Controller.\ClkDivider.$procmux$1504_Y, Q = \Controller.ClkDivider.pulse_counter).
Adding SRST signal on $flatten\Controller.$procdff$4204 ($dff) from module top (D = $flatten\Controller.$procmux$2455_Y, Q = \Controller.finish_execution, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$4889 ($sdff) from module top (D = $flatten\Controller.$procmux$2455_Y, Q = \Controller.finish_execution).
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$4781 ($dffe) from module top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$4781 ($dffe) from module top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$4781 ($dffe) from module top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$4781 ($dffe) from module top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$4781 ($dffe) from module top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$4781 ($dffe) from module top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$4781 ($dffe) from module top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$4781 ($dffe) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$4593 ($sdffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$4593 ($sdffe) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 33 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 34 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 35 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 36 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 37 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 38 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 39 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 40 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 41 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 42 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 43 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 44 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 45 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 46 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 47 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 48 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 49 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 50 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 51 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 52 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 53 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 54 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 55 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 56 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 57 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 58 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 59 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 60 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 61 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 62 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.
Setting constant 0-bit at position 63 on $auto$ff.cc:266:slice$4574 ($dffe) from module top.

21.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 174 unused cells and 179 unused wires.
<suppressed ~175 debug messages>

21.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~33 debug messages>

21.13.9. Rerunning OPT passes. (Maybe there is more to do..)

21.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~123 debug messages>

21.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$4648: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.fsm_state [3:2] \Controller.Uart.i_uart_rx.fsm_state [0] }
    New ctrl vector for $pmux cell $flatten\Core.\CSR_Unit.$procmux$2767: { $flatten\Core.\CSR_Unit.$procmux$2779_CMP $flatten\Core.\CSR_Unit.$procmux$2778_CMP $flatten\Core.\CSR_Unit.$procmux$2777_CMP $flatten\Core.\CSR_Unit.$procmux$2722_CMP $flatten\Core.\CSR_Unit.$procmux$2749_CMP $flatten\Core.\CSR_Unit.$procmux$2760_CMP $flatten\Core.\CSR_Unit.$procmux$2739_CMP $flatten\Core.\CSR_Unit.$procmux$2730_CMP $auto$opt_reduce.cc:134:opt_pmux$4287 $auto$opt_reduce.cc:134:opt_pmux$4285 $auto$opt_reduce.cc:134:opt_pmux$4283 $auto$opt_reduce.cc:134:opt_pmux$4281 }
  Optimizing cells in module \top.
Performed a total of 2 changes.

21.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~99 debug messages>
Removed a total of 33 cells.

21.13.13. Executing OPT_DFF pass (perform DFF optimizations).

21.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 3 unused cells and 36 unused wires.
<suppressed ~4 debug messages>

21.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.13.16. Rerunning OPT passes. (Maybe there is more to do..)

21.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~123 debug messages>

21.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.13.20. Executing OPT_DFF pass (perform DFF optimizations).

21.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.13.23. Finished OPT passes. (There is nothing left to do.)

21.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 22 address bits (of 32) from memory init port top.$flatten\Controller.\Data_Memory.$auto$proc_memwr.cc:45:proc_memwr$4245 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory read port top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$777 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory init port top.$flatten\Controller.\Memory.$auto$proc_memwr.cc:45:proc_memwr$4245 (Controller.Memory.memory).
Removed top 22 address bits (of 32) from memory read port top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$777 (Controller.Memory.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\Controller.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$4244 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$967 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory init port top.$flatten\Controller.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$4244 (Controller.Uart.TX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port top.$flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$967 (Controller.Uart.TX_FIFO.memory).
Removed top 27 address bits (of 32) from memory init port top.$flatten\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$4246 (Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\Core.\RegisterBank.$auto$proc_memwr.cc:45:proc_memwr$4248 (Core.RegisterBank.registers).
Removed top 27 address bits (of 32) from memory init port top.$flatten\Core.\RegisterBank.$meminit$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:22$187 (Core.RegisterBank.registers).
Removed top 1 bits (of 2) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$4463 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$4488 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$4501 ($ne).
Removed top 1 bits (of 2) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$4438 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1068 ($gt).
Removed top 3 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:219$1025 ($eq).
Removed top 6 bits (of 32) from port B of cell top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1029 ($add).
Removed top 29 bits (of 32) from port B of cell top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1032 ($add).
Removed top 8 bits (of 32) from port A of cell top.$flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1041 ($lt).
Removed top 8 bits (of 32) from port A of cell top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1046 ($eq).
Removed top 8 bits (of 32) from port A of cell top.$flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1048 ($ge).
Removed top 3 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1531_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1532_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell top.$flatten\Controller.\Interpreter.$procmux$1534 ($mux).
Removed top 3 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1536_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1537_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1538_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1539_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1540_CMP0 ($eq).
Removed top 5 bits (of 8) from mux cell top.$flatten\Controller.\Interpreter.$procmux$1542 ($mux).
Removed top 3 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1544_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1545_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell top.$flatten\Controller.\Interpreter.$procmux$1547 ($mux).
Removed top 3 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1549_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1550_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1554_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1555_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1556_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell top.$flatten\Controller.\Interpreter.$procmux$1558 ($mux).
Removed top 4 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1560_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1561_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1562_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell top.$flatten\Controller.\Interpreter.$procmux$1564 ($mux).
Removed top 4 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1566_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell top.$flatten\Controller.\Interpreter.$procmux$1568 ($mux).
Removed top 4 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1570_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1571_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1572_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1573_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1574_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1575_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1576_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell top.$flatten\Controller.\Interpreter.$procmux$1578 ($mux).
Removed top 5 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1580_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell top.$flatten\Controller.\Interpreter.$procmux$1582 ($mux).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1584_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1585_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell top.$flatten\Controller.\Interpreter.$procmux$1587 ($mux).
Removed top 4 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1589_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1590_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1593_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell top.$flatten\Controller.\Interpreter.$procmux$1592 ($pmux).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1594_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1595_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1596_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1597_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1598_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1599_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1600_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1601_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1602_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1603_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1604_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1605_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1606_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1607_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1608_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1609_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1610_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1611_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1612_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1613_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1614_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1615_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1616_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell top.$flatten\Controller.\Interpreter.$procmux$1618 ($mux).
Removed top 7 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1620_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell top.$flatten\Controller.\Interpreter.$procmux$1622 ($mux).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1656_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1657_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1658_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1691_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1846_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1847_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1848_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$1891_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$2017_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$2050_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$2051_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$2124_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell top.$flatten\Controller.\Interpreter.$procmux$2125_CMP0 ($eq).
Removed top 29 bits (of 32) from port B of cell top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:95$999 ($lt).
Removed top 29 bits (of 32) from port B of cell top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:159$1004 ($lt).
Removed top 3 bits (of 4) from port B of cell top.$flatten\Controller.\Uart.$procmux$2303_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\Controller.\Uart.$procmux$2309_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\Controller.\Uart.$procmux$2310_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\Controller.\Uart.$procmux$2322_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\Controller.\Uart.$procmux$2324 ($mux).
Removed top 2 bits (of 4) from port B of cell top.$flatten\Controller.\Uart.$procmux$2373_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\Controller.\Uart.$procmux$2374_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell top.$flatten\Controller.\Uart.$procmux$2388_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\Controller.\Uart.$procmux$2396_CMP0 ($eq).
Removed top 3 bits (of 4) from mux cell top.$flatten\Controller.\Uart.$procmux$2404 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1215 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1203 ($mux).
Removed top 31 bits (of 32) from port B of cell top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987 ($sub).
Removed top 25 bits (of 32) from port Y of cell top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987 ($sub).
Removed top 26 bits (of 32) from mux cell top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$986 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$984 ($eq).
Removed top 26 bits (of 32) from mux cell top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$970 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$968 ($eq).
Removed top 3 bits (of 6) from mux cell top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1215 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1203 ($mux).
Removed top 31 bits (of 32) from port B of cell top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987 ($sub).
Removed top 25 bits (of 32) from port Y of cell top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987 ($sub).
Removed top 26 bits (of 32) from mux cell top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$986 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$984 ($eq).
Removed top 26 bits (of 32) from mux cell top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$970 ($mux).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969 ($add).
Removed top 3 bits (of 6) from port B of cell top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$968 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$4449 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1139 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1138 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1137 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1136 ($mux).
Removed top 2 bits (of 9) from port B of cell top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:110$1131 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:108$1129 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:152$1105 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:137$1097 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:135$1095 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1092 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1091 ($ne).
Removed top 1 bits (of 3) from port B of cell top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:120$1087 ($eq).
Removed top 30 bits (of 32) from mux cell top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1082 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1081 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1080 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1079 ($mux).
Removed top 3 bits (of 4) from port B of cell top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:94$1075 ($eq).
Removed top 1 bits (of 9) from port B of cell top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:92$1073 ($eq).
Removed top 22 bits (of 32) from mux cell top.$flatten\Controller.\Memory.$procmux$2446 ($mux).
Removed top 22 bits (of 32) from mux cell top.$flatten\Controller.\Data_Memory.$procmux$2446 ($mux).
Removed top 20 bits (of 32) from mux cell top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:96$754 ($mux).
Removed top 20 bits (of 32) from mux cell top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$738 ($mux).
Removed top 20 bits (of 32) from mux cell top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$737 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$4884 ($ne).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$4894 ($ne).
Removed top 32 bits (of 64) from mux cell top.$flatten\Core.\CSR_Unit.$procmux$2708 ($mux).
Removed top 2 bits (of 12) from port B of cell top.$flatten\Core.\CSR_Unit.$procmux$2722_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\Core.\CSR_Unit.$procmux$2730_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\Core.\CSR_Unit.$procmux$2739_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\Core.\CSR_Unit.$procmux$2749_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\Core.\CSR_Unit.$procmux$2760_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\Core.\CSR_Unit.$procmux$2777_CMP0 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\Core.\Alu.$ternary$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:37$9 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\Core.\Alu.$ternary$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:53$20 ($mux).
Removed top 2 bits (of 4) from port B of cell top.$flatten\Core.\Alu.$procmux$4110_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\Core.\Alu.$procmux$4117_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\Core.\Alu.$procmux$4118_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\Core.\Alu.$procmux$4119_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell top.$flatten\Core.\Alu.$procmux$4120_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\Core.\ALU_Control.$procmux$4105_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\Core.\ALU_Control.$procmux$4089_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\Core.\ALU_Control.$procmux$4090_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\Core.\ALU_Control.$procmux$4091_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell top.$flatten\Core.\ALU_Control.$procmux$4093 ($mux).
Removed top 1 bits (of 3) from mux cell top.$flatten\Core.\Control_Unit.$ternary$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:114$30 ($mux).
Removed top 5 bits (of 7) from port B of cell top.$flatten\Core.\Control_Unit.$eq$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:197$34 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\Core.\Control_Unit.$eq$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:282$47 ($eq).
Removed top 31 bits (of 32) from mux cell top.$flatten\Core.\Control_Unit.$ternary$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:566$68 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\Core.\Control_Unit.$ternary$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:586$74 ($mux).
Removed top 2 bits (of 3) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$2829_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$2830_CMP0 ($eq).
Removed top 1 bits (of 3) from mux cell top.$flatten\Core.\Control_Unit.$procmux$2832 ($pmux).
Removed top 1 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3011_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3012_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3013_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3014_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3015_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3016_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3017_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3053_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3061_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3062_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3066_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3067_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3068_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3069_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3074_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3075_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3077_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3078_CMP0 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3079_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3081_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3094_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3095_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3100_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3102_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3104_CMP0 ($eq).
Removed top 5 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3105_CMP0 ($eq).
Removed top 3 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3185_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3209_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3210_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3211_CMP0 ($eq).
Removed top 4 bits (of 6) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3212_CMP0 ($eq).
Removed top 5 bits (of 6) from mux cell top.$flatten\Core.\Control_Unit.$procmux$3311 ($mux).
Removed top 5 bits (of 6) from mux cell top.$flatten\Core.\Control_Unit.$procmux$3336 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\Core.\Control_Unit.$procmux$3396 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\Core.\Control_Unit.$procmux$3448 ($mux).
Removed top 5 bits (of 6) from mux cell top.$flatten\Core.\Control_Unit.$procmux$3478 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\Core.\Control_Unit.$procmux$3511 ($mux).
Removed top 1 bits (of 6) from mux cell top.$flatten\Core.\Control_Unit.$procmux$3547 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\Core.\Control_Unit.$procmux$3585 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\Core.\Control_Unit.$procmux$3634 ($mux).
Removed top 3 bits (of 6) from mux cell top.$flatten\Core.\Control_Unit.$procmux$3685 ($mux).
Removed top 1 bits (of 6) from mux cell top.$flatten\Core.\Control_Unit.$procmux$3737 ($mux).
Removed top 1 bits (of 6) from mux cell top.$flatten\Core.\Control_Unit.$procmux$3793 ($mux).
Removed top 1 bits (of 6) from mux cell top.$flatten\Core.\Control_Unit.$procmux$3847 ($mux).
Removed top 1 bits (of 7) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3911_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3966_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3967_CMP0 ($eq).
Removed top 2 bits (of 7) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3970_CMP0 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\Core.\Control_Unit.$procmux$3972_CMP0 ($eq).
Removed top 32 bits (of 64) from port A of cell top.$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:74$118 ($mul).
Removed top 32 bits (of 64) from port B of cell top.$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:74$118 ($mul).
Removed top 31 bits (of 32) from port B of cell top.$flatten\Core.\Mdu.$eq$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:109$142 ($eq).
Removed top 32 bits (of 64) from port Y of cell top.$flatten\Core.\Mdu.$sub$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:116$144 ($sub).
Removed top 32 bits (of 64) from port B of cell top.$flatten\Core.\Mdu.$sub$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:116$144 ($sub).
Removed top 1 bits (of 2) from port B of cell top.$flatten\Core.\Mdu.$procmux$2544_CMP0 ($eq).
Removed top 1 bits (of 2) from mux cell top.$flatten\Core.\Mdu.$procmux$2546 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\Core.\Mdu.$procmux$2629_CMP0 ($eq).
Removed top 1 bits (of 2) from mux cell top.$flatten\Core.\Mdu.$procmux$2631 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$flatten\Core.\AluInputBMUX.$procmux$2534_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\Core.\AluInputBMUX.$procmux$2535_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\Core.\AluInputBMUX.$procmux$2536_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\Core.\AluInputAMUX.$procmux$2534_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\Core.\AluInputAMUX.$procmux$2535_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\Core.\AluInputAMUX.$procmux$2536_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\Core.\MemoryDataMUX.$procmux$2534_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\Core.\MemoryDataMUX.$procmux$2535_CMP0 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\Core.\MemoryDataMUX.$procmux$2536_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\Core.\MemoryAddressMUX.$procmux$2536_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\Core.\CSR_Unit.$add$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:116$105 ($add).
Removed top 1 bits (of 2) from port B of cell top.$flatten\ResetBootSystem.$procmux$2798_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell top.$flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$702 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$701 ($add).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$701 ($add).
Removed top 27 bits (of 32) from port B of cell top.$flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$700 ($lt).
Removed cell top.$flatten\Core.\CSR_Unit.$procmux$2705 ($mux).
Removed top 20 bits (of 32) from wire top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$737_Y.
Removed top 22 bits (of 32) from wire top.$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_ADDR[31:0]$781.
Removed top 7 bits (of 8) from wire top.$flatten\Controller.\Interpreter.$procmux$1534_Y.
Removed top 5 bits (of 8) from wire top.$flatten\Controller.\Interpreter.$procmux$1542_Y.
Removed top 1 bits (of 8) from wire top.$flatten\Controller.\Interpreter.$procmux$1547_Y.
Removed top 4 bits (of 8) from wire top.$flatten\Controller.\Interpreter.$procmux$1558_Y.
Removed top 6 bits (of 8) from wire top.$flatten\Controller.\Interpreter.$procmux$1564_Y.
Removed top 4 bits (of 8) from wire top.$flatten\Controller.\Interpreter.$procmux$1568_Y.
Removed top 7 bits (of 8) from wire top.$flatten\Controller.\Interpreter.$procmux$1578_Y.
Removed top 1 bits (of 8) from wire top.$flatten\Controller.\Interpreter.$procmux$1582_Y.
Removed top 6 bits (of 8) from wire top.$flatten\Controller.\Interpreter.$procmux$1587_Y.
Removed top 1 bits (of 8) from wire top.$flatten\Controller.\Interpreter.$procmux$1592_Y.
Removed top 6 bits (of 8) from wire top.$flatten\Controller.\Interpreter.$procmux$1618_Y.
Removed top 7 bits (of 8) from wire top.$flatten\Controller.\Interpreter.$procmux$1622_Y.
Removed top 22 bits (of 32) from wire top.$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$775_ADDR[31:0]$781.
Removed top 1 bits (of 4) from wire top.$flatten\Controller.\Uart.$procmux$2324_Y.
Removed top 3 bits (of 4) from wire top.$flatten\Controller.\Uart.$procmux$2404_Y.
Removed top 3 bits (of 6) from wire top.$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_ADDR[5:0]$972.
Removed top 3 bits (of 6) from wire top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_ADDR[5:0]$981.
Removed top 26 bits (of 32) from wire top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969_Y.
Removed top 26 bits (of 32) from wire top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985_Y.
Removed top 28 bits (of 32) from wire top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$970_Y.
Removed top 3 bits (of 6) from wire top.$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_ADDR[5:0]$972.
Removed top 3 bits (of 6) from wire top.$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$962_ADDR[5:0]$981.
Removed top 26 bits (of 32) from wire top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969_Y.
Removed top 26 bits (of 32) from wire top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985_Y.
Removed top 26 bits (of 32) from wire top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$970_Y.
Removed top 26 bits (of 32) from wire top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$986_Y.
Removed top 31 bits (of 32) from wire top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1136_Y.
Removed top 30 bits (of 32) from wire top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1137_Y.
Removed top 31 bits (of 32) from wire top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1138_Y.
Removed top 30 bits (of 32) from wire top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1139_Y.
Removed top 31 bits (of 32) from wire top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1079_Y.
Removed top 30 bits (of 32) from wire top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1080_Y.
Removed top 31 bits (of 32) from wire top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1081_Y.
Removed top 31 bits (of 32) from wire top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1082_Y.
Removed top 1 bits (of 4) from wire top.$flatten\Core.\ALU_Control.$procmux$4093_Y.
Removed top 31 bits (of 32) from wire top.$flatten\Core.\Alu.$eq$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:45$15_Y.
Removed top 31 bits (of 32) from wire top.$flatten\Core.\Alu.$ternary$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:37$9_Y.
Removed top 31 bits (of 32) from wire top.$flatten\Core.\Alu.$ternary$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:53$20_Y.
Removed top 32 bits (of 64) from wire top.$flatten\Core.\CSR_Unit.$procmux$2708_Y.
Removed top 3 bits (of 6) from wire top.$flatten\Core.\Control_Unit.$10\nextstate[5:0].
Removed top 1 bits (of 6) from wire top.$flatten\Core.\Control_Unit.$11\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\Core.\Control_Unit.$12\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\Core.\Control_Unit.$14\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\Core.\Control_Unit.$16\nextstate[5:0].
Removed top 5 bits (of 6) from wire top.$flatten\Core.\Control_Unit.$19\nextstate[5:0].
Removed top 5 bits (of 6) from wire top.$flatten\Core.\Control_Unit.$21\nextstate[5:0].
Removed top 1 bits (of 6) from wire top.$flatten\Core.\Control_Unit.$5\nextstate[5:0].
Removed top 1 bits (of 6) from wire top.$flatten\Core.\Control_Unit.$6\nextstate[5:0].
Removed top 3 bits (of 6) from wire top.$flatten\Core.\Control_Unit.$8\nextstate[5:0].
Removed top 31 bits (of 32) from wire top.$flatten\Core.\Control_Unit.$ternary$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:586$74_Y.
Removed top 1 bits (of 2) from wire top.$flatten\Core.\Mdu.$procmux$2546_Y.
Removed top 1 bits (of 2) from wire top.$flatten\Core.\Mdu.$procmux$2631_Y.
Removed top 32 bits (of 64) from wire top.$flatten\Core.\Mdu.$sub$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:116$144_Y.
Removed top 26 bits (of 32) from wire top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$701_Y.

21.15. Executing PEEPOPT pass (run peephole optimizers).

21.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 57 unused wires.
<suppressed ~1 debug messages>

21.17. Executing SHARE pass (SAT-based resource sharing).
Found 6 cells in module top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\Core.\RegisterBank.$memrd$\registers$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/registers.v:28$169 ($memrd):
    Found 12 activation_patterns using ctrl signal { $auto$opt_reduce.cc:134:opt_pmux$4409 $flatten\Core.\AluInputBMUX.$procmux$2534_CMP $flatten\Core.\Alu.$procmux$4121_CMP $flatten\Core.\Alu.$procmux$4120_CMP $flatten\Core.\Alu.$procmux$4119_CMP $flatten\Core.\Alu.$procmux$4118_CMP $flatten\Core.\Alu.$procmux$4115_CMP $flatten\Core.\Alu.$procmux$4114_CMP $flatten\Core.\Alu.$procmux$4113_CMP $flatten\Core.\Alu.$procmux$4112_CMP $flatten\Core.\Alu.$procmux$4111_CMP $flatten\Core.\Alu.$procmux$4110_CMP $auto$opt_reduce.cc:134:opt_pmux$4411 }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Core.\Alu.$sshr$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:51$18 ($sshr):
    Found 1 activation_patterns using ctrl signal $flatten\Core.\Alu.$procmux$4110_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\Core.\Alu.$shr$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:49$17 ($shr):
    Found 1 activation_patterns using ctrl signal $flatten\Core.\Alu.$procmux$4111_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\Core.\Alu.$shl$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:47$16 ($shl):
    Found 1 activation_patterns using ctrl signal $flatten\Core.\Alu.$procmux$4112_CMP.
    No candidates found.
  Analyzing resource sharing options for $flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$777 ($memrd):
    Found 2 activation_patterns using ctrl signal { \Controller.Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1574_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$777 ($memrd):
    Found 1 activation_patterns using ctrl signal { \Controller.Data_Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1574_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.

21.18. Executing TECHMAP pass (map to technology primitives).

21.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

21.18.2. Continuing TECHMAP pass.
Using template $paramod$141b0f41d8ab4b936f42c52ead39f1f9a7c93200\_90_lut_cmp_ for cells of type $lt.
No more expansions possible.
<suppressed ~223 debug messages>

21.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 6 unused wires.
<suppressed ~1 debug messages>

21.21. Executing TECHMAP pass (map to technology primitives).

21.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

21.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

21.21.3. Continuing TECHMAP pass.
Using template $paramod$e88c2150f27e199b5b4c38f191932e407250eaa3\_80_mul for cells of type $mul.
Using template $paramod$de927ffa49f2a1327665483e9418148a52f3d36b\_80_mul for cells of type $__mul.
Using template $paramod$fac210dc6e441ade6153a47dcf32d681f9d41bee\_80_mul for cells of type $__mul.
Using template $paramod$ba1b36458f074a6329f9cad9c8b71be8774bccea\_80_mul for cells of type $__mul.
Using template $paramod$f84b7e774a64cf6bd61391522b3eee9d216e6e7e\_80_mul for cells of type $__mul.
Using template $paramod$84e4af21b083f56ce59bb3210f4da5751fbe9bb3\_80_mul for cells of type $__mul.
Using template $paramod$0c59eac522c8fc6cf582c390b8c4bd5bae1bb887\_80_mul for cells of type $__mul.
Using template $paramod$7c1afd677c664a6f211892c24ab4c74153b5be67\$__MUL18X18 for cells of type $__MUL18X18.
Using template $paramod$bef2a6330e4e8c17c10f220fb2d17af741212f04\$__MUL18X18 for cells of type $__MUL18X18.
Using template $paramod$e5ade21dea2c4d51df0cdca72b2a93a08fd8e7d1\$__MUL18X18 for cells of type $__MUL18X18.
Using template $paramod$ab0a030b3329c9db46a487d220064a2a8467942a\$__MUL18X18 for cells of type $__MUL18X18.
No more expansions possible.
<suppressed ~670 debug messages>

21.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:74$118.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4967 ($add).
  creating $macc model for $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:74$118.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4964 ($add).
  creating $macc model for $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:74$118.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$4961 ($add).
  creating $macc model for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1069 ($sub).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1024 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1028 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1029 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1032 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1039 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1043 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1031 ($sub).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1006 ($add).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1001 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1150 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1161 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1099 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1110 ($add).
  creating $macc model for $flatten\Core.$add$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:167$712 ($add).
  creating $macc model for $flatten\Core.$sub$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:165$711 ($sub).
  creating $macc model for $flatten\Core.\Alu.$add$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:33$6 ($add).
  creating $macc model for $flatten\Core.\Alu.$sub$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:35$7 ($sub).
  creating $macc model for $flatten\Core.\CSR_Unit.$add$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:116$105 ($add).
  creating $macc model for $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:127$150 ($neg).
  creating $macc model for $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:129$152 ($neg).
  creating $macc model for $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:97$126 ($neg).
  creating $macc model for $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:98$130 ($neg).
  creating $macc model for $flatten\Core.\Mdu.$sub$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:116$144 ($sub).
  creating $macc model for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$701 ($add).
  creating $alu model for $macc $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$701.
  creating $alu model for $macc $flatten\Core.\Mdu.$sub$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:116$144.
  creating $alu model for $macc $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:98$130.
  creating $alu model for $macc $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:97$126.
  creating $alu model for $macc $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:129$152.
  creating $alu model for $macc $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:127$150.
  creating $alu model for $macc $flatten\Core.\CSR_Unit.$add$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:116$105.
  creating $alu model for $macc $flatten\Core.\Alu.$sub$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:35$7.
  creating $alu model for $macc $flatten\Core.\Alu.$add$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:33$6.
  creating $alu model for $macc $flatten\Core.$sub$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:165$711.
  creating $alu model for $macc $flatten\Core.$add$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:167$712.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1110.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1099.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1161.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1150.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1001.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1006.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1031.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1043.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1039.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1032.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1029.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1028.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1024.
  creating $alu model for $macc $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1069.
  creating $alu model for $macc $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:74$118.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$4961.
  creating $alu model for $macc $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:74$118.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4964.
  creating $alu model for $macc $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:74$118.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4967.
  creating $alu model for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1068 ($gt): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1048 ($ge): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1041 ($lt): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1048.
  creating $alu model for $flatten\Core.\Alu.$ge$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:53$19 ($ge): new $alu
  creating $alu model for $flatten\Core.\Alu.$lt$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:37$8 ($lt): merged with $flatten\Core.\Alu.$ge$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:53$19.
  creating $alu model for $flatten\Core.\Mdu.$le$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:115$143 ($le): new $alu
  creating $alu model for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$700 ($lt): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1046 ($eq): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1048.
  creating $alu model for $flatten\Core.\Alu.$eq$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:45$15 ($eq): merged with $flatten\Core.\Alu.$ge$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:53$19.
  creating $alu model for $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$702 ($eq): merged with $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$700.
  creating $alu cell for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$700, $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$702: $auto$alumacc.cc:485:replace_alu$4981
  creating $alu cell for $flatten\Core.\Mdu.$le$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:115$143: $auto$alumacc.cc:485:replace_alu$4992
  creating $alu cell for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1048, $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1041, $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1046: $auto$alumacc.cc:485:replace_alu$5005
  creating $alu cell for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1068: $auto$alumacc.cc:485:replace_alu$5018
  creating $alu cell for $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:74$118.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4967: $auto$alumacc.cc:485:replace_alu$5023
  creating $alu cell for $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:74$118.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$4964: $auto$alumacc.cc:485:replace_alu$5026
  creating $alu cell for $techmap$flatten\Core.\Mdu.$mul$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:74$118.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$4961: $auto$alumacc.cc:485:replace_alu$5029
  creating $alu cell for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1069: $auto$alumacc.cc:485:replace_alu$5032
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1024: $auto$alumacc.cc:485:replace_alu$5035
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1028: $auto$alumacc.cc:485:replace_alu$5038
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1029: $auto$alumacc.cc:485:replace_alu$5041
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1032: $auto$alumacc.cc:485:replace_alu$5044
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1039: $auto$alumacc.cc:485:replace_alu$5047
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1043: $auto$alumacc.cc:485:replace_alu$5050
  creating $alu cell for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1031: $auto$alumacc.cc:485:replace_alu$5053
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1006: $auto$alumacc.cc:485:replace_alu$5056
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1001: $auto$alumacc.cc:485:replace_alu$5059
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969: $auto$alumacc.cc:485:replace_alu$5062
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985: $auto$alumacc.cc:485:replace_alu$5065
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987: $auto$alumacc.cc:485:replace_alu$5068
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$969: $auto$alumacc.cc:485:replace_alu$5071
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$985: $auto$alumacc.cc:485:replace_alu$5074
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$987: $auto$alumacc.cc:485:replace_alu$5077
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1150: $auto$alumacc.cc:485:replace_alu$5080
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1161: $auto$alumacc.cc:485:replace_alu$5083
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1099: $auto$alumacc.cc:485:replace_alu$5086
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1110: $auto$alumacc.cc:485:replace_alu$5089
  creating $alu cell for $flatten\Core.$add$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:167$712: $auto$alumacc.cc:485:replace_alu$5092
  creating $alu cell for $flatten\Core.$sub$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/core.v:165$711: $auto$alumacc.cc:485:replace_alu$5095
  creating $alu cell for $flatten\Core.\Alu.$ge$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:53$19, $flatten\Core.\Alu.$lt$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:37$8, $flatten\Core.\Alu.$eq$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:45$15: $auto$alumacc.cc:485:replace_alu$5098
  creating $alu cell for $flatten\Core.\Alu.$add$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:33$6: $auto$alumacc.cc:485:replace_alu$5111
  creating $alu cell for $flatten\Core.\Alu.$sub$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/alu.v:35$7: $auto$alumacc.cc:485:replace_alu$5114
  creating $alu cell for $flatten\Core.\CSR_Unit.$add$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/csr_unit.v:116$105: $auto$alumacc.cc:485:replace_alu$5117
  creating $alu cell for $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:127$150: $auto$alumacc.cc:485:replace_alu$5120
  creating $alu cell for $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:129$152: $auto$alumacc.cc:485:replace_alu$5123
  creating $alu cell for $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:97$126: $auto$alumacc.cc:485:replace_alu$5126
  creating $alu cell for $flatten\Core.\Mdu.$neg$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:98$130: $auto$alumacc.cc:485:replace_alu$5129
  creating $alu cell for $flatten\Core.\Mdu.$sub$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/mdu.v:116$144: $auto$alumacc.cc:485:replace_alu$5132
  creating $alu cell for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$701: $auto$alumacc.cc:485:replace_alu$5135
  created 39 $alu and 0 $macc cells.

21.23. Executing OPT pass (performing simple optimizations).

21.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~4 debug messages>

21.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~123 debug messages>

21.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

21.23.6. Executing OPT_DFF pass (perform DFF optimizations).

21.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 66 unused wires.
<suppressed ~2 debug messages>

21.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.23.9. Rerunning OPT passes. (Maybe there is more to do..)

21.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~123 debug messages>

21.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.23.13. Executing OPT_DFF pass (perform DFF optimizations).

21.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.23.16. Finished OPT passes. (There is nothing left to do.)

21.24. Executing MEMORY pass.

21.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

21.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

21.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing top.Controller.Data_Memory.memory write port 0.
  Analyzing top.Controller.Memory.memory write port 0.
  Analyzing top.Controller.Uart.RX_FIFO.memory write port 0.
  Analyzing top.Controller.Uart.TX_FIFO.memory write port 0.
  Analyzing top.Core.RegisterBank.registers write port 0.
  Analyzing top.Core.RegisterBank.registers write port 1.
  Analyzing top.Core.RegisterBank.registers write port 2.

21.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

21.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\Controller.Data_Memory.memory'[0] in module `\top': no output FF found.
Checking read port `\Controller.Memory.memory'[0] in module `\top': no output FF found.
Checking read port `\Controller.Uart.RX_FIFO.memory'[0] in module `\top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\Controller.Uart.TX_FIFO.memory'[0] in module `\top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\Core.RegisterBank.registers'[0] in module `\top': no output FF found.
Checking read port `\Core.RegisterBank.registers'[1] in module `\top': merging output FF to cell.
    Write port 0: don't care on collision.
    Write port 1: non-transparent.
    Write port 2: non-transparent.
Checking read port `\Core.RegisterBank.registers'[2] in module `\top': merging output FF to cell.
    Write port 0: don't care on collision.
    Write port 1: non-transparent.
    Write port 2: non-transparent.
Checking read port address `\Controller.Data_Memory.memory'[0] in module `\top': no address FF found.
Checking read port address `\Controller.Memory.memory'[0] in module `\top': no address FF found.
Checking read port address `\Core.RegisterBank.registers'[0] in module `\top': address FF has fully-defined init value, not supported.

21.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 4 unused cells and 86 unused wires.
<suppressed ~9 debug messages>

21.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory top.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.Core.RegisterBank.registers by address:
  Merging ports 0, 2 (address 5'00000).
Consolidating write ports of memory top.Core.RegisterBank.registers by address:
Consolidating write ports of memory top.Core.RegisterBank.registers using sat-based resource sharing:
  Checking group clocked with posedge \Core.CSR_Unit.clk, width 32: ports 0, 1.
  Common input cone for all EN signals: 14 cells.
  Size of unconstrained SAT problem: 110 variables, 305 clauses
  Merging port 1 into port 0.

21.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

21.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

21.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory top.Controller.Data_Memory.memory via $__TRELLIS_DPR16X4_
mapping memory top.Controller.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory top.Controller.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of top.Controller.Uart.RX_FIFO.memory: $\Controller.Uart.RX_FIFO.memory$rdreg[0]
mapping memory top.Controller.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of top.Controller.Uart.TX_FIFO.memory: $\Controller.Uart.TX_FIFO.memory$rdreg[0]
mapping memory top.Core.RegisterBank.registers via $__TRELLIS_DPR16X4_
Extracted data FF from read port 1 of top.Core.RegisterBank.registers: $\Core.RegisterBank.registers$rdreg[1]
Extracted data FF from read port 2 of top.Core.RegisterBank.registers: $\Core.RegisterBank.registers$rdreg[2]
<suppressed ~1178 debug messages>

21.27. Executing TECHMAP pass (map to technology primitives).

21.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

21.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

21.27.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$514fc941ac1ae997c717a8e6a1180ed8e0cf8fa9\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~1107 debug messages>

21.28. Executing OPT pass (performing simple optimizations).

21.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~314 debug messages>

21.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

21.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\ResetBootSystem.$procdff$4241 ($dff) from module top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding SRST signal on $auto$ff.cc:266:slice$4814 ($dffe) from module top (D = $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1043_Y, Q = \Controller.Interpreter.memory_page_number, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$4753 ($dffe) from module top (D = $flatten\Controller.\Interpreter.$procmux$1802_Y [1:0], Q = \Controller.Interpreter.temp_buffer [1:0]).
Adding SRST signal on $auto$ff.cc:266:slice$4536 ($dffe) from module top (D = \Core.Mdu.quociente_msk [31:1], Q = \Core.Mdu.quociente_msk [30:0], rval = 31'0000000000000000000000000000000).
Adding SRST signal on $auto$ff.cc:266:slice$4522 ($dffe) from module top (D = $flatten\Core.\Mdu.$procmux$2563_Y [63], Q = \Core.Mdu.divisor [63], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$4495 ($dffe) from module top (D = $flatten\ResetBootSystem.$procmux$2795_Y, Q = \ResetBootSystem.counter, rval = 6'000000).

21.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 9 unused cells and 7676 unused wires.
<suppressed ~10 debug messages>

21.28.5. Rerunning OPT passes. (Removed registers in this run.)

21.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~7 debug messages>

21.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$7695 ($sdffce) from module top (D = $auto$wreduce.cc:461:run$4954 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).
Adding SRST signal on $auto$ff.cc:266:slice$7694 ($dffe) from module top (D = \Core.Mdu.divisor [31:1], Q = \Core.Mdu.divisor [30:0], rval = 31'0000000000000000000000000000000).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$7693 ($sdffce) from module top.

21.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 7 unused cells and 10 unused wires.
<suppressed ~10 debug messages>

21.28.10. Rerunning OPT passes. (Removed registers in this run.)

21.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.28.13. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$7702 ($dffe) from module top (D = $flatten\Core.\Mdu.$procmux$2563_Y [62], Q = \Core.Mdu.divisor [62], rval = 1'0).

21.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.28.15. Rerunning OPT passes. (Removed registers in this run.)

21.28.16. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.28.17. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.28.18. Executing OPT_DFF pass (perform DFF optimizations).

21.28.19. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.28.20. Finished fast OPT passes.

21.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

21.30. Executing OPT pass (performing simple optimizations).

21.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $auto$memory_share.cc:453:consolidate_wr_using_sat$5239: $auto$rtlil.cc:2497:ReduceOr$5233 -> 1'1
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~81 debug messages>

21.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$7689: { $auto$opt_dff.cc:194:make_patterns_logic$7686 $auto$opt_dff.cc:194:make_patterns_logic$4756 $auto$opt_dff.cc:194:make_patterns_logic$4754 $auto$fsm_map.cc:74:implement_pattern_cache$4483 }
    Consolidated identical input bits for $mux cell $flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$737:
      Old ports: A=\Controller.core_address_memory [11:0], B={ \Controller.Interpreter.memory_page_number [5:0] \Controller.core_address_memory [5:0] }, Y=$auto$wreduce.cc:461:run$4899 [11:0]
      New ports: A=\Controller.core_address_memory [11:6], B=\Controller.Interpreter.memory_page_number [5:0], Y=$auto$wreduce.cc:461:run$4899 [11:6]
      New connections: $auto$wreduce.cc:461:run$4899 [5:0] = \Controller.core_address_memory [5:0]
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1542:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$4902 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$4902 [2] $auto$wreduce.cc:461:run$4902 [0] }
      New connections: $auto$wreduce.cc:461:run$4902 [1] = $auto$wreduce.cc:461:run$4902 [0]
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1547:
      Old ports: A=7'1010010, B=7'0010101, Y=$auto$wreduce.cc:461:run$4903 [6:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$4903 [1:0]
      New connections: $auto$wreduce.cc:461:run$4903 [6:2] = { $auto$wreduce.cc:461:run$4903 [1] 3'010 $auto$wreduce.cc:461:run$4903 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1558:
      Old ports: A=4'1100, B=4'0000, Y=$auto$wreduce.cc:461:run$4904 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4904 [2]
      New connections: { $auto$wreduce.cc:461:run$4904 [3] $auto$wreduce.cc:461:run$4904 [1:0] } = { $auto$wreduce.cc:461:run$4904 [2] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1568:
      Old ports: A=4'1001, B=4'0000, Y=$auto$wreduce.cc:461:run$4906 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4906 [0]
      New connections: $auto$wreduce.cc:461:run$4906 [3:1] = { $auto$wreduce.cc:461:run$4906 [0] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1582:
      Old ports: A=7'0000110, B=7'1010111, Y=$auto$wreduce.cc:461:run$4908 [6:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4908 [0]
      New connections: $auto$wreduce.cc:461:run$4908 [6:1] = { $auto$wreduce.cc:461:run$4908 [0] 1'0 $auto$wreduce.cc:461:run$4908 [0] 3'011 }
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1977:
      Old ports: A=8'00001011, B=302978816, Y=$flatten\Controller.\Interpreter.$procmux$1977_Y
      New ports: A=5'01011, B=20'10010011111011100000, Y=$flatten\Controller.\Interpreter.$procmux$1977_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1977_Y [7:5] = 3'000
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2102:
      Old ports: A={ 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, B={ 40'0000000000000000000000000001010000000000 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2102_Y
      New ports: A=\Controller.Interpreter.communication_buffer [31:8], B={ 24'000000000000000000010100 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2102_Y [23:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$2102_Y [31:24] = 8'00000000
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2112: $auto$opt_reduce.cc:134:opt_pmux$4377
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2316:
      Old ports: A=4'0000, B={ 1'0 $auto$wreduce.cc:461:run$4914 [2:0] 12'000100100011 }, Y=$flatten\Controller.\Uart.$procmux$2316_Y
      New ports: A=3'000, B={ $auto$wreduce.cc:461:run$4914 [2:0] 9'001010011 }, Y=$flatten\Controller.\Uart.$procmux$2316_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2316_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2324:
      Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$4914 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4914 [2]
      New connections: $auto$wreduce.cc:461:run$4914 [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2400:
      Old ports: A=4'0010, B=4'0100, Y=$flatten\Controller.\Uart.$procmux$2400_Y
      New ports: A=2'01, B=2'10, Y=$flatten\Controller.\Uart.$procmux$2400_Y [2:1]
      New connections: { $flatten\Controller.\Uart.$procmux$2400_Y [3] $flatten\Controller.\Uart.$procmux$2400_Y [0] } = 2'00
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_rx.$procmux$1358:
      Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$4927 [0] 1'0 $auto$wreduce.cc:461:run$4928 [1:0] 2'01 \Controller.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$4930 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$4927 [0] $auto$wreduce.cc:461:run$4928 [1:0] 1'1 \Controller.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$4930 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1139:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$4930 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4930 [0]
      New connections: $auto$wreduce.cc:461:run$4930 [1] = $auto$wreduce.cc:461:run$4930 [0]
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_tx.$procmux$1495:
      Old ports: A=3'000, B={ 2'00 \Controller.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$4932 [1:0] 2'01 \Controller.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$4934 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \Controller.Uart.uart_tx_en $auto$wreduce.cc:461:run$4932 [1:0] 1'1 \Controller.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$4934 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1082:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$4934 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4934 [0]
      New connections: $auto$wreduce.cc:461:run$4934 [1] = $auto$wreduce.cc:461:run$4934 [0]
    Consolidated identical input bits for $mux cell $flatten\Core.\ALU_Control.$procmux$4085:
      Old ports: A=4'1001, B=4'0011, Y=$flatten\Core.\ALU_Control.$procmux$4085_Y
      New ports: A=2'10, B=2'01, Y={ $flatten\Core.\ALU_Control.$procmux$4085_Y [3] $flatten\Core.\ALU_Control.$procmux$4085_Y [1] }
      New connections: { $flatten\Core.\ALU_Control.$procmux$4085_Y [2] $flatten\Core.\ALU_Control.$procmux$4085_Y [0] } = 2'01
    Consolidated identical input bits for $mux cell $flatten\Core.\ALU_Control.$procmux$4093:
      Old ports: A=3'010, B=3'110, Y=$auto$wreduce.cc:461:run$4935 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4935 [2]
      New connections: $auto$wreduce.cc:461:run$4935 [1:0] = 2'10
    Consolidated identical input bits for $pmux cell $flatten\Core.\Control_Unit.$procmux$3003:
      Old ports: A=4'0000, B=8'10001001, Y=\Core.control_unit_aluop
      New ports: A=2'00, B=4'1011, Y={ \Core.control_unit_aluop [3] \Core.control_unit_aluop [0] }
      New connections: \Core.control_unit_aluop [2:1] = 2'00
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3320:
      Old ports: A=6'101101, B=6'000000, Y=$flatten\Core.\Control_Unit.$20\nextstate[5:0]
      New ports: A=1'1, B=1'0, Y=$flatten\Core.\Control_Unit.$20\nextstate[5:0] [0]
      New connections: $flatten\Core.\Control_Unit.$20\nextstate[5:0] [5:1] = { $flatten\Core.\Control_Unit.$20\nextstate[5:0] [0] 1'0 $flatten\Core.\Control_Unit.$20\nextstate[5:0] [0] $flatten\Core.\Control_Unit.$20\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3355:
      Old ports: A=6'000000, B=6'100101, Y=$flatten\Core.\Control_Unit.$18\nextstate[5:0]
      New ports: A=1'0, B=1'1, Y=$flatten\Core.\Control_Unit.$18\nextstate[5:0] [0]
      New connections: $flatten\Core.\Control_Unit.$18\nextstate[5:0] [5:1] = { $flatten\Core.\Control_Unit.$18\nextstate[5:0] [0] 2'00 $flatten\Core.\Control_Unit.$18\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3511:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$4942 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$4942 [2] $auto$wreduce.cc:461:run$4942 [0] }
      New connections: $auto$wreduce.cc:461:run$4942 [1] = $auto$wreduce.cc:461:run$4942 [0]
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3547:
      Old ports: A=5'00000, B=5'10010, Y=$auto$wreduce.cc:461:run$4941 [4:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$4941 [1]
      New connections: { $auto$wreduce.cc:461:run$4941 [4:2] $auto$wreduce.cc:461:run$4941 [0] } = { $auto$wreduce.cc:461:run$4941 [1] 3'000 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3585:
      Old ports: A=3'110, B=3'000, Y=$auto$wreduce.cc:461:run$4940 [2:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$4940 [1]
      New connections: { $auto$wreduce.cc:461:run$4940 [2] $auto$wreduce.cc:461:run$4940 [0] } = { $auto$wreduce.cc:461:run$4940 [1] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3634:
      Old ports: A=3'101, B=3'000, Y=$flatten\Core.\Control_Unit.$9\nextstate[5:0] [2:0]
      New ports: A=1'1, B=1'0, Y=$flatten\Core.\Control_Unit.$9\nextstate[5:0] [0]
      New connections: $flatten\Core.\Control_Unit.$9\nextstate[5:0] [2:1] = { $flatten\Core.\Control_Unit.$9\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3737:
      Old ports: A=5'00101, B=5'11000, Y=$flatten\Core.\Control_Unit.$7\nextstate[5:0] [4:0]
      New ports: A=2'01, B=2'10, Y={ $flatten\Core.\Control_Unit.$7\nextstate[5:0] [3] $flatten\Core.\Control_Unit.$7\nextstate[5:0] [0] }
      New connections: { $flatten\Core.\Control_Unit.$7\nextstate[5:0] [4] $flatten\Core.\Control_Unit.$7\nextstate[5:0] [2:1] } = { $flatten\Core.\Control_Unit.$7\nextstate[5:0] [3] $flatten\Core.\Control_Unit.$7\nextstate[5:0] [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3793:
      Old ports: A=5'00011, B=5'10110, Y=$auto$wreduce.cc:461:run$4948 [4:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$4948 [2] $auto$wreduce.cc:461:run$4948 [0] }
      New connections: { $auto$wreduce.cc:461:run$4948 [4:3] $auto$wreduce.cc:461:run$4948 [1] } = { $auto$wreduce.cc:461:run$4948 [2] 2'01 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3908:
      Old ports: A=6'000110, B=6'101111, Y=$flatten\Core.\Control_Unit.$4\nextstate[5:0]
      New ports: A=1'0, B=1'1, Y=$flatten\Core.\Control_Unit.$4\nextstate[5:0] [0]
      New connections: $flatten\Core.\Control_Unit.$4\nextstate[5:0] [5:1] = { $flatten\Core.\Control_Unit.$4\nextstate[5:0] [0] 1'0 $flatten\Core.\Control_Unit.$4\nextstate[5:0] [0] 2'11 }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$4027:
      Old ports: A=6'000000, B=6'101110, Y=$flatten\Core.\Control_Unit.$2\nextstate[5:0]
      New ports: A=1'0, B=1'1, Y=$flatten\Core.\Control_Unit.$2\nextstate[5:0] [1]
      New connections: { $flatten\Core.\Control_Unit.$2\nextstate[5:0] [5:2] $flatten\Core.\Control_Unit.$2\nextstate[5:0] [0] } = { $flatten\Core.\Control_Unit.$2\nextstate[5:0] [1] 1'0 $flatten\Core.\Control_Unit.$2\nextstate[5:0] [1] $flatten\Core.\Control_Unit.$2\nextstate[5:0] [1] 1'0 }
    New ctrl vector for $pmux cell $flatten\Core.\Control_Unit.$procmux$4033: { $flatten\Core.\Control_Unit.$procmux$3214_CMP \Core.Control_Unit.ir_write $flatten\Core.\Control_Unit.$procmux$3105_CMP $flatten\Core.\Control_Unit.$procmux$3104_CMP $flatten\Core.\Control_Unit.$procmux$3212_CMP $flatten\Core.\Control_Unit.$procmux$3185_CMP $flatten\Core.\Control_Unit.$procmux$3077_CMP $auto$opt_reduce.cc:134:opt_pmux$4391 $flatten\Core.\Control_Unit.$procmux$3211_CMP $flatten\Core.\Control_Unit.$procmux$3017_CMP $flatten\Core.\Control_Unit.$procmux$3068_CMP $flatten\Core.\Control_Unit.$procmux$3102_CMP $flatten\Core.\Control_Unit.$procmux$3210_CMP $flatten\Core.\Control_Unit.$procmux$3016_CMP $flatten\Core.\Control_Unit.$procmux$3100_CMP $flatten\Core.\Control_Unit.$procmux$3209_CMP $flatten\Core.\Control_Unit.$procmux$3015_CMP $flatten\Core.\Control_Unit.$procmux$3013_CMP $flatten\Core.\Control_Unit.$procmux$3012_CMP $auto$opt_reduce.cc:134:opt_pmux$7708 $flatten\Core.\Control_Unit.$procmux$3094_CMP $flatten\Core.\Control_Unit.$procmux$3010_CMP $auto$opt_reduce.cc:134:opt_pmux$7706 $flatten\Core.\Control_Unit.$procmux$3089_CMP $flatten\Core.\Control_Unit.$procmux$2880_CMP $flatten\Core.\Control_Unit.$procmux$3088_CMP $flatten\Core.\Control_Unit.$procmux$3208_CMP $flatten\Core.\Control_Unit.$procmux$3007_CMP $flatten\Core.\Control_Unit.$procmux$3006_CMP $flatten\Core.\Control_Unit.$procmux$3085_CMP $flatten\Core.\Control_Unit.$procmux$3005_CMP $flatten\Core.\Control_Unit.$procmux$3004_CMP $flatten\Core.\Control_Unit.$procmux$3082_CMP $flatten\Core.\Control_Unit.$procmux$2879_CMP \Core.Mdu.start $flatten\Core.\Control_Unit.$procmux$3072_CMP }
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$ternary$/var/lib/jenkins/workspace/Risco-5/Risco-5/src/core/control_unit.v:114$30:
      Old ports: A=2'11, B=2'01, Y=\Core.Control_Unit.second_block_write_src_b [1:0]
      New ports: A=1'1, B=1'0, Y=\Core.Control_Unit.second_block_write_src_b [1]
      New connections: \Core.Control_Unit.second_block_write_src_b [0] = 1'1
    Consolidated identical input bits for $pmux cell $flatten\Core.\Immediate_Generator.$procmux$2688:
      Old ports: A={ \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31] \Core.instruction_register [31:20] }, B={ \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24:20] 20'00000000000000000000 \Core.instruction_register [31:20] 27'000000000000000000000000000 \Core.instruction_register [24:20] }, Y=$flatten\Core.\Immediate_Generator.$2\immediate[31:0]
      New ports: A={ \Core.instruction_register [31] \Core.instruction_register [31:25] }, B={ \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] \Core.instruction_register [24] 1'0 \Core.instruction_register [31:25] 8'00000000 }, Y=$flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12:5]
      New connections: { $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [31:13] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [4:0] } = { $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] $flatten\Core.\Immediate_Generator.$2\immediate[31:0] [12] \Core.instruction_register [24:20] }
    Consolidated identical input bits for $mux cell $flatten\Core.\Mdu.$procmux$2560:
      Old ports: A={ 1'0 $flatten\Core.\Mdu.$procmux$2563_Y [62:31] 31'0000000000000000000000000000000 }, B={ 2'00 \Core.Mdu.divisor [62:1] }, Y=$flatten\Core.\Mdu.$procmux$2560_Y
      New ports: A={ $flatten\Core.\Mdu.$procmux$2563_Y [62:31] 31'0000000000000000000000000000000 }, B={ 1'0 \Core.Mdu.divisor [62:1] }, Y=$flatten\Core.\Mdu.$procmux$2560_Y [62:0]
      New connections: $flatten\Core.\Mdu.$procmux$2560_Y [63] = 1'0
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2806: { $flatten\ResetBootSystem.$procmux$2799_CMP $flatten\ResetBootSystem.$procmux$2798_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2809:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2809_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2809_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2809_Y [0] = 1'0
    New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$7705: { $flatten\Core.\Control_Unit.$procmux$3011_CMP $flatten\Core.\Control_Unit.$procmux$3009_CMP $flatten\Core.\Control_Unit.$procmux$3008_CMP }
  Optimizing cells in module \top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2394:
      Old ports: A=4'0000, B={ 3'000 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2400_Y 8'00010011 }, Y=$flatten\Controller.\Uart.$procmux$2394_Y
      New ports: A=3'000, B={ 2'00 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2400_Y [2:1] 7'0001011 }, Y=$flatten\Controller.\Uart.$procmux$2394_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2394_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3375:
      Old ports: A=6'100001, B=$flatten\Core.\Control_Unit.$18\nextstate[5:0], Y=$flatten\Core.\Control_Unit.$17\nextstate[5:0]
      New ports: A=2'01, B={ $flatten\Core.\Control_Unit.$18\nextstate[5:0] [0] $flatten\Core.\Control_Unit.$18\nextstate[5:0] [0] }, Y={ $flatten\Core.\Control_Unit.$17\nextstate[5:0] [2] $flatten\Core.\Control_Unit.$17\nextstate[5:0] [0] }
      New connections: { $flatten\Core.\Control_Unit.$17\nextstate[5:0] [5:3] $flatten\Core.\Control_Unit.$17\nextstate[5:0] [1] } = { $flatten\Core.\Control_Unit.$17\nextstate[5:0] [0] 3'000 }
    Consolidated identical input bits for $pmux cell $flatten\Core.\Control_Unit.$procmux$3963:
      Old ports: A=6'000000, B={ 6'000010 $flatten\Core.\Control_Unit.$4\nextstate[5:0] 42'001000001001001010001100001101001110001111 }, Y=$flatten\Core.\Control_Unit.$3\nextstate[5:0]
      New ports: A=5'00000, B={ 5'00010 $flatten\Core.\Control_Unit.$4\nextstate[5:0] [0] $flatten\Core.\Control_Unit.$4\nextstate[5:0] [0] 2'11 $flatten\Core.\Control_Unit.$4\nextstate[5:0] [0] 35'01000010010101001100011010111001111 }, Y={ $flatten\Core.\Control_Unit.$3\nextstate[5:0] [5] $flatten\Core.\Control_Unit.$3\nextstate[5:0] [3:0] }
      New connections: $flatten\Core.\Control_Unit.$3\nextstate[5:0] [4] = 1'0
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2815:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2809_Y, Y=$flatten\ResetBootSystem.$procmux$2815_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2809_Y [1], Y=$flatten\ResetBootSystem.$procmux$2815_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2815_Y [0] = 1'0
  Optimizing cells in module \top.
Performed a total of 44 changes.

21.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

21.30.6. Executing OPT_DFF pass (perform DFF optimizations).

21.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 5 unused wires.
<suppressed ~2 debug messages>

21.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~1 debug messages>

21.30.9. Rerunning OPT passes. (Maybe there is more to do..)

21.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~83 debug messages>

21.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\Core.\Control_Unit.$procmux$3847:
      Old ports: A={ $auto$wreduce.cc:461:run$4948 [4] $auto$wreduce.cc:461:run$4948 [4] $auto$wreduce.cc:461:run$4948 [0] 1'0 $auto$wreduce.cc:461:run$4948 [0] }, B={ $auto$wreduce.cc:461:run$4948 [4] 1'0 $auto$wreduce.cc:461:run$4948 [4] 1'1 $auto$wreduce.cc:461:run$4948 [0] }, Y=$auto$wreduce.cc:461:run$4947 [4:0]
      New ports: A={ $auto$wreduce.cc:461:run$4948 [4] $auto$wreduce.cc:461:run$4948 [0] 1'0 }, B={ 1'0 $auto$wreduce.cc:461:run$4948 [4] 1'1 }, Y=$auto$wreduce.cc:461:run$4947 [3:1]
      New connections: { $auto$wreduce.cc:461:run$4947 [4] $auto$wreduce.cc:461:run$4947 [0] } = { $auto$wreduce.cc:461:run$4948 [4] $auto$wreduce.cc:461:run$4948 [0] }
  Optimizing cells in module \top.
Performed a total of 1 changes.

21.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.30.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$4633 ($sdff) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$4677 ($sdffe) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$4705 ($sdffe) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$4807 ($sdffe) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$4807 ($sdffe) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$4807 ($sdffe) from module top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$4834 ($dffe) from module top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$4834 ($dffe) from module top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$4834 ($dffe) from module top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$4834 ($dffe) from module top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$4834 ($dffe) from module top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$4834 ($dffe) from module top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$4834 ($dffe) from module top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$4834 ($dffe) from module top.

21.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

21.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~4 debug messages>

21.30.16. Rerunning OPT passes. (Maybe there is more to do..)

21.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~84 debug messages>

21.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1552:
      Old ports: A=8'00000100, B={ 3'000 \Controller.Interpreter.return_state [4:0] }, Y=$flatten\Controller.\Interpreter.$procmux$1552_Y
      New ports: A=5'00100, B=\Controller.Interpreter.return_state [4:0], Y=$flatten\Controller.\Interpreter.$procmux$1552_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1552_Y [7:5] = 3'000
  Optimizing cells in module \top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1530:
      Old ports: A=8'00000000, B={ 7'0000000 $auto$wreduce.cc:461:run$4912 [0] 6'000000 $auto$wreduce.cc:461:run$4905 [1:0] 1'0 $auto$wreduce.cc:461:run$4910 [6:0] 14'00001101000011 $auto$wreduce.cc:461:run$4909 [1:0] 3'000 \Controller.Interpreter.return_state [4:0] 1'0 $auto$wreduce.cc:461:run$4908 [6] 1'0 $auto$wreduce.cc:461:run$4908 [6] 3'011 $auto$wreduce.cc:461:run$4908 [6] 7'0000011 \Controller.Uart.read_response 4'0000 $auto$wreduce.cc:461:run$4904 [3] 2'00 $auto$wreduce.cc:461:run$4904 [3] 6'000010 $auto$wreduce.cc:461:run$4905 [1:0] 20'00001000000010110000 $auto$wreduce.cc:461:run$4904 [3] $auto$wreduce.cc:461:run$4904 [3] 18'000000010100000100 $flatten\Controller.\Interpreter.$procmux$1552_Y 1'0 $auto$wreduce.cc:461:run$4903 [6] 3'010 $auto$wreduce.cc:461:run$4903 [2] $auto$wreduce.cc:461:run$4903 [6] $auto$wreduce.cc:461:run$4903 [2] 13'0001001100010 $auto$wreduce.cc:461:run$4902 [2:1] $auto$wreduce.cc:461:run$4902 [1] 31'0001011001010010000100000001000 $auto$wreduce.cc:461:run$4901 [0] 8'00000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1530_Y
      New ports: A=7'0000000, B={ 6'000000 $auto$wreduce.cc:461:run$4912 [0] 5'00000 $auto$wreduce.cc:461:run$4905 [1:0] $auto$wreduce.cc:461:run$4910 [6:0] 12'000110100011 $auto$wreduce.cc:461:run$4909 [1:0] 2'00 \Controller.Interpreter.return_state [4:0] $auto$wreduce.cc:461:run$4908 [6] 1'0 $auto$wreduce.cc:461:run$4908 [6] 3'011 $auto$wreduce.cc:461:run$4908 [6] 6'000011 \Controller.Uart.read_response 3'000 $auto$wreduce.cc:461:run$4904 [3] 2'00 $auto$wreduce.cc:461:run$4904 [3] 5'00010 $auto$wreduce.cc:461:run$4905 [1:0] 17'00010000001011000 $auto$wreduce.cc:461:run$4904 [3] $auto$wreduce.cc:461:run$4904 [3] 18'000000101000010000 $flatten\Controller.\Interpreter.$procmux$1552_Y [4:0] $auto$wreduce.cc:461:run$4903 [6] 3'010 $auto$wreduce.cc:461:run$4903 [2] $auto$wreduce.cc:461:run$4903 [6] $auto$wreduce.cc:461:run$4903 [2] 11'00100110010 $auto$wreduce.cc:461:run$4902 [2:1] $auto$wreduce.cc:461:run$4902 [1] 27'001011010100100010000001000 $auto$wreduce.cc:461:run$4901 [0] 7'0000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1530_Y [6:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1530_Y [7] = 1'0
  Optimizing cells in module \top.
Performed a total of 2 changes.

21.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.30.20. Executing OPT_DFF pass (perform DFF optimizations).

21.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.30.23. Rerunning OPT passes. (Maybe there is more to do..)

21.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~84 debug messages>

21.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.30.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.30.27. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$4862 ($sdff) from module top.

21.30.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.30.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~1 debug messages>

21.30.30. Rerunning OPT passes. (Maybe there is more to do..)

21.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~84 debug messages>

21.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.30.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.30.34. Executing OPT_DFF pass (perform DFF optimizations).

21.30.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.30.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.30.37. Finished OPT passes. (There is nothing left to do.)

21.31. Executing TECHMAP pass (map to technology primitives).

21.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

21.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $dffe.
Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $bmux.
Using extmapper simplemap for cells of type $not.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $dff.
Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $lut.
Using template $paramod$c04af8dbf0e5d1d69bbccb2c7bd8a93fc9ef54dc\_80_ecp5_alu for cells of type $alu.
Using template $paramod$8a99b868050f542c83270fc93de09787e35f2c64\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ecp5_alu for cells of type $alu.
Using template $paramod$039520c137afc9cd69dd56c3fb11a4e1fbe5f664\_80_ecp5_alu for cells of type $alu.
Using template $paramod$bdc78fe5225b43c64ccdf13e5eb67d9dcf228e8a\_80_ecp5_alu for cells of type $alu.
Using template $paramod$ff467a932a72bec5a93c27dba04bf3daba067451\_80_ecp5_alu for cells of type $alu.
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$c9511eeb847f2aa95252b1013477609463f67ee0\_80_ecp5_alu for cells of type $alu.
Using template $paramod$a7b312e4ba8fdc79d4c5e0789e4e6c41ea3896fb\_90_pmux for cells of type $pmux.
Using template $paramod$7a385d5b7a2e603dbc5beef838648775b433f248\_90_pmux for cells of type $pmux.
Using template $paramod$54a4503cc57b9df40b70c1899504d6aac2650719\_90_pmux for cells of type $pmux.
Using template $paramod$59b03ae2620a41577de8da5f5c97b2919e82362b\_90_pmux for cells of type $pmux.
Using template $paramod$24fb226dd75c9d3f6955ec2ad61d794776778cf6\_90_pmux for cells of type $pmux.
Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using template $paramod$ac45afa5bcd8e16ca475cce13f9d19bb109f1516\_80_ecp5_alu for cells of type $alu.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using template $paramod$73d715d333263ca9cf422f13d07e21664e3ab775\_80_ecp5_alu for cells of type $alu.
Using template $paramod$ed6389a5938b09f91843a91d67becca5abedb1bd\_90_pmux for cells of type $pmux.
Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux.
Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux.
Using template $paramod$c96def1cdcef2eee3c62e5dfb7ba2dd09c9f74dd\_90_pmux for cells of type $pmux.
Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$335cfd09f1afa8139c4aafcbbe5f361887b79c5e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$5180471e6f22625c8e3c4261cd538e11648586b5\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.
Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\_90_pmux for cells of type $pmux.
Using template $paramod$95ab7b964273918a033d1324366ecc612d202989\_90_pmux for cells of type $pmux.
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using template $paramod$a285b5a57fe61eabc57c91b8c412748ee1151a85\_90_pmux for cells of type $pmux.
Using template $paramod$e25898cce02b4d043ab08e065e45db8cf66c901c\_90_pmux for cells of type $pmux.
Using template $paramod$730057d8259da96d4776b15a47b747852ed4c479\_90_pmux for cells of type $pmux.
Using template $paramod$e13ed4cc4d636b3e93547ec233231d1aa3a8ac92\_90_pmux for cells of type $pmux.
Using template $paramod$c6baa65225090ac0a120feab1b920965244aa496\_80_ecp5_alu for cells of type $alu.
Using template $paramod$610911f8769324f781128d641f7fe2120143c328\_80_ecp5_alu for cells of type $alu.
Using template $paramod$2126a3039e9678f6a4bd73d35a1f58ee2616afb2\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~6510 debug messages>

21.32. Executing OPT pass (performing simple optimizations).

21.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~13037 debug messages>

21.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6312 debug messages>
Removed a total of 2104 cells.

21.32.3. Executing OPT_DFF pass (perform DFF optimizations).

21.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 2054 unused cells and 6905 unused wires.
<suppressed ~2060 debug messages>

21.32.5. Finished fast OPT passes.

21.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

21.35. Executing TECHMAP pass (map to technology primitives).

21.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

21.35.2. Continuing TECHMAP pass.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template $paramod\$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PN_.
No more expansions possible.
<suppressed ~1636 debug messages>

21.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~89 debug messages>

21.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

21.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in top.

21.39. Executing ATTRMVCP pass (move or copy attributes).

21.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 8395 unused wires.
<suppressed ~1 debug messages>

21.41. Executing TECHMAP pass (map to technology primitives).

21.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

21.41.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

21.42. Executing ABC9 pass.

21.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.3. Executing PROC pass (convert processes to netlists).

21.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$45954'.
Cleaned up 1 empty switch.

21.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45955 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.3.4. Executing PROC_INIT pass (extract init attributes).

21.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45955'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45953_EN[3:0]$45961
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45953_DATA[3:0]$45960
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45953_ADDR[3:0]$45959
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$45954'.

21.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45937_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45938_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45942_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45943_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45947_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45939_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45948_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45952_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45944_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45940_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45949_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45945_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45950_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45951_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45946_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$45941_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45953_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45955'.
  created $dff cell `$procdff$46005' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45953_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45955'.
  created $dff cell `$procdff$46006' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$45953_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45955'.
  created $dff cell `$procdff$46007' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$45954'.
  created direct connection (no actual register cell created).

21.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$45979'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$45955'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$45954'.
Cleaned up 1 empty switch.

21.42.3.12. Executing OPT_EXPR pass (perform const folding).

21.42.4. Executing PROC pass (convert processes to netlists).

21.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$46025'.
Cleaned up 1 empty switch.

21.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46026 in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

21.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

21.42.4.4. Executing PROC_INIT pass (extract init attributes).

21.42.4.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

21.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46026'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46024_EN[3:0]$46031
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46024_DATA[3:0]$46030
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46024_ADDR[3:0]$46032
Creating decoders for process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$46025'.

21.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\i' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46008_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46010_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46011_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46015_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46016_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46020_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46012_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46021_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46017_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46013_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46022_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46018_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46023_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46019_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46014_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$46009_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46024_DATA' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46026'.
  created $dff cell `$procdff$46076' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46024_EN' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46026'.
  created $dff cell `$procdff$46077' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$46024_ADDR' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46026'.
  created $dff cell `$procdff$46078' with positive edge clock.
Creating register for signal `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.\muxwre' using process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$46025'.
  created direct connection (no actual register cell created).

21.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$46050'.
Found and cleaned up 1 empty switch in `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$46026'.
Removing empty process `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$46025'.
Cleaned up 1 empty switch.

21.42.4.12. Executing OPT_EXPR pass (perform const folding).

21.42.5. Executing SCC pass (detecting logic loops).
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$10041 $auto$simplemap.cc:126:simplemap_reduce$10308 $auto$simplemap.cc:126:simplemap_reduce$10306 $auto$simplemap.cc:126:simplemap_reduce$10044 $auto$simplemap.cc:126:simplemap_reduce$10042 $auto$simplemap.cc:38:simplemap_not$10349 $auto$ff.cc:266:slice$23975 $auto$ff.cc:479:convert_ce_over_srst$44327 $auto$ff.cc:266:slice$23973 $auto$ff.cc:479:convert_ce_over_srst$44323 $auto$opt_expr.cc:617:replace_const_cells$44015 $auto$ff.cc:266:slice$23971 $auto$ff.cc:479:convert_ce_over_srst$44319 $auto$ff.cc:266:slice$23976 $auto$ff.cc:479:convert_ce_over_srst$44329 $auto$simplemap.cc:126:simplemap_reduce$10274 $auto$simplemap.cc:38:simplemap_not$25499 $auto$ff.cc:266:slice$23974 $auto$ff.cc:479:convert_ce_over_srst$44325 $auto$simplemap.cc:38:simplemap_not$10006 $auto$alumacc.cc:485:replace_alu$4981.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$4981.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$4981.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$10277 $auto$simplemap.cc:126:simplemap_reduce$10273 $auto$simplemap.cc:38:simplemap_not$25497 $auto$ff.cc:266:slice$23972 $auto$ff.cc:479:convert_ce_over_srst$44321 $auto$simplemap.cc:126:simplemap_reduce$21994 $auto$simplemap.cc:75:simplemap_bitop$10028 $auto$simplemap.cc:126:simplemap_reduce$10279 $auto$simplemap.cc:126:simplemap_reduce$10275 $auto$simplemap.cc:38:simplemap_not$38777
Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$43593 $auto$ff.cc:266:slice$16798 $auto$simplemap.cc:126:simplemap_reduce$16899 $auto$simplemap.cc:126:simplemap_reduce$16914 $auto$ff.cc:266:slice$16797 $auto$ff.cc:266:slice$16796 $auto$simplemap.cc:126:simplemap_reduce$30623 $auto$simplemap.cc:75:simplemap_bitop$30638 $auto$simplemap.cc:267:simplemap_mux$16885 $auto$simplemap.cc:225:simplemap_logbin$16888 $auto$simplemap.cc:196:simplemap_lognot$16903 $auto$simplemap.cc:126:simplemap_reduce$16901 $auto$simplemap.cc:126:simplemap_reduce$16898 $auto$simplemap.cc:38:simplemap_not$30568 $auto$opt_expr.cc:617:replace_const_cells$43603 $auto$simplemap.cc:267:simplemap_mux$30640 $auto$simplemap.cc:126:simplemap_reduce$30631 $auto$simplemap.cc:126:simplemap_reduce$30628 $auto$simplemap.cc:75:simplemap_bitop$30636 $auto$simplemap.cc:196:simplemap_lognot$16918 $auto$simplemap.cc:126:simplemap_reduce$16916 $auto$simplemap.cc:126:simplemap_reduce$16913 $auto$ff.cc:266:slice$16795 $auto$simplemap.cc:126:simplemap_reduce$10708 $auto$simplemap.cc:126:simplemap_reduce$10706 $auto$simplemap.cc:225:simplemap_logbin$16844 $auto$simplemap.cc:196:simplemap_lognot$16854 $auto$simplemap.cc:126:simplemap_reduce$16852 $auto$opt_expr.cc:617:replace_const_cells$43605 $auto$simplemap.cc:267:simplemap_mux$30641 $auto$simplemap.cc:126:simplemap_reduce$30626
Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$43959 $auto$ff.cc:266:slice$16799 $auto$ff.cc:266:slice$16807 $auto$opt_expr.cc:617:replace_const_cells$43233 $auto$ff.cc:266:slice$16806 $auto$simplemap.cc:126:simplemap_reduce$16936 $auto$opt_expr.cc:617:replace_const_cells$43231 $auto$ff.cc:266:slice$16805 $auto$ff.cc:266:slice$16804 $auto$simplemap.cc:126:simplemap_reduce$16939 $auto$simplemap.cc:126:simplemap_reduce$16935 $auto$simplemap.cc:38:simplemap_not$30691 $auto$ff.cc:266:slice$16803 $auto$ff.cc:266:slice$16802 $auto$ff.cc:266:slice$16801 $auto$simplemap.cc:126:simplemap_reduce$16933 $auto$ff.cc:266:slice$16800 $auto$simplemap.cc:126:simplemap_reduce$10614 $auto$simplemap.cc:196:simplemap_lognot$16945 $auto$simplemap.cc:126:simplemap_reduce$16943 $auto$simplemap.cc:126:simplemap_reduce$16941 $auto$simplemap.cc:126:simplemap_reduce$16938 $auto$simplemap.cc:126:simplemap_reduce$16934 $auto$simplemap.cc:38:simplemap_not$30690
Found an SCC: $auto$ff.cc:266:slice$14636 $auto$opt_expr.cc:617:replace_const_cells$43631 $auto$ff.cc:266:slice$14635 $auto$simplemap.cc:126:simplemap_reduce$16749 $auto$simplemap.cc:126:simplemap_reduce$16780 $auto$opt_expr.cc:617:replace_const_cells$43629 $auto$ff.cc:266:slice$14634 $auto$simplemap.cc:38:simplemap_not$30617 $auto$ff.cc:266:slice$14633 $auto$simplemap.cc:126:simplemap_reduce$16752 $auto$simplemap.cc:126:simplemap_reduce$16748 $auto$simplemap.cc:126:simplemap_reduce$16783 $auto$simplemap.cc:126:simplemap_reduce$16779 $auto$simplemap.cc:38:simplemap_not$30616 $auto$ff.cc:266:slice$14632 $auto$opt_expr.cc:617:replace_const_cells$43625 $auto$ff.cc:266:slice$14631 $auto$simplemap.cc:126:simplemap_reduce$16778 $auto$simplemap.cc:126:simplemap_reduce$16747 $auto$simplemap.cc:38:simplemap_not$30614 $auto$ff.cc:266:slice$14630 $auto$ff.cc:266:slice$14629 $auto$simplemap.cc:196:simplemap_lognot$16789 $auto$simplemap.cc:126:simplemap_reduce$16787 $auto$simplemap.cc:126:simplemap_reduce$16785 $auto$simplemap.cc:126:simplemap_reduce$16782 $auto$simplemap.cc:126:simplemap_reduce$16777 $auto$simplemap.cc:38:simplemap_not$30612 $auto$simplemap.cc:225:simplemap_logbin$16731 $auto$simplemap.cc:196:simplemap_lognot$16758 $auto$simplemap.cc:126:simplemap_reduce$16756 $auto$simplemap.cc:126:simplemap_reduce$16754 $auto$simplemap.cc:126:simplemap_reduce$16751 $auto$simplemap.cc:126:simplemap_reduce$16746 $auto$ff.cc:266:slice$14628 $auto$simplemap.cc:167:logic_reduce$10259 $auto$simplemap.cc:225:simplemap_logbin$16730
Found 4 SCCs in module top.
Found 4 SCCs.

21.42.6. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.7. Executing PROC pass (convert processes to netlists).

21.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

21.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

21.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

21.42.7.4. Executing PROC_INIT pass (extract init attributes).

21.42.7.5. Executing PROC_ARST pass (detect async resets in processes).

21.42.7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

21.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

21.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

21.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs).

21.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

21.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

21.42.7.12. Executing OPT_EXPR pass (perform const folding).

21.42.8. Executing TECHMAP pass (map to technology primitives).

21.42.8.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.42.8.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~164 debug messages>

21.42.9. Executing OPT pass (performing simple optimizations).

21.42.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.

21.42.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

21.42.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Performed a total of 0 changes.

21.42.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

21.42.9.6. Executing OPT_DFF pass (perform DFF optimizations).

21.42.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4..

21.42.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.

21.42.9.9. Finished OPT passes. (There is nothing left to do.)

21.42.10. Executing TECHMAP pass (map to technology primitives).

21.42.10.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

21.42.10.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~1080 debug messages>

21.42.11. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

21.42.12. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

21.42.13. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.14. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

21.42.15. Executing TECHMAP pass (map to technology primitives).

21.42.15.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

21.42.15.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~203 debug messages>

21.42.16. Executing OPT pass (performing simple optimizations).

21.42.16.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~18 debug messages>

21.42.16.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

21.42.16.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.16.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.42.16.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.42.16.6. Executing OPT_DFF pass (perform DFF optimizations).

21.42.16.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

21.42.16.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.42.16.9. Rerunning OPT passes. (Maybe there is more to do..)

21.42.16.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

21.42.16.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

21.42.16.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

21.42.16.13. Executing OPT_DFF pass (perform DFF optimizations).

21.42.16.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

21.42.16.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

21.42.16.16. Finished OPT passes. (There is nothing left to do.)

21.42.17. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

21.42.18. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 8633 cells with 52879 new cells, skipped 6522 cells.
  replaced 4 cell types:
    2516 $_OR_
     211 $_XOR_
       1 $_ORNOT_
    5905 $_MUX_
  not replaced 11 cell types:
      25 $scopeinfo
     554 $_NOT_
    1857 $_AND_
    1510 TRELLIS_FF
       4 MULT18X18D
     419 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
      24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp
       1 $__ABC9_SCC_BREAKER
    1052 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
      24 $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4
    1052 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4

21.42.18.1. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.18.2. Executing ABC9_OPS pass (helper functions for ABC9).

21.42.18.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 22722 AND gates and 68013 wires from module `top' to a netlist network with 5953 inputs and 1719 outputs.

21.42.18.4. Executing ABC9_EXE pass (technology mapping using ABC9).

21.42.18.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   5953/   1719  and =   21069  lev =   44 (3.09)  mem = 0.63 MB  box = 1495  bb = 1076
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   5953/   1719  and =   28068  lev =   55 (2.14)  mem = 0.71 MB  ch = 2560  box = 1479  bb = 1076
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   64. Obj =  148. Set =  672. CutMin = no
ABC: Node =   28068.  Ch =  1882.  Total mem =    8.37 MB. Peak cut mem =    0.23 MB.
ABC: P:  Del = 5921.00.  Ar =   38647.0.  Edge =    39840.  Cut =   337610.  T =     0.16 sec
ABC: P:  Del = 5871.00.  Ar =   38608.0.  Edge =    39837.  Cut =   333732.  T =     0.16 sec
ABC: P:  Del = 5871.00.  Ar =   24999.0.  Edge =    33913.  Cut =   791114.  T =     0.35 sec
ABC: F:  Del = 5871.00.  Ar =   11331.0.  Edge =    25895.  Cut =   625227.  T =     0.29 sec
ABC: A:  Del = 5871.00.  Ar =    9889.0.  Edge =    24686.  Cut =   613428.  T =     0.50 sec
ABC: A:  Del = 5871.00.  Ar =    9802.0.  Edge =    24532.  Cut =   602131.  T =     0.63 sec
ABC: Total time =     2.09 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   5953/   1719  and =   21521  lev =   33 (2.31)  mem = 0.64 MB  box = 1479  bb = 1076
ABC: Mapping (K=7)  :  lut =   6436  edge =   24352  lev =   12 (1.26)  Boxes are not in a topological order. Switching to level computation without boxes.
ABC: levB =   33  mem = 0.32 MB
ABC: LUT = 6436 : 2=803 12.5 %  3=1847 28.7 %  4=2375 36.9 %  5=1003 15.6 %  6=166 2.6 %  7=242 3.8 %  Ave = 3.78
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 19.96 seconds, total: 19.96 seconds

21.42.18.6. Executing AIGER frontend.
<suppressed ~15372 debug messages>
Removed 27771 unused cells and 58365 unused wires.

21.42.18.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     6449
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      403
ABC RESULTS:   $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp cells:       24
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:     1052
ABC RESULTS:           input signals:     1166
ABC RESULTS:          output signals:      297
Removing temp directory.

21.42.19. Executing TECHMAP pass (map to technology primitives).

21.42.19.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

21.42.19.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4 for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$d1cad21b87e74b01c8dcd657997284bb4d05c02a\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000110 for cells of type $__ABC9_SCC_BREAKER.
No more expansions possible.
<suppressed ~2577 debug messages>
Removed 461 unused cells and 85101 unused wires.

21.43. Executing TECHMAP pass (map to technology primitives).

21.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

21.43.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$540d19b8a46cefa2c5fb0babb817359ee295fdd5\$lut for cells of type $lut.
Using template $paramod$86383343966e3bff32e6853693315c5777aea5e0\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec\$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71\$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod$5bb4589aef4e67d4113ef14e01c5bb618a3e9139\$lut for cells of type $lut.
Using template $paramod$eaea85d27cc0950ed001348e061727a194f5cf9c\$lut for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod$9cc51547ab44a72dd506ee5bb84a864365a103da\$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod$3a0a392069bc969f34c65c546a8c56fbbb67e282\$lut for cells of type $lut.
Using template $paramod$94e65f323749ab2f501acf5577af42456678fff9\$lut for cells of type $lut.
Using template $paramod$11e42b90959ff31fabde13b33b2981b990d8da58\$lut for cells of type $lut.
Using template $paramod$6e2b27a23561eba4d5d7a3612a01502854865858\$lut for cells of type $lut.
Using template $paramod$0fa1c6e5d65a4e509c15b676a94b9aed076b9f4d\$lut for cells of type $lut.
Using template $paramod$11f7a95762c5b4b70c087a0502121611638269c5\$lut for cells of type $lut.
Using template $paramod$9fc14cb0ba5120a1da0c687a9fb19472f206fdfe\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$6023c671e114c4eb0467aa8a0b08e183f33ec2fd\$lut for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod$3c5eb16fa418cfbbe1710d24d17e7d0b5448c3c1\$lut for cells of type $lut.
Using template $paramod$d546db88fc169832512e499a9cdf9a41b89ab74e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod$a47d3f6fd9a7aebdb1b556bc977da3380a17c8cf\$lut for cells of type $lut.
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod$2de23df76a24087ecc0fa38a78ecc970cd3f2492\$lut for cells of type $lut.
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut.
Using template $paramod$df5c8730c0a53792c3f54c2192a2221c27162fb5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod$90dc599eed99da511e64ad217d69e7ff2c1e56cc\$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$b18a3edb490ff3a49fefc94182a05f36efbdbba2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$ccd3e15dc00d71b9284dff48e88ccef5be7362c8\$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod$fb7bbfbe62f17d1abd6f8eaee546f5a966c46c29\$lut for cells of type $lut.
Using template $paramod$c8f2b00a2feb859040935d06cafa51f6c4e20e0d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$30f4da6ff0d10c116990e5fb74d5fd3e137d77f7\$lut for cells of type $lut.
Using template $paramod$877859204cc06b766f4cb38f89dea559af1e3734\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$62d7282b645842e91e72b88a8416253acec2fcfc\$lut for cells of type $lut.
Using template $paramod$5348912da867a611a8088b6b8b27a62d65f1de6e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut.
Using template $paramod$f0bef4a30c0ab8325e910c7b53ed5044c4e7d707\$lut for cells of type $lut.
Using template $paramod$8e1c82b304528085a78e4651c993ce9e1ef6b8a8\$lut for cells of type $lut.
Using template $paramod$bce98cbc4c7663d9534fcdf870483176065e0cfd\$lut for cells of type $lut.
Using template $paramod$03d0edf20ed1469b09ef5ea8e93986bf65c1867c\$lut for cells of type $lut.
Using template $paramod$a2f8c0f49f5179aa0ab5b87e4b39f0b9aaf82f5a\$lut for cells of type $lut.
Using template $paramod$6b9cd69b1e76a46d20d4fcfe7e78c87a68771565\$lut for cells of type $lut.
Using template $paramod$760cbd2b0865be4df85054ed8df8a4e88164e55a\$lut for cells of type $lut.
Using template $paramod$796a976cd67711f2c509e1e9b3c47121c5427850\$lut for cells of type $lut.
Using template $paramod$abb59c83b8ed9f89252ad5e5d1ca1d0e979fcd98\$lut for cells of type $lut.
Using template $paramod$991f5fcb82fd10139056a359ffc4a67f44aea8ab\$lut for cells of type $lut.
Using template $paramod$86b3760cb96b770d612108cec5e7aac5497f3312\$lut for cells of type $lut.
Using template $paramod$80fd3f90b6a7b38da9d25588666decbe3adaf5ec\$lut for cells of type $lut.
Using template $paramod$5c19119f33c3c4c71a99794afcfb22b3879c3f21\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$56c17e6b75008244fc881c7eb75e21c7a76da222\$lut for cells of type $lut.
Using template $paramod$8dc7036079d7be3e5b8905f947c0888c82aab734\$lut for cells of type $lut.
Using template $paramod$692c4ee85d95f8cc4959911841a85a43ebfd3f05\$lut for cells of type $lut.
Using template $paramod$384dd8fd176e9fb45aae56ef8f5af5a6b7507981\$lut for cells of type $lut.
Using template $paramod$2387b865264d2d5dd6e9369a05ee6aefeacaedc6\$lut for cells of type $lut.
Using template $paramod$dd8f09456cc0557d76e7a209e6cf5c8b8adde891\$lut for cells of type $lut.
Using template $paramod$c9b437eae7cbae92bcce00de6505397a13545859\$lut for cells of type $lut.
Using template $paramod$d6e6d411b16e057eae3ca70523bb1b2722704525\$lut for cells of type $lut.
Using template $paramod$965f8f2fa1a796a6c51222eabb50fbd26e97d98b\$lut for cells of type $lut.
Using template $paramod$432f26b811c14bf54c5e87c8670ec65cbcaf38ac\$lut for cells of type $lut.
Using template $paramod$a6b2d4693fada6bebbe4480262641915d709d280\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$8c2f43e08c9cc2b49de93af951f385231789cba4\$lut for cells of type $lut.
Using template $paramod$323fbd8da0ac5986920f0496885d4acac13656a5\$lut for cells of type $lut.
Using template $paramod$88e557ff47f35512152dcd123e39a7dd2f3f82eb\$lut for cells of type $lut.
Using template $paramod$e800d193f17c895194d1649dde3e5037bf808d28\$lut for cells of type $lut.
Using template $paramod$cd14f2ec08667ca50a951d6d9af08c05385f11fd\$lut for cells of type $lut.
Using template $paramod$4237ec31543859d6444b0df9382030ab13f55b7e\$lut for cells of type $lut.
Using template $paramod$375cab7262c9d7ee4744a5653313680b6745f29f\$lut for cells of type $lut.
Using template $paramod$98dbdcd471ba0a28148297d600246e9d7dd9fa99\$lut for cells of type $lut.
Using template $paramod$7ac0d693e8b843c95e28e03fd4fd6964982c85ff\$lut for cells of type $lut.
Using template $paramod$f587be5dee6fb7e49a5d3ac9ec8f717822a31ea2\$lut for cells of type $lut.
Using template $paramod$184cc4d1a21ffdaab9f51bd678a8002afa0d20c9\$lut for cells of type $lut.
Using template $paramod$06e62c2045624c211a1abe4f2f36c8f22c688165\$lut for cells of type $lut.
Using template $paramod$95c50498433da1a7bcd81cd4bbcc14d8afa1d99f\$lut for cells of type $lut.
Using template $paramod$70c7a29c0eecf1b0e2c5fe73ab7bdb3355f0e4f1\$lut for cells of type $lut.
Using template $paramod$7927bcf0ebf9ad32c99c221ff948f324620c5795\$lut for cells of type $lut.
Using template $paramod$0b8aade62caf8009a7529766eee65bfb9f886187\$lut for cells of type $lut.
Using template $paramod$f9a0ee47e847498cc2c73a71676b0bb314dba181\$lut for cells of type $lut.
Using template $paramod$abe30241e91d635f642fd4b1487275dfd81be8aa\$lut for cells of type $lut.
Using template $paramod$1e06da73d21c5736c1f943dd00fdcd4f80e36a2b\$lut for cells of type $lut.
Using template $paramod$7052bb73849c84c4a3e13a9f5c8c1cfa327a857f\$lut for cells of type $lut.
Using template $paramod$25276620941218706745e8e30698403f5fe815fc\$lut for cells of type $lut.
Using template $paramod$d7372df0dc02a6c940130cc6e3dbb5dc0398486d\$lut for cells of type $lut.
Using template $paramod$7e8d331d1e06632d29fbdf6c3afc2de1856d3c67\$lut for cells of type $lut.
Using template $paramod$852c9e8f9569e58eab2a26a88e78feae599a76e3\$lut for cells of type $lut.
Using template $paramod$234fd643079033ba0cbc98ff572df9b7b7a0dc86\$lut for cells of type $lut.
Using template $paramod$ab6391b7aa9150f964629cd88de8d120d54fdbef\$lut for cells of type $lut.
Using template $paramod$6e424bd4a747f8421ac946af3d9bb3a47fd0b233\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$de81bb4f24bddd9c01fb4a8d2c0db4e04ac2517e\$lut for cells of type $lut.
Using template $paramod$c6877cca211c96bd98fd8e58ef57c17dd114bfc3\$lut for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$afcd666aa0d6e4a9a7d8b5a2bd4ab2f7ccb6ea4a\$lut for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
Using template $paramod$63dfb5d507c3c0842cdb02014ffa50dbe5770b84\$lut for cells of type $lut.
Using template $paramod$59386926660204821db84ea6ffbaed946c83731b\$lut for cells of type $lut.
Using template $paramod$ed15ce309f0e9cc1a0a56b9ebd3a7f0f503b5307\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut.
Using template $paramod$f9b715fbf1040e81e900b2461c2390d17ed5e988\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut.
Using template $paramod$903905cca899aab473483ca27c3db12d7108e3a5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$0d5c5cc9e622bb1fd6d05a71dc387f5106b764d5\$lut for cells of type $lut.
Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut.
Using template $paramod$4fc6efaec5bd8994232500ce8f8be9cb357522d5\$lut for cells of type $lut.
Using template $paramod$3331a91b4e24483a258fc0d47474cffbd93ab577\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut.
Using template $paramod$5502a85110dbca29ac631107f0b0635e7fade476\$lut for cells of type $lut.
Using template $paramod$6f946605d401d287ca204d65d6119ccd7ff7419c\$lut for cells of type $lut.
Using template $paramod$59601b4481617ef8784cc027d3c1241388c1c653\$lut for cells of type $lut.
Using template $paramod$d5c8c8245682ad8e9d887074f98492fd9ae619fc\$lut for cells of type $lut.
Using template $paramod$5a439d3fe9d59f4064420d2449c67e37851616ca\$lut for cells of type $lut.
Using template $paramod$4eb848e991ac2a992be9b4be01f278b220c0efac\$lut for cells of type $lut.
Using template $paramod$c7eaad6a588218ef0ba5a17502d003bdff2bbd3e\$lut for cells of type $lut.
Using template $paramod$ae9483265228e4e0b2c20bd8c835dd40724e466e\$lut for cells of type $lut.
Using template $paramod$b035762d6265eb7c924c8c10d28889d1029384d1\$lut for cells of type $lut.
Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut.
Using template $paramod$5289dac6f25369a9a495c69c724c25ee83ad0e78\$lut for cells of type $lut.
Using template $paramod$058a3c6c4a5973a6fa96322456e9fa0d3a1a38f6\$lut for cells of type $lut.
Using template $paramod$60096d1cdb5f7f55fdf4ed3aab322b5c7375f61e\$lut for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut.
Using template $paramod$4127e3976804cc3e2776f400bd237bcbcbc6c10f\$lut for cells of type $lut.
Using template $paramod$e71cf4ecb6134cf09d0f364e10de17b50d29f5ea\$lut for cells of type $lut.
Using template $paramod$415e222a12b303e67849afa76b3b77c687e431a8\$lut for cells of type $lut.
Using template $paramod$63c21a63caf7b85f1f888b02cf745b7d3944fb57\$lut for cells of type $lut.
Using template $paramod$551255077450f9c1e924b6d1a14c12bea820b3ab\$lut for cells of type $lut.
Using template $paramod$9a3e28b389c1f3cb6cf0807228c461506fb829f5\$lut for cells of type $lut.
Using template $paramod$30ca20dc788fa30ea61dcb4fd06646750dab3381\$lut for cells of type $lut.
Using template $paramod$b308ed763aba7ea4c9494721302f5b77689bbba7\$lut for cells of type $lut.
Using template $paramod$4609d6170df9df51ab903023a98ef7fe930e70d9\$lut for cells of type $lut.
Using template $paramod$bf6de8dce6d7dd51475db454722c4388347732a0\$lut for cells of type $lut.
Using template $paramod$2de8b2d0f6086e896d2b4145ba0913d9a18e16c8\$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod$b8bc93a50860defb026422e051b1b5c80f73638b\$lut for cells of type $lut.
Using template $paramod$faae99167d1a68b4706629f7377db56fc7d6de28\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$2b3cd97aa558ca86457a503c9831e52714a436eb\$lut for cells of type $lut.
Using template $paramod$3be30a5a9f993377f0c44a54aadf0fabaaafa2c9\$lut for cells of type $lut.
Using template $paramod$8ccf61cbd280c99ab22986f0067fd91897da1e7f\$lut for cells of type $lut.
Using template $paramod$f3b4f70f83b4fad4bafcc347ba5e929e791ac7fb\$lut for cells of type $lut.
Using template $paramod$d204dcd684fb26edc5d9b574bf529711b8d47355\$lut for cells of type $lut.
Using template $paramod$46969734f619307bdfb8ca4ad5af273b11115f8d\$lut for cells of type $lut.
Using template $paramod$c4fe0d52e4fa3d649d75cb9587992cb08e44f263\$lut for cells of type $lut.
Using template $paramod$6d4cc4f82cbeec9f11ee20382d2e8cbca780ab4d\$lut for cells of type $lut.
Using template $paramod$bea03cef725dcf7c46c2a545abcb366bab781bdd\$lut for cells of type $lut.
Using template $paramod$27102b9cbeb32c3f0f3712aec95903cf8e16c53e\$lut for cells of type $lut.
Using template $paramod$2c9fdd9f81a9a0f20f195228573ae06ae3d35480\$lut for cells of type $lut.
Using template $paramod$f9138effd5f0d2e3613ca65cf38b42608ca25610\$lut for cells of type $lut.
Using template $paramod$23c77cbf9f37322cb0fd161a8ebaaf97fb311128\$lut for cells of type $lut.
Using template $paramod$6bc1c24c556d3221f333f107616cd98e6a577ee1\$lut for cells of type $lut.
Using template $paramod$f4257f9b9dfe762de25d0a149f2ea6e405c888f2\$lut for cells of type $lut.
Using template $paramod$19f568890ed784cb1efc3ce1b67eed20a6c54d9a\$lut for cells of type $lut.
Using template $paramod$79a5f4f6c85f6353a05008626bbb50a513afc30e\$lut for cells of type $lut.
Using template $paramod$742d6501cca9749526a1afa5731f29741703db84\$lut for cells of type $lut.
Using template $paramod$ab2d8c2b9d8aa7f76721394c261b87284f763090\$lut for cells of type $lut.
Using template $paramod$a191129d10a368b82781b98ff31865427345b51c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut.
Using template $paramod$3f552d60fdb6aa7edeac8ab63bebd75a2ed178fa\$lut for cells of type $lut.
Using template $paramod$d462c1036b159cddae3de55d4cd2ced9cedf9818\$lut for cells of type $lut.
Using template $paramod$181d49f34bcb31fbb5a26e11f31af35e57e71eb0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut.
Using template $paramod$d732751b64000306ae965d2ca14a7d0605ee3312\$lut for cells of type $lut.
Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514\$lut for cells of type $lut.
Using template $paramod$83c1b6108170249166239e09804c5f4542556524\$lut for cells of type $lut.
Using template $paramod$94d5907cd943cfeee8b51d0867911bf046b5b43a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod$cb0fb1720ac2cc9a1fd4c68c65532135911f6918\$lut for cells of type $lut.
Using template $paramod$409279b79277055c92c645b01c2deb7a6d1a6a87\$lut for cells of type $lut.
Using template $paramod$423640a8cbe9f4d060f0a0cfd687aa9e86435507\$lut for cells of type $lut.
Using template $paramod$a05e9a6aa781ee5d859ffba39d06dc0dc1044e96\$lut for cells of type $lut.
Using template $paramod$1221ecddf806ed98cf6cee2f2b5a80f38aeb4bee\$lut for cells of type $lut.
Using template $paramod$89f79d27281dc84f00f8f0c6de79cd1b091e2005\$lut for cells of type $lut.
Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707\$lut for cells of type $lut.
Using template $paramod$7dad2285b6a41fd718a0863efc009b14ae7d121a\$lut for cells of type $lut.
Using template $paramod$b135cb4d1e5a108815ac7673044f66e05fc804c5\$lut for cells of type $lut.
Using template $paramod$62ed4c3299b68c9865de35b2752762287f7bd37f\$lut for cells of type $lut.
Using template $paramod$b0a1a60564bf9a70cd83ff82c322d8476b608c8d\$lut for cells of type $lut.
Using template $paramod$0d1f6636064b3f61aa72fb16a6f6d779cbf82959\$lut for cells of type $lut.
Using template $paramod$ddaf26d85d4c0279addf8c719cc62af3cb1cd9b3\$lut for cells of type $lut.
Using template $paramod$5270c3d7267ddafe30b04eb78a6e5508a88f9272\$lut for cells of type $lut.
Using template $paramod$4fba8a92c4059c922ed67976ce06bc019c16459f\$lut for cells of type $lut.
Using template $paramod$c4eb5cf5a6531671a7b92d59929b76cf882df6b8\$lut for cells of type $lut.
Using template $paramod$684656d704045786d5250a9d412d120fad866846\$lut for cells of type $lut.
Using template $paramod$8b16f299a851b69ee5e760e5b818281d3215ccdb\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$8fc91576c5f54b15fc99c4e874cc805c3b7b5df9\$lut for cells of type $lut.
Using template $paramod$6bf74d43098222579e639c5a64a5885252736467\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod$98706df86741f6151e6f5b18a040de5d8e4da678\$lut for cells of type $lut.
Using template $paramod$fd20f44aba4f0852c2a1d01eca984f768dc8703f\$lut for cells of type $lut.
Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$3ba1d7fad4fdd5e23c8c439dae13f5b171e940b0\$lut for cells of type $lut.
Using template $paramod$a5b54db957e9a0bcf23273141971a98d5b15429d\$lut for cells of type $lut.
Using template $paramod$b37c5d845fb0835db15f4b4d1b378430d8b52d15\$lut for cells of type $lut.
Using template $paramod$f7cbd8f5974233f70d25c33ef6a692898e4f6377\$lut for cells of type $lut.
Using template $paramod$64a5583ed4578f469f46798a9cdd87659c2e6dd8\$lut for cells of type $lut.
Using template $paramod$023f15a12a5ec0c08c0b5bda45596e635dfb297d\$lut for cells of type $lut.
Using template $paramod$ac82afd16b66f271f344b8c60907f0fe3883da51\$lut for cells of type $lut.
Using template $paramod$266d7cad54b576ece8b63c7f264d772544a5664a\$lut for cells of type $lut.
Using template $paramod$bcfa3a9d7fc9307b720401d437d1b7293fda0772\$lut for cells of type $lut.
Using template $paramod$e6504163a6aac7eb100aad063fcf1dad8ffd4e1b\$lut for cells of type $lut.
Using template $paramod$5ad5dab2319eaa393748d74a6ae3cf6d24e40054\$lut for cells of type $lut.
Using template $paramod$193d365ba3260f56de4ca734b1cedcf9dc72302b\$lut for cells of type $lut.
Using template $paramod$fd27d56d839cebdc9de7486e8cbea966b721f845\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$3dfdb778126ab011e4d5dd8bd717182a0c306ecc\$lut for cells of type $lut.
Using template $paramod$7ce1e218e4ea0c35c951204232bf991fd4f1425d\$lut for cells of type $lut.
Using template $paramod$52b16e02f9802938606ca1b07736b1ecf69f6eb1\$lut for cells of type $lut.
Using template $paramod$2646f79d883fe55c6115f3a5c1d9911a69497523\$lut for cells of type $lut.
Using template $paramod$55cd24dc75c9df441970d5c4021e3e4022d76c6c\$lut for cells of type $lut.
Using template $paramod$2e42f4cdfa2b7be54cbecc74818d81b621a7793c\$lut for cells of type $lut.
Using template $paramod$9fca8120d2355d1c76ab090838dcf26ce69a9df5\$lut for cells of type $lut.
Using template $paramod$03d7da0d848b4f563fda6bc83a08135cc5ded340\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$804ece54d80153d24c1fcff2ee9fb5baf9b414bd\$lut for cells of type $lut.
Using template $paramod$e3a393f86ce09c680bf2cab6a272b9655da6b686\$lut for cells of type $lut.
Using template $paramod$b12bf8b3d3a35444f0dac3518aabb7d4365a4282\$lut for cells of type $lut.
Using template $paramod$e216ec9ff15b5193c7194d2d286a9a1eb9bd2cc0\$lut for cells of type $lut.
Using template $paramod$d96938b933811903763c8fc48238ba3a4fe3fe61\$lut for cells of type $lut.
Using template $paramod$410654a338494d4983a424035c9c9af4ae257a26\$lut for cells of type $lut.
Using template $paramod$db53c36ba1a6e87cd5bec148a0c4dfe55c67649c\$lut for cells of type $lut.
Using template $paramod$e7dd21ebe2a209013c5158379d639c69fca86be9\$lut for cells of type $lut.
Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut.
Using template $paramod$6cc2e8cf339d58b651237e4afe9edc82863bc3b0\$lut for cells of type $lut.
Using template $paramod$dc828a6f122724e6c4ab2d0c2a4bb5abe04e2ece\$lut for cells of type $lut.
Using template $paramod$44b595ed4c088ee19bdbc74239e8827202b256f5\$lut for cells of type $lut.
Using template $paramod$b3c773c892ad0cc3f97d181752f1c532c3ff4fca\$lut for cells of type $lut.
Using template $paramod$c5d791b2dd3d8afd456f4384acfd996b0f093f14\$lut for cells of type $lut.
Using template $paramod$b4286900da1bbbce775d940132d12ee69163aa6e\$lut for cells of type $lut.
Using template $paramod$d20968da9bac46a74e2f40e940a3fa628ad430e6\$lut for cells of type $lut.
Using template $paramod$e54f0bf27c491826d9170f979fd786dc4f4d9af9\$lut for cells of type $lut.
Using template $paramod$019965b2e87d32721f1d87cc369dec085bb0c395\$lut for cells of type $lut.
Using template $paramod$cd05caaf261e4148f336c0ecc488c806e4433d99\$lut for cells of type $lut.
Using template $paramod$12b93181fde40368887ce43b59fecaa09cb41fa7\$lut for cells of type $lut.
Using template $paramod$b1241bb2f9028a57b5d511f41eb42255eb327e39\$lut for cells of type $lut.
Using template $paramod$1cda4f14c12024f5b9cd69258237909bd7b548fc\$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod$f01b27bd3e9f17a779c010dc32b31e32e1d5ecd6\$lut for cells of type $lut.
Using template $paramod$f94cf08026d21db794b98b1a8efaec5f34ff8975\$lut for cells of type $lut.
Using template $paramod$3e895991b845b8c620b8c9e0068c52e372d1fbc1\$lut for cells of type $lut.
Using template $paramod$9cb0b16a9f4a12dee51ccd9f814781f77df4be6e\$lut for cells of type $lut.
Using template $paramod$ad2a305d4550f1ab660bdb398658500978722948\$lut for cells of type $lut.
Using template $paramod$e5195969509d5f639482b043983463bced129a07\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$8925c83088e549cc9571d10991f850482dea6c12\$lut for cells of type $lut.
Using template $paramod$20ba583962918fa0136fc97b1558cc45cc91cc29\$lut for cells of type $lut.
Using template $paramod$810a2243edb88360cc6c97a79484157a2d72b37e\$lut for cells of type $lut.
Using template $paramod$4510fd209bba60d6262358777611af3f9cb61cb3\$lut for cells of type $lut.
Using template $paramod$62fc4ac57a0b73f1d95465f30f5df060addcd3ec\$lut for cells of type $lut.
Using template $paramod$5b1b69a756efcf8f4c2f44592487a861efa56807\$lut for cells of type $lut.
Using template $paramod$fd3ed3a223484aac184d1b7412ec4cfe4ca64c32\$lut for cells of type $lut.
Using template $paramod$d35161d1d7976dcc02e7c7d51172431be85143b4\$lut for cells of type $lut.
Using template $paramod$aa635ec680991eed2bacd2eef5177202e99a1691\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee\$lut for cells of type $lut.
Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$63114da772fb28945ba24699e32f1e30ca7142f4\$lut for cells of type $lut.
Using template $paramod$7e9df0afb32b76fe5fce0691b8752aca650057fa\$lut for cells of type $lut.
Using template $paramod$7d813eb49700f971f2635a434700eafdfa816bc3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
Using template $paramod$97108e3cc0d0482a6e72e932e86430aa2177750b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$fc318a7df7fe07fd6e06d67fcbc358e9823ea389\$lut for cells of type $lut.
Using template $paramod$d2845ee2da121e591069744d16cf238f53bde61d\$lut for cells of type $lut.
Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut.
Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut.
Using template $paramod$516e0c30d66d0cb1c81ba299a22eaf236a4b303a\$lut for cells of type $lut.
Using template $paramod$c6a1f9ea79b7bb1672d5d3c63312684d0f3defb6\$lut for cells of type $lut.
Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut.
Using template $paramod$d76edc10344198fdbbc083cbc9765a888a1f48f2\$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$1b53a9695a0f80de7517b50863b438fd2b7f56da\$lut for cells of type $lut.
Using template $paramod$9dfe2a25d99d8640a9f67a2438aaca85b684d257\$lut for cells of type $lut.
Using template $paramod$ea2ed7b6000d8bc7d418a28d22dd562f94afdeff\$lut for cells of type $lut.
Using template $paramod$1c8aea8d15a8caa53bcd106d813c48ea86657836\$lut for cells of type $lut.
Using template $paramod$94d2f1f461ef911482e15efdba185521de732c99\$lut for cells of type $lut.
Using template $paramod$4888f2121a1fba4d507203534ae54782bc81e02e\$lut for cells of type $lut.
Using template $paramod$611e5863a30eeacc19b5015939188ef7be763eab\$lut for cells of type $lut.
Using template $paramod$80bc945f6d438f16387422ec284dc12b4bb4e68f\$lut for cells of type $lut.
Using template $paramod$dcba541ad53a9873d71bfba6c13dc2a8e2a60a79\$lut for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod$efe7edbda0bcb435c2e0f2c62fcb400fdc96882a\$lut for cells of type $lut.
Using template $paramod$b2192df6f90569fea4015d0a6658bdc192199f95\$lut for cells of type $lut.
Using template $paramod$5a3b726670ce434c27ab6d39e16edfbe9baa03b2\$lut for cells of type $lut.
Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut.
Using template $paramod$ebdfc07f371983eb68dd70ec63edee869ba600bd\$lut for cells of type $lut.
Using template $paramod$a5decf35c8e89d7ee0a60057106759110775301b\$lut for cells of type $lut.
Using template $paramod$4bf8ce4ba3837f34813021ea7ba48081e9887a3e\$lut for cells of type $lut.
Using template $paramod$90edad2b6a4dec5adef9ce6a532f7a1edb48db32\$lut for cells of type $lut.
Using template $paramod$42605c48f264c357570bf238df7715488931c6b0\$lut for cells of type $lut.
Using template $paramod$17f1b90a5c6d7e6613368c5e7d3f44dd634e59e2\$lut for cells of type $lut.
Using template $paramod$12fb017f90e7463fe74789d2ec23494cce2be24a\$lut for cells of type $lut.
Using template $paramod$d11fd0cafe28c6509f05d39c9d5671060ee4e821\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000100 for cells of type $lut.
Using template $paramod$5f3abb125a0361a143f12eec230ed33f6f988a00\$lut for cells of type $lut.
Using template $paramod$857512ea84a5fe5464efcd374b77666399ea78e1\$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod$158ffd8e6cb0924866d9bc35302735abacf679a0\$lut for cells of type $lut.
Using template $paramod$381611b500514811fb8bbbfdb6c4a52e262017a4\$lut for cells of type $lut.
Using template $paramod$35d6d6bee07fbed4c99d77928117736fae8df929\$lut for cells of type $lut.
Using template $paramod$a5a9d48041af65bd5d7b6a1f6014e7ed22f6b87a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut.
Using template $paramod$cbb2dfe31d344d3326d567c2ed5a4b2a29f63219\$lut for cells of type $lut.
Using template $paramod$b7792e1962fb8b65865c48433cacb9941e24b485\$lut for cells of type $lut.
Using template $paramod$9cf976b4f3a576aa2cd6b51304cf5de7fc836fbd\$lut for cells of type $lut.
Using template $paramod$c214b4f4a9031361a7ff4859158ca8c9d48de37d\$lut for cells of type $lut.
Using template $paramod$9dbe36982f6b8ca20db05cfcd5650178f13179f3\$lut for cells of type $lut.
Using template $paramod$b45308ffeb4031bc5d55ef31b149afd94d3d7565\$lut for cells of type $lut.
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut.
Using template $paramod$9ea34eb01f9b75f8b9132856d9e5332a707924f2\$lut for cells of type $lut.
Using template $paramod$0b8d6fc791fa7aabae7ac8a1db71a7d15d45f7f4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$4834046533425f54583d6bd31e49deb63455e1a5\$lut for cells of type $lut.
Using template $paramod$47671b68495b53d6eea5a9dd67c114907e17980b\$lut for cells of type $lut.
Using template $paramod$8829675bb8c52553aed9f101ec0d5ef0c865e5c7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$bea08a495d16293f8cc454a45845d26cde0762b6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut.
Using template $paramod$a5dd9ee10fc2202a29791f7d68d4afcce241aee5\$lut for cells of type $lut.
Using template $paramod$dbd6bfc0079f30bdbd8251243755394b48ae1fbb\$lut for cells of type $lut.
Using template $paramod$609ff53b8e25fddda2f58be8d19c2d47b81baf45\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
Using template $paramod$dff8e7e8854dc948604d9ed7dea9d198697a573d\$lut for cells of type $lut.
Using template $paramod$b68f9800cc1bf69afcfbc0567a25e43ebb01456c\$lut for cells of type $lut.
Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut.
Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut.
Using template $paramod$181733d3e31dcdcea8c52d0a4fc252b3aa453564\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$a5f20fb2f07da47fc82a54256d711012d9ea90d3\$lut for cells of type $lut.
Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$7ca4db46d3cd57dbe2541a389808e6d33af02319\$lut for cells of type $lut.
Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$7bccb9c410d396b7f6c8d1f48396148fc5f7efcd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut.
Using template $paramod$d52cb446bc89fafcaa49f2b908e540f513a4d760\$lut for cells of type $lut.
Using template $paramod$faf4b69e2195a9ce52b7c3bce83fa5ea343bc378\$lut for cells of type $lut.
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010011 for cells of type $lut.
Using template $paramod$523564eac00ace45f8b8dbd4352b829368c2e8b8\$lut for cells of type $lut.
Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut.
Using template $paramod$413d040dcd860cd74ca61a70644516a95d328ae7\$lut for cells of type $lut.
Using template $paramod$7fed74f2cef975f9d09dcb0a10cb49d92a5c6372\$lut for cells of type $lut.
Using template $paramod$b7ffccfabd6e7ca08ce1262cc41379da0e08bf9a\$lut for cells of type $lut.
Using template $paramod$b615004ebff9228145b881021ca021846a7f9002\$lut for cells of type $lut.
Using template $paramod$4a5cb9a6822416135c3ccf2a28bcf23a857f7920\$lut for cells of type $lut.
Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut.
Using template $paramod$42fa10564c54ade9da2173f612e0982cf8afb5a0\$lut for cells of type $lut.
Using template $paramod$12e9049d8709286a770fe60b59ec4d94c39ce3c9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod$ede67ae6159d4864b11272c4fe0692c3419120cd\$lut for cells of type $lut.
Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut.
Using template $paramod$c145f84e6b9aba2d7bbf6cd4a827e636b5fa3ae0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut.
Using template $paramod$a5627e8ad36aa9b4fe2f6188097d151d45fefa8a\$lut for cells of type $lut.
Using template $paramod$cf8d1dad1681cfac7d8629b08a1bd833c99195d4\$lut for cells of type $lut.
Using template $paramod$52953750219effadf43093a566baf492fdd6b6c8\$lut for cells of type $lut.
Using template $paramod$6375ab94b303a3f3c8d7ca6946328cb3c0b443a7\$lut for cells of type $lut.
Using template $paramod$d25a0f1ed4a99ef8d1bf6a91b3015ece3e01714b\$lut for cells of type $lut.
Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0\$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$a2657580ee705348a33a1ee3bd7383820950f23b\$lut for cells of type $lut.
Using template $paramod$7ea2352f8f054781a715aeddf3e67f1db65f005a\$lut for cells of type $lut.
Using template $paramod$9a383ca297ef012b6f33ce559547f89432250d88\$lut for cells of type $lut.
Using template $paramod$e718d2f5eb562e6029d6a1b1e060511bf1c65df1\$lut for cells of type $lut.
Using template $paramod$5afdc7428159757eedf89ce514f7efa32b31c8e7\$lut for cells of type $lut.
Using template $paramod$e62442126c3ec4db4ea7200e579fef7f8acaa783\$lut for cells of type $lut.
Using template $paramod$0d26e42822227428593a6f2ed183ae9b22d4b575\$lut for cells of type $lut.
Using template $paramod$8925aba7894ac7ccf9ac7c221fef926db9623020\$lut for cells of type $lut.
Using template $paramod$98dd5f38e0117c44d93d8e3812b44b0b0edd2ec0\$lut for cells of type $lut.
Using template $paramod$faba0cf60f1c89602d59ba2d491152c8f0d36384\$lut for cells of type $lut.
Using template $paramod$099af7f70fcc70b41da4ec1f8df6dd0abf473cb5\$lut for cells of type $lut.
Using template $paramod$707701b498a5cd123a043548b93e61e0b6bdc440\$lut for cells of type $lut.
Using template $paramod$6e46ec5a196ba1a24b8e69ab094cadc07c13ac1f\$lut for cells of type $lut.
Using template $paramod$51b138c6601401861f3f66aa30cc9212c6a6619a\$lut for cells of type $lut.
Using template $paramod$653ed1fca2cbea6092fc92115114dddd9158d22d\$lut for cells of type $lut.
Using template $paramod$fd8cbfbb0ad6945f17419290e86ae48a85480aca\$lut for cells of type $lut.
Using template $paramod$9e1755e3954600257bb9b9ab192e2c0243b0f35a\$lut for cells of type $lut.
Using template $paramod$478e33feeac3aa53ff57d491aada044b8aedceae\$lut for cells of type $lut.
Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut.
Using template $paramod$8f7210088a40da1859d27e900c288fd298d68bed\$lut for cells of type $lut.
Using template $paramod$c52825d0b1a0cfc6362b36af6d13149a97d3e424\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$e0e0b9515c7031ae11155409478b65d3742b804e\$lut for cells of type $lut.
Using template $paramod$f6205ea4d16154fcc0de4d21dff0bd55a57f1ba0\$lut for cells of type $lut.
Using template $paramod$f0ee8f1fac2e8dfb2b7c2829afefa281d87aa802\$lut for cells of type $lut.
Using template $paramod$1dbc005c3ca46176ed5f71d3318762a2498d170f\$lut for cells of type $lut.
Using template $paramod$1fd785bf11bc9d753ee0cbd45ad8d84e98a705db\$lut for cells of type $lut.
Using template $paramod$b40080b643baa8bb528ec249e10d82b2d80dfed9\$lut for cells of type $lut.
Using template $paramod$183ec76ed3429a430a8be24b57f3de734985f568\$lut for cells of type $lut.
Using template $paramod$d8905128edf1384eccfd1b9f150a88db7c8175f1\$lut for cells of type $lut.
Using template $paramod$022f25e351f4370d3db4af915ee589ef82048c31\$lut for cells of type $lut.
Using template $paramod$c08a774c89ef1ea6ee2ef4d8c3b071eb141d4259\$lut for cells of type $lut.
Using template $paramod$812f633adb63ee5c3031a25df88a84362040bd10\$lut for cells of type $lut.
Using template $paramod$c958b3a888f937f082b94811ff62d71e32a2b4eb\$lut for cells of type $lut.
Using template $paramod$f6d9b5b6571142725a334297d4143cd8fd67b25d\$lut for cells of type $lut.
Using template $paramod$db4421b8cd8e111f0252332f4864a714ac72aaf0\$lut for cells of type $lut.
Using template $paramod$6fb487e03b9eb2189ab4deaeea6214b936634463\$lut for cells of type $lut.
Using template $paramod$eea99bc84cf5347c20723d7c9448a7e739d98164\$lut for cells of type $lut.
Using template $paramod$f52df4b90f46c2ab9e801e1f39516c9cb1bb6ae7\$lut for cells of type $lut.
Using template $paramod$2955ab75367a3dc9d6f50d3655eebcd4f615031f\$lut for cells of type $lut.
Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011111 for cells of type $lut.
Using template $paramod$993b4f1762899d4359410690d334eafca84b9285\$lut for cells of type $lut.
Using template $paramod$15deee21bfb7f6f9f3963bae01e1abc87728ceb1\$lut for cells of type $lut.
Using template $paramod$fc8c464f8ac53dcc1fb890ccd386eddd18c67c7b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut.
Using template $paramod$f8d5d066d4e5f7165e8ed9a8f737e8a8d3ad99fa\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut.
Using template $paramod$0d32e36bab4cd3e24dbcc94204821aa7f75d106e\$lut for cells of type $lut.
Using template $paramod$b304cf58995814bfcb142bd23c9043c6fb0fd926\$lut for cells of type $lut.
Using template $paramod$1875a64980687d84476cca9206287369bec7f34d\$lut for cells of type $lut.
Using template $paramod$c8d1ea13545ff94b0a3e963a50c2a7208486c6a0\$lut for cells of type $lut.
Using template $paramod$625b44527a6320960a991295842340eeca84d995\$lut for cells of type $lut.
Using template $paramod$22641603d8fa727856e499ecf3ff9bfa826a5891\$lut for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$18df3812bc12364e5ebcb6c3ed05c0294e4c26fc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut.
Using template $paramod$15dcd80d72f8269cefeea2cbc86007d3271f025d\$lut for cells of type $lut.
Using template $paramod$2d70e360329f2b83357618532825d0cf30a325f3\$lut for cells of type $lut.
Using template $paramod$18b66a2dc66be2a0d172c3d50ba03932f5924e22\$lut for cells of type $lut.
Using template $paramod$24c475e55866ef2ed375f1bcba93c519be3b9547\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut.
Using template $paramod$cae86cc3087f0ba749b437cbf8d16c8515959860\$lut for cells of type $lut.
Using template $paramod$a077abf7f5e6621cefe1e8e13fd9dcab66e4d471\$lut for cells of type $lut.
Using template $paramod$bf0916c6d7935eef0257c8c924841f67bcefce14\$lut for cells of type $lut.
Using template $paramod$95d3441a86b9e9e603092771e991bc2687a210d0\$lut for cells of type $lut.
Using template $paramod$29e6d4598488760861f6b73d2b7f65cb302fdcde\$lut for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut.
Using template $paramod$c7017ce6f918370601990fdcd7ae7caf301de017\$lut for cells of type $lut.
Using template $paramod$f7a897257decedfb6cc642e53d65fef7fc0df390\$lut for cells of type $lut.
Using template $paramod$061bf509610e3c6080c8b516973b11121df0b78c\$lut for cells of type $lut.
Using template $paramod$92ba463554af19910d47a5b3fbbe5278c7f099aa\$lut for cells of type $lut.
Using template $paramod$64f43dc318f4c77b4186c3ebcba0aa7863e84359\$lut for cells of type $lut.
Using template $paramod$3666188b96545248717c2ff7edce939f185fe6fd\$lut for cells of type $lut.
Using template $paramod$c441dbd41fa7b52ce609b1fb3e8a706905598601\$lut for cells of type $lut.
Using template $paramod$a2241d5ec0a8f3e22a06d121139c830891d880d6\$lut for cells of type $lut.
Using template $paramod$20f3f4b8e32f8a8b038b0056872dc94926194798\$lut for cells of type $lut.
Using template $paramod$88c7fa4cebf7dcb13ff45f839cb2ced3333f7369\$lut for cells of type $lut.
Using template $paramod$a462117541566384a2f7b7f7d9d41b1139721862\$lut for cells of type $lut.
Using template $paramod$20f82dd03802038bc013e5804609eaebb5d257db\$lut for cells of type $lut.
Using template $paramod$d315acbf930db7c20b3f4ac2dad3b7982b1f437c\$lut for cells of type $lut.
Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut.
Using template $paramod$106df73d596ba84cd5c87355d01d2ea0a5c5dcb4\$lut for cells of type $lut.
Using template $paramod$37be11c6c8d2b9c52a2237d19b839661720eff1e\$lut for cells of type $lut.
Using template $paramod$655e7cdf1fce9923e771969f28446489197085e2\$lut for cells of type $lut.
Using template $paramod$620586420e818d3afa7e5b51fcf19f5c6ea83ad4\$lut for cells of type $lut.
Using template $paramod$dc41a956c02896bb314b3585a99557a5e53688a4\$lut for cells of type $lut.
Using template $paramod$aab54572d5ffecd31253b36e73e9cb718d05be34\$lut for cells of type $lut.
Using template $paramod$34b993dceb5fdc659be86890696f92d33385d233\$lut for cells of type $lut.
Using template $paramod$7f937f9b61bf542e3f85320ab27ebb3043b4337a\$lut for cells of type $lut.
Using template $paramod$af574ac083faf8d8036edb1d34eb40d28d20ac3a\$lut for cells of type $lut.
Using template $paramod$9becc6376cac3c55b34ebe436ca01b702d34d09e\$lut for cells of type $lut.
Using template $paramod$ac8209247811fc80703397b7db338e556c500393\$lut for cells of type $lut.
Using template $paramod$3047492e26a89986a585d0cb18765b19c46a7824\$lut for cells of type $lut.
Using template $paramod$2a4b250d89be3556c74aa0e719a4f6242369d42f\$lut for cells of type $lut.
Using template $paramod$875bdc6f957a2a7141afe3a3f5d42e10fc3a7688\$lut for cells of type $lut.
Using template $paramod$071ef78ef050a8e3f1c7fc362b575932ee043820\$lut for cells of type $lut.
Using template $paramod$b419810ab1d51da1962917a1949cecc5f27935eb\$lut for cells of type $lut.
Using template $paramod$63b93fb099f48f0c09f0ff623677f8fb8aa6a591\$lut for cells of type $lut.
Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d\$lut for cells of type $lut.
Using template $paramod$cf93df6a751c015d454aef52e32716809f254f3e\$lut for cells of type $lut.
Using template $paramod$f2972f00f781f1a033cecbb6cc420de13224764a\$lut for cells of type $lut.
Using template $paramod$66bf2c1f0aa76f60f50d37e63c6fb3163b1ca684\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101110 for cells of type $lut.
Using template $paramod$1e9d7896e1dd3d2af9633eefc9c29afb478cef41\$lut for cells of type $lut.
Using template $paramod$0bd570700cf8cad0539c515a93aa6679c2fc4116\$lut for cells of type $lut.
Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut.
Using template $paramod$c9d86860d7b8a94fe4e147db4941c14e73dd3281\$lut for cells of type $lut.
Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut.
Using template $paramod$8c13ad014d500c3a349fa680995aa7f6f9eaaf87\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$ab4188c7524eec831e9177bc675d62b21a3ccd8b\$lut for cells of type $lut.
Using template $paramod$e4723c78131b859cdb296cc7099a965ce6bf28d9\$lut for cells of type $lut.
Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut.
Using template $paramod$6c30e96f9a581ef20d66e60c8c4849cf1b34156f\$lut for cells of type $lut.
Using template $paramod$471732eaa35ff34fe29d9dba50f3121d479caafc\$lut for cells of type $lut.
Using template $paramod$e77dca5e1fc847f9005cbcedebcb6de355499010\$lut for cells of type $lut.
Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a\$lut for cells of type $lut.
Using template $paramod$50222e4d0527635d5cf211ed95d1ccfc839e99e8\$lut for cells of type $lut.
Using template $paramod$7295da7c5b19f528a428229f2570e0a23ad372af\$lut for cells of type $lut.
Using template $paramod$50ec6039d9de561a6d0a8dc470847f22a306b04f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut.
Using template $paramod$9664b2f5fd61944d7798b30cde43b99ccda87303\$lut for cells of type $lut.
Using template $paramod$127c0f065cbdbfc01465fd58161d13b20251be83\$lut for cells of type $lut.
Using template $paramod$899a7d400185b4f778bea81a50f62c95a0b19d77\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut.
Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut.
Using template $paramod$bf8a2eb9c34204449ae734db198784b474646269\$lut for cells of type $lut.
Using template $paramod$02b63907fb626de3e5f6572173cbabd407ece191\$lut for cells of type $lut.
Using template $paramod$bff60da521de773f8caf46fbc0845c3d7d3e2310\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut.
Using template $paramod$b637cf4714c2e93484bb499728e176a6ab69c910\$lut for cells of type $lut.
Using template $paramod$17c2f243a1da896c622c9087a9b7432bee6819fa\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$1b4dd6457d07f8f165ec99061b8d6c5023635c5b\$lut for cells of type $lut.
Using template $paramod$34536926332939882b8ff52380fffc08ed1f405f\$lut for cells of type $lut.
Using template $paramod$fb5ee0bdef1c4e74aaf1fd8efae98b46a2f5e564\$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$eb764785a67ae0903625e17df40813438d0457e8\$lut for cells of type $lut.
Using template $paramod$4e170b31b7c789f1d8d96ab4432fdb7e5773d3c7\$lut for cells of type $lut.
Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5\$lut for cells of type $lut.
Using template $paramod$a778b5c2132d9b5c5fee9d4dbc2918c250f71acf\$lut for cells of type $lut.
Using template $paramod$1843b3c15f2447d117e2d5de9b00f791ef5f9fa3\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~13920 debug messages>

21.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153467.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153721.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153532.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153565.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153601.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153607.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153671.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153696.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153716.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153425.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153486.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153503.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153539.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153541.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153548.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153579.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$32393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$32261.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$31560.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$31506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31417.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$31367.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$30975.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$30499.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30189.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$29789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29779.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$29660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$29266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29266.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$28824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$28809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$28309.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$27813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27724.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153800.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$27410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27295.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$26972.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$26506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26196.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26109.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$26103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26080.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$26053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$26053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$26035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$25925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$25585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25229.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$25174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$24714.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$23982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$23799.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23387.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$23288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23037.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22927.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$22918.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$22433.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22025.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$21972.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21882.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21669.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$21551.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$21024.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$20899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$20899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$20899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$20899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$20760.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$20465.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$20065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$19567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19497.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$19452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$19452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$19443.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$19396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19321.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$18644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$18514.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$17544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$17484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16500.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16500.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16500.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153754.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153755.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153756.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16033.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$15959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153825.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$15498.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153829.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$15446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$15339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15282.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153801.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153789.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153792.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$14798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14788.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14783.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153785.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14641.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$14617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153811.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153814.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153815.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14451.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14369.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14306.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14165.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153823.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14089.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14072.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13923.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13859.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13793.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13699.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13658.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13642.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13576.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153794.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13448.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13417.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13402.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$13402.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13402.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13402.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13402.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153786.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153783.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13353.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13208.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$13157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$13157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153790.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153795.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12971.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12857.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$12845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$12804.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12782.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$12636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$12546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12345.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12149.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12132.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12052.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153838.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$11987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$11987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$11970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$11906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$11906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$11818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$11651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$11633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$11633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$11633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$11603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$11633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$11665.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$11671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$11678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$11684.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$11694.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$11721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$11721.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$11818.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$11856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$11856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$11970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$11996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153835.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153834.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12168.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12193.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12224.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12354.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12529.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153841.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12619.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12644.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$12676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$12683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12705.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12817.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$12866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$12980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13062.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13117.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$13157.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$13217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13280.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13336.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13362.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13374.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13402.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$13487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13487.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153798.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13667.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153793.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153802.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13868.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13948.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153806.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153822.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14165.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153819.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14245.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14315.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14315.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14378.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14460.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14539.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14631.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$14651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14666.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14680.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14708.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14721.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14798.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$14806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14806.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14829.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14876.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$14894.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$14990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15071.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15105.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15158.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15173.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15181.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15223.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15296.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$15310.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15327.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15349.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15353.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15387.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15411.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15415.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15450.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15523.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15538.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$15587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15623.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15627.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153824.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15658.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15717.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15721.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15747.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15783.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15810.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$15826.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15852.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15876.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$15913.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$15969.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$15999.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16013.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16027.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153759.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16080.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16203.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16209.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16236.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16246.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16269.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16290.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16323.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16343.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16354.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153753.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153828.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16405.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16440.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16446.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16459.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16478.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16494.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16505.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$16543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$16557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16727.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16757.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16772.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$16812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17202.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17335.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17390.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$17484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$17507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$17531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17544.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$17569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$17577.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$17595.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$17606.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$17626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17668.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17676.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17718.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$17999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$auto$opt_dff.cc:219:make_patterns_logic$4502.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$18395.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18466.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18514.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18553.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18571.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18590.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18597.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18752.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18847.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18865.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18886.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18895.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18918.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18942.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18951.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$18978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19008.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19267.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$19396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19404.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$19404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$19411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19421.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$19447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19452.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$19464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$19475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$19501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19520.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$19526.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$19546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19567.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$19628.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$19649.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19665.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$19742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$19780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$19972.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20018.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20024.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20042.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20074.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20097.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20104.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20141.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20169.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20190.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20251.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$20302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20420.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20443.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20469.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20474.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20505.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20505.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20523.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20532.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20532.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20591.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20597.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20617.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$20655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20720.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20899.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$20976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21029.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21059.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21077.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21087.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21126.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21152.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21217.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21221.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21228.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21281.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21400.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21405.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21446.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21504.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21525.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21583.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21589.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21607.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21628.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$21679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$21737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21768.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21887.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21948.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$21976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$21981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22029.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22038.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22183.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22203.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22381.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22404.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22415.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22469.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22469.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22487.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22506.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22511.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22511.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22552.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22558.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22578.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$22613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22878.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22895.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22931.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$22975.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$23047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$23105.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23123.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23288.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23310.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23400.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23439.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23459.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23465.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23509.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23516.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$23520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23541.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23554.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23753.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23760.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23760.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23778.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23808.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23831.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23855.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23865.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23904.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$24050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24102.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24115.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24215.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24233.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24263.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24286.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24310.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24349.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24357.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24377.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24403.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24434.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$24438.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24459.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24506.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24686.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24696.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24719.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24742.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24775.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24806.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24834.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$24931.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24949.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24962.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$24983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25019.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25149.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25178.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25242.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25269.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25349.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25356.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$25363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$25554.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25607.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25640.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25687.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25697.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25717.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25786.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$25824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$25912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26053.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26088.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$26103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26113.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26133.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26133.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$26206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26206.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26213.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26226.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26457.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26464.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26511.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26608.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26628.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26654.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$26692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26710.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26757.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26827.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26932.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$26976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26981.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27004.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27011.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27029.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27039.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27059.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27098.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27132.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$27170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$27361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27386.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27392.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27415.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27481.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27487.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27534.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27541.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$27592.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27623.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27680.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27704.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27813.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27861.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27866.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27889.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27896.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27896.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27914.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27923.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27946.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$27961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27988.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28008.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28029.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$28046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28077.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28266.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28284.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28291.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28314.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28337.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28344.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28362.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28371.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28371.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28561.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$28578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28609.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28630.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28723.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28733.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28754.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28762.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$28797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28809.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$28824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28835.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28843.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28843.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28900.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28906.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28913.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28926.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$28950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$28964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28982.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29029.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29074.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29115.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29217.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29239.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29294.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29338.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29345.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29365.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29412.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29436.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$29450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29481.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29515.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29619.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29637.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29664.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29692.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29699.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29717.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29756.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29779.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$29789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29853.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29866.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$29904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29956.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$29992.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30032.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30032.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30050.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30080.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30127.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30189.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30193.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$30199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30199.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30219.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$30257.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30333.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30474.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30508.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30538.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30556.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30711.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30735.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$30749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30933.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30951.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30980.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$30992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31011.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31029.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31037.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31076.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31183.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$31241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31338.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31349.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31349.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31417.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31421.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31440.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31445.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31486.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31524.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31548.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$153379$lut$aiger153378$31604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31617.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$31655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31720.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31825.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31843.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31867.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31945.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$31965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32053.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$32091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32236.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32330.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32484.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32508.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32515.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$32522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$32645.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27258.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$auto$opt_dff.cc:219:make_patterns_logic$4569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$auto$opt_dff.cc:219:make_patterns_logic$4688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$18045.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[17].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[22].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[24].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[26].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[2].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[30].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[3].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[6].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[7].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$rtlil.cc:2628:Mux$5237[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$auto$opt_dff.cc:219:make_patterns_logic$4848.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$153379$lut$flatten\Controller.\Interpreter.$procmux$1530.Y[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$153379$lut$aiger153378$18784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19719.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$flatten\Controller.\Interpreter.$procmux$2009_Y.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut\Controller.Memory.address[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23193.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$auto$fsm_map.cc:170:map_fsm$4429[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$19240.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut\Controller.Memory.address[4].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$153379$lut$aiger153378$23611.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30837.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153612.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$23930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$24840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$25760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$26352.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$27104.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$28434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$29789.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$30630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31102.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31492.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$19014.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$31992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$32393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$20196.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$22101.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153413.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153440.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153448.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153456.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153466.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153467.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153471.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153474.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153487.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153514.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153489.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153515.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153519.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153515.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153500.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153524.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153555.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153562.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153563.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153541.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153553.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153535.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153581.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153586.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153586.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153599.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153604.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153615.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153617.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153639.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153634.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153629.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153643.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153647.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153651.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153653.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153662.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153675.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153681.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153683.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153685.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153695.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153696.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153706.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153720.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153715.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153590.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153752.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153757.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153758.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153760.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153761.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153763.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153764.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153765.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153770.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153433.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153494.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13585.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$153379$lut$aiger153378$13802.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153821.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153827.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153832.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$153840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
Removed 0 unused cells and 18063 unused wires.

21.45. Executing AUTONAME pass.
Renamed 823462 objects in module top (289 iterations).
<suppressed ~26854 debug messages>

21.46. Executing HIERARCHY pass (managing design hierarchy).

21.46.1. Analyzing design hierarchy..
Top module:  \top

21.46.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

21.47. Printing statistics.

=== top ===

   Number of wires:              12390
   Number of wire bits:          32072
   Number of public wires:       12390
   Number of public wire bits:   32072
   Number of ports:                 10
   Number of port bits:             10
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              15859
     $scopeinfo                     25
     CCU2C                         403
     L6MUX21                       892
     LUT4                         9646
     MULT18X18D                      4
     PFUMX                        2303
     TRELLIS_DPR16X4              1076
     TRELLIS_FF                   1510

21.48. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

21.49. Executing JSON backend.

Warnings: 324 unique messages, 325 total
End of script. Logfile hash: f92bed187d, CPU: user 34.32s system 0.36s, MEM: 338.81 MB peak
Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)
Time spent: 36% 1x abc9_exe (19 sec), 13% 1x autoname (7 sec), ...
/eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \
	--lpf /eda/processor-ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \
	--speed 6 --lpf-allow-unconstrained --report report_timing.json \
	--detailed-timing-report 
/eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config  --bit colorlight_i9.bit

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/Risco-5/Risco-5
[Pipeline] {
[Pipeline] sh
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p Risco-5 -b colorlight_i9 -l
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/Risco-5/Risco-5/build_colorlight_i9.tcl
Makefile executado com sucesso.
Sa��da do Makefile:
/eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 colorlight_i9.bit
empty
Found 1 compatible device:
	0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE

Loading: [====                                              ] 6.92%
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Loading: [==============                                    ] 27.70%
Loading: [==================                                ] 34.62%
Loading: [=====================                             ] 41.55%
Loading: [=========================                         ] 48.47%
Loading: [============================                      ] 55.40%
Loading: [================================                  ] 62.07%
Loading: [===================================               ] 68.99%
Loading: [======================================            ] 75.91%
Loading: [==========================================        ] 82.58%
Loading: [=============================================     ] 89.51%
Loading: [================================================= ] 96.43%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
[Pipeline] echo
Testando FPGA colorlight_i9.
[Pipeline] dir
Running in /var/lib/jenkins/workspace/Risco-5/Risco-5
[Pipeline] {
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Aborted by Julio Nunes Avelar
Sending interrupt signal to process
Sending interrupt signal to process
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/Risco-5/Risco-5/build_digilent_nexys4_ddr.tcl
Erro ao executar o Makefile.
Terminated
make: *** [/eda/processor-ci/makefiles/digilent_nexys4_ddr.mk:12: digilent_nexys4_ddr.bit] Error 143

Terminated
script returned exit code 143
[Pipeline] }
[Pipeline] // dir
Click here to forcibly terminate running steps
[Pipeline] }
Aborted by Julio Nunes Avelar
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_nexys4_ddr
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/Risco-5/Risco-5
[Pipeline] {
[Pipeline] sh
+ rm -rf CONTRIBUTING.md Jenkinsfile LICENSE LICENSE-CC LICENSE-MIT README.md README_pt.md build_colorlight_i9.tcl build_digilent_nexys4_ddr.tcl clockInfo.txt colorlight_i9.bit colorlight_i9.config colorlight_i9.json colorlight_i9_pnr.json config.vh debug digilent_nexys4ddr_clock_utilization.rpt digilent_nexys4ddr_control_sets.rpt digilent_nexys4ddr_io.rpt digilent_nexys4ddr_utilization_hierarchical_place.rpt digilent_nexys4ddr_utilization_place.rpt docs fpga report_timing.json run_test.sh simulation.out software src tests tight_setup_hold_pins.txt
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 2b85c102-ffe6-451d-847a-15fa9b963182
Finished: ABORTED